Cache status reporting

Abstract

Aspects of the present disclosure relate to a network entity and a method for supporting cache status reporting. In one aspect, the UE determines whether uplink data of at least one logical channel belonging to at least one logical channel group (LCG) becomes unavailable for a media access control (MAC) entity of the UE. If the UE determines that uplink data becomes unavailable, the UE triggers at least one first buffer status report (BSR) for at least one logical channel or for at least one LCG. Each of the at least one first BSR indicates that a first cache size of one of the at least one LCG is equal to zero.

Description

Technical Field

[0001] This disclosure relates to wireless communication, and more specifically, to apparatus and methods for supporting cache status reporting. Background Technology

[0002] A wireless communication system may include one or more network communication devices (such as base stations), which may also be referred to as eNodeB (eNB), next-generation NodeB (gNB), or other suitable terms. Each network communication device (such as a base station) may support wireless communication with one or more user communication devices, which may also be referred to as user equipment (UE), or other suitable terms. The wireless communication system may support wireless communication with one or more user communication devices by utilizing the resources of the wireless communication system (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)). Additionally, the wireless communication system may support wireless communication across a variety of wireless access technologies, including third-generation (3G) wireless access technology, fourth-generation (4G) wireless access technology, fifth-generation (5G) wireless access technology, and other suitable wireless access technologies above 5G (e.g., sixth-generation (6G)).

[0003] Extended reality (XR) (including augmented reality (AR) and virtual reality (VR)) and cloud gaming present new and promising categories of connected devices, applications, and services. XR applications typically require high throughput and low latency, and feature large packet sizes, variable data packet sizes, and arrival jitter.

[0004] In some cases, reusing a Fill Buffer Status Report (BSR) with a buffer size of zero as an Implicit End of Data Burst (EoDB) indicator for the Radio Access Network (RAN) is not feasible. For example, a base station will not determine that the buffer size for a Logical Channel Group (LCG) has become zero based on a received BSR that does not have a buffer size of zero for the LCG. As another example, if the UE does not report a BSR, the base station will not determine that the buffer size for the LCG has become zero. Summary of the Invention

[0005] This disclosure relates to a UE and a method for supporting buffer status reporting. Through this method, a base station can determine the buffer size of at least one logical channel, or that the buffer size for at least one LCG becomes zero.

[0006] Some implementations of the UE described herein may include: determining whether uplink data belonging to at least one logical channel of at least one LCG becomes unavailable to the UE's Media Access Control (MAC) entity; and based on determining that uplink data becomes unavailable, triggering at least one first BSR for at least one logical channel or for at least one LCG, each of the at least one first BSR indicating that the first buffer size of one of the at least one LCG is equal to zero.

[0007] In some implementations, the UE is configured to determine that uplink data has become unavailable by detecting at least one end of at least one data burst of at least one logical channel.

[0008] In some implementations, at least one first BSR includes at least one dedicated BSR.

[0009] In some implementations, the first priority of at least one dedicated BSR is higher than, equal to, or lower than the second priority of a regular BSR or a periodic BSR.

[0010] In some implementations, the first priority of at least one dedicated BSR is higher than, equal to or lower than the second priority of the filling BSR.

[0011] In some implementations, the UE is also configured to: based on determining that only one first LCG has data available for transmission, transmit a second BSR in short BSR format of the first LCG to the base station via a transceiver, the second BSR including a second buffer size equal to a non-zero value.

[0012] In some implementations, the second BSR includes one of the following: a regular BSR, a periodic BSR, or a filler BSR.

[0013] In some implementations, the UE is also configured to: based on the determination that none of the at least one LCG has data available for transmission, transmit a second BSR to the base station via a transceiver in a short BSR format for one of the at least one LCGs, the second BSR including a second buffer size equal to zero.

[0014] In some implementations, the UE is configured to trigger at least one first BSR based on the following: determining that uplink data becomes unavailable; and a third BSR that is not triggered indicates that the first buffer size is equal to zero.

[0015] In some implementations, the UE is also configured to: based on the determination that the uplink grant can accommodate all pending data available for transmission, but is insufficient to additionally accommodate the MAC control element (CE) and the subheader of the MAC CE, not cancel at least one triggered first BSR, wherein the MAC CE includes at least one triggered first BSR.

[0016] In some implementations, the UE is configured to determine whether uplink data belonging to at least one logical channel of at least one LCG has become unavailable by: receiving configuration for at least one logical channel or for at least one LCG from the base station via a transceiver; and determining whether uplink data has become unavailable based on the configuration.

[0017] Some implementations of the UE described herein may include: determining a first CG for autonomous transmission of first delay information, the first delay information indicating a first remaining time of the PDCP discard timer; determining a first time point of autonomous transmission as a first reference time; and determining the first delay information based on the value of the PDCP discard timer and the first reference time.

[0018] In some implementations, the UE is also configured to: determine a second CG for the initial transmission of the second delay information, the second delay information indicating a second remaining time of the PDCP discard timer; determine a second time point of the initial transmission as a second reference time; and determine the second delay information based on the value of the PDCP discard timer and the second reference time.

[0019] In some implementations, the UE is also configured to: generate a Media Access Control (MAC) Protocol Data Unit (PDU) including second delay information; deliver the MAC PDU and the second CG to the identified Hybrid Automatic Repeat Request (HARQ) procedure; instruct the HARQ procedure to initiate a first new transmission of the MAC PDU; and cancel the first new transmission.

[0020] In some implementations, the UE is also configured to: determine a third CG for a previous autonomous transmission for third delay information, the third delay information indicating a third remaining time of the PDCP discard timer; determine a third time point of the previous autonomous transmission as a third reference time; and determine the third delay information based on the value of the PDCP discard timer and the third reference time.

[0021] In some implementations, the UE is also configured to: obtain the MAC PDU from the identified Hybrid Automatic Repeat Request (HARQ) procedure of the third CG based on the fact that no PUSCH transmission has been fully executed in at least one Physical Uplink Shared Channel (PUSCH) transmission of the MAC PDU; update the MAC PDU using third delay information; deliver the MAC PDU and the third CG to the identified HARQ procedure; instruct the HARQ procedure to initiate a second new transmission of the MAC PDU; and cancel the second new transmission.

[0022] In some implementations, the UE is also configured to: obtain the MAC PDU from the HARQ process identified by the first CG based on the fact that none of the PUSCH transmissions in at least one of the MAC PDU transmissions has been fully executed; update the MAC PDU using the first delay information; and transmit the MAC PDU to the base station via the transceiver.

[0023] In some implementations, the UE is also configured to obtain the MAC PDU from the identified HARQ process based on the determination that the CG prior to the first CG is downgraded.

[0024] In some implementations, the UE is configured to determine the first delay information by: determining the first delay information based on the fact that a first trigger report for the third delay information has not yet been canceled.

[0025] In some implementations, the UE is also configured to trigger a second report for the first delay information for autonomous transmission via the first CG, based on the determination that the first trigger report for the third delay information has been cancelled.

[0026] In some implementations, the first CG, second CG, and third CG are associated with a single HARQ procedure identifier.

[0027] Some implementations of the UE described herein may include: determining a status report format for at least one BSR for at least one LCG; and sending at least one BSR to the base station in the status report format.

[0028] In some implementations, the UE is configured to determine the status report format by: determining a first status report format as the status report format, the first status report format including a first field and a second field, the first field being related to a first buffer size of at least one LCG, and the second field being related to delay information for at least one LCG, the delay information indicating the remaining time of the Packet Data Convergence Protocol (PDCP) discard timer.

[0029] In some implementations, the first status report format also includes a third field, which indicates whether the second field exists or not.

[0030] In some implementations, the first status report format also includes a fourth field, which indicates whether the first field exists or not.

[0031] In some implementations, the UE is configured to determine the first status report format as the status report format by: determining the first status report format as the status report format based on the determination that the UE is configured to report delay information.

[0032] In some implementations, the UE is configured to determine the first status report format as the status report format by: determining that at least one LCG has delay information that can be used for transmission.

[0033] In some implementations, the UE is configured to determine the first status report format as the status report format by: determining that at least one LCG has data available for transmission and that at least one LCG is configured to report delay information.

[0034] In some implementations, the UE is configured to determine the status report format by: determining a second status report format as the status report format, the second status report format including a first field and excluding either the second field or the third field, the first field being related to the buffer size of at least one LCG.

[0035] In some implementations, the UE is configured to determine the second status report format as the status report format by: determining that at least one LCG has data available for transmission and that none of the LCGs in at least one LCG have delay information for at least one LCG available for transmission, wherein the delay information indicates the remaining time of the PDCP discard timer.

[0036] In some implementations, the UE is configured to determine the second status report format as the status report format by: determining that at least one LCG has data available for transmission and that none of the LCGs in at least one LCG are configured to report delay information for at least one LCG available for transmission, wherein the delay information indicates the remaining time of the PDCP discard timer.

[0037] In some implementations, the UE is configured to determine the second status report format as the status report format by: determining that the uplink grant is insufficient to accommodate the first status report format but sufficient to accommodate the second status report format, the first status report format including a first field and a second field, the second field being associated with delay information for at least one LCG, the delay information indicating the remaining time of the PDCP discard timer.

[0038] In some implementations, at least one LCG includes a first LCG and a second LCG, the first LCG having a first priority equal to the second priority of the second LCG, the first LCG having delay information available for transmission, and the second LCG not having delay information available for transmission; and the UE is configured to send at least one BSR by: determining that the uplink grant is insufficient to accommodate a first status report format, and reporting at least one BSR for the first LCG and the second LCG in the order of the first LCG and the second LCG.

[0039] It should be understood that the summary section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0040] Figure 1 An example of a wireless communication system supporting cache status reporting according to various aspects of this disclosure is illustrated;

[0041] Figure 2 The diagram illustrates a flowchart of a method for supporting cache state reporting according to some aspects of this disclosure;

[0042] Figure 3 Examples of delay information generation and reporting according to some implementations of this disclosure are illustrated;

[0043] Figure 4 The diagram illustrates a flowchart of a method for determining the first delay information according to various aspects of this disclosure;

[0044] Figure 5 Examples of delay information generation and reporting according to some implementations of this disclosure are illustrated;

[0045] Figure 6 The diagram illustrates a flowchart of a method for determining the second delay information according to various aspects of this disclosure;

[0046] Figure 7 The diagram illustrates a flowchart of a method for reporting second delay information according to various aspects of this disclosure;

[0047] Figure 8The diagram illustrates a flowchart of a method for reporting supporting first delay information according to various aspects of this disclosure;

[0048] Figure 9 Examples of delay information generation and reporting according to some implementations of this disclosure are illustrated;

[0049] Figure 10 The diagram illustrates a flowchart of a method for determining third delay information according to various aspects of this disclosure;

[0050] Figure 11 The diagram illustrates a flowchart of a method for reporting third-party delay information according to various aspects of this disclosure;

[0051] Figure 12 A flowchart illustrating a method for determining the support status report format according to various aspects of this disclosure is provided.

[0052] Figure 13 The illustration shows an example of a device that supports cache state reporting according to some aspects of this disclosure;

[0053] Figure 14 An example of a device supporting the reporting of first delay information according to other aspects of this disclosure is illustrated;

[0054] Figure 15 An example of a device defined according to a support status report format in accordance with other aspects of this disclosure is illustrated;

[0055] Figure 16 An example of a processor that supports cache status reporting according to various aspects of this disclosure is illustrated;

[0056] Figure 17 The illustration shows an example of a processor supporting the determination of first delay information according to various aspects of this disclosure; and

[0057] Figure 18 An example of a processor defined according to the support status report format of various aspects of this disclosure is illustrated. Detailed Implementation

[0058] The principles of this disclosure will now be described with reference to some embodiments. It should be understood that these embodiments are described for illustrative purposes only and to assist those skilled in the art in understanding and implementing this disclosure, and do not imply any limitation on the scope of this disclosure. The disclosure described herein can be implemented in various ways other than those described below.

[0059] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0060] References to "an embodiment," "example embodiment," "embodiment," and "some embodiments," etc., in this disclosure indicate that the described embodiments(s) may include specific features, structures, or characteristics, but not every embodiment necessarily includes such specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same(s) embodiments(s). Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, it is assumed that in conjunction with other embodiments (whether explicitly described or not) affecting such a feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0061] It should be understood that although the terms “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may also be referred to as a second element without departing from the scope of the embodiments, and similarly, a second element may also be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the listed terms.

[0062] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” used herein also include the plural forms only. It will be further understood that the terms “comprises,” “comprising,” “has,” “having,” “includes,” and / or “including,” when used herein, specify the presence of the described features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0063] As mentioned above, in some cases, it is not feasible to reuse a padded BSR with a cache size of zero as an implicit EoDB indicator for the RAN.

[0064] In the first case, if more than one LCG has data available for transmission, and the uplink (UL) grant is insufficient to accommodate a long-filled BSR but sufficient to accommodate a short-truncated BSR (which is truncated for the LCG with the highest priority logical channel available for transmission), then the base station cannot determine whether the buffer size of the LCG is equal to zero or not equal to zero.

[0065] For example, a UE has LCG#1, LCG#2, and LCG#3. The buffer size for LCG#1 and LCG#3 is greater than zero, and the buffer size for LCG#2 is equal to zero. LCG#1 has a higher priority than LCG#2, and the priority of LCG#2 is equal to the priority of LCG#3. If a truncated BSR is used, the truncated BSR only includes the buffer size for LCG#1 that is greater than zero. In this case, upon receiving the truncated BSR, the base station cannot determine whether the buffer sizes for LCG#2 and LCG#3 are equal to or not equal to zero.

[0066] In the second case, if the UL authorization is insufficient to accommodate any additional padding BSR Media Access Control (MAC) Control Element (CE) and MAC CE subheaders, then no padding BSR is triggered.

[0067] In the third case, if the UL grant is insufficient to accommodate the triggered BSR, then if all triggered BSRs can be cancelled, all triggered BSRs can be cancelled if at least one UL grant is sufficient to accommodate all pending data available for transmission, but insufficient to accommodate the additional BSR MAC CE and MAC CE subheaders.

[0068] In view of the above, this disclosure provides a solution supporting cache status reporting. In this solution, the UE determines whether uplink data belonging to at least one logical channel of at least one LCG has become unavailable to the UE's MAC entity. If the UE determines that uplink data has become unavailable, the UE triggers at least one first BSR for at least one logical channel or for at least one LCG. Each of the at least one first BSR indicates that the first cache size of one of the at least one LCG is equal to zero. In this way, the base station can determine that the cache size of at least one logical channel or at least one LCG has become zero.

[0069] Various aspects of this disclosure are described in the context of a wireless communication system.

[0070] Figure 1An example of a wireless communication system 100 supporting cached state reporting according to various aspects of this disclosure is illustrated. The wireless communication system 100 may include at least one network entity 102 (also referred to as a network device (NE)), one or more terminal devices or UEs 104, a core network 106, and a packet data network 108. The wireless communication system 100 may support various wireless access technologies. In some implementations, the wireless communication system 100 may be a 4G network, such as an LTE network or an LTE-A network. In some other implementations, the wireless communication system 100 may be a 5G network, such as an NR network. In other implementations, the wireless communication system 100 may be a combination of 4G and 5G networks, or other suitable wireless access technologies, including IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), and IEEE 802.20. The wireless communication system 100 may support wireless access technologies beyond 5G. Additionally, the wireless communication system 100 may support technologies such as Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), or Code Division Multiple Access (CDMA).

[0071] Network entity 102 can be collectively referred to as network entity 102, or it can be referred to as network entity 102 alone.

[0072] Network entities 102 can be distributed throughout a geographic area to form a wireless communication system 100. One or more network entities 102 described herein can be, include, or may be referred to as network nodes, base stations (BS), network elements, radio access network (RAN) nodes, base transceiver stations, access points, NodeBs, eNodeBs (eNBs), next-generation NodeBs (gNBs), or other suitable terms. Network entities 102 and UE 104 can communicate via communication link 110, which can be a wireless or wired connection. For example, network entities 102 and UE 104 can perform wireless communication (e.g., receiving signaling, sending signaling) via a Uu interface.

[0073] Network entity 102 can provide a geographic coverage area 112 for which it can support services (e.g., voice, video, packet data, messaging, broadcasting, etc.) for one or more UEs 104 within the geographic coverage area 112. For example, network entity 102 and UE 104 can support wireless communication of signals associated with services (e.g., voice, video, packet data, messaging, broadcasting, etc.) based on one or more radio access technologies. In some implementations, network entity 102 can be mobile, for example, a satellite associated with a non-terrestrial network. In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies can overlap, but different geographic coverage areas 112 can be associated with different network entities 102. The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0074] One or more UEs 104 may be distributed throughout the geographic area of ​​the wireless communication system 100. UE 104 may include or be referred to as a mobile device, wireless device, remote device, remote unit, handheld device, or subscriber device, or some other suitable term. In some implementations, UE 104 may be referred to as a unit, station, terminal, or client, etc. Additionally or alternatively, UE 104 may be referred to as an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a Machine Type Communication (MTC) device, etc. In some implementations, UE 104 may be stationary within the wireless communication system 100. In some other implementations, UE 104 may be mobile within the wireless communication system 100.

[0075] One or more UEs 104 can be devices in different forms or with different capabilities. Figure 1 The diagram illustrates some examples of UE 104. UE 104 can communicate with various types of devices, such as network entity 102, other UEs 104, or network devices (e.g., core network 106, packet data network 108, relay equipment, integrated access and backhaul (IAB) node, or another network device). Figure 1 As shown. Alternatively or additionally, UE 104 may support communication with other network entities 102 or UE 104 that may act as relays in wireless communication system 100.

[0076] UE 104 can also support direct wireless communication with other UE 104s via communication link 114. For example, UE 104 can support direct wireless communication with another UE 104 via a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular V2X deployments, communication link 114 may be referred to as a side link. For example, UE 104 can support direct wireless communication with another UE 104 via a PC5 interface.

[0077] Network entity 102 may support communication with core network 106, or with another network entity 102, or both. For example, network entity 102 may interface with core network 106 via one or more backhaul links 116 (e.g., via S1, N2, N2, or another network interface). Network entities 102 may communicate with each other via backhaul links 116 (e.g., via X2, Xn, or another network interface). In some implementations, network entities 102 may communicate directly with each other (e.g., between network entities 102). In some other implementations, network entities 102 may communicate with each other or indirectly (e.g., via core network 106). In some implementations, one or more network entities 102 may include sub-components, such as access network entities, which may be examples of access node controllers (ANCs). An ANC may communicate with one or more UEs 104 via one or more other access network transport entities (which may be referred to as radio headends, smart radio headends, or transmit-receive points (TRPs)).

[0078] In some implementations, network entity 102 can be configured with a decomposed architecture that can utilize protocol stacks physically or logically distributed across two or more network entities 102, such as an Integrated Access Backhaul (IAB) network, an Open Radio Access Network (O-RAN) (e.g., a network configuration sponsored by the O-RAN Alliance), or a Virtualized RAN (vRAN) (e.g., a Cloud RAN (C-RAN)). For example, network entity 102 may include one or more of the following: a Central Unit (CU), a Distributed Unit (DU), a Radio Unit (RU), a RAN Intelligent Controller (RIC) (e.g., a near-real-time RIC (near RTRIC), a non-real-time RIC (non-RT RIC)), a Service Management and Orchestration (SMO) system, or any combination thereof.

[0079] An RU can also be referred to as a radio headend, intelligent radio headend, remote radio headend (RRH), remote radio unit (RRU), or transmit-receive point (TRP). In a decomposed RAN architecture, one or more components of network entity 102 can be co-located, or one or more components of network entity 102 can be located in distributed locations (e.g., separate physical locations). In some implementations, one or more network entities 102 in a decomposed RAN architecture can be implemented as virtual units (e.g., virtual CU (VCU), virtual DU (VDU), virtual RU (VRU)).

[0080] The functional splitting among CU, DU, and RU can be flexible and can support different functions based on the functions performed at the CU, DU, or RU (e.g., network layer functions, protocol layer functions, baseband functions, radio frequency functions, and any combination thereof). For example, protocol stack functional splitting can be adopted between CU and DU, allowing the CU to support one or more layers of the protocol stack and the DU to support one or more different layers of the protocol stack. In some implementations, the CU can host upper-layer protocol layer (e.g., Layer 3 (L3), Layer 2 (L2)) functions and signaling (e.g., Radio Resource Control (RRC), Serving Data Adaptation Protocol (SDAP), Packet Data Convergence Protocol (PDCP)). The CU can connect to one or more DUs or RUs, and one or more DUs or RUs can host lower-layer protocol layer (e.g., Layer 1 (L1) (e.g., Physical (PHY) layer) or L2 (e.g., Radio Link Control (RLC) layer, Media Access Control (MAC) layer) functions and signaling), and each of them can be at least partially controlled by the CU 160.

[0081] Additionally or alternatively, functional splitting of the protocol stack can be employed between the DU and RU, such that the DU can support one or more layers of the protocol stack and the RU can support one or more different layers of the protocol stack. The DU can support one or more different cells (e.g., via one or more RUs). In some implementations, functional splitting between the CU and DU or between the DU and RU can be within the protocol layer (e.g., some functions of the protocol layer can be performed by one of the CU, DU, or RU, while other functions of the protocol layer are performed by different items in the CU, DU, or RU).

[0082] The CU can be further functionally divided into CU control plane (CU-CP) and CU user plane (CU-UP) functions. The CU can be connected to one or more DUs via mid-range communication links (e.g., F1, F1-c, F1-u), and the DUs can be connected to one or more RUs via fronthaul communication links (e.g., open fronthaul (FH) interfaces). In some implementations, the mid-range or fronthaul communication links can be implemented based on interfaces (e.g., channels) between layers of a protocol stack supported by the corresponding network entity 102 communicating via such communication links.

[0083] Core network 106 can support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. Core network 106 can be an evolved packet core (EPC) or a 5G core (5GC), which may include control plane entities that manage access and mobility (e.g., Mobility Management Entity (MME), Access and Mobility Management Function (AMF)) and user plane entities that route packets or interconnects to external networks (e.g., Serving Gateway (S-GW), Packet Data Network (PDN) Gateway (P-GW), or User Plane Function (UPF)). In some implementations, control plane entities may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signaling bearers, etc.) for one or more UEs 104 served by one or more network entities 102 associated with core network 106.

[0084] Core network 106 can communicate with packet data network 108 via one or more backhaul links 116 (e.g., via S1, N2, N2, or another network interface). Packet data network 108 may include application server 118. In some implementations, one or more UEs 104 may communicate with application server 118. UE 104 may establish a session (e.g., Protocol Data Unit (PDU) session, etc.) with core network 106 via network entity 102. Core network 106 can use the established session (e.g., an established PDU session) to route services (e.g., control information, data, etc.) between UE 104 and application server 118. A PDU session may be an example of a logical connection between UE 104 and core network 106 (e.g., one or more network functions of core network 106).

[0085] In the wireless communication system 100, network entity 102 and UE 104 can use the resources of the wireless communication system 100 (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)) to perform various operations (e.g., wireless communication). In some implementations, network entity 102 and UE 104 can support different resource structures. For example, network entity 102 and UE 104 can support different frame structures. In some implementations (such as in 4G), network entity 102 and UE 104 can support a single frame structure. In some other implementations (such as in 5G and other suitable wireless access technologies), network entity 102 and UE 104 can support various frame structures (i.e., multiple frame structures). Network entity 102 and UE 104 can support various frame structures based on one or more digital schemes.

[0086] The wireless communication system 100 may support one or more digital schemes, and the digital schemes may include subcarrier spacing and cyclic prefixes. A first digital scheme (e.g., μ =0) can be associated with the first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first digital scheme (e.g., ...) associated with the first subcarrier spacing (e.g., 15 kHz) is... μ =0) can utilize one time slot per subframe. The second digital scheme (e.g., μ =1) can be associated with the second subcarrier spacing (e.g., 30 kHz) and the normal cyclic prefix. The third digital scheme (e.g., μ =2) can be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth digital scheme (e.g., μ =3) can be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth digital scheme (e.g., μ =4) can be associated with the fifth subcarrier spacing (e.g., 240 kHz) and the normal cyclic prefix.

[0087] The time intervals of resources (e.g., communication resources) can be organized according to frames (also known as radio frames). Each frame can have a duration, for example, 10 milliseconds (ms). In some implementations, each frame can include multiple subframes. For example, each frame can include 10 subframes, and each subframe can have a duration, for example, 1 ms. In some implementations, each frame can have the same duration. In some implementations, each subframe of a frame can have the same duration.

[0088] Alternatively or concurrently, the time intervals of resources (e.g., communication resources) can be organized according to time slots. For example, a subframe may include a certain number (e.g., quantity) of time slots. The number of time slots in each subframe may also depend on one or more digital schemes supported in the wireless communication system 100. For example, a first digital scheme, a second digital scheme, a third digital scheme, a fourth digital scheme, and a fifth digital scheme (i.e., ...) associated with corresponding subcarrier intervals of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz. μ =0、 μ =1、 μ =2、 μ =3、 μ =4) A single time slot per subframe, two time slots per subframe, four time slots per subframe, eight time slots per subframe, and 16 time slots per subframe can be used, respectively. Each time slot can include a certain number (e.g., quantity) of symbols (e.g., OFDM symbols). In some implementations, the number (e.g., quantity) of time slots in a subframe can depend on the digital scheme. For a normal cyclic prefix, a time slot can include 14 symbols. For an extended cyclic prefix (e.g., for a 60kHz subcarrier spacing), a time slot can include 12 symbols. The relationship between the number of symbols per time slot, the number of time slots per subframe, and the number of time slots per frame for both normal and extended cyclic prefixes can depend on the digital scheme. It should be understood that for a first digital scheme (e.g., quantity) associated with a first subcarrier spacing (e.g., 15kHz), μ The reference of =0 can be used interchangeably between subframes and time slots.

[0089] In the wireless communication system 100, the electromagnetic (EM) spectrum can be divided into various categories, frequency bands, frequency channels, etc., based on frequency or wavelength. For example, the wireless communication system 100 can support one or more operating frequency bands, such as frequency range names FR1 (410MHz-7.125GHz), FR2 (24.25GHz-52.6GHz), FR3 (7.125GHz-24.25GHz), FR4 (52.6GHz-114.25GHz), FR4a or FR4-1 (52.6GHz-71GHz), and FR5 (114.25GHz-300GHz). In some implementations, network entity 102 and UE 104 can perform wireless communication on one or more operating frequency bands. In some implementations, FR1 can be used by network entity 102 and UE 104, as well as other devices or equipment, for cellular communication services (e.g., control information, data). In some implementations, FR2 can be used by network entity 102 and UE 104, as well as other devices or equipment, for short-range, high-data-rate capabilities.

[0090] FR1 can be associated with one or more number schemes (e.g., at least three number schemes). For example, FR1 can be associated with the following: a first number scheme (e.g., μ =0), which includes a 15kHz subcarrier spacing; the second digital scheme (e.g., μ =1), which includes a 30kHz subcarrier spacing; a third digital scheme (e.g., μ =2), which includes a subcarrier spacing of 60 kHz. FR2 can be associated with one or more digital schemes (e.g., at least two digital schemes). For example, FR2 can be associated with a third digital scheme (e.g., μ =2), which includes a 60kHz subcarrier spacing; the fourth digital scheme (e.g., μ =3), which includes a subcarrier spacing of 120kHz.

[0091] Figure 2 A flowchart illustrating a method 200 supporting cached state reporting according to various aspects of this disclosure is shown. Operation of method 200 can be implemented by the device or components thereof described herein. For example, operation of method 200 can be performed by the UE 104 described herein. In some implementations, the device can execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device can use dedicated hardware to perform aspects of the described functions.

[0092] At 210, UE 104 determines whether uplink (UL) data of at least one logical channel (e.g., belonging to at least one LCG) becomes unavailable (e.g., becomes zero) for UE 104's MAC entity. For example, UE 104 determines whether UL data of all at least one logical channel belonging to all at least one LCG becomes unavailable for UE 104's MAC entity. For example, UE 104 determines whether uplink (UL) data of all at least one logical channel belonging to at least one LCG becomes unavailable for UE 104's MAC entity.

[0093] If UE 104 determines that UL data becomes unavailable (e.g., becomes zero), then at 220, UE 104 triggers at least one first BSR for at least one logical channel or for at least one LCG. Each of the at least one first BSR indicates that the first buffer size of one of the at least one LCG is equal to zero.

[0094] If UE 104 determines that UL data becomes unavailable (e.g., becomes zero), then at 220, UE 104 triggers at least one first BSR for at least one logical channel or for at least one LCG, and detects at least one end of at least one data burst for at least one logical channel. Each of the at least one first BSR indicates that the first buffer size of one of the at least one LCG is equal to zero.

[0095] In some implementations, UE 104 can determine that the UL data of at least one logical channel (e.g., belonging to at least one LCG) becomes unavailable to UE 104's MAC entity (e.g., becomes zero) by detecting at least the end of at least one data burst of at least one logical channel. If UE 104 detects at least the end of at least one data burst of at least one logical channel, it means that data available for transmission for at least one LCG has been sent or contained in the UL grant. For example, UE 104 can determine whether the UL data of at least one logical channel belonging to at least one LCG becomes unavailable to UE 104's MAC entity by detecting at least the end of at least one data burst of all at least one logical channel. For example, UE 104 can determine whether the UL data of at least one logical channel belonging to at least one LCG becomes unavailable to UE 104's MAC entity by detecting at least the end of at least one data burst of all at least one logical channel.

[0096] If UE 104 determines that UL data belonging to at least one logical channel of at least one LCG becomes unavailable to UE 104's MAC entity (e.g., becomes zero) and / or detects at least one end of at least one data burst of at least one logical channel, UE 104 may send at least one first BSR to base station 102. Each of the at least one first BSR indicates that the first buffer size of one of the at least one LCG is equal to zero. For example, after determining that UL data belonging to at least one LCG or all at least one logical channel of all at least one LCG becomes unavailable to UE 104's MAC entity, or after detecting at least one end of at least one data burst of at least one logical channel or all at least one logical channel, UE 104 may send at least one first BSR to base station 102.

[0097] If UE 104 triggers a BSR for at least one logical channel belonging to at least one LCG, where the UL data of that logical channel becomes unavailable to UE 104's MAC entity (e.g., becomes zero), and / or detects at least one end of at least one data burst of at least one logical channel, then UE 104 may send at least one first BSR to base station 102. Each of the at least one first BSR indicates that the first buffer size of one of the at least one LCG is equal to zero.

[0098] If base station 102 receives at least one first BSR, base station 102 can determine the end of data burst transmission for at least one logical channel to instruct UE 104 to enter discontinuous reception (DRX) inactive mode to save power for UE 104.

[0099] In some implementations, UE 104 may receive configuration for at least one logical channel from base station 102. UE 104 may determine, based on the configuration for at least one logical channel, whether UL data belonging to at least one LCG becomes unavailable (e.g., becomes zero) to UE 104's MAC entity.

[0100] For example, LCG#1 includes logical channel #1 and logical channel #2. UE 104 receives a first configuration for logical channel #1 from base station 102. The first configuration may indicate that if UL data for logical channel #1 becomes unavailable to UE 104's MAC entity (e.g., becomes zero), UE 104 may trigger a BSR for logical channel #1 or for LCG#1. The BSR indicates that the buffer size for LCG#1 is equal to zero.

[0101] If UE 104 determines that UL data for logical channel #1 becomes unavailable for UE 104's MAC entity, and logical channel #2 has no data available for transmission, then UE 104 can determine that the buffer size of LCG #1 becomes zero. Therefore, UE 104 can trigger a BSR for either logical channel #1 or LCG #1 based on a first configuration. The BSR indicates that the buffer size of LCG #1 is equal to zero.

[0102] In some implementations, UE 104 may receive a second configuration for at least one LCG from base station 102. UE 104 may determine, based on the second configuration, whether UL data belonging to at least one logical channel of at least one LCG becomes unavailable to UE 104's MAC entity, or whether the BSR of at least one logical channel belonging to at least one LCG becomes or equals zero.

[0103] For example, LCG#1 includes logical channel #1 and logical channel #2. UE 104 receives a second configuration for LCG#1 from base station 102. The configuration for logical channel #1 can indicate that if the buffer size of LCG#1 becomes zero, UE 104 can trigger a BSR for LCG#1. The BSR indicates that the buffer size of LCG#1 is equal to zero.

[0104] If UE 104 determines that UL data on logical channel #1 becomes unavailable for UE 104's MAC entity, and logical channel #2 has no data available for transmission, then UE 104 can determine that the buffer size of LCG #1 becomes zero. Therefore, UE 104 can trigger a BSR for LCG #1 based on the second configuration. The BSR indicates that the buffer size of LCG #1 is equal to zero.

[0105] In some implementations, each of the at least one first BSR may include a dedicated BSR. For example, each of the at least one first BSR may be a new BSR separate from the conventional BSR. The conventional BSR may include a regular BSR, a periodic BSR, or a filler BSR.

[0106] In some implementations, a new BSR can be identified by a MAC subheader with an LCID, as specified in Table 6.2.1-2 of TS 38.321. This LCID comes from a specific LCID allocated in a reserved index for the new BSR. Table 1 provides examples of LCID values ​​for new BSRs. Table 1

[0107] Alternatively, in some implementations, each of the at least one first BSR may include a conventional BSR. A conventional BSR may include a regular BSR or a padded BSR.

[0108] For example, if UE 104 triggers a regular BSR, the BSR should be triggered if any of the following events occur: - For a logical channel belonging to an LCG or all (multiple) LCGs or all logical channels, and optionally, for that logical channel, it is configured to trigger a BSR when the amount of data available for transmission becomes zero, and UL data becomes unavailable for the MAC entity; In this context, BSR will be referred to as "regular BSR" below; - For a logical channel belonging to an LCG or all (or more) LCGs, or all logical channels, and optionally, for that logical channel, it is configured to trigger a BSR when the amount of data available for transmission becomes zero. retxBSR-TimerIf a BSR becomes unavailable to a MAC entity upon expiration, in this case, the BSR will be referred to as a "regular BSR" below.

[0109] For example, if UE 104 triggers a regular BSR, the BSR should be triggered if any of the following events occur: - The UE detects the end of a data burst for a logical channel belonging to an LCG or all (multiple) LCGs or for all logical channels; In this context, BSR will be referred to as "regular BSR" below; - For a logical channel belonging to an LCG or all (or more) LCGs, or all logical channels, and optionally, for that logical channel, it is configured to trigger a BSR when the amount of data available for transmission becomes zero. retxBSR-Timer When the data burst expires and the UE detects the end of the data burst, the BSR is referred to as "regular BSR" below.

[0110] In some implementations, if UE 104 determines that only one first LCG has data available for transmission, UE 104 may send a second BSR for the first LCG to base station 102 in a short BSR format. The second BSR includes a second buffer size equal to or greater than zero. For example, the first LCG may be included in at least one LCG, as described above. Alternatively, the first LCG may be separate from at least one LCG, as described above.

[0111] In some implementations, if UE 104 determines that none of the at least one LCG has data available for transmission, UE 104 may send a second BSR for one of the at least one LCG to base station 102 in a short BSR format. The second BSR includes a second buffer size equal to zero.

[0112] In some implementations, the second BSR may include one of the following: a regular BSR, a periodic BSR, or a filler BSR.

[0113] For example, if UE 104 triggers a regular BSR or a periodic BSR, and if UE 104 triggers a padding BSR, and if no LCG has data available for transmission, UE 104 will still report a regular BSR to base station 104 to indicate that the buffer size for UE 104 is equal to 0. The LCG ID in the BSR can be any LCG ID assigned to UE 104 or a special value different from the LCG. For example, the content determination and reporting of a regular BSR can be the following underlined text. For both regular and periodic BSRs, the MAC entity should: 1> If, when a MAC PDU containing a BSR is constructed, more than one LCG has data available for transmission, then: 2> The report is for the long BSR of all LCGs with data available for transmission. 1> Otherwise, if only one LCG has data available for transmission when the BSR is constructed, then: 2> Report a short BSR of the LCG with data that can be used for transmission. 1> Otherwise (if no LCG has data available for transmission when the BSR is constructed), then: 2> Report a short BSR.

[0114] For example, if UE 104 triggers a fill BSR, and no LCG has data available for transmission, UE 104 will still report a fill BSR to indicate that the buffer size for UE 104 is equal to 0. The LCGID in truncated BSR format or short BSR format can be any LCG ID, or the LCG ID of at least one LCG, or a special value different from the LCG assigned to UE 104. For example, the fill BSR content determination and reporting can be as follows (underlined text). For filling BSRs, the MAC entity should: 1> If the number of padding bits is equal to or greater than the size of the short BSR plus its subheading, but less than the size of the long BSR plus its subheading, then: 2> If, at the time the BSR is constructed, more than one LCG has data available for transmission, then: 3> If the number of padding bits is equal to the short BSR plus the size of its subheading, then: 4> Report a short-truncated BSR of the LCG with the highest priority logical channel that can be used for data transmission. 3> Otherwise: 4> In each of these (multiple) LCGs, the highest priority logical channels (with or without data available for transmission) are ordered in descending order, and in the case of equal priorities, the long truncated BSRs of the (multiple) LCGs with logical channels available for transmission are reported in ascending order of LCG ID. 2> Otherwise, if only one LCG has data available for transmission when the BSR is constructed, then: 3> Report a short BSR of the LCG with data that can be used for transmission. 2> Otherwise (if no LCG has data available for transmission when the BSR is constructed), then 3> Report a short BSR. 1> Otherwise, if the number of padding bits is equal to or greater than the length of the BSR plus the size of its subheading, then: 2> The report is for the long BSR of all LCGs with data available for transmission.

[0115] In some implementations, the format of at least one first BSR can be a special BSR format (e.g., a new BSR format) or a traditional BSR format. Traditional BSRs can include long BSR formats, long truncated BSR formats, and short BSR formats.

[0116] In some implementations, the dedicated BSR format may not include MAC CE content, meaning that only the MAC subheader with a specific LCID is included.

[0117] In some implementations, BSR triggering enhancement can be performed. In BSR triggering enhancement, if UE 104 determines that UL data for at least one logical channel or UL data for at least one LCG becomes unavailable to UE 104's MAC entity (e.g., becomes zero), and determines that no triggered third BSR indicates that the first buffer size is equal to zero, then UE 104 can trigger at least one first BSR for at least one logical channel or for at least one LCG. The at least one logical channel can be in at least one LCG. Each of the at least one first BSR indicates that the first buffer size of one of the at least one LCG is equal to zero.

[0118] In some implementations, the fact that UL data for at least one logical channel becomes unavailable to the UE's MAC entity means that the amount of data available for transmission on at least one logical channel becomes 0 or equal to 0 after the MAC PDU is constructed. Similarly, the fact that UL data for at least one LCG becomes unavailable to the UE's MAC entity means that the amount of data available for transmission on the LCG becomes 0 or equal to 0.

[0119] In some implementations, the triggered third BSR may include a filling BSR, a regular BSR, or a periodic BSR.

[0120] For example, a UE has LCG#1, LCG#2, and LCG#3. The buffer size for LCG#1 and LCG#3 is greater than zero, and the buffer size for LCG#2 is equal to zero. LCG#1 has a higher priority than LCG#2, and the priority of LCG#2 is equal to that of LCG#3. UE 104 triggers a padding BSR, and the padding BSR uses a truncated BSR format. In the truncated format, the triggered padding BSR only includes the buffer size of LCG#1 that is greater than zero. In this case, upon receiving the padding BSR, base station 120 cannot determine whether the buffer size for LCG#2 and LCG#3 is equal to zero or not. Therefore, the untriggered BSR indicates that the buffer size of LCG#2 is equal to zero. If UE 104 determines that UL data belonging to at least one logical channel of LCG#2 becomes unavailable for UE 104's MAC entity, UE 104 may trigger a BSR for at least one logical channel or for LCG#2. BSR indicates that the cache size of LCG#2 is zero.

[0121] In some implementations, UE 104 can receive configuration for BSR triggering enhancement from base station 102. Then, UE 104 can trigger at least one first BSR for at least one logical channel or for at least one LCG based on this configuration.

[0122] In some implementations, BSR cancellation enhancement can be performed. In BSR cancellation enhancement, UE 104 has determined that UL data for at least one logical channel or UL data for at least one LCG has become unavailable, and has triggered at least one first BSR for at least one logical channel or at least one LCG. If the UL grant is sufficient to accommodate all pending data available for transmission, but insufficient to additionally accommodate the MAC CE and its subheading, UE 104 will not cancel the triggered at least one first BSR. The MAC CE includes the triggered at least one first BSR.

[0123] In some implementations, BSR cancellation enhancement can be performed. In BSR cancellation enhancement, UE 104 has determined that UL data for all at least one logical channel or UL data for all at least one LCG has become unavailable, and has triggered at least one first BSR for all at least one logical channel or for all at least one LCG. All at least one logical channel may be included in at least one LCG. If the UL grant is sufficient to accommodate all pending data available for transmission, but insufficient to additionally accommodate the MAC CE and its sub-header, then UE 104 will not cancel the triggered at least one first BSR. The MAC CE includes the triggered at least one first BSR.

[0124] For example, if it is not necessary for any of the at least one LCG or any of the at least one logical channel to report a buffer size equal to or reduced to 0, then all triggered BSRs can be cancelled when the (multiple) UL grants are able to accommodate all pending data available for transmission, but are insufficient to accommodate additional BSR MAC CEs plus their subheadings.

[0125] In some implementations, UE 104 can receive a BSR cancellation enhancement configuration from base station 102. Therefore, UE 104 can cancel at least one first BSR triggered for at least one logical channel or for at least one LCG without relying on the configuration.

[0126] In some implementations, if at least one first BSR includes at least one dedicated BSR (e.g., a new BSR), then the priority between the dedicated BSR and the traditional BSR should be specified.

[0127] In some implementations, at least one dedicated BSR has a first priority higher than the second priority of a regular or periodic BSR. In other words, at least one dedicated BSR has a first priority higher than the second priority of a BSR, except for BSRs included for filling purposes.

[0128] For example, logical channels should be prioritized in the following order (highest priority listed first): - C-RNTI MAC CE or data from UL-CCCH; - Configure authorization confirmation MAC CE or MAC CE for BFR or multi-entry configuration authorization confirmation MAC CE; - Side link configuration authorization confirmation MAC CE; - LBT failure MAC CE; - MAC CE for scheduled advance reporting; - MAC CE for SL-BSRs given priority under Clause 5.22.1.6; - MAC CE for dedicated BSRs (e.g., new BSRs) ; - MAC CE for BSR, except for BSR used for filling; - Single-entry PHR MAC CE or multi-entry PHR MAC CE; - MAC CE for the number of symbols to be protected; - MAC CE for preemptive BSR; - MAC CE for SL-BSR, excluding SL-BSRs given priority under Clause 5.22.1.6 and SL-BSRs included for filling; - Data from any logical channel, except for data from UL-CCCH; - MAC CE for recommending bitrate queries; - MAC CE for inclusion in the BSR used for filling; - MAC CE for inclusion in the SL-BSR used for filling.

[0129] In some implementations, the first priority of at least one dedicated BSR is equal to the second priority of a regular or periodic BSR. In other words, the first priority of at least one dedicated BSR is equal to the second priority of a BSR, except for BSRs included for padding. The UE implementation determines which BSR to report from the two BSRs; that is, the priority between the two MAC CEs depends on the UE implementation.

[0130] For example, logical channels should be prioritized in the following order (highest priority listed first): - C-RNTI MAC CE or data from UL-CCCH; - Configure authorization confirmation MAC CE or MAC CE for BFR or multi-entry configuration authorization confirmation MAC CE; - Side link configuration authorization confirmation MAC CE; - LBT failure MAC CE; - MAC CE for scheduled advance reporting; - MAC CE for SL-BSRs given priority under Clause 5.22.1.6; - MAC CE for BSR, excluding BSR for filling, or For use in dedicated BSRs (e.g., new BSRs) MAC CE ; - Single-entry PHR MAC CE or multi-entry PHR MAC CE; - MAC CE for the number of symbols to be protected; - MAC CE for preemptive BSR; - MAC CE for SL-BSR, excluding SL-BSRs given priority under Clause 5.22.1.6 and SL-BSRs included for filling; - Data from any logical channel, except for data from UL-CCCH; - MAC CE for recommending bitrate queries; - MAC CE for inclusion in the BSR used for filling; - MAC CE for inclusion in the SL-BSR used for filling.

[0131] In some implementations, the first priority of at least one dedicated BSR is lower than the second priority of a regular BSR or a periodic BSR. In other words, the first priority of at least one dedicated BSR is lower than the second priority of a BSR, except for BSRs included for filling purposes.

[0132] In some implementations, the first priority of at least one dedicated BSR is higher than the priority of data from any logical channel, except for data from UL-CCCH;

[0133] For example, logical channels should be prioritized in the following order (highest priority listed first): - C-RNTI MAC CE or data from UL-CCCH; - Configure authorization confirmation MAC CE or MAC CE for BFR or multi-entry configuration authorization confirmation MAC CE; - Side link configuration authorization confirmation MAC CE; - LBT failure MAC CE; - MAC CE for scheduled advance reporting; - MAC CE for SL-BSRs given priority under Clause 5.22.1.6; - MAC CE for BSR, except for BSR used for filling; - MAC CE for dedicated BSRs (e.g., new BSRs) ; - Single-entry PHR MAC CE or multi-entry PHR MAC CE; - MAC CE for the number of symbols to be protected; - MAC CE for preemptive BSR; - MAC CE for SL-BSR, excluding SL-BSRs given priority under Clause 5.22.1.6 and SL-BSRs included for filling; - Data from any logical channel, except for data from UL-CCCH; - MAC CE for recommending bitrate queries; - MAC CE for inclusion in the BSR used for filling; - MAC CE for inclusion in the SL-BSR used for filling.

[0134] In some implementations, the first priority of at least one dedicated BSR is lower than the priority of data from any logical channel, except for data from UL-CCCH;

[0135] In some implementations, the first priority of at least one dedicated BSR is higher than the second priority of the filling BSR.

[0136] For example, logical channels should be prioritized in the following order (highest priority listed first): - C-RNTI MAC CE or data from UL-CCCH; - Configure authorization confirmation MAC CE or MAC CE for BFR or multi-entry configuration authorization confirmation MAC CE; - Side link configuration authorization confirmation MAC CE; - LBT failure MAC CE; - MAC CE for scheduled advance reporting; - MAC CE for SL-BSRs given priority under Clause 5.22.1.6; - MAC CE for BSR, except for BSR used for filling; - Single-entry PHR MAC CE or multi-entry PHR MAC CE; - MAC CE for the number of symbols to be protected; - MAC CE for preemptive BSR; - MAC CE for SL-BSR, excluding SL-BSRs given priority under Clause 5.22.1.6 and SL-BSRs included for filling; - Data from any logical channel, except for data from UL-CCCH; - MAC CE for recommending bitrate queries; - MAC CE for dedicated BSRs (e.g., new BSRs) ; - MAC CE for inclusion in the BSR used for filling; - MAC CE for inclusion in the SL-BSR used for filling.

[0137] In some implementations, the first priority of at least one dedicated BSR is equal to the second priority of the filling BSR. The UE implementation is responsible for selecting which BSR to report from the two BSRs; that is, the priority between the two MAC CEs depends on the UE implementation.

[0138] For example, logical channels should be prioritized in the following order (highest priority listed first): - C-RNTI MAC CE or data from UL-CCCH; - Configure authorization confirmation MAC CE or MAC CE for BFR or multi-entry configuration authorization confirmation MAC CE; - Side link configuration authorization confirmation MAC CE; - LBT failure MAC CE; - MAC CE for scheduled advance reporting; - MAC CE for SL-BSRs given priority under Clause 5.22.1.6; - MAC CE for BSR, except for BSR used for filling; - Single-entry PHR MAC CE or multi-entry PHR MAC CE; - MAC CE for the number of symbols to be protected; - MAC CE for preemptive BSR; - MAC CE for SL-BSR, excluding SL-BSRs given priority under Clause 5.22.1.6 and SL-BSRs included for filling; - Data from any logical channel, except for data from UL-CCCH; - MAC CE for recommending bitrate queries; - For use with MAC CE included in the BSR for filling, or MAC for dedicated BSRs (e.g., new BSRs) CE ; - MAC CE for inclusion in the SL-BSR used for filling.

[0139] In some implementations, the first priority of at least one dedicated BSR is lower than the second priority of the filling BSR.

[0140] For example, logical channels should be prioritized in the following order (highest priority listed first): - C-RNTI MAC CE or data from UL-CCCH; - Configure authorization confirmation MAC CE or MAC CE for BFR or multi-entry configuration authorization confirmation MAC CE; - Side link configuration authorization confirmation MAC CE; - LBT failure MAC CE; - MAC CE for scheduled advance reporting; - MAC CE for SL-BSRs given priority under Clause 5.22.1.6; - MAC CE for BSR, except for BSR used for filling; - Single-entry PHR MAC CE or multi-entry PHR MAC CE; - MAC CE for the number of symbols to be protected; - MAC CE for preemptive BSR; - MAC CE for SL-BSR, excluding SL-BSRs given priority under Clause 5.22.1.6 and SL-BSRs included for filling; - Data from any logical channel, except for data from UL-CCCH; - MAC CE for recommending bitrate queries; - MAC CE for inclusion in the BSR used for filling; - MAC CE for dedicated BSRs (e.g., new BSRs) ; - MAC CE for inclusion in the SL-BSR used for filling.

[0141] It should be noted that the priority between BFR configuration authorization confirmation MAC CE, multi-entry configuration authorization confirmation MAC CE, and MAC CE depends on the UE implementation.

[0142] In some implementations, BSRs can be reported per logical channel. If UE 104 determines that UL data for at least one logical channel or all of at least one logical channel becomes unavailable to UE 104's MAC entity, then at 220, UE 104 triggers at least one first BSR for at least one logical channel. Each of the at least one first BSR indicates that the first buffer size of one of the at least one logical channel is equal to zero.

[0143] In some implementations, UE 104 can determine that UL data for at least one logical channel or all at least one logical channel (e.g., belonging to at least one LCG or all at least one LCG) becomes unavailable to UE 104's MAC entity by detecting at least one end of at least one data burst of at least one logical channel or all at least one logical channel. If UE 104 detects at least one end of at least one data burst of at least one logical channel or all at least one logical channel, it means that data available for transmission for at least one logical channel has been sent or contained in the UL authorization.

[0144] Upon determining that UL data for at least one logical channel becomes unavailable to the MAC entity of UE 104, or upon detecting at least one termination of at least one data burst in at least one logical channel or all at least one logical channel, UE 104 may send at least one first BSR to base station 102. Each of the at least one first BSR indicates that the first buffer size of one of the at least one logical channel is equal to zero. In some implementations, delay reports, including delay information, can be de-prioritized due to intra-UE priorities. In such implementations, consideration needs to be given to how delay reports are processed to ensure that the base station can determine the correct reference time for the delay information using autonomous transmission grants. This will refer to... Figure 3 Describe it.

[0145] Figure 3 Examples of delay information generation and reporting according to some implementations of this disclosure are illustrated. Figure 3 As shown, the UE can trigger a delay information report at T1 and generate a MAC CE including the delay information at T2. The delay information indicates the remaining time of the Packet Data Convergence Protocol (PDCP) discard timer. The UE can determine the reference time for the delay information as T3. When the base station receives this MAC PDU, the base station determines the reference time for the delay information as T3. However, if the UE's physical layer discards the Configuration Grant (CG) at T3 due to a higher-priority PHY index UL transmission, the UE can use subsequent CG resources through the same HARQ procedure to perform at least one autonomous transmission of the MAC PDU, retrieved from the same HARQ procedure of a previously downgraded grant. The autonomous transmission grant can be downgraded multiple times. When the base station receives this MAC PDU, the base station cannot determine the reference time for the delay information as T3. Therefore, the base station cannot accurately determine the remaining time of the PDCP discard timer.

[0146] In view of the above, this disclosure provides a solution supporting delay information reporting. In this solution, the UE determines a first CG for autonomous transmission of delay information. The delay information indicates the remaining time of the PDCP discard timer. The UE determines the first time point of autonomous transmission as a first reference time. Furthermore, the UE determines the delay information based on the value of the PDCP discard timer and the first reference time.

[0147] Figure 4A flowchart illustrating a method 400 for determining first delay information according to various aspects of this disclosure is shown. Operation of method 400 may be implemented by the device or components thereof described herein. For example, operation of method 400 may be performed by the UE 104 described herein. In some implementations, the device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the described functions.

[0148] At 410, UE 104 determines the first CG for autonomous transmission of the first delay information. The first delay information indicates the first remaining time of the PDCP discard timer.

[0149] In some implementations, delay information can correspond to data volume information. For example, delay information can indicate the remaining time of a PDCP drop timer for at least one PDCP Service Data Unit (SDU), at least one set of PDUs, or at least one data burst of an LCG or logical channel with data available for transmission. The remaining time of the Packet Data Convergence Protocol (PDCP) drop timer can be the shortest value of available data for transmission of an LCG or logical channel. In this case, at most one delay information corresponds to a logical channel or LCG. In another case, a logical channel or LCG can have more than one delay information indicating the remaining time of a PDCP drop timer for (multiple) different PDCP Service Data Units (SDUs), (multiple) different sets of PDUs, or (multiple) different data bursts of an LCG or logical channel with data available for transmission.

[0150] At position 420, UE 104 determines the first time point of autonomous transmission as the first reference time.

[0151] At 430, UE 104 determines the first delay information based on the value of the PDCP discard timer and the first reference time.

[0152] By means of method 400, upon receiving the first delay information, the base station 102 can accurately determine the remaining time of the PDCP discard timer.

[0153] In some implementations, the autonomous transmission of the first delayed information can immediately follow the initial transmission of the second delayed information. This will refer to... Figure 5 , Figure 6 and Figure 7 Describe it.

[0154] Figure 5 Examples of delay information generation and reporting according to some implementations of this disclosure are illustrated. Figure 5As shown, at T1, UE 104 triggers the reporting of second delay information. Furthermore, UE 104 can determine the second delay information by executing method 600, which will be described below.

[0155] Figure 6 A flowchart illustrating a method 600 for determining second delay information according to various aspects of this disclosure is shown. Operation of method 600 may be implemented by the device or components thereof described herein. For example, operation of method 600 may be performed by the UE 104 described herein. In some implementations, the device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the described functions.

[0156] At 610, UE 104 determines a second CG (such as...) for the initial transmission of the second delay information. Figure 5 (CG#2 in the original text). The second delay information indicates the second remaining time of the PDCP discard timer.

[0157] At position 620, UE 104 determines the second time point of the initial transmission as the second reference time. For example, in Figure 5 In the example, the second time point of the initial transmission is T3. Therefore, UE 104 determines T3 as the second reference time.

[0158] At 630, UE 104 determines the second delay information based on the value of the PDCP discard timer and the second reference time. For example, UE 104 may generate the second delay information based on the value of the PDCP discard timer and the second reference time.

[0159] In some implementations, in order to report the second delay information to base station 102, UE 104 may execute method 700, which will be described below.

[0160] Figure 7 A flowchart illustrating a method 700 for reporting second delay information according to various aspects of this disclosure is shown. Operation of method 700 may be implemented by the device or components thereof described herein. For example, operation of method 700 may be performed by the UE 104 described herein. In some implementations, the device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the described functions.

[0161] At point 710, UE 104 generates a MAC PDU that includes the second delay information. For example, UE 104 can generate a MAC PDU that includes the second delay information at point T2, such as... Figure 5 As shown.

[0162] At 720, UE 104 will use the MAC PDU and the second CG (such as...) Figure 5 The CG#2 in the middle is delivered to the identified Hybrid Automatic Repeat Request (HARQ) process.

[0163] At 730, UE 104 instructs the HARQ procedure to initiate the first new transmission of the MAC PDU.

[0164] In some implementations, the second CG (such as Figure 5 CG#2 in the list can be lowered in priority. In other words, the second CG can be disregarded.

[0165] For example, for those configured with lch-based Prioritization If a CG's corresponding PUSCH transmission is canceled by a Cancellation Indicator Radio Network Temporary Identifier (CI-RNTI), or by a high PHY priority PUCCH or PUSCH transmission, then the CG is considered a lower priority CG.

[0166] In this implementation, if the second CG (such as...) Figure 5 If CG#2 in the code is downgraded, then in Figure 7 At position 740, UE 104 cancels the first new transmission of the MAC PDU, which includes the second delay information. For example, in Figure 5 The first new transmission at T3 in the process is cancelled. Then, the physical layer of UE 104 can notify the MAC layer of UE 104 of the cancelled transmission of the CG with lower priority.

[0167] In some implementations, if the trigger report for the second delay information has not yet been cancelled, UE 104 can determine the first delay information by executing method 400 as described above.

[0168] For example, in Figure 5 In the example, UE 104 determines a first CG (such as) for the autonomous transmission of first delay information. Figure 5 (CG#1 in the original text). The first delay information indicates that the PDCP discards the first remaining time of the timer.

[0169] Furthermore, UE 104 determines the first time point of autonomous transmission as the first reference time. For example, in Figure 5 In the example, the first time point of the initial transmission is T4. Therefore, UE 104 determines T4 as the first reference time.

[0170] Furthermore, UE 104 determines the first delay information based on the value of the PDCP discard timer and the first reference time (such as T4).

[0171] In some implementations, if the report triggered for the second delay information has been cancelled, UE 104 may trigger a second report for the first delay information for use via the first CG (such as...). Figure 5 The CG#1 in the middle is transmitted autonomously.

[0172] In some implementations, in order to report the first delay information to base station 102, UE 104 may execute method 800, which will be described below.

[0173] Figure 8 A flowchart illustrating a method 800 for reporting first delay information according to various aspects of this disclosure is shown. Operation of method 800 may be implemented by the device or components thereof described herein. For example, operation of method 800 may be performed by the UE 104 described herein. In some implementations, the device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the described functions.

[0174] At 810, if UE 104 determines that no PUSCH transmission in at least one Physical Uplink Shared Channel (PUSCH) transmission of the MAC PDU has been fully executed, then UE 104 retrieves the PUSCH from the first CG (such as...). Figure 5 The MAC PDU is obtained during the HARQ process identified by CG#1 in the CG. Alternatively, if UE 104 determines in the first CG (such as CG#1) Figure 5 The second CG before CG#1 (such as...) Figure 5 If CG#2 in the first CG is downgraded in priority, then UE 104 will be removed from the HARQ procedure identified by the first CG (such as...). Figure 5 Obtain the MAC PDU from CG#1.

[0175] At 820, UE 104 updates the MAC PDU using the first delay information.

[0176] For example, if the configuration grant corresponding to the HARQ procedure is configured with autonomous transmission (Tx), and in the BWP, the previous configuration grant for the HARQ procedure is downgraded; and if delay information has been included in the MACPDU for transmission under the configuration grant through the HARQ procedure, but has not yet been sent by the lower layer, the UE implementation is responsible for how to handle the delay information content (e.g., updating the delay information based on the reference time from the autonomous transmission CG point).

[0177] For example, if the HARQ procedure is configured with cg-RetransmissionTimerFurthermore, if the delay information has been included in the MAC PDU for transmission under configuration authorization via the HARQ procedure, but has not yet been sent by the lower layer, the UE is responsible for how to handle (e.g., update) the delay information content.

[0178] At 830, UE 104 sends a MAC PDU to base station 102.

[0179] In some implementations, in order to send a MAC PDU to base station 102, UE 104 may deliver the MAC PDU and a first CG to the identified HARQ procedure. Furthermore, UE 104 may instruct the HARQ procedure to initiate a third new transmission of the MAC PDU to base station 102.

[0180] Alternatively, in some implementations, the autonomous transmission of the first delayed information may immediately follow the previous autonomous transmission of the third delayed information. This will refer to... Figure 9 , Figure 10 and Figure 11 Describe it.

[0181] Figure 9 Examples of delay information generation and reporting according to some implementations of this disclosure are illustrated. Figure 9 As shown, at T1, UE 104 triggers the reporting of the second delay information. Furthermore, UE 104 can determine the second delay information by executing method 600 as described above.

[0182] In some implementations, in order to report the second delay information to base station 102, UE 104 may perform method 700 as described above.

[0183] In some implementations, the second CG (such as Figure 9 CG#2 in the code can have its priority reduced. In other words, the second CG can be disregarded. In this implementation, in Figure 7 At position 740, UE 104 cancels the first new transmission of the MACPDU, which includes the second delay information. For example, Figure 9 The first new transmission at T3 in the process was canceled.

[0184] In some implementations, if the report triggered for the second delay information has not been cancelled, UE 104 can determine the third delay information by performing method 1000, which will be described below.

[0185] Figure 10A flowchart illustrating a method 1000 for determining third delay information according to various aspects of this disclosure is provided. The operation of method 1000 can be implemented by the device or components thereof described herein. For example, the operation of method 1000 can be performed by the UE 104 described herein. In some implementations, the device can execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device can use dedicated hardware to perform aspects of the described functions.

[0186] At 1010, UE 104 determines the third CG of the previous autonomous transmission used for the third delay information. The third delay information indicates the third remaining time of the PDCP discard timer.

[0187] At position 1020, UE 104 determines the third time point of the previously autonomous transmission as the third reference time. For example, in Figure 9 In the example, the third time point of the previous autonomous transmission is T5. Therefore, UE 104 determines T5 as the third reference time.

[0188] At 1030, UE 104 determines the third delay information based on the value of the PDCP discard timer and the third reference time.

[0189] In some implementations, in order to report third delay information to base station 102, UE 104 may execute method 1100, which will be described below.

[0190] Figure 11 A flowchart illustrating a method 1100 for reporting third delay information according to various aspects of this disclosure is shown. Operation of method 1100 may be implemented by the device or components thereof described herein. For example, operation of method 1100 may be performed by the UE 104 described herein. In some implementations, the device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device may use dedicated hardware to perform aspects of the described functions.

[0191] At 1110, if UE 104 determines that no PUSCH transmission in at least one PUSCH transmission of the MAC PDU has been fully executed, then UE 104 retrieves the PUSCH transmission from the third CG (such as...). Figure 9 The MACPDU is obtained during the HARQ process identified by CG#3 in the middle.

[0192] At position 1120, UE 104 updates the MAC PDU using the third delay information. For example, UE 104 updates the MAC PDU using the third delay information at... Figure 9 The MAC PDU generated at point T2 in the code.

[0193] At 1130, UE 104 delivers the MAC PDU and the third CG to the identified HARQ procedure.

[0194] At 1140, UE 104 instructs the HARQ procedure to initiate a second new transmission of the MAC PDU.

[0195] In some implementations, third-party CG (such as Figure 9 CG#3 in the code can have its priority reduced. In other words, the third CG can be disregarded. In this implementation, in Figure 11 At position 1150, UE 104 cancels the second new transmission. For example, Figure 9 The second new transmission at T5 was cancelled.

[0196] In some implementations, the second CG can be downgraded by another prioritized UL grant, and UE 104 uses a first new transmission using a MAC PDU that includes delay information about the other prioritized UL grant, the delay information being determined based on the transmission time of the prioritized UL grant. In other words, delay information corresponding to the second delay information can be transmitted on the prioritized grant. In this implementation, even if the MAC PDU including the second delay information has been delivered to a lower layer (e.g., the physical layer) for a new transmission and the transmission has been cancelled, UE 104 still uses a first new transmission using a MAC PDU that includes delay information about the other prioritized UL grant.

[0197] In some implementations, the second CG can be downgraded by another prioritized UL grant. UE 104 uses a first new transmission of a MAC PDU that includes delay information about the other prioritized UL grant, and the delay information is determined based on the transmission time of the prioritized UL grant. In other words, delay information corresponding to the second delay information can be transmitted on the prioritized grant, and the MAC PDU including the second delay information delivered to the lower layer can be further updated, for example, by removing the second delay data from the MAC PDU.

[0198] In some implementations, the third CG can be downgraded by another prioritized UL grant, and UE 104 uses a first new transmission using a MAC PDU that includes delay information about the other prioritized UL grant. In other words, delay information corresponding to the third delay information can be sent on the prioritized grant. In this implementation, even if the MAC PDU including the third delay information has been delivered to a lower layer (e.g., the physical layer) for a new transmission and the transmission has been cancelled, UE 104 still uses a first new transmission using a MAC PDU that includes delay information about the other prioritized UL grant.

[0199] In some implementations, the second CG can be downgraded by another preferred UL grant. UE 104 uses a first new transmission of a MAC PDU that includes delay information about the other preferred UL grant, and the delay information is determined based on the transmission time of the preferred UL grant. Furthermore, the MAC PDU that includes third delay information delivered to the lower layer is updated, for example, by removing the third delay information from the MAC PDU.

[0200] In some implementations, if the trigger report for the third delay information has not been cancelled, UE 104 can determine the first delay information by performing method 400 as described above.

[0201] For example, in Figure 9 In the example, UE 104 determines a first CG (such as) for the autonomous transmission of first delay information. Figure 9 (CG#1 in the original text). The first delay information indicates that the PDCP discards the first remaining time of the timer.

[0202] Furthermore, UE 104 determines the first time point of autonomous transmission as the first reference time. For example, in Figure 9 In the example, the first time point of the initial transmission is T4. Therefore, UE 104 determines T4 as the first reference time.

[0203] Furthermore, UE 104 determines the first delay information based on the value of the PDCP discard timer and the first reference time (such as T4).

[0204] In some implementations, if a report triggered for the third delay information has been cancelled, UE 104 may trigger a report for the first delay information for use via the first CG (such as...). Figure 9 The CG#1 in the middle is transmitted autonomously.

[0205] In some implementations, in order to report the first delay information to base station 102, UE 104 may perform method 800 as described above.

[0206] In some implementations, the first CG, the second CG, and the third CG are associated with a single HARQ procedure identifier (ID).

[0207] It should be understood that method 200 can be performed in combination with at least one of methods 400, 600, 700, 800, 1000, and 1100. The scope of this disclosure is not limited in this respect.

[0208] Figure 12A flowchart illustrating method 1200 for determining a support status report format according to various aspects of this disclosure is shown. Operation of method 1200 can be implemented by the device or components thereof described herein. For example, operation of method 1200 can be performed by UE 104 described herein. In some implementations, the device can execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device can use dedicated hardware to perform aspects of the described functions.

[0209] At 1210, UE 104 determines the status report format for at least one BSR for at least one LCG.

[0210] At 1220, UE 104 sends at least one BSR to base station 102 in status report format.

[0211] In some implementations, UE 104 may define a first state report format as the state report format. The first state report format may include a first field and a second field. The first field relates to a first buffer size for at least one LCG, and the second field relates to delay information for at least one LCG. The delay information indicates the remaining time of the PDCP discard timer. Hereinafter, the first state report format may be referred to as the Enhanced BSR (EBSR) format. In some implementations, the first state report format may also include a third field, and the third field indicates whether the second field is present or absent, or whether there is available delay information available for transmission. The first state report format may also include the first field. The first state report format may also include a fourth field.

[0212] In some implementations, the first status report format may also include a fourth field, which indicates whether the first field exists or not, or whether there is available delay information that can be used for transmission.

[0213] In some implementations, UE 104 may define a second status report format as the status report format. The second status report format may include a first field, but may not include either the second or third field. The first field relates to the size of the buffer for at least one LCG. The second field relates to latency information for at least one LCG. The third field indicates whether the second field is present or absent. The second status report format may include a fourth field.

[0214] In some implementations, at least one LCG in the first state report can be replaced by at least one logical channel.

[0215] In some implementations, the second status report format may include one of the following: a regular BSR format, a periodic BSR format, or a populated BSR format.

[0216] In some implementations, UE 104 may receive a configuration of the status report format from base station 102. This configuration may indicate that one of a first status report format and a second status report format will be used. UE 104 may determine the status report format based on the configuration. For example, the configuration may indicate that one of the first and second status report formats will be used for at least one LCG. For example, the configuration may indicate that one of the first and second status report formats will be used for at least one logical channel. If the LCG includes at least one logical channel, the LCG is considered to use the first status report.

[0217] In some implementations, UE 104 may receive configuration information for at least one LCG from base station 102. This configuration may instruct at least one LCG to be configured to report delay information. In other words, UE 104 may be configured to report delay information for at least one logical channel belonging to at least one LCG. UE 104 determines at least one LCG configured to report delay information based on at least one logical channel included in the at least one LCG. Alternatively, UE 104 may be configured to report delay information for at least one LCG.

[0218] In some implementations, if UE 104 is configured to report delay information, UE 104 can determine the first status report format as the status report format.

[0219] In this implementation, if the reporting of delay information has been cancelled (i.e., the delay information is not available for transmission) or not cancelled (i.e., the delay information is available for transmission), but at least one LCG has data available for transmission (i.e., the buffer size to be reported), and at least one LCG is configured to report delay information, then UE 104 may determine the first status report format as the status report format.

[0220] In this implementation, even if only the LCG that is different from all at least one LCG has data available for transmission (i.e., the buffer size to be reported), and the LCG is not configured to report delay information, UE 104 can determine the first status report format as the status report format.

[0221] In some implementations, if at least one LCG has delay information that can be used for transmission, UE 104 may determine the first status report format as the status report format.

[0222] In some implementations, if at least one LCG has data available for transmission and at least one LCG is configured to report delay information, then UE 104 may determine the first status report format as the status report format.

[0223] In some implementations, the enhanced BSR has a first status report format, while the BSR has a second status report format.

[0224] For example, for regular BSRs, periodic BSRs, or filler BSRs, the MAC entity should: 1> If, when a MAC PDU containing a BSR is constructed, at least one LCG has data available for transmission, and delay information reporting is configured for transmission, then: 2> The report is for the enhanced BSR for all LCGs with data available for transmission. 1> Otherwise: 2> The report is for the BSR of all LCGs that have data available for transmission.

[0225] For example, for regular BSRs, periodic BSRs, or filler BSRs, the MAC entity should: 1> If, when a MAC PDU containing a BSR is constructed, and with enhanced status reporting configured for transmission, at least one LCG has data available for transmission, then: 2> The report is for the enhanced BSR for all LCGs with data available for transmission. 1> Otherwise: 2> The report is for the BSR of all LCGs that have data available for transmission.

[0226] For example, for regular BSRs, periodic BSRs, or padding BSRs, the MAC entity of UE 104 should: 1> If, when a MAC PDU containing a BSR is constructed, at least one LCG has data available for transmission and delay information available for transmission, then: 2> The report is for an enhanced BSR for all LCGs with data available for transmission. 1> Otherwise: 2> The report is for the BSR of all LCGs that have data available for transmission but no delay information.

[0227] In some implementations, if at least one LCG has data available for transmission, and none of the LCGs in at least one LCG have delay information for at least one LCG available for transmission, then UE 104 may determine the second status report format as the status report format.

[0228] In some implementations, if only the LCG that is different from all at least one LCG has data available for transmission, and all LCGs in the LCG are not configured to report delay information, then UE 104 may determine the second status report format as the status report format.

[0229] In some implementations, if only the LCGs that are different from all at least one LCG have data available for transmission, and all LCGs are not configured to use the first status report, then UE 104 may determine the second status report format as the status report format.

[0230] In some implementations, a BSR in the second-state report format may include one of the following: a regular BSR, a periodic BSR, or a populated BSR.

[0231] For example, for regular BSRs, periodic BSRs, or filler BSRs, the MAC entity should: 1> If, when a MAC PDU containing a BSR is constructed, at least one LCG has data available for transmission and delay information available for transmission, then: 2> The report is for an enhanced BSR for all LCGs with data available for transmission. 1> Otherwise: 2> The report is for the BSR of all LCGs that have data available for transmission.

[0232] In some implementations, if the uplink grant is insufficient to accommodate the first status report format but sufficient to accommodate the second status report format, then UE 104 may determine the second status report format as the status report format.

[0233] For example, for filling a BSR, the MAC entity should: 1> If the UL authorization is insufficient to include a long EBSR, but sufficient to include a long BSR, then: 2> UE reports a long BSR; 1> If the UL authorization is insufficient to include the short EBSR, but sufficient to include the short BSR, then: 2> UE reports a short BSR; 1> If the UL authorization is insufficient to include the long truncated EBSR, but sufficient to include the long truncated BSR, then: 2> UE Report Long Truncation BSR

[0234] For example, when (multiple) UL authorizations can accommodate all pending data that can be used for transmission, but are insufficient to accommodate additional BSR MAC CE and its sub-headers, all triggered BSRs can be cancelled.

[0235] In some implementations, at least one LCG may include a first LCG and a second LCG, or at least one LCG may include a first LCG and the second LCG is not configured to report delay information. The first LCG has a first priority equal to the second LCG has a second priority. The first LCG has delay information available for transmission, while the second LCG does not have delay information available for transmission. In this implementation, if the uplink grant is insufficient to accommodate a first state report format, UE 104 may report at least one BSR for the first LCG and the second LCG in the order of the first LCG and the second LCG.

[0236] In this implementation, if UE 104 reports an EBSR, and if the UL authorization is insufficient to include a long EBSR but sufficient to include a long truncated EBSR, then the EBSR is reported in descending order of the highest logical channel priority of each LCG in the LCG, and if the priorities are equal, UE 104 reports the EBSR for (multiple) LCGs in the order of having delay information available for transmission and not having delay information available for transmission.

[0237] In this implementation, if UE 104 reports an EBSR, and if the UL authorization is insufficient to include a long EBSR but sufficient to include a long truncated EBSR, then the EBSR is reported in descending order of the highest logical channel priority of each LCG in the LCG, in the order of (multiple) LCGs with delay information available for transmission and those without delay information available for transmission, and in the case of equal priority and delay information available for transmission, in the order of (multiple) LCGs with delay information, UE 104 reports the EBSR for (multiple) LCGs.

[0238] In this implementation, if UE 104 reports an EBSR, and if the UL authorization is insufficient to include a long EBSR but sufficient to include a long truncated EBSR, then the EBSR is reported in descending order of the highest logical channel priority of each LCG in the LCG, in the order of (multiple) LCGs with delay information available for transmission and those without delay information available for transmission, and in the case of equal priority and delay information available for transmission, in the order of (multiple) LCGs with delay information, and in the case of equal priority and equal delay information available for transmission, in ascending order of LCG ID.

[0239] For example, for filling a BSR, the MAC entity should: 1> If the number of padding bits is equal to or greater than the size of the short BSR plus its subheading, but less than the size of the long BSR plus its subheading, then: 2> If, at the time the BSR is constructed, more than one LCG has data available for transmission, then: 3> If the number of padding bits is equal to the short BSR plus the size of its subheading, then: 4> Report a short truncated BSR for the LCG with the highest priority logical channel available for data transmission. 3> Otherwise: 4> Following the descending order of the highest priority logical channels (with and without data available for transmission) in each of these (multiple) LCGs, in the case of equal priorities, and in the case of having and not having delay information in each of these LCGs, optionally in the order of having delay information and not having delay information, and in the case of equal priorities and having delay information, optionally in the ascending order of delay information, and in the case of equal priorities and having equal delay information, optionally in the ascending order of LCG ID, and in the case of equal priorities and not having delay information, in the ascending order of LCG ID, report the long truncated BSR of the (multiple) LCGs with logical channels available for transmission. 2> Otherwise: 3> Report a short BSR. 1> Otherwise, if the number of padding bits is equal to or greater than the length of the BSR plus the size of its subheading, then: 2> The report is for the long BSR of all LCGs with data available for transmission.

[0240] In some implementations, the reporting of delay information can be cancelled. In some implementations, when a MAC PDU is sent and the MAC PDU includes a long EBSR MAC CE or a short EBSR MAC CE, all reports of at least one delay information report that was triggered before the MAC PDU assembly, which contains delay information up to (and including) the last event that triggered the report before the MAC PDU assembly, should be cancelled.

[0241] In some implementations, when at least one UL authorization is sufficient to accommodate all pending data with delay information that is available for transmission, but is insufficient to additionally accommodate the EBSR MAC CE and its subheadings, all triggered EBS reports in at least one EBS report triggered by the delay information can be cancelled.

[0242] It should be understood that method 1200 can be performed in combination with at least one of methods 200, 400, 600, 700, 800, 1000, and 1100. The scope of this disclosure is not limited in this respect.

[0243] Figure 13 An example of a device 1300 supporting cached state reporting according to various aspects of this disclosure is illustrated. Device 1300 may be an example of a UE 104 as described herein. Device 1300 may support wireless communication with one or more network entities 102, UE 104, or any combination thereof. Device 1300 may include components for bidirectional communication, including components for transmitting and receiving communications (such as processor 1302, memory 1304, transceiver 1306, and optionally, I / O controller 1308). These components may communicate electronically or be otherwise coupled (e.g., operative ground, communication ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., bus).

[0244] Processor 1302, memory 1304, transceiver 1306, or various combinations thereof, or various components thereof, may be examples of components used to perform the various aspects of this disclosure described herein. For example, processor 1302, memory 1304, transceiver 1306, or various combinations thereof, or components thereof, may support methods for performing one or more of the operations described herein.

[0245] In some implementations, processor 1302, memory 1304, transceiver 1306, or various combinations or components thereof may be implemented in hardware (e.g., in a communication management circuitry system). The hardware may include a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, configured to or otherwise supporting components for performing the functions described herein. In some implementations, processor 1302 and memory 1304 coupled to processor 1302 may be configured to perform one or more of the functions described herein (e.g., instructions stored in memory 1304 are executed by processor 1302).

[0246] For example, according to the examples disclosed herein, processor 1302 may support wireless communication at device 1300. Processor 1302 may be configured to operate to support components for performing: determining whether uplink data belonging to at least one logical channel of at least one LCG becomes unavailable to the UE's Media Access Control (MAC) entity; and based on determining that the uplink data becomes unavailable, triggering at least one first BSR for at least one logical channel or for at least one LCG, each of the at least one first BSR indicating that the first buffer size of one of the at least one LCG is equal to zero.

[0247] Processor 1302 may include intelligent hardware devices (e.g., general-purpose processors, DSPs, CPUs, microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some implementations, processor 1302 may be configured to use a memory controller to operate a memory array. In some other implementations, the memory controller may be integrated into processor 1302. Processor 1302 may be configured to execute computer-readable instructions stored in memory (e.g., memory 1304) to cause device 1300 to perform various functions of this disclosure.

[0248] Memory 1304 may include random access memory (RAM) and read-only memory (ROM). Memory 1304 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1302, cause device 1300 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. In some implementations, the code may not be directly executed by processor 1302, but may cause a computer (e.g., when compiled and executed) to perform the functions described herein. In some implementations, memory 1304 may include a basic I / O system (BIOS) that controls basic hardware or software operations, such as interaction with peripheral components or devices.

[0249] I / O controller 1308 can manage input and output signals for device 1300. I / O controller 1308 can also manage peripheral devices not integrated into device M02. In some implementations, I / O controller 1308 can represent a physical connection or port to an external peripheral device. In some implementations, I / O controller 1308 can utilize an operating system such as iOS®, ANDROID®, MS WINDOWS®, OS / 2®, UNIX®, LINUX®, or another known operating system. In some implementations, I / O controller 1308 can be implemented as part of a processor (such as processor 1306). In some implementations, a user can interact with device 1300 via I / O controller 1308 or via hardware components controlled by I / O controller 1308.

[0250] In some implementations, device 1300 may include a single antenna 1310. However, in other implementations, device 1300 may have more than one antenna 1310 (i.e., multiple antennas), including multiple antenna panels or antenna arrays, which may be able to transmit or receive multiple wireless transmissions concurrently. Transceiver 1306 may communicate bidirectionally via one or more antennas 1310, wired or wireless links, as described herein. For example, transceiver 1306 may represent a wireless transceiver and may communicate bidirectionally with another wireless transceiver. Transceiver 1306 may also include a modem to modulate packets, provide modulated packets to one or more antennas 1310 for transmission, and demodulate packets received from one or more antennas 1310. Transceiver 1306 may include one or more transmit chains, one or more receive chains, or combinations thereof.

[0251] The transmission chain can be configured to generate and transmit signals (e.g., control information, data, packets). The transmission chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques, such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes such as phase shift keying (PSK) or quadrature amplitude modulation (QAM). The transmission chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over a wireless medium. The transmission chain may also include one or more antennas 1310 for transmitting the amplified signal into the air or wireless medium.

[0252] The receiver chain can be configured to receive signals (e.g., control information, data, packets) via a wireless medium. For example, the receiver chain may include one or more antennas 1310 for receiving signals over the air or via a wireless medium. The receiver chain may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain may include at least one demodulator configured to demodulate the received signal and acquire the transmitted data by reversing the modulation technique applied during signal transmission. The receiver chain may include at least one decoder for decoding the demodulated signal to receive the transmitted data.

[0253] Figure 14An example of device 1400 supporting the determination of first delay information according to various aspects of this disclosure is illustrated. Device 1400 may be an example of UE 104 as described herein. Device 1400 may support wireless communication with one or more network entities 102, UE 104, or any combination thereof. Device 1400 may include components for bidirectional communication, including components for transmitting and receiving communications (such as processor 1402, memory 1404, transceiver 1406, and optionally, I / O controller 1408). These components may communicate electronically or be otherwise coupled (e.g., operative ground, communication ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., bus).

[0254] Processor 1402, memory 1404, transceiver 1406, or various combinations thereof, or various components thereof, may be examples of components used to perform the various aspects of this disclosure described herein. For example, processor 1402, memory 1404, transceiver 1406, or various combinations thereof, or components thereof, may support methods for performing one or more of the operations described herein.

[0255] In some implementations, processor 1402, memory 1404, transceiver 1406, or various combinations or components thereof may be implemented in hardware (e.g., in a communication management circuitry system). The hardware may include a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, configured to or otherwise supporting components for performing the functions described in this disclosure. In some implementations, processor 1402 and memory 1404 coupled to processor 1402 may be configured to perform one or more of the functions described herein (e.g., instructions stored in memory 1404 are executed by processor 1402).

[0256] For example, according to the examples disclosed herein, processor 1402 may support wireless communication at device 1400. Processor 1402 may be configured to operate to support components for performing the following: determining a first CG for autonomous transmission of first delay information, the first delay information indicating a first remaining time of a PDCP discard timer; determining a first time point of autonomous transmission as a first reference time; and determining the first delay information based on the value of the PDCP discard timer and the first reference time.

[0257] Processor 1402 may include intelligent hardware devices (e.g., general-purpose processors, DSPs, CPUs, microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some implementations, processor 1402 may be configured to use a memory controller to operate a memory array. In some other implementations, the memory controller may be integrated into processor 1402. Processor 1402 may be configured to execute computer-readable instructions stored in memory (e.g., memory 1404) to cause device 1400 to perform various functions of this disclosure.

[0258] Memory 1404 may include random access memory (RAM) and read-only memory (ROM). Memory 1404 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1402, cause device 1400 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. In some implementations, the code may not be directly executed by processor 1402, but may cause a computer (e.g., when compiled and executed) to perform the functions described herein. In some implementations, memory 1404 may include a basic I / O system (BIOS) that controls basic hardware or software operations, such as interaction with peripheral components or devices.

[0259] I / O controller 1408 can manage input and output signals for device 1400. I / O controller 1408 can also manage peripheral devices not integrated into device M02. In some implementations, I / O controller 1408 can represent a physical connection or port to an external peripheral device. In some implementations, I / O controller 1408 can utilize an operating system such as iOS®, ANDROID®, MS WINDOWS®, OS / 2®, UNIX®, LINUX®, or another known operating system. In some implementations, I / O controller 1408 can be implemented as part of a processor (such as processor 1406). In some implementations, a user can interact with device 1400 via I / O controller 1408 or via hardware components controlled by I / O controller 1408.

[0260] In some implementations, device 1400 may include a single antenna 1410. However, in other implementations, device 1400 may have more than one antenna 1410 (i.e., multiple antennas), including multiple antenna panels or antenna arrays, which may be able to transmit or receive multiple wireless transmissions concurrently. Transceiver 1406 may communicate bidirectionally via one or more antennas 1410, wired or wireless links, as described herein. For example, transceiver 1406 may represent a wireless transceiver and may communicate bidirectionally with another wireless transceiver. Transceiver 1406 may also include a modem to modulate packets, provide modulated packets to one or more antennas 1410 for transmission, and demodulate packets received from one or more antennas 1410. Transceiver 1406 may include one or more transmit chains, one or more receive chains, or combinations thereof.

[0261] The transmission chain can be configured to generate and transmit signals (e.g., control information, data, packets). The transmission chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques, such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes such as phase shift keying (PSK) or quadrature amplitude modulation (QAM). The transmission chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over a wireless medium. The transmission chain may also include one or more antennas 1410 for transmitting the amplified signal into the air or wireless medium.

[0262] The receiver chain can be configured to receive signals (e.g., control information, data, packets) via a wireless medium. For example, the receiver chain may include one or more antennas 1410 for receiving signals over the air or via a wireless medium. The receiver chain may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain may include at least one demodulator configured to demodulate the received signal and acquire the transmitted data by reversing the modulation technique applied during signal transmission. The receiver chain may include at least one decoder for decoding the demodulated signal to receive the transmitted data.

[0263] Figure 15An example of a device 1500 defined according to a support status report format in accordance with various aspects of this disclosure is illustrated. Device 1500 may be an example of a UE 104 as described herein. Device 1500 may support wireless communication with one or more network entities 102, UE 104, or any combination thereof. Device 1500 may include components for bidirectional communication, including components for transmitting and receiving communications (such as processor 1502, memory 1504, transceiver 1506, and optionally, I / O controller 1508). These components may communicate electronically or be otherwise coupled (e.g., operative ground, communication ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., bus).

[0264] Processor 1502, memory 1504, transceiver 1506, or various combinations thereof, or various components thereof, may be examples of components used to perform the various aspects of this disclosure described herein. For example, processor 1502, memory 1504, transceiver 1506, or various combinations thereof, or components thereof, may support methods for performing one or more of the operations described herein.

[0265] In some implementations, processor 1502, memory 1504, transceiver 1506, or various combinations or components thereof may be implemented in hardware (e.g., in a communication management circuitry system). The hardware may include a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, configured to or otherwise supporting components for performing the functions described herein. In some implementations, processor 1502 and memory 1504 coupled to processor 1502 may be configured to perform one or more of the functions described herein (e.g., instructions stored in memory 1504 are executed by processor 1502).

[0266] For example, according to the examples disclosed herein, processor 1502 may support wireless communication at device 1500. Processor 1502 may be configured to operate to support components for performing the following: determining a status report format for at least one BSR for at least one LCG; and transmitting at least one BSR to a base station in the status report format.

[0267] Processor 1502 may include intelligent hardware devices (e.g., general-purpose processors, DSPs, CPUs, microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some implementations, processor 1502 may be configured to use a memory controller to operate a memory array. In some other implementations, the memory controller may be integrated into processor 1502. Processor 1502 may be configured to execute computer-readable instructions stored in memory (e.g., memory 1504) to cause device 1500 to perform various functions of this disclosure.

[0268] Memory 1504 may include random access memory (RAM) and read-only memory (ROM). Memory 1504 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1502, cause device 1500 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. In some implementations, the code may not be directly executed by processor 1502, but may cause a computer (e.g., when compiled and executed) to perform the functions described herein. In some implementations, memory 1504 may include a basic I / O system (BIOS) that controls basic hardware or software operations, such as interaction with peripheral components or devices.

[0269] I / O controller 1508 can manage input and output signals for device 1500. I / O controller 1508 can also manage peripheral devices not integrated into device M02. In some implementations, I / O controller 1508 can represent a physical connection or port to an external peripheral device. In some implementations, I / O controller 1508 can utilize an operating system such as iOS®, ANDROID®, MS WINDOWS®, OS / 2®, UNIX®, LINUX®, or another known operating system. In some implementations, I / O controller 1508 can be implemented as part of a processor (such as processor 1506). In some implementations, a user can interact with device 1500 via I / O controller 1508 or via hardware components controlled by I / O controller 1508.

[0270] In some implementations, device 1500 may include a single antenna 1510. However, in other implementations, device 1500 may have more than one antenna 1510 (i.e., multiple antennas), including multiple antenna panels or antenna arrays, which may be able to transmit or receive multiple wireless transmissions concurrently. Transceiver 1506 may communicate bidirectionally via one or more antennas 1510, wired or wireless links, as described herein. For example, transceiver 1506 may represent a wireless transceiver and may communicate bidirectionally with another wireless transceiver. Transceiver 1506 may also include a modem to modulate packets, provide modulated packets to one or more antennas 1510 for transmission, and demodulate packets received from one or more antennas 1510. Transceiver 1506 may include one or more transmit chains, one or more receive chains, or combinations thereof.

[0271] The transmission chain can be configured to generate and transmit signals (e.g., control information, data, packets). The transmission chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques, such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes such as phase shift keying (PSK) or quadrature amplitude modulation (QAM). The transmission chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over a wireless medium. The transmission chain may also include one or more antennas 1510 for transmitting the amplified signal into the air or wireless medium.

[0272] The receiver chain can be configured to receive signals (e.g., control information, data, packets) via a wireless medium. For example, the receiver chain may include one or more antennas 1510 for receiving signals over the air or via a wireless medium. The receiver chain may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain may include at least one demodulator configured to demodulate the received signal and acquire the transmitted data by reversing the modulation technique applied during signal transmission. The receiver chain may include at least one decoder for decoding the demodulated signal to receive the transmitted data.

[0273] Figure 16An example of a processor 1600 supporting cache status reporting according to various aspects of this disclosure is illustrated. Processor 1600 may be an example of a processor configured to perform various operations according to the examples described herein. Processor 1600 may include a controller 1602 configured to perform various operations according to the examples described herein. Processor 1600 may optionally include at least one memory 1604, such as an L1 / L2 / L3 cache. Additionally or alternatively, processor 1600 may optionally include one or more arithmetic logic units (ALUs) 1600. One or more of these components may be electronically communicated or otherwise coupled (e.g., operative ground, communicative ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., buses).

[0274] Processor 1600 may be a processor chipset and includes a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receive, acquire, retrieve, send, output, forward, store, determine, identify, access, write, read) according to the examples described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the processor chipset or included in the processor chipset (e.g., processor 1600)) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), etc.).

[0275] Controller 1602 can be configured to manage and coordinate various operations of processor 1600 (e.g., signaling, receiving, acquiring, retrieving, sending, outputting, forwarding, storing, determining, identifying, accessing, writing, and reading) to enable processor 1600 to support various operations according to the examples described herein. For example, controller 1602 can operate as a control unit of processor 1600, generating control signals that manage the operation of various components of processor 1600. These control signals include enabling or disabling functional units, selecting data paths, initiating memory accesses, and coordinating operation timing.

[0276] Controller 1602 can be configured to fetch (e.g., fetch, retrieve, receive) instructions from memory 1604 and determine subsequent instructions(s) to be executed, enabling processor 1600 to support various operations according to the examples described herein. Controller 1602 can be configured to track the memory addresses of instructions associated with memory 1604. Controller 1602 can be configured to decode instructions to determine the operations to be performed and the operands involved. For example, controller 1602 can be configured to interpret instructions and determine control signals to be output to other components of processor 1600, enabling processor 1600 to support various operations according to the examples described herein. Additionally or alternatively, controller 1602 can be configured to manage data flow within processor 1600. Controller 1602 can be configured to control data transfers between registers, arithmetic logic unit (ALU), and other functional units of processor 1600.

[0277] Memory 1604 may include one or more caches (e.g., memory or other memory, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc., either local to or included in processor 1600). In some implementations, memory 1604 may reside within or on the processor chipset (e.g., locally to processor 1600). In some other implementations, memory 1604 may reside outside the processor chipset (e.g., remotely from processor 1600).

[0278] Memory 1604 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1600, cause processor 1600 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. Controller 1602 and / or processor 1600 may be configured to execute computer-readable instructions stored in memory 1604 to cause processor 1600 to perform various functions. For example, processor 1600 and / or controller 1602 may be coupled to or connected to memory 1604, and processor 1600, controller 1602, and memory 1604 may be configured to perform the various functions described herein. In some examples, processor 1600 may include multiple processors, and memory 1604 may include multiple memories. One or more of the multiple processors may be coupled to one or more of the multiple memories, which may be configured individually or collectively to perform the various functions described herein.

[0279] One or more ALU 1600s can be configured to support a variety of operations as described in the examples herein. In some implementations, one or more ALU 1600s may reside within or on a processor chipset (e.g., processor 1600). In some other implementations, one or more ALU 1600s may reside outside the processor chipset (e.g., processor 1600). One or more ALU 1600s can perform one or more computations (such as addition, subtraction, multiplication, and division) on data. For example, one or more ALU 1600s may receive input operands and an opcode that determines the operation to be performed. One or more ALU 1600s are configured with a variety of logic and arithmetic circuitry, including adders, subtractors, shifters, and logic gates, to process and manipulate data according to the operations. Additionally or alternatively, one or more ALU 1600s may support logical operations (such as AND, OR, XOR, NOR, and NAND), enabling one or more ALU 1600s to handle conditional operations, comparisons, and bitwise operations.

[0280] Based on the examples disclosed herein, processor 1600 may support wireless communication. Processor 1600 may be configured or operable to support components for performing the following: determining whether uplink data belonging to at least one logical channel of at least one LCG becomes unavailable to the UE's Media Access Control (MAC) entity; and, based on the determination that uplink data becomes unavailable, triggering at least one first BSR for at least one logical channel or for at least one LCG, each of the at least one first BSR indicating that the first buffer size of one of the at least one LCG is equal to zero.

[0281] Figure 17 An example of a processor 1700 supporting the determination of first delay information according to various aspects of this disclosure is illustrated. Processor 1700 may be an example of a processor configured to perform various operations according to the examples described herein. Processor 1700 may include a controller 1702 configured to perform various operations according to the examples described herein. Processor 1700 may optionally include at least one memory 1704, such as an L1 / L2 / L3 cache. Additionally or alternatively, processor 1700 may optionally include one or more arithmetic logic units (ALUs) 1700. One or more of these components may be electronically communicated or otherwise coupled (e.g., operative ground, communicative ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., buses).

[0282] Processor 1700 may be a processor chipset and includes a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receive, acquire, retrieve, send, output, forward, store, determine, identify, access, write, read) according to the examples described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the processor chipset or included in the processor chipset (e.g., processor 1700)) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), etc.).

[0283] Controller 1702 can be configured to manage and coordinate various operations of processor 1700 (e.g., signaling, receiving, acquiring, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, and reading) to enable processor 1700 to support various operations according to the examples described herein. For example, controller 1702 can operate as a control unit of processor 1700, generating control signals that manage the operation of various components of processor 1700. These control signals include enabling or disabling functional units, selecting data paths, initiating memory accesses, and coordinating operation timing.

[0284] Controller 1702 can be configured to fetch (e.g., fetch, retrieve, receive) instructions from memory 1704 and determine subsequent instructions(s) to be executed, enabling processor 1700 to support various operations according to the examples described herein. Controller 1702 can be configured to track the memory addresses of instructions associated with memory 1704. Controller 1702 can be configured to decode instructions to determine the operations to be performed and the operands involved. For example, controller 1702 can be configured to interpret instructions and determine control signals to be output to other components of processor 1700, enabling processor 1700 to support various operations according to the examples described herein. Additionally or alternatively, controller 1702 can be configured to manage data flow within processor 1700. Controller 1702 can be configured to control data transfers between registers, arithmetic logic unit (ALU), and other functional units of processor 1700.

[0285] Memory 1704 may include one or more caches (e.g., memory or other memory, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc., either local to or included in processor 1700). In some implementations, memory 1704 may reside within or on the processor chipset (e.g., locally to processor 1700). In some other implementations, memory 1704 may reside outside the processor chipset (e.g., remotely from processor 1700).

[0286] Memory 1704 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1700, cause processor 1700 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. Controller 1702 and / or processor 1700 may be configured to execute computer-readable instructions stored in memory 1704 to cause processor 1700 to perform various functions. For example, processor 1700 and / or controller 1702 may be coupled to or connected to memory 1704, and processor 1700, controller 1702, and memory 1704 may be configured to perform the various functions described herein. In some examples, processor 1700 may include multiple processors, and memory 1704 may include multiple memories. One or more of the multiple processors may be coupled to one or more of the multiple memories, which may be configured individually or collectively to perform the various functions described herein.

[0287] One or more ALU 1700s can be configured to support a variety of operations as described in the examples herein. In some implementations, one or more ALU 1700s may reside within or on a processor chipset (e.g., processor 1700). In some other implementations, one or more ALU 1700s may reside outside the processor chipset (e.g., processor 1700). One or more ALU 1700s can perform one or more computations (such as addition, subtraction, multiplication, and division) on data. For example, one or more ALU 1700s may receive input operands and an opcode that determines the operation to be performed. One or more ALU 1700s are configured with a variety of logic and arithmetic circuitry, including adders, subtractors, shifters, and logic gates, to process and manipulate data according to the operations. Additionally or alternatively, one or more ALU 1700s may support logical operations (such as AND, OR, XOR, NOR, and NAND), enabling one or more ALU 1700s to handle conditional operations, comparisons, and bitwise operations.

[0288] Based on the examples disclosed herein, processor 1700 may support wireless communication. Processor 1700 may be configured or operable to support components for performing the following: determining a first CG for autonomous transmission of first delay information, the first delay information indicating a first remaining time of the PDCP discard timer; determining a first time point of autonomous transmission as a first reference time; and determining the first delay information based on the value of the PDCP discard timer and the first reference time.

[0289] Figure 18 An example of a processor 1800 defined according to a support status report format according to various aspects of this disclosure is illustrated. Processor 1800 may be an example of a processor configured to perform various operations according to the examples described herein. Processor 1800 may include a controller 1802 configured to perform various operations according to the examples described herein. Processor 1800 may optionally include at least one memory 1804, such as an L1 / L2 / L3 cache. Additionally or alternatively, processor 1800 may optionally include one or more arithmetic logic units (ALUs) 1800. One or more of these components may be electronically communicated or otherwise coupled (e.g., operative ground, communicative ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., buses).

[0290] Processor 1800 may be a processor chipset and includes a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receive, acquire, retrieve, send, output, forward, store, determine, identify, access, write, read) according to the examples described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the processor chipset or included in the processor chipset (e.g., processor 1800)) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), etc.).

[0291] Controller 1802 can be configured to manage and coordinate various operations of processor 1800 (e.g., signaling, receiving, acquiring, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, and reading) to enable processor 1800 to support various operations according to the examples described herein. For example, controller 1802 can operate as a control unit of processor 1800, generating control signals that manage the operation of various components of processor 1800. These control signals include enabling and disabling functional units, selecting data paths, initiating memory accesses, and coordinating operation timing.

[0292] Controller 1802 can be configured to fetch (e.g., fetch, retrieve, receive) instructions from memory 1804 and determine subsequent instructions(s) to be executed, enabling processor 1800 to support various operations according to the examples described herein. Controller 1802 can be configured to track the memory addresses of instructions associated with memory 1804. Controller 1802 can be configured to decode instructions to determine the operations to be performed and the operands involved. For example, controller 1802 can be configured to interpret instructions and determine control signals to be output to other components of processor 1800, enabling processor 1800 to support various operations according to the examples described herein. Additionally or alternatively, controller 1802 can be configured to manage data flow within processor 1800. Controller 1802 can be configured to control data transfers between registers, arithmetic logic unit (ALU), and other functional units of processor 1800.

[0293] Memory 1804 may include one or more caches (e.g., memory or other memory, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc., either local to or included in processor 1800). In some implementations, memory 1804 may reside within or on the processor chipset (e.g., locally to processor 1800). In some other implementations, memory 1804 may reside outside the processor chipset (e.g., remotely from processor 1800).

[0294] Memory 1804 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1800, cause processor 1800 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. Controller 1802 and / or processor 1800 may be configured to execute computer-readable instructions stored in memory 1804 to cause processor 1800 to perform various functions. For example, processor 1800 and / or controller 1802 may be coupled to or connected to memory 1804, and processor 1800, controller 1802, and memory 1804 may be configured to perform the various functions described herein. In some examples, processor 1800 may include multiple processors, and memory 1804 may include multiple memories. One or more of the multiple processors may be coupled to one or more of the multiple memories, which may be configured individually or collectively to perform the various functions described herein.

[0295] One or more ALU 1800s can be configured to support a variety of operations as described in the examples herein. In some implementations, one or more ALU 1800s may reside within or on a processor chipset (e.g., processor 1800). In some other implementations, one or more ALU 1800s may reside outside the processor chipset (e.g., processor 1800). One or more ALU 1800s can perform one or more computations (such as addition, subtraction, multiplication, and division) on data. For example, one or more ALU 1800s may receive input operands and an opcode that determines the operation to be performed. One or more ALU 1800s are configured with various logic and arithmetic circuitry, including adders, subtractors, shifters, and logic gates, to process and manipulate data according to the operations. Additionally or alternatively, one or more ALU 1800s may support logical operations (such as AND, OR, XOR, NOR, and NAND), enabling one or more ALU 1800s to handle conditional operations, comparisons, and bitwise operations.

[0296] Based on the examples disclosed herein, processor 1800 may support wireless communication. Processor 1800 may be configured or operable to support components for performing the following: determining a status report format for at least one BSR for at least one LCG; and transmitting at least one BSR to a base station in the status report format.

[0297] It should be noted that the methods described in this paper describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, aspects from two or more methods can be combined.

[0298] The various illustrative boxes and components disclosed herein can be implemented or executed by a general-purpose processor, DSP, ASIC, CPU, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0299] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including being distributed such that portions of the functions are implemented in different physical locations.

[0300] Computer-readable media include both non-transitory computer storage media and communication media, encompassing any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium accessible by a general-purpose or special-purpose computer. For example, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), flash memory, optical disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

[0301] As used herein, including in the claims, the article “a (a)” preceding an element is unrestricted and should be understood to refer to “at least one” or “one or more” of those elements. The terms “a (a),” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. As used herein, including in the claims, the “or” used in a list of items (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…” or “one or two of…”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase “based on” should not be construed as a reference to a closed set of conditions. For example, an example step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase “based on” should be interpreted in the same manner as the phrase “at least partially based on.” Furthermore, as used herein, including in the claims, a “set” may include one or more elements.

[0302] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A user equipment (UE), comprising: processor; as well as The transceiver is coupled to the processor. The processor is configured as follows: Determine whether uplink data belonging to at least one logical channel in at least one logical channel group (LCG) becomes unavailable to the UE's media access control (MAC) entity; as well as Based on the determination that the uplink data has become unavailable, at least one first buffer status report (BSR) is triggered for the at least one logical channel or for the at least one LCG, each of the at least one first BSR indicating that the first buffer size of one of the at least one LCG is equal to zero.

2. The UE of claim 1, wherein the processor is configured to determine that the uplink data becomes unavailable by: Detect at least one end of at least one data burst in the at least one logical channel.

3. The UE according to claim 1, wherein the at least one first BSR comprises at least one dedicated BSR.

4. The UE according to claim 3, wherein the first priority of the at least one dedicated BSR is higher than, equal to or lower than the second priority of the regular BSR or the periodic BSR.

5. The UE of claim 1, wherein the processor is configured to trigger the at least one first BSR by: The at least one first BSR is triggered based on the following criteria: The uplink data became unavailable; and The third BSR that was not triggered indicates that the size of the first cache is equal to zero.

6. The UE according to claim 1, wherein the processor is further configured to: Based on the determination that the uplink grant is sufficient to accommodate all pending data available for transmission, but insufficient to accommodate additional MAC control elements (CEs) and the sub-headers of the MAC CEs, the triggered at least one first BSR is not cancelled, the MAC CE including the triggered at least one first BSR.

7. The UE of claim 1, wherein the processor is configured to determine whether the uplink data belonging to the at least one logical channel of the at least one LCG becomes unavailable by: Receive configurations for the at least one logical channel or the at least one LCG from the base station via the transceiver; and The configuration is used to determine whether the uplink data becomes unavailable.

8. A user equipment (UE), comprising: processor; as well as The transceiver is coupled to the processor. The processor is configured as follows: A first configuration grant (CG) is determined for the autonomous transmission of first delay information, the first delay information indicating a first remaining time of the Packet Data Convergence Protocol (PDCP) discard timer; The first time point of the autonomous transmission is determined as the first reference time; as well as The first delay information is determined based on the value of the PDCP discard timer and the first reference time.

9. The UE of claim 8, wherein the processor is further configured to: Based on the determination that no PUSCH transmission has been fully executed in at least one Physical Uplink Shared Channel (PUSCH) transmission of Media Access Control (MAC) Protocol Data Unit (PDU), the MAC PDU is obtained from the identified Hybrid Automatic Repeat Request (HARQ) process of the first CG. Update the MAC PDU using the first delay information; as well as The MAC PDU is sent to the base station via the transceiver.

10. The UE of claim 8, wherein the processor is further configured to: Based on the determination that the CG preceding the first CG is downgraded, Media Access Control (MAC) Protocol Data Units (PDUs) are obtained from the identified Hybrid Automatic Repeat Request (HARQ) process.

11. A user equipment (UE), comprising: processor; as well as The transceiver is coupled to the processor. The processor is configured as follows: Determine the status report format for at least one buffer status report (BSR) for at least one logical channel group (LCG); and The at least one BSR is sent to the base station via the transceiver in the stated status report format.

12. The UE of claim 11, wherein the processor is configured to determine the status report format by: The first status report format is determined as the status report format, which includes a first field and a second field. The first field is related to a first buffer size of the at least one LCG, and the second field is related to latency information for the at least one LCG, which indicates the remaining time of the Packet Data Convergence Protocol (PDCP) discard timer.

13. The UE of claim 12, wherein the processor is configured to determine the first status report format as the status report format by: Based on the determination that the UE is configured to report the delay information or use the first status report, the first status report format is determined as the status report format.

14. The UE of claim 12, wherein the processor is configured to determine the first status report format as the status report format by: Based on the determination that the at least one LCG has the delay information that can be used for transmission, the first status report format is determined as the status report format.

15. The UE of claim 12, wherein the processor is configured to determine the first status report format as the status report format by: Based on the determination that the at least one LCG has data available for transmission and that the at least one LCG is configured to report the delay information or use the first status report, the first status report format is determined as the status report format.

16. The UE of claim 11, wherein the processor is configured to determine the status report format by: The second status report format is determined as the status report format, which includes a first field and does not include either the second field or the third field, wherein the first field is related to the cache size of the at least one LCG.

17. The UE of claim 16, wherein the processor is configured to determine the second status report format as the status report format by: Based on the determination that the at least one LCG has data available for transmission, and that none of the at least one LCG has delay information for the at least one LCG available for transmission, the second status report format is determined as the status report format, wherein the delay information indicates the remaining time of the Packet Data Convergence Protocol (PDCP) discard timer.

18. The UE of claim 16 or 17, wherein the processor is configured to determine the second status report format as the status report format by: Based on the determination that the at least one LCG has data available for transmission, and that none of the at least one LCG is configured to report delay information or use the first status report for the at least one LCG available for transmission, the second status report format is determined as the status report format, wherein the delay information indicates the remaining time of the Packet Data Convergence Protocol (PDCP) discard timer.

19. The UE of claim 16, wherein the processor is configured to determine the second status report format as the status report format by: Based on the determination that the uplink grant is insufficient to accommodate the first status report format but sufficient to accommodate the second status report format, the first status report format includes the first field and the second field, the second field being related to delay information for the at least one LCG, the delay information indicating the remaining time of the Packet Data Convergence Protocol (PDCP) discard timer.

20. The UE of claim 12, wherein the at least one LCG comprises a first LCG and a second LCG, the first LCG having a first priority equal to the second priority of the second LCG, the first LCG having delay information available for transmission, and the second LCG not having delay information available for transmission; and The processor is configured to send the at least one BSR via the following: Based on the determination that the uplink authorization is insufficient to accommodate the first status report format, the at least one BSR for the first LCG and the second LCG is reported in the order of the first LCG and the second LCG.

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