Mainboard device and expansion card detection method thereof

Abstract

The invention discloses a mainboard device and an expansion card detection method of the mainboard device. The mainboard device comprises a bus slot, a switching circuit and a controller. The bus slot comprises a first pin end point and a second pin end point. The switching circuit comprises a first end, a second end, a third end and a control end. The first end is coupled to the first pin endpoint, the second end is coupled to the second pin endpoint, and the third end is coupled to the first end and the clock enabling end. The controller provides a control signal to the control end according to detection information of the bus slot, so that the first end and the third end or the second end and the third end are selectively conducted in the switching circuit.

Description

Technical Field

[0001] This invention relates to a bus technology for computer systems, and more particularly to a motherboard device and a method for detecting expansion cards of the motherboard device. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe) is a common bus technology standard used in computer systems, enabling communication between computing components (such as processors, chipsets, caches, memory, expansion cards, graphics cards, and storage devices). As the technology has evolved, multiple versions of the PCIe bus have been released, with corresponding specifications developed for different types of computing components (such as graphics cards). Currently, PCIe 3.0 and PCIe 4.0 are the mainstream PCIe bus standards used on graphics cards.

[0003] However, PCIe versions 3.0 (including earlier versions) and PCIe 4.0 (including later versions) have some functional conflicts in their pin definitions for graphics cards. In other words, the PCIe bus may have incompatible functions for certain pins. Therefore, in order for the motherboard to support both types of graphics card standards simultaneously, appropriate handling must be done for the specific pins with functional conflicts to meet the compatibility or switching requirements of different versions of graphics cards. In conclusion, motherboard manufacturers must resolve the pin function conflicts between different PCIe versions of graphics cards during the design process to provide flexible compatibility. Summary of the Invention

[0004] This invention provides a method for detecting motherboard devices and expansion cards, enabling computer devices to smoothly support different types of bus expansion cards and avoiding incompatibility between motherboard devices and bus expansion cards.

[0005] The motherboard device of this invention includes a bus slot, a switching circuit, and a controller. The bus slot includes a first pin endpoint and a second pin endpoint. The switching circuit includes a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal is coupled to the first pin endpoint, the second terminal is coupled to the second pin endpoint, and the third terminal is coupled to the first terminal and a clock enable terminal, wherein the clock enable terminal is used to provide a clock enable signal. The controller is coupled to the bus slot and the control terminal of the switching circuit. The controller is configured to provide a control signal to the control terminal based on detection information from the bus slot, so as to selectively activate the first terminal and the third terminal or activate the second terminal and the third terminal in the switching circuit.

[0006] The expansion card detection method for a motherboard device according to an embodiment of the present invention includes: determining detection information of a bus slot, wherein the bus slot includes a first pin endpoint and a second pin endpoint; according to the detection information, a controller provides a corresponding control signal to a control terminal of a switching circuit, wherein the switching circuit includes a first terminal, a second terminal, a third terminal, and a control terminal, wherein the first terminal is coupled to the first pin endpoint, the second terminal is coupled to the second pin endpoint, and the third terminal is coupled to the first terminal and a clock enable terminal, wherein the clock enable terminal is used to provide a clock enable signal; and according to the provided control signal, the switching circuit selectively connects the first terminal and the third terminal or connects the second terminal and the third terminal.

[0007] Based on the above, the motherboard device and expansion card detection method of the present invention, through a switching circuit and the detection information of the expansion card (e.g., expansion card type detection), selectively provides the corresponding signals (e.g., clock signal, clock request signal) of the expansion card to the correct pin endpoints in different card types. Therefore, the present invention enables the motherboard device to smoothly support expansion cards of different bus types (e.g., PCIe 3.0 and PCIe 4.0 PCIe expansion cards), avoiding incompatibility between the motherboard device and the expansion card. Attached Figure Description

[0008] Figure 1A and Figure 1B This is a schematic diagram illustrating the use of a PCIe expansion card of type PCIe 3.0 and a PCIe expansion card of type PCIe 4.0, respectively, according to one embodiment of the present invention.

[0009] Figure 2 This is a block diagram of a computer device according to an embodiment of the present invention.

[0010] Figures 3A to 3C These are schematic diagrams of the switching circuit and controller according to the first to third embodiments of the present invention.

[0011] Figure 4 This is a flowchart of an expansion card detection method for a motherboard device according to an embodiment of the present invention.

[0012] Figure 5 This is a timing diagram illustrating the signal waveforms in the JEDEC Solid State Technology Association's PCIe specification according to an embodiment of the present invention.

[0013] Figure 6 These are waveform diagrams of various signals in the detection method according to an embodiment of the present invention.

[0014] The reference numerals in the attached figures are explained as follows:

[0015] 100: Electronic devices

[0016] 110-1, 110-2: PCIe expansion cards

[0017] 120-1, 120-2: Motherboard

[0018] 125-1, 125-2: PCIe slots

[0019] 130-1, 130-2: Hot-plug detection logic

[0020] 140: Clock Request Logic

[0021] 150: Processing chip

[0022] 20: Computer devices

[0023] 200: Motherboard device

[0024] 210: PCIe Expansion Card

[0025] 225: PCIe slot

[0026] 250: Switching circuit

[0027] 260: Controller

[0028] S405~S490: Steps of the expansion card detection method

[0029] 510, 520, 610~640, S450, S460, S470-1, S470-2: Markings

[0030] BIOS_Detect: BIOS detection endpoint

[0031] Vaux: Standby voltage

[0032] Vss: System operating voltage

[0033] PERST#: Reset signal

[0034] PRESENT: Insertion / removal detection signal

[0035] REFCLK: Reference clock signal

[0036] CLK_REQ: Clock request signal

[0037] PIN_A1, PIN_A13, PIN_A14, PIN_B12, PIN_B17: Pin endpoints

[0038] PINA1, PINB12, PINB17: Pins

[0039] GPI: Endpoint

[0040] N / A: Not applicable

[0041] N1: First end

[0042] N2: Second end

[0043] N3: Third end

[0044] CN: Control Terminal

[0045] CKEN: Clock enable pin

[0046] CS1: Control signal

[0047] GND: Ground terminal

[0048] RU21, RU22: Impedance elements

[0049] NM1: Transistor

[0050] PCIe 3.0: PCIe 3.0 type

[0051] PCIe 4.0: PCIe 4.0 type Detailed Implementation

[0052] Figure 1A and Figure 1B This is a schematic diagram illustrating a PCIe expansion card using PCIe 3.0 and a PCIe 4.0 expansion card according to an embodiment of the present invention. The PCIe expansion card in this embodiment is a device that adopts the PCIe interface specification, such as a graphics card or other peripheral device of a computer system. Here, the card type using PCIe 3.0 technology as a PCIe expansion card is referred to as a "PCIe 3.0 type PCIe expansion card," and the card type using PCIe 4.0 technology as a PCIe expansion card is referred to as a "PCIe 4.0 type PCIe expansion card," for ease of subsequent description.

[0053] In this embodiment, "PCIe 3.0 type" refers to the technologies encompassing PCIe 3.0 specification versions and previously disclosed corresponding PCIe specification versions (e.g., PCIe 1.X, PCIe 2.X, etc.). In this embodiment, "PCIe 4.0 type" refers to the technologies encompassing PCIe 4.0 specification versions and subsequently disclosed corresponding PCIe specification versions (e.g., PCIe 5.X, PCIe 6.X, etc.). In other words, the embodiments of this invention are not limited to the content of PCIe 3.0 and PCIe 4.0 specification versions, but rather involve corresponding technological development based on different clock signals.

[0054] Figure 1A The computer system includes a PCIe expansion card 110-1 (PCIe 3.0 type) and a motherboard 120-1. The motherboard 120-1 has a PCIe slot 125-1. Both the pins (commonly known as gold fingers) on the PCIe expansion card 110-1 and the PCIe slot 125-1 have two sides, referred to here as side A and side B. In other words, the motherboard 120-1 and the PCIe slot 125-1 can be collectively referred to as the motherboard device.

[0055] The PCIe 3.0 type selectively toggles the clock signal supply via the PREST#2 function of pin endpoint PIN_B17. Specifically, when the PCIe expansion card 110-1 is inserted into the PCIe slot 125-1, since pins PINA1 and PINB17 of the PCIe expansion card 110-1 are electrically coupled, and pin endpoint PIN_A1 in the PCIe slot 125-1 is connected to ground, the hot-plug detection logic 130-1 in the motherboard 120-1 can determine whether the PCIe expansion card 110-1 has been successfully inserted into the PCIe slot 125-1 based on whether pin endpoint PIN_B17 is connected to ground.

[0056] After the hot-plug detection logic 130-1 confirms that the PCIe slot 125-1 is indeed inserted via pin endpoint PIN_B17, the processing logic on the motherboard 120-1 correspondingly enables the clock signal and provides this clock signal to the PCIe expansion card 110-1, enabling the PCIe expansion card 110-1 to operate. The PCIe 3.0 type pin endpoint PIN_B12 is not connected or used. Figure 1A Indicated as not applicable (N / A).

[0057] Figure 1B The image shows a PCIe expansion card 110-2 and a motherboard 120-2 compliant with PCIe 4.0 in a computer system. The motherboard 120-2 and PCIe slot 125-2 can be collectively referred to as a motherboard device. Compared to PCIe 3.0, the PCIe 4.0 expansion card 110-2 adds a clock request (CLK_REQ) function to its pin endpoint PIN_B12. Specifically, the clock request function allows a computer system with PCIe slot 125-2 (e.g., motherboard 120-2 and clock request logic 140) to communicate bidirectionally with the processing chip 150 in the PCIe expansion card 110-2 via pin endpoint PIN_B12, thereby adjusting the clock signal and selectively performing functions such as operation or power saving.

[0058] This would cause the clock signal enable function in PCIe 3.0 to conflict with the CLK_REQ function in PCIe 4.0. PCIe 3.0 selectively toggles the clock signal supply via the PREST#2 function on pin PIN_B17. Compared to the CLK_REQ function in PCIe 4.0, PCIe 3.0 only determines whether to enable the clock signal for PCIe expansion card 110-1 and does not offer power-saving functionality. In other words, PCIe 4.0, in addition to retaining the PREST#2 function on pin PIN_B17, implements the CLK_REQ function on pin PIN_B12. PCIe expansion card 110-2 and motherboard 120-2 can communicate via pin PIN_B12 and achieve power-saving functions by controlling the clock signal. In other words, the two connection methods for the aforementioned clock signals cannot coexist. If the two clock signals are implemented simultaneously due to an incorrect connection, it will cause unexpected problems such as abnormal operation of the PCIe expansion card.

[0059] Between PCIe 3.0 and PCIe 4.0, which use different pins to implement functions such as clock signals (e.g., PCIe 3.0 uses pin PIN_B17, while PCIe 4.0 uses pin PIN_B12), designing a motherboard and corresponding computer system that simultaneously supports both types or ensures backward compatibility (i.e., compatibility with PCIe 3.0) for PCIe 4.0 is extremely difficult. Many motherboards only allow manual adjustment of settings (e.g., using jumpers) to select between PCIe 3.0 and PCIe 4.0. However, this approach is very inconvenient for users.

[0060] This invention provides a switching device and a corresponding controller in the motherboard device. This allows the motherboard device to determine the type of the PCIe expansion card and controls the switching device via the computer system's Basic Input / Output System (BIOS) or hardware circuitry (e.g., Platform Path Controller (PCH), Central Processing Unit, or Embedded Controller) to decide whether to pass a clock signal to a specific pin endpoint (e.g., pin endpoint PIN_B12). This enables the motherboard to support the PCIe 3.0 clock enable signal and PCIe 4.0 clock request function on the graphics card, thus successfully resolving potential incompatibility issues between the graphics card and the motherboard. The following embodiments conforming to this invention are provided as examples.

[0061] Figure 2This is a block diagram of a computer device 20 according to an embodiment of the present invention. The computer device 20 mainly includes a motherboard device 200, a PCIe expansion card 210, and other components (e.g., a central processing unit, etc.) configured on the motherboard device 200. The motherboard device 200 includes a bus slot, a switching circuit 250, and a controller 260. The bus slot is, for example, a high-speed peripheral component interconnect (PCIe) bus slot 225 (also referred to as a PCIe slot 225). The PCIe slot 225 includes a first pin endpoint PIN_B12 and a second pin endpoint PIN_B17. In this embodiment, the first pin endpoint PIN_B12 is connected to pin endpoint number 12 on the second side (e.g., side B) of the PCIe slot 225. The second pin endpoint PIN_B17 is connected to pin endpoint number 17 on the second side (side B) of the PCIe slot 225.

[0062] The switching circuit 250 includes a first terminal N1, a second terminal N2, a third terminal N3, and a control terminal CN. The first terminal N1 is coupled to the first pin endpoint PIN_B12. The second terminal N2 is coupled to the second pin endpoint PIN_B17. The third terminal N3 is coupled to the first terminal N1 and the clock enable terminal CKEN. The clock enable terminal CKEN is used to provide a clock enable signal.

[0063] The controller 260 provides a control signal CS1 to the control terminal CN of the switching circuit 250 based on the detection information of the bus slot. Specifically, the controller 260 is coupled to the PCIe slot 225 and the control terminal CN of the switching circuit 250. The detection information of the bus slot can be the type of PCIe expansion card configured in the PCIe slot, such as the device identification code of the PCIe expansion card or a voltage signal on a specific pin endpoint. The controller 260 determines the card type of the PCIe expansion card 210 as either a first PCIe type (e.g., PCIe 3.0) or a second PCIe type (e.g., PCIe 4.0) through the PCIe slot 225, and provides the control signal CS1 to the control terminal CN, thereby selectively activating either the first terminal N1 and the third terminal N3 or the second terminal N2 and the third terminal N3 in the switching circuit 250. In this embodiment, the controller 260 can be one or a combination of a basic input / output system (BIOS), a platform path controller (PCH), a central processing unit, and an embedded controller.

[0064] This section describes the two states of switching circuit 250: on and off. Switching circuit 250 is preset to the off state. The off state of switching circuit 250 means that the first terminal N1 and the second terminal N2 of switching circuit 250 are not connected to each other. Furthermore, the first terminal N1 and the clock enable terminal CKEN are normally connected. From... Figure 1BIt is known that the PCIe 4.0 expansion card 110-2 cannot enable the first terminal N1 and the second terminal N2 of the switching circuit 250 to conduct, so that the hot-plug signal on pin endpoint PIN_B17 of PCIe slot 120-2 and the clock request signal CLR_REQ on pin endpoint PIN_B12 of PCIe slot 120-2 do not conflict. That is, these two signals are transmitted through different paths. In other words, when Figure 2 Controller 260 determines that PCIe expansion card 210 is a PCIe 4.0 type PCIe expansion card (e.g., Figure 1B When the PCIe expansion card 110-2 is used, the switching circuit 250 will be turned off, that is, the control switching circuit 250 will be turned off so that its first terminal N1 and second terminal N2 are not connected to each other.

[0065] The conducting state of switching circuit 250 means that the first terminal N1 and the second terminal N2 in switching circuit 250 are mutually conductive, and the first terminal N1 is normally conductive with the clock enable terminal CKEN. Therefore, in the conducting state of switching circuit 250, the first terminal N1, the second terminal N2, and the third terminal N3 are at the same potential. Figure 1A In the PCIe 3.0 type described, pin PINB17 of the PCIe expansion card 110-1 is electrically coupled to pin PINA1. Furthermore, after the PCIe expansion card 110-1 is inserted into the PCIe slot 120-1, the clock enable signal (i.e., the signal on the GND terminal of the PCIe slot 120-1) is electrically coupled to pin PIN_B17 of the PCIe slot 120-1 through pins PINA1 and PINB17 of the PCIe expansion card 110-1. Moreover, since pin PIN_B12 of the PCIe slot 120-1 is inactive (N / A), the voltage on pin PIN_B12 will not affect the operation of the PCIe expansion card 110-1. In other words, when... Figure 2 Controller 260 determines that PCIe expansion card 210 is a PCIe 3.0 type PCIe expansion card (e.g., Figure 1A When the PCIe expansion card 110-1 is used, the switching circuit 250 will be activated, that is, the first terminal N1 and the second terminal N2 in the switching circuit 250 will be connected to each other.

[0066] Figures 3A to 3C These are schematic diagrams of the switching circuit 250 and the controller 260 according to the first to third embodiments of the present invention. Figures 3A to 3CThe switching circuit 250 in the circuit is implemented using an NMOS transistor NM1. The first terminal (e.g., the drain terminal) of transistor NM1 serves as the first terminal N1 of switching circuit 250. The second terminal (e.g., the source terminal) of transistor NM1 serves as the second terminal N2 of switching circuit 250. The gate terminal of transistor NM1 serves as the control terminal CN of switching circuit 250.

[0067] At Figure 3A In the first embodiment, the controller 260 can identify the card type of the PCIe expansion card 210 through its device identification code. In addition to the first pin endpoint PIN_B12 and the second pin endpoint PIN_B17, the PCIe slot also includes pin endpoints PIN_A13 and PIN_A14. Pin endpoints PIN_A13 and PIN_A14 are defined in the PCIe specification as the reference clock differential pair signal REFCLK. The controller 260 can set pin endpoints PIN_A13 and PIN_A14 to start when the computer device is powered on and the boot process begins, and then obtain relevant information about the PCIe expansion card 210, such as its device identification code, through the BIOS. In this embodiment, the timing of the controller 260's boot process can be included in... Figure 4 Step S410 is the power-on self-test. For example... Figure 3A In this embodiment, the controller 260 and the BIOS communicate via the BIOS detection endpoint BIOS_Detect to exchange information about the PCIe expansion card 210. In this way, the controller 260 can determine whether the PCIe expansion card 210 is PCIe 3.0 or PCIe 4.0 based on its device identification code, and selectively provide the control signal CS1 to the control terminal CN of the switching circuit 250.

[0068] Furthermore, the controller 260 may also include a corresponding memory, which stores the card type of the current PCIe expansion card 210. When the computer system boots up again or when it needs to determine the card type of the PCIe expansion card 210, the controller 260 selectively provides a control signal CS1 to the control terminal CN of the switching circuit 250 based on the card type of the PCIe expansion card 210 stored in the memory.

[0069] When the PCIe expansion card 210 is a PCIe 3.0 type, the controller 260 sets the control signal CS1 to logic high, causing the first and second terminals of transistor NM1 in the control circuit 250 to conduct, i.e., entering the conducting state of the control circuit 250. Conversely, when the PCIe expansion card 210 is a PCIe 4.0 type, the controller 260 sets the control signal CS1 to logic low, causing the first and second terminals of transistor NM1 in the control circuit 250 to de-conduct, i.e., entering the cut-off state of the control circuit 250.

[0070] The memory also contains device identification code and related PCIe type comparison information (e.g., comparison table), so that after the controller 260 obtains the device identification code of the PCIe expansion card 210, it can know the card type of the PCIe expansion card 210 through the aforementioned comparison information (comparison table).

[0071] At Figure 3B In the second embodiment, the controller 260 can identify the card type of the PCIe expansion card 210 via the voltage signal on the first pin endpoint PIN_B12. From Figure 1A and Figure 1B It can be seen that, Figure 1A The voltage signal on the first pin endpoint PIN_B12 is not fixed, but Figure 1B The voltage signal on the first pin endpoint PIN_B12 is the clock request signal CLK_REQ, which is at a stable voltage level when the device is first powered on. Therefore, in this embodiment, the card type of the PCIe expansion card 210 can be determined by judging the voltage signal on the first terminal N1 of the switching circuit 250. Figure 3B In the process, the controller 260 obtains the voltage signal on the first terminal N1 of the switching circuit 250 through the impedance elements RU21, RU22 and the terminal GPI, and then determines the card type of the PCIe expansion card 210. Figure 3B Operation of switching circuit 250 and controller 260 Figure 3A They are similar, but differ in that they use different methods to identify the card type of the PCIe expansion card 210.

[0072] Figure 3C The third embodiment integrates the methods used in the first and second embodiments for identifying the card type of the PCIe expansion card 210. Figure 3C The controller 260 can set the PCIe reference clock differential pair signal REFCLK to start when the computer device is powered on, and then detect the device identification code of its PCIe expansion card 210 through the BIOS to determine the card type of the PCIe expansion card 210, or it can determine the card type of the PCIe expansion card 210 by obtaining the voltage signal on the first terminal N1 of the switching circuit 250. Figure 3C Operation of switching circuit 250 and controller 260 Figure 3A and Figure 3B The three are similar, but differ in that they use different methods to identify the card type of the PCIe expansion card 210.

[0073] Figure 4 This is a flowchart of an expansion card detection method according to an embodiment of the present invention. Figure 4 Detection methods can be achieved through Figure 2 , Figures 3A to 3C The computer device is used to implement this. Figure 4 The detection method uses the Basic Input / Output System (BIOS) in the computer device as... Figure 2 Controller 260 is used as an example.

[0074] In step S405, the computer device is powered on to initiate the power-on process. At this time, the controller (e.g., the Basic Input / Output System (BIOS)) receives the standby voltage Vaux and begins startup, while the system operating voltage Vss gradually rises and stabilizes. In step S410, the controller is started and begins the Power-On Self-Test (POST) procedure. During the POST procedure, if it is determined that no PCIe expansion card is inserted into the PCIe slot, the process proceeds from step S410 to step S415, where the controller stops providing clock signals to the PCIe slot.

[0075] In the BIOS POST procedure, the controller in this embodiment will determine the PCIe slot (e.g., Figure 2 The PCIe expansion card type currently configured in PCIe slot 225 is detected. Furthermore, if the PCIe expansion card type currently configured in PCIe slot 225 is not present in the memory, or if the data for the PCIe expansion card stored in the memory is different from the PCIe expansion card type currently configured in PCIe slot 225, the detection method described in this embodiment of the invention is executed.

[0076] In detail, Figure 4 In step S420, the controller searches its memory for relevant data of a PCIe expansion card, or determines whether the data of a PCIe expansion card stored in the memory is the same as or corresponds to the current PCIe expansion card. The purpose of this step is to confirm whether the embodiment of the invention has detected and stored the data of the PCIe expansion card for subsequent use. If the type of PCIe expansion card currently configured in PCIe slot 225 is not stored in the memory, or if the data of the PCIe expansion card stored in the memory is different from the type of PCIe expansion card currently configured in PCIe slot 225, the process proceeds from step S420 to step S430.

[0077] If the controller's memory already contains data for the PCIe expansion card, this embodiment of the invention also needs to determine whether the data for the PCIe expansion card in the memory is the same as or corresponds to the PCIe expansion card currently being detected and interacted with by the controller. The reason for this is that the user may replace the PCIe expansion card in this PCIe slot in the computer device before powering on or by hot-swapping. Therefore, for the sake of rigor, during step S420, this embodiment of the invention still uses the controller (e.g., BIOS) to detect whether the corresponding information of the PCIe expansion card located in this PCIe slot has changed based on the corresponding data record (i.e., the data of the PCIe expansion card) in its own memory.

[0078] If step S420 is yes, the controller obtains the PCIe expansion card data from the memory, which includes the device identification code. The controller determines the card type of the PCIe expansion card based on the aforementioned device identification code, and sets the control signal CS1 based on the card type of the PCIe expansion card.

[0079] If step S420 is not successful, then proceed to step S430. In step S430, the controller determines whether the PCIe expansion card's identification code (e.g., ...) can be obtained from the BIOS detection endpoint BIOS_Detect via BIOS detection. Figure 3A The card type of the PCIe expansion card can be determined by (and corresponding descriptions), or by confirming the status of the signals on the endpoint GPI (such as...). Figure 3B The controller determines the card type of the PCIe expansion card based on the aforementioned device identification code or the state of the signal on the endpoint GPI. In step S440, the controller determines the card type of the PCIe expansion card based on the aforementioned device identification code or the state of the signal on the endpoint GPI, and decides whether the control signal CS1 is logic high or logic low.

[0080] Step S450 is when the control signal CS1 is logic high, indicating that the PCIe expansion card type is PCIe 3.0. The controller stores the PCIe expansion card type in the memory and sets CS1 to logic high.

[0081] Step S460 is when the control signal CS1 is logic low, indicating that the PCIe expansion card type is PCIe 4.0. The controller stores the PCIe expansion card type in the memory, sets CS1 to logic low, and adjusts the clock enable signal on the clock enable terminal CKEN based on the clock request function.

[0082] In step S470, the switching circuit will be in an on or off state according to the control signal set by the controller. After the other parts of the POST program have completed, the POST program ends in step S480. When the POST program is completed, the computer device is successfully powered on in step S490.

[0083] Figure 5 This is a timing diagram illustrating the signal waveforms in the JEDEC Solid State Technology Association's PCIe specification according to an embodiment of the present invention. JEDEC is a standards organization for the solid-state and semiconductor industry. Figure 5 The following signals are displayed sequentially: standby voltage Vaux, system operating voltage Vss, reset signal PERST# on pin PIN_A11, hot-plug detection signal PRESENT (PCIe 3.0 type, pin PIN_B17), reference clock signal REFCLK (PCIe 3.0 type, pins PIN_A13 and PIN_A14), hot-plug detection signal PRESENT (PCIe 4.0 type, pin PIN_B17), clock request signal CLK_REQ (PCIe 4.0 type, pin PIN_B12), and reference clock signal REFCLK (PCIe 4.0 type, pins PIN_A13 and PIN_A14). For PCIe 3.0 and earlier versions, the reference clock signal REFCLK on pins PIN_A13 and PIN_A14 is continuously output after power-on. For PCIe 4.0 and later versions, the reference clock signal REFCLK on pin endpoints PIN_A13 / A14 is controlled by the clock request signal CLK_REQ (pin endpoint PIN_B12). The system outputs the reference clock signal REFCLK (pin endpoints PIN_A13 and PIN_A14) when the CLK_REQ voltage level is pulled low, and stops outputting the reference clock signal REFCLK (pin endpoints PIN_A13 and PIN_A14) when the voltage level is pulled high.

[0084] Figure 6 These are waveform diagrams of various signals in the detection method according to an embodiment of the present invention. Figure 6 The control signals related to the PCIe bus CLK_REQ are presented at the first pin endpoint (PIN_B12) and the second pin endpoint (PIN_B17) to control whether the reference clock signal REFCLK (pin endpoints PIN_A13 and PIN_A14) is sent. Simultaneously, Figure 6 The timing diagrams for the control signal CS1 (PCIe 3.0) and the control signal CS1 (PCIe 4.0) corresponding to PCIe 3.0 type are also presented.

[0085] Please refer to Figure 5 and Figure 6Marks 510 and 610 indicate that the system operating voltage Vss is in a stable state and execution has begun. Figure 4 Detection method. Marks 520 and 620 indicate that when a PCIe expansion card of type PCIe 3.0 is inserted, the motherboard device begins to provide a reference clock signal REFCLK to the PCIe expansion card. Figure 6 Mark 630 indicates the time point at which the controller determines the card type of the PCIe expansion card, which is... Figure 4 The execution time points of steps S425 and S440. Figure 6 Marker 640 indicates that, after the computer device is powered on, the PCIe 4.0 type sets the PCIe expansion card to power-saving mode via the clock request signal CLK_REQ.

[0086] The designation S450 is used to indicate Figure 4 In step S450, the controller determines that the PCIe expansion card is of type PCIe 3.0, and therefore sets the control signal CS1 to logic high. The label S460 indicates... Figure 4 In step S460, the controller determines that the PCIe expansion card is of type PCIe 4.0, and therefore keeps the control signal SCC1 set to logic low.

[0087] The markings S470-1 and S470-2 are used to indicate Figure 4 The situation in step S470. Marked as S470-1, when the control signal CS1 is set to logic high, the switching circuit is in the ON state due to the control signal CS1. That is, the first terminal N1 and the second terminal N2 in the switching circuit 250 are mutually connected, and the first terminal N1 and the clock enable terminal CKEN are normally connected. Marked as S470-1, when the control signal CS1 is set to logic low, the switching circuit is in the OFF state due to the control signal CS1. That is, the first terminal N1 and the second terminal N2 in the switching circuit 250 are not mutually connected.

[0088] In summary, the motherboard device and expansion card detection method described in this embodiment of the invention, through a switching circuit and the detection information of the expansion card (e.g., expansion card type detection), selectively provides the corresponding signals (e.g., clock signals, clock request signals) of the expansion card to the correct pin endpoints for different card types. Therefore, this embodiment of the invention enables the motherboard device to smoothly support expansion cards with different bus types (e.g., PCIe 3.0 and PCIe 4.0 PCIe expansion cards), avoiding incompatibility between the motherboard device and the expansion card.

[0089] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A motherboard device, comprising: A bus slot, including a first pin endpoint and a second pin endpoint; The switching circuit includes a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal is coupled to the first pin endpoint, the second terminal is coupled to the second pin endpoint, and the third terminal is coupled to the first terminal and a clock enable terminal, wherein the clock enable terminal is used to provide a clock enable signal. as well as A controller, coupled to the bus slot and the control terminal of the switching circuit, wherein the controller is configured to provide a control signal to the control terminal based on the detection information of the bus slot, so as to selectively connect the first terminal and the third terminal or the second terminal and the third terminal in the switching circuit.

2. The motherboard device of claim 1, wherein the bus slot is a high-speed peripheral interconnect slot, and the detection information is the high-speed peripheral interconnect expansion card type configured in the high-speed peripheral interconnect slot.

3. The motherboard device of claim 2, wherein the first pin endpoint is connected to pin endpoint 12 on the second side of the high-speed peripheral component interconnect slot, and the second pin endpoint is connected to pin endpoint 17 on the second side of the high-speed peripheral component interconnect slot.

4. The motherboard device as claimed in claim 1, wherein the switching circuit is preset to a cut-off state, and the cut-off state means that the first terminal and the second terminal of the switching circuit are not connected to each other.

5. The motherboard device of claim 2, wherein the controller obtains the device identification code of the high-speed peripheral interconnect expansion card through the detection of the basic input / output system, and determines the type of the high-speed peripheral interconnect expansion card based on the device identification code of the high-speed peripheral interconnect expansion card.

6. The motherboard device of claim 2, wherein the controller determines the type of the high-speed peripheral component interconnect expansion card by judging the voltage signal on the first terminal of the switching circuit.

7. The motherboard device of claim 2, wherein when the controller determines that the high-speed peripheral component interconnect expansion card is a first high-speed peripheral component interconnect type, it turns on the first terminal and the second terminal of the switching circuit through the control signal, thereby turning on the second terminal and the third terminal, and... When the controller determines that the high-speed peripheral component interconnect expansion card is of the second high-speed peripheral component interconnect type, it cuts off the first and second terminals of the switching circuit through the control signal, and makes the first terminal and the third terminal conduct.

8. The motherboard device of claim 1, wherein the switching circuit comprises: A transistor, wherein its first terminal serves as the first terminal of the switching circuit, its second terminal serves as the second terminal of the switching circuit, and its gate terminal serves as the control terminal of the switching circuit.

9. The motherboard device of claim 1, wherein the controller is one or a combination of a basic input / output system, a platform path controller, a central processing unit, and an embedded controller.

10. The motherboard device as claimed in claim 2, further comprising: memory, The controller stores the type of the high-speed peripheral component interconnect expansion card in the memory. Furthermore, the controller is configured to provide the control signal to the control terminal of the switching circuit according to the type of the high-speed peripheral component interconnect expansion card stored in the memory.

11. A method for detecting an expansion card in a motherboard device, the detection method comprising: Determine the detection information of the bus slot, wherein the bus slot includes a first pin endpoint and a second pin endpoint; Based on the detection information, the controller provides a corresponding control signal to the control terminal of the switching circuit. The switching circuit includes a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal is coupled to the first pin endpoint, the second terminal is coupled to the second pin endpoint, and the third terminal is coupled to the first terminal and the clock enable terminal, wherein the clock enable terminal is used to provide a clock enable signal. According to the provided control signal, the switching circuit selectively connects the first terminal and the third terminal or connects the second terminal and the third terminal.

12. The expansion card detection method of claim 11, wherein the bus slot is a high-speed peripheral component interconnect (PSI) slot, and the detection information is the type of high-speed peripheral component interconnect (PSI) expansion card configured in the high-speed PSI slot.

13. The expansion card detection method of claim 12, wherein the first pin endpoint is connected to the 12th pin endpoint on the second side of the high-speed peripheral component interconnect slot, and the second pin endpoint is connected to the 17th pin endpoint on the second side of the high-speed peripheral component interconnect slot.

14. The expansion card detection method as described in claim 11, wherein the switching circuit is preset to a cut-off state, and the cut-off state means that the first terminal and the second terminal of the switching circuit are not connected to each other.

15. The expansion card detection method as described in claim 12, wherein the step of determining the type of the high-speed peripheral component interconnect (PSI) expansion card in the high-speed peripheral component interconnect slot includes: The device identification code of the high-speed peripheral interconnect expansion card is obtained from the basic input / output system through detection, and the type of the high-speed peripheral interconnect expansion card is determined based on the device identification code of the high-speed peripheral interconnect expansion card.

16. The expansion card detection method as described in claim 12, wherein the step of determining the type of the high-speed peripheral component interconnect (HS-IP) expansion card in the high-speed peripheral component interconnect (HS-IP) slot includes: The type of the high-speed peripheral component interconnect expansion card is determined by judging the voltage signal on the first terminal of the switching circuit.

17. The expansion card detection method of claim 12, wherein the controller provides a corresponding control signal to the control terminal of the switching circuit according to the type of the high-speed peripheral component interconnect expansion card, and the step of selectively switching the first terminal and the third terminal or switching the second terminal and the third terminal according to the provided control signal includes: In response to the high-speed peripheral component interconnect expansion card being of the first high-speed peripheral component interconnect type, the first and second terminals of the switching circuit are turned on by the control signal, thereby turning on the second terminal and the third terminal. as well as In response to the high-speed peripheral component interconnect expansion card being of the second high-speed peripheral component interconnect type, the first and second terminals of the switching circuit are cut off by the control signal, and the first terminal is connected to the third terminal.

18. The expansion card detection method as described in claim 12, further comprising: The high-speed peripheral component interconnect expansion card type is stored in the memory; as well as The control signal is provided to the control terminal of the switching circuit through the high-speed peripheral component interconnect expansion card type stored in the memory.

19. The expansion card detection method as described in claim 18, further comprising: The power-on self-test (POST) procedure of the basic input / output system determines the type of the high-speed peripheral component interconnect (HS-IP) expansion card currently configured in the high-speed peripheral component interconnect slot. as well as The detection method is executed in response to the absence of a high-speed peripheral interconnect expansion card type currently configured in the high-speed peripheral interconnect slot in the memory, or in response to the presence of high-speed peripheral interconnect expansion card data stored in the memory that is different from the high-speed peripheral interconnect expansion card type currently configured in the high-speed peripheral interconnect slot.

20. The expansion card detection method as described in claim 19, further comprising: In response to the determination in the BIOS self-test procedure that no High-Speed ​​Peripheral Component Interconnect (HS-PIC) expansion card is configured into the H-PIC slot, the clock enable signal is stopped.

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