Storage data protection method and device, equipment and storage medium

Abstract

The invention discloses a storage data protection method and device, equipment and a storage medium, and the method comprises the steps: reading a threshold voltage measurement value in a calibration data block, and obtaining a first measurement value; according to the first measurement value, calculating the data retention duration of the stored data in the NAND FLASH memory; and under the condition that the data retention duration reaches a preset time threshold value, carrying out data storage scanning on the NAND FLASH memory and executing data refreshing so as to protect storage data in the NAND FLASH memory. Therefore, the data retention duration is dynamically calculated by reading the threshold voltage measurement value of the calibration data block, and the data scanning and refreshing operation is triggered when the preset threshold value is reached, so that the problem of maintenance lag caused by a fixed refreshing mechanism in the prior art can be effectively solved; the actual retention state of the stored data can be monitored in real time, the data maintenance operation can be dynamically triggered, and the problem of maintenance lag or excessive refresh caused by a fixed refresh cycle is effectively avoided.

Description

Technical Field

[0001] This application relates to the field of storage device technology, and in particular to a storage data protection method, apparatus, device and storage medium. Background Technology

[0002] In practical applications of NAND flash memory, managing its read, write, erase, and data maintenance operations through a main control chip is crucial to ensuring the reliability of stored data. This technology is widely used in electronic devices such as solid-state drives and embedded storage modules. NAND flash memory uses floating-gate transistors as its basic storage units, and its data storage mechanism relies on the ability to retain charge. However, because the floating-gate charge in the storage unit naturally leaks over time, this data storage characteristic, known as Data Retention, causes the threshold voltage for stored data to gradually decay. When data retention exceeds a certain period without timely processing, it will cause read errors or even permanent data loss.

[0003] Currently, the mainstream data maintenance solution relies on the timing refresh mechanism of the main control chip to periodically maintain stored data. While this solution is effective under normal operating conditions, it has significant drawbacks in practical applications. When the NAND flash memory is powered off or the main control chip enters sleep mode, the timing refresh function is forced to stop. Due to the lack of effective monitoring methods, the system cannot accurately obtain the actual retention time of stored data, resulting in the inability to promptly identify and maintain risky data with excessively long retention times. This situation is particularly severe in backup storage devices that are not powered on for extended periods, potentially leading to irreversible loss of critical data.

[0004] Another limitation of existing technical solutions is that they rely on fixed time periods for data refresh, failing to fully consider the individual differences of different storage units in actual usage environments. Factors such as process variations, usage frequency, and ambient temperature of NAND FLASH memory can all affect the data retention characteristics of specific storage units. A uniform timed refresh strategy is difficult to adapt to these diverse needs, which may result in unnecessary refresh operations that affect the lifespan of the device, or may miss high-risk data blocks that truly require maintenance.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main objective of this application is to provide a storage data protection method, apparatus, device, and storage medium that can monitor the actual retention status of stored data in real time and dynamically trigger data maintenance operations, effectively avoiding the problems of maintenance lag or excessive refresh caused by fixed refresh cycles.

[0007] Firstly, this application proposes a method for protecting stored data, which includes:

[0008] The data protection methods applied to the controller of NAND FLASH memory, which contains calibration data blocks, include:

[0009] Read the threshold voltage measurement value from the calibration data block to obtain the first measurement value;

[0010] Based on the first measurement value, calculate the data retention time of the stored data in the NAND FLASH memory;

[0011] When the data retention time reaches a preset time threshold, the NAND FLASH memory is scanned for data storage and refreshed to protect the stored data in the NAND FLASH memory.

[0012] Furthermore, this application also proposes that the method for protecting stored data further includes:

[0013] A calibration data block is defined at a preset location in the NAND FLASH memory. The calibration data block is used to record the threshold voltage, which is positively correlated with the retention time of the data stored in the NAND FLASH memory.

[0014] Furthermore, this application also proposes a step of defining a calibration data block at a predetermined location in the NAND FLASH memory, including:

[0015] During the mass production testing phase of NAND FLASH memory, an independent storage area is divided in the physical storage array of NAND FLASH memory as a candidate calibration data block. The candidate calibration data block and the data block containing the stored data in the NAND FLASH memory use the same storage medium and process parameters.

[0016] Write preset reference data into the candidate calibration data block so that the initial threshold voltage in the candidate calibration data block is within the preset reference range;

[0017] The validity of the candidate calibration data blocks is verified to ensure that the change of the threshold voltage of the candidate calibration data blocks over time is consistent with the data stored in the NAND FLASH memory.

[0018] The validated candidate calibration data blocks are defined as calibration data blocks.

[0019] Furthermore, this application also proposes a step for calculating the data retention time of stored data in the NAND FLASH memory based on a first measurement value, including:

[0020] Obtain the initial threshold voltage measurement value of the calibration data block to obtain the second measurement value; wherein, the second measurement value is the reference threshold voltage recorded when the calibration data block is defined;

[0021] The difference between the first and second measured values ​​is calculated to obtain the threshold voltage change.

[0022] Call the preset fitting curve of threshold voltage change and storage time. The fitting curve is a function curve generated by performing retention tests on the same type of calibration data blocks for multiple time periods. The fitting curve is used to reflect the correspondence between threshold voltage change and the retention time of stored data.

[0023] Based on the first measurement, the fitted curve is queried to determine the data retention time corresponding to the stored data in the NAND FLASH memory.

[0024] Furthermore, this application also proposes steps for protecting the stored data in the NAND FLASH memory by performing data storage scanning and data refresh on the NAND FLASH memory, including:

[0025] Perform a data storage scan on the NAND flash memory to locate risky data blocks. Risky data blocks are those whose threshold voltage measurement is below a preset normal threshold voltage range, or whose threshold voltage change exceeds a preset safe change threshold.

[0026] Repair the stored data in the risky data block to protect the stored data in the NAND FLASH memory.

[0027] Furthermore, this application also proposes steps for repairing stored data in risky data blocks, including:

[0028] Read the risk storage data from the risk data block and write the risk storage data to the temporary cache area;

[0029] The risky stored data in the temporary buffer is erased to remove any residual charge.

[0030] The valid data in the temporary cache area is returned and written to the risky data block, so that the threshold voltage of the risky data block is restored to the preset normal threshold voltage range, thereby repairing the risky stored data.

[0031] Furthermore, this application also proposes that the method for protecting stored data further includes:

[0032] Detect the operating status of the NAND FLASH memory;

[0033] The steps for reading the threshold voltage measurement value from the calibration data block include:

[0034] The threshold voltage measurement value in the calibration data block is read when the NAND FLASH memory is in a power-off state or in a sleep state.

[0035] Furthermore, this application also proposes a data protection device applied to the controller of a NAND FLASH memory, wherein calibration data blocks are defined in the NAND FLASH memory, and the data protection device includes:

[0036] The reading unit is used to read the threshold voltage measurement value in the calibration data block to obtain the first measurement value;

[0037] The calculation unit is used to calculate the data retention time of the stored data in the NAND FLASH memory based on the first measurement value;

[0038] The protection unit is used to perform data storage scans and data refreshes on the NAND FLASH memory when the data retention time reaches a preset time threshold, in order to protect the stored data in the NAND FLASH memory.

[0039] Furthermore, this application also proposes an apparatus comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the above-described data protection method.

[0040] Furthermore, this application also proposes a storage medium storing an executable program for the storage data protection method, which, when executed, implements the steps of the aforementioned storage data protection method.

[0041] As can be seen from the above, the data protection method, apparatus, device and storage medium provided in this application dynamically calculates the data retention time by reading the threshold voltage measurement value of the calibration data block, and triggers data scanning and refresh operations when the preset threshold is reached. This can effectively solve the maintenance lag problem caused by the fixed refresh mechanism in the prior art, and can monitor the actual retention status of the stored data in real time and dynamically trigger data maintenance operations, effectively avoiding the maintenance lag or over-refreshing problems caused by the fixed refresh cycle. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A flowchart illustrating the first embodiment of the data storage protection method provided in this application;

[0045] Figure 2 A flowchart illustrating a second embodiment of the data storage protection method provided in this application.

[0046] Figure 3 A flowchart illustrating a third embodiment of the data storage protection method provided in this application;

[0047] Figure 4 A flowchart illustrating the fourth embodiment of the data storage protection method provided in this application.

[0048] Figure 5 This is a schematic diagram of a data storage protection device proposed in this application.

[0049] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0050] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0051] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0052] In traditional NAND flash memory data maintenance solutions, the timing refresh mechanism driven by the system clock of the main controller chip has inherent flaws. When the storage device enters a power-off state or the main controller chip is in sleep mode, the timer stops running, making it impossible to continuously track the actual charge retention state of the storage cells. Since the charge leakage rate of NAND flash storage media is affected by multiple factors such as ambient temperature, number of erase / write cycles, and process deviations, prediction models based solely on time accumulation cannot accurately reflect the true data retention state of the storage cells, resulting in inaccurate timing of charge decay monitoring and data refresh operations.

[0053] For example, in solid-state drives (SSDs) employing multi-layer storage cell technology, when the controller chip enters low-power mode, the timer stops working, preventing the updating of data block retention time records. When the ambient temperature fluctuates drastically, the actual charge leakage rate of the storage cells may exceed the range predicted by the preset model. At this time, the threshold voltage of some data blocks has fallen below the reliable read level, but because the controller chip cannot obtain the actual retention time, it fails to trigger the data refresh operation in time. After the device is powered on again, the read operations of these data blocks will produce uncorrectable errors, leading to user data loss or file system corruption.

[0054] If the above problems are not addressed, the data integrity guarantee mechanism of the storage system will have systemic vulnerabilities. Threshold voltage drift caused by charge leakage will have a cumulative effect over time, leading to increased read interference between adjacent storage cells. Failed data blocks that are not refreshed in time may cause an exponential increase in the bit error rate, resulting in irreversible damage to the physical structure of the storage medium. In non-volatile storage applications of industrial control systems, such data failures may directly lead to the loss of control parameters, causing equipment malfunctions or production accidents.

[0055] Faced with the aforementioned problems, this application first considers how to establish a charge decay monitoring mechanism independent of the system clock. Traditional timing refresh schemes rely on the continuous operation of the main control chip, but the timing function fails when power is off, making it impossible to track the actual retention time. While using an independent hardware timer can solve the power-off timing problem, it increases chip area and power consumption, and cannot eliminate the influence of environmental factors on the charge leakage rate. Another approach is to monitor temperature changes through environmental sensors and correct the timing model, but sensor data acquisition requires continuous power and cannot work in sleep mode.

[0056] Further analysis in this application reveals that charge leakage directly manifests as a drift in the threshold voltage of the storage cell, a physical characteristic directly related to the process parameters of the storage medium. If a monitoring unit with the same charge decay pattern can be installed within the storage array, the actual retention status of the stored data can be indirectly reflected by measuring its voltage change. This approach eliminates the need for external timers or sensors, and voltage measurements can be performed even when the main controller is in sleep mode through intermittent wake-ups.

[0057] Based on this, this application provides a storage data protection method applied to the controller of a NAND FLASH memory, wherein calibration data blocks are defined in the NAND FLASH memory. (See also...) Figure 1 , Figure 1 A flowchart illustrating the first embodiment of the data storage protection method provided in this application.

[0058] In this embodiment, the data storage protection method includes steps S11 to S13:

[0059] Step S11: Read the threshold voltage measurement value in the calibration data block to obtain the first measurement value.

[0060] The calibration data block refers to a pre-defined independent storage area within the physical storage array of the NAND FLASH memory. It uses the same storage medium and process parameters as the storage data block. By writing reference data to this calibration data block and verifying the consistency of its threshold voltage change pattern with that of the storage data block, synchronous monitoring of charge decay characteristics is achieved. The configuration of this calibration data block allows the charge retention status of the stored data to be indirectly reflected through its threshold voltage change even when the power is off or in sleep mode.

[0061] The threshold voltage measurement refers to the process of detecting the voltage of the storage cells of the calibration data block through the controller when the NAND FLASH memory is in a power-off or sleep state, and obtaining the actual measured value of the current threshold voltage. This operation does not rely on the system clock, thus solving the problem of the traditional timing refresh mechanism failing in non-working states.

[0062] Step S12: Calculate the data retention time of the stored data in the NAND FLASH memory based on the first measurement value.

[0063] The calculation of data retention time involves estimating the charge retention time of the stored data block based on the difference between the current threshold voltage and the initial reference value of the calibration data block, by querying a pre-established fitting curve of voltage change versus storage time. This fitting curve is generated through multi-period retention tests on similar calibration data blocks to ensure that the estimated results match the actual charge leakage level.

[0064] Step S13: When the data retention time reaches the preset time threshold, perform data storage scan and data refresh on the NAND FLASH memory to protect the stored data in the NAND FLASH memory.

[0065] The data storage scanning and refresh process involves performing a full scan of the storage array when the estimated retention time reaches a preset threshold. This scan identifies risky data blocks with abnormal threshold voltages or excessive voltage changes, and restores their charge state by erasing residual charge and rewriting valid data. This operation directly compensates for threshold voltage deviations caused by charge leakage, rather than relying on periodic timing triggers.

[0066] The core innovation of this application lies in setting up calibration data blocks with physical characteristics identical to the stored data blocks, and dynamically calculating the actual data retention time using the threshold voltage change of these calibration data blocks, thus overcoming the limitation of traditional timing mechanisms failing in power-off or sleep states. This solution establishes a monitoring model based on the physical laws of charge decay in storage media, achieving accurate identification of retention time through offline voltage measurement and curve fitting queries, and proactively refreshing the data when a critical value is reached, fundamentally solving the data loss problem caused by insufficient data maintenance during non-working states.

[0067] The working process and principle of this application are as follows: a data protection method is applied to the controller of a NAND flash memory. A calibration data block is defined within the NAND flash memory to monitor the charge decay state of the stored data. First, the threshold voltage measurement value in the calibration data block is read to obtain the first measurement value. The calibration data block uses the same storage medium and process parameters as the stored data and has the same charge decay characteristics. By measuring the threshold voltage change of the calibration data block, the charge retention state of the stored data can be indirectly reflected.

[0068] Based on the first measurement value, the data retention time in the NAND FLASH memory is calculated. The specific calculation process includes obtaining the initial threshold voltage value of the calibration data block, calculating the threshold voltage change, and then querying a preset fitting curve between the threshold voltage change and storage time to determine the corresponding data retention time. The fitting curve is generated by performing retention tests on the same type of calibration data block over multiple time periods, reflecting the correspondence between the threshold voltage change and the data retention time.

[0069] When the calculated data retention time reaches a preset time threshold, a data storage scan and data refresh are performed on the NAND FLASH memory. The data storage scan is used to locate risky data blocks, i.e., data blocks whose threshold voltage measurement values ​​are below the preset normal range or whose changes exceed the safety threshold. The stored data in the risky data blocks is repaired, including reading the data into a temporary cache, erasing the original data block to remove residual charge, and rewriting the valid data back to restore the threshold voltage of the data block to the normal range.

[0070] This method is independent of the system clock and can accurately monitor the actual retention status of stored data in power-off states or master controller sleep modes. Synchronous monitoring of storage medium characteristics is achieved through data block calibration settings. The voltage change-based calculation method eliminates dependence on the system clock, making it particularly suitable for data monitoring in non-operating states. Pre-set fitting curves ensure the accuracy of data retention time estimation. The data refresh operation fundamentally solves the data failure problem caused by charge leakage by scanning and locating risky data blocks and performing charge compensation.

[0071] As a preferred embodiment, the solution of this application is implemented as follows: An independent storage area is partitioned within the physical storage array of the NAND FLASH memory as a calibration data block. The calibration data block uses the same storage medium and process parameters as the data block containing the stored data. Preset reference data is written to the calibration data block to ensure that the initial threshold voltage is within the preset reference range. The validity of the calibration data block is verified to ensure that the change in its threshold voltage over time is consistent with that of the stored data.

[0072] When the NAND flash memory is powered off or the controller is in sleep mode, the threshold voltage measurement value of the calibration data block is read to obtain the first measurement value. The initial threshold voltage value recorded when the calibration data block was defined is obtained as the second measurement value. The difference between the first measurement value and the second measurement value is calculated to obtain the threshold voltage change.

[0073] The system retrieves a pre-established fitted curve relating threshold voltage change to storage time. This curve was generated by performing retention tests on similar calibration data blocks over multiple time periods, reflecting the correlation between threshold voltage change and data retention duration. Based on the calculated threshold voltage change, the system queries the fitted curve to determine the corresponding data retention duration.

[0074] When the data retention time reaches a preset time threshold, a data storage scan is performed on the NAND FLASH memory. During the scan, risky data blocks are identified, namely data blocks whose threshold voltage measurement values ​​are below the preset normal range or whose changes exceed the safety threshold.

[0075] Repair the stored data in the risky data block. Read the data from the risky data block and write it to a temporary buffer. Erase the data in the temporary buffer to remove residual charge. Rewrite the valid data in the temporary buffer back into the risky data block, restoring the threshold voltage of the data block to the preset normal range.

[0076] As one implementation, before step S10, the data protection method proposed in this application further includes: detecting the working state of the NAND FLASH memory;

[0077] The threshold voltage measurement value in the calibration data block is read when the NAND FLASH memory is in a power-off state or in a sleep state.

[0078] The step of detecting the operating status can be triggered by signals from a hardware status register or the power management module. For example, a power-down state can be determined when the power supply voltage is lower than a preset threshold, or a sleep state can be determined when the main control chip enters a low-power mode. The operation of reading the threshold voltage measurement value can be performed periodically in non-operating states, such as initiating a reading process every 24 hours, or triggering an emergency read when a voltage fluctuation exceeding 5% is detected. The threshold voltage measurement can be completed through a charge sensing circuit, with measurement accuracy controllable within ±0.1V.

[0079] In power-off or sleep mode, the reading operation of the calibration data block is decoupled from the timing refresh mechanism of the main control chip. The operation of necessary circuits is maintained by an independent power supply module, such as using a spare capacitor or button battery to provide temporary power to the charge sensing circuit. The calculation of the threshold voltage change can be based on a pre-stored reference threshold voltage, for example, an initial reference value of 3.5V. When the current value is detected to drop to 2.8V, a data retention limit judgment is triggered.

[0080] Specifically, when the NAND FLASH memory is detected to be in a power-down or sleep state, the power management module sends an interrupt signal to the main control chip, triggering the threshold voltage reading program. The charge sensing circuit measures the calibration data block at a preset sampling frequency, for example, acquiring the voltage value every 30 seconds, and stores the measurement results in a non-volatile buffer. The main control chip calculates the actual data retention time by comparing the current measured value with the initial reference value and calling the fitted curve. If the calculation result shows that the retention time exceeds 72 hours, the main control chip immediately performs data scanning and refresh operations after power is restored.

[0081] In sleep mode, read operations are achieved by reducing the power consumption of the charge sensing circuit, for example, by limiting the operating current to below 10mA, while shutting down unnecessary peripheral circuits. Measurement data is transmitted to the main control chip's dedicated register via a serial interface, avoiding the occupation of system bus resources. When a voltage change exceeding a safety threshold is detected, such as a single measurement drop exceeding 0.3V, the main control chip can wake up in advance and execute the data maintenance process.

[0082] Therefore, it can continuously monitor data retention status even when not in operation, solving the maintenance failure problem caused by power outages in the timing refresh mechanism. Through a detection and reading mechanism independent of the main control's operating status, it ensures that the calculation of data retention time is not limited by the device's operating mode, effectively reducing the risk of data loss due to charge leakage.

[0083] As a preferred embodiment, the solution of this application specifically includes: the data storage protection method further includes detecting the operating status of the NAND FLASH memory. Specifically, it can be determined whether the memory is in a power-down state or a sleep state by monitoring the power supply status of the NAND FLASH memory and the operating mode of the main control chip. For example, a status monitoring module can be set in the main control chip, which monitors the operating status of the memory in real time by sampling the power supply voltage of the NAND FLASH memory and the operating clock frequency of the main control chip.

[0084] Furthermore, when reading the threshold voltage measurement value from the calibration data block, the operating status of the NAND FLASH memory is first determined. If the memory is detected to be in a power-off or sleep state, a read operation is triggered. Therefore, even if the main control chip is not functioning properly, the threshold voltage information of the calibration data block can still be obtained.

[0085] Specifically, a separate low-power read circuit can be configured within the NAND flash memory, maintaining minimal functionality even when the memory is in a power-down or sleep state. When these abnormal operating states are detected, the low-power read circuit is activated, performing a threshold voltage measurement operation on the calibration data block. The measured data can be temporarily stored in a dedicated non-volatile cache for further processing after the memory resumes normal operation.

[0086] As a preferred implementation, a fixed time interval, such as every 24 hours, can be set to trigger the reading operation of the memory's operating status detection and calibration data blocks. This ensures that even during prolonged periods of inactivity, threshold voltage changes can be periodically acquired, providing necessary data support for subsequent data retention duration calculations.

[0087] Through the above technical solution, this application enables the monitoring of data retention time even when the NAND FLASH memory is in a power-off or sleep state. This method overcomes the limitation of traditional timing refresh mechanisms, which can only be executed when the main control chip is working normally, allowing the storage device to continuously monitor the actual data retention status under various operating conditions. This significantly improves the reliability and continuity of data protection, effectively reducing the risk of data loss due to prolonged power outages or sleep states. Simultaneously, this method also optimizes the power consumption management of the storage device, ensuring data security without significantly increasing the device's energy consumption in non-operating states.

[0088] This application addresses the problem of NAND flash memory's inability to accurately identify the actual retention time of stored data during power-down states or controller sleep modes. By setting calibration data blocks within the storage array and utilizing their identical charge decay characteristics to the stored data, dynamic monitoring of the charge retention status of the stored data is achieved. This method is independent of the system clock and can continuously track the actual charge status of storage cells in non-operating states. The actual retention time of stored data is calculated based on the threshold voltage change of the calibration data blocks, overcoming the limitation of traditional timers failing during power-down states. When the monitored data retention time reaches a critical value, a data scanning and refresh mechanism is promptly initiated, effectively preventing data failure caused by charge leakage. This monitoring method based on storage medium characteristics accurately reflects the impact of factors such as ambient temperature and the number of erase / write cycles on the charge leakage rate, improving the accuracy and timeliness of data maintenance. By scanning and locating risky data blocks and performing charge compensation, the problem of data errors and loss caused by charge leakage is fundamentally solved, improving the data integrity and reliability of the storage system.

[0089] Based on the first embodiment, a second embodiment of the data protection method of this application is proposed. Please refer to [link to embodiment]. Figure 2 , Figure 2 A flowchart illustrating a second embodiment of the data storage protection method provided in this application.

[0090] In this embodiment, the data storage protection method further includes step S10:

[0091] Step S10: Define a calibration data block at a preset location in the NAND FLASH memory.

[0092] The calibration data block is used to record the threshold voltage, which is positively correlated with the retention time of data stored in the NAND FLASH memory.

[0093] The preset location is limited to a specific area of ​​the physical memory array, such as the middle of adjacent memory blocks or the edge of the memory plane. The candidate calibration data block and the memory data block use the same storage medium and process parameters to ensure synchronization in charge leakage rate. The write parameters for the reference data include the programming voltage amplitude and pulse width; for example, the same programming voltage value as the user data is used, and the initial threshold voltage is controlled within the range of 3.5V to 4.2V. Validity verification is achieved by periodically sampling the threshold voltage change of the candidate calibration data block; for example, the voltage value is measured every 24 hours. Verification is considered successful when the voltage decay rate of three consecutive measurements deviates from the charge leakage rate of the memory data block by less than 5%. The physical binding of the calibration data block and the memory data block is achieved through a shared bus structure of the memory cell array, ensuring that both have the same charge retention characteristics under temperature changes and electric field interference.

[0094] Specifically, calibration data blocks are pre-allocated to the physical center of the storage array, sharing the same manufacturing process parameters as the user data blocks' storage cells. During mass production testing, candidate calibration data blocks are programmed with an all-"1" data pattern and the same programming voltage pulse as the user data blocks is applied to stabilize the initial threshold voltage at a reference value of 3.8V. During device operation, the calibration data blocks and user data blocks undergo a charge leakage process synchronously. When the device enters sleep mode, the main control chip reads the current threshold voltage value of the calibration data blocks; for example, if the voltage drops to 2.9V, it calculates that the stored data has been retained for 120 hours based on a preset voltage-time correspondence. This voltage change directly reflects the degree of charge decay in the storage medium. By limiting the physical location of the calibration data blocks to the storage plane where the user data blocks are located, it ensures that both maintain a synchronized charge leakage pattern during the medium aging process. Thus, even in a power-off state, the retention status of user data can still be accurately inferred from the voltage changes of the calibration data blocks. When the threshold voltage change exceeds the safety threshold, the system automatically triggers a data refresh mechanism, effectively avoiding data errors caused by excessive charge leakage.

[0095] As a preferred embodiment, the solution of this application is implemented as follows: A calibration data block is defined at a preset location in the NAND FLASH memory. This calibration data block is used to record a threshold voltage, which is positively correlated with the retention time of data stored in the NAND FLASH memory. Specifically, an independent storage area is partitioned as a calibration data block within the physical storage array of the NAND FLASH memory. The calibration data block can be located at a specific location in the storage array, such as the first or last page of each storage cell. Further, preset reference data is written into the calibration data block so that the initial threshold voltage in the calibration data block is within the preset reference range. Thus, the change in the threshold voltage of the calibration data block can reflect the charge leakage situation of the entire memory.

[0096] Through the above technical solution, this application solves the problem of consistency between the physical characteristics of the calibration benchmark and the stored data. The selection of the preset location ensures that the calibration data block and the stored data block are in the same storage medium environment, avoiding calibration failure due to process deviations or regional characteristic differences. The threshold voltage recorded by the calibration data block directly reflects the change in the charge state of the storage cell, and its positive correlation with retention time establishes a physically quantifiable monitoring model, making the measured value of the threshold voltage a direct indicator of the degree of charge leakage in the stored data. This technical approach, by physically binding the calibration data block and the stored data block, achieves synchronous monitoring of the aging law of the storage medium, thus enabling accurate inference of data retention time based on threshold voltage changes even in power-off or dormant states, providing a reliable basis for subsequent data refresh.

[0097] In one embodiment, the step of defining a calibration data block at a preset location in the NAND FLASH memory includes:

[0098] (1) During the mass production testing phase of NAND FLASH memory, an independent storage area is divided in the physical storage array of NAND FLASH memory as candidate calibration data blocks;

[0099] The candidate calibration data block and the data block containing the stored data in the NAND FLASH memory use the same storage medium and process parameters.

[0100] (2) Write preset reference data into the candidate calibration data block so that the initial threshold voltage in the candidate calibration data block is within the preset reference range;

[0101] (3) Verify the validity of the candidate calibration data blocks to determine whether the change law of the threshold voltage of the candidate calibration data blocks over time is consistent with the data stored in the NAND FLASH memory;

[0102] (4) Define the verified candidate calibration data blocks as calibration data blocks.

[0103] In some of the solutions described above in this application, a calibration data block is defined at a preset location to record the threshold voltage. However, in the process of defining the calibration data block, if there are differences in the storage medium or process parameters between the candidate calibration data block and the actual storage data block, the threshold voltage change pattern may be inconsistent, which may result in the inability to accurately reflect the actual retention status of the stored data and ultimately affect the reliability of the data retention time calculation.

[0104] To address this, this application further proposes that during the mass production testing phase of NAND FLASH memory, an independent storage region is partitioned within the physical storage array of the NAND FLASH memory as a candidate calibration data block. The candidate calibration data block uses the same storage medium and process parameters as the data block containing the stored data in the NAND FLASH memory. Preset reference data is written into the candidate calibration data block to ensure that the initial threshold voltage in the candidate calibration data block is within the preset reference range. The validity of the candidate calibration data block is verified to determine that the change in the threshold voltage of the candidate calibration data block over time is consistent with the data stored in the NAND FLASH memory. The verified candidate calibration data block is defined as a calibration data block.

[0105] When partitioning candidate calibration data blocks within the physical storage array, the partitioning location can be either the array edge or the array center. For example, specific physical blocks can be reserved using address mapping during mass production testing. The candidate calibration data blocks and the storage data blocks use the same storage medium, such as a multilayer cell structure, and the process parameters, including ion implantation dose or oxide layer thickness, are controlled within ±3% error range. When writing reference data, the preset reference range can be 2.5V to 3.0V. The initial threshold voltage is adjusted by the number of programming pulses, for example, using progressive pulse programming until the target voltage value is reached. In the validity verification step, the consistency of the variation pattern can be verified through accelerated aging tests, such as applying a bias voltage at a high temperature to simulate a charge leakage process, monitoring that the difference in threshold voltage decay rate between the candidate block and the storage block does not exceed 5%.

[0106] Specifically, during the mass production testing phase, candidate calibration data blocks and storage data blocks in the physical storage array share the same manufacturing process and material characteristics, such as using the same wafer cutting region, ensuring that they are homogeneous in charge retention characteristics. The writing of reference data stabilizes the initial threshold voltage within a preset range by precisely controlling the programming voltage and pulse width, for example, controlling the initial voltage error within ±0.1V through closed-loop feedback adjustment. During validity verification, candidate calibration data blocks are subjected to the same temperature and humidity conditions as the actual storage environment, and the threshold voltage decay curve is recorded by periodic sampling, for example, data is collected every 24 hours, and monitored continuously for 30 days. When the voltage decay rate of the candidate block deviates from the standard rate of the storage data block by less than a preset threshold, for example, the deviation does not exceed 2%, it is considered to have passed verification. Finally, the verified candidate blocks are marked as formal calibration data blocks, and their storage addresses are written into the configuration table of the main control chip for use as a benchmark for calculating subsequent data retention time.

[0107] As a preferred embodiment, the specific implementation of the solution in this application includes: during the mass production testing phase of NAND FLASH memory, firstly, dividing the physical storage array into independent storage regions as candidate calibration data blocks. These candidate calibration data blocks use the exact same storage medium and process parameters as the data blocks in the NAND FLASH memory used to store actual data. For example, a certain number of storage blocks can be reserved as candidate calibration data blocks at specific locations in each storage cell array.

[0108] Next, preset reference data is written into the candidate calibration data block. The reference data can be a specific bit pattern or data sequence used to initialize the threshold voltage of the candidate calibration data block. The write operation precisely controls the programming voltage and timing to ensure that the initial threshold voltage in the candidate calibration data block is within the preset reference range. For example, the initial threshold voltage can be controlled between 2.5V and 3.0V.

[0109] The candidate calibration data blocks are then validated for validity. The validation process includes threshold voltage measurements at multiple time points to determine whether the threshold voltage variation of the candidate calibration data blocks over time is consistent with the actual data stored in the NAND flash memory. Testing can be conducted under different temperature and humidity conditions to simulate various real-world usage environments. For example, threshold voltage changes at 0 days, 30 days, 90 days, and 180 days can be measured at room temperature, high temperature, and low temperature, respectively, and compared with the variation trends of actual data blocks under the same conditions.

[0110] Finally, the verified candidate calibration data blocks are formally defined as calibration data blocks. The location information of these calibration data blocks is recorded in the management area of ​​the NAND FLASH memory for subsequent data retention calculations. Candidate calibration data blocks that fail verification are marked as invalid and are no longer used for calibration purposes.

[0111] Through the above technical solution, this application ensures the consistency of physical characteristics between the calibration data block and the actual stored data block. Since the calibration data block and the stored data block use the same storage medium and process parameters, their threshold voltage variation patterns are highly similar. Through a rigorous initialization and verification process, calibration data blocks that accurately reflect the actual retention status of the stored data are selected. This method avoids threshold voltage variation deviations caused by differences in materials or processes, improving the accuracy and reliability of data retention time calculation. Furthermore, based on accurate retention time calculation, data refresh operations can be performed more promptly and accurately, effectively preventing data loss and extending the lifespan of the NAND FLASH memory.

[0112] Based on the first embodiment, a third embodiment of the data protection method of this application is proposed. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 A flowchart illustrating the third embodiment of the data storage protection method provided in this application.

[0113] In this embodiment, step S20 of the data storage protection method includes steps S21 to S24:

[0114] Step S21: Obtain the initial threshold voltage measurement value of the calibration data block to obtain the second measurement value;

[0115] The second measurement value is the reference threshold voltage recorded when the calibration data block is defined.

[0116] Step S22: Calculate the difference between the first measured value and the second measured value to obtain the threshold voltage change;

[0117] Step S23: Call the preset fitting curve of threshold voltage change versus storage time;

[0118] The fitting curve is a function curve generated by performing retention tests on the same type of calibration data blocks over multiple time periods. The fitting curve is used to reflect the correspondence between the threshold voltage change and the retention time of the stored data.

[0119] Step S24: Based on the first measurement value, query the fitted curve to determine the data retention time corresponding to the stored data in the NAND FLASH memory.

[0120] When obtaining the second measurement value, the reference threshold voltage can be determined by averaging multiple samples during the calibration data block definition phase. For example, after initially writing the reference data, the threshold voltage can be measured three times consecutively and the average value calculated. During the difference calculation, a temperature compensation coefficient can be introduced to calculate the threshold voltage change. For example, the weighting of the voltage change can be adjusted based on the current ambient temperature to eliminate the impact of temperature fluctuations on the measurement results. When calling the fitted curve, the function curve can be generated based on an exponential decay model or a polynomial regression algorithm. For example, the least squares method can be used to fit the test data to ensure that the relationship between voltage change and time meets the accuracy requirement of less than 5% error. When querying the fitted curve, the data retention time can be determined using an interpolation algorithm. For example, when the threshold voltage change is between two known test points, the corresponding storage time can be calculated using linear interpolation.

[0121] Specifically, in the data retention time calculation process, an initial reference value is first established by calibrating the reference threshold voltage of the data block, providing a traceable physical benchmark for subsequent voltage change calculations. By calculating the difference between the current measured value and the initial reference value, the absolute voltage value is converted into a relative change, effectively eliminating measurement bias caused by individual differences in storage units. When calling the pre-established fitting curve, a function relationship is generated based on multi-period test data of the same type of calibration data block, creating a mathematical mapping between voltage change and time decay. For example, when the threshold voltage change reaches 50mV, a quantitative result of 30 days of storage time can be obtained by querying the fitting curve. This process replaces the traditional timing mechanism with objective measurement of physical quantity changes, solving the problem of not being able to track the actual storage time under power failure conditions. At the same time, since the fitting curve is generated based on actual test data of the same batch of storage media, it can adapt to the aging rate differences under different process parameters, avoiding maintenance errors caused by using a fixed threshold. In practice, when the ambient temperature rises and charge leakage accelerates, the change in threshold voltage within the same time interval will increase. At this time, by querying the fitted curve, the calculated data retention time can be automatically shortened, thereby triggering the data refresh operation in advance and ensuring the reliability of the stored data.

[0122] As a preferred embodiment, the solution of this application specifically includes: obtaining an initial threshold voltage measurement value of the calibration data block to obtain a second measurement value. The second measurement value is the reference threshold voltage recorded when the calibration data block is defined. For example, during the mass production testing phase of NAND FLASH memory, a high-precision voltage measuring instrument can be used to measure the threshold voltage of the calibration data block, and the measured voltage value can be stored as the second measurement value in the non-volatile memory of the controller.

[0123] The difference between the first and second measured values ​​is calculated to obtain the change in threshold voltage. Specifically, the stored second measured value can be subtracted from the currently read first measured value to obtain the absolute change in threshold voltage.

[0124] The program invokes a pre-defined fitting curve of threshold voltage change versus storage time. This fitting curve is a function curve generated by performing multi-period retention tests on similar calibration data blocks, reflecting the correlation between threshold voltage change and data retention duration. Furthermore, mathematical methods such as polynomial or exponential fitting can be used to fit a smooth curve function based on multiple sets of experimental data points.

[0125] Based on the first measurement, the fitted curve is consulted to determine the data retention time corresponding to the stored data in the NAND FLASH memory. Therefore, the calculated threshold voltage change can be substituted into the fitted curve function to solve for the corresponding time value, which is the data retention time.

[0126] Through the above technical solution, this application establishes an objective evaluation model based on changes in physical quantities, solving the problem of failure of traditional timing mechanisms under power-off conditions. Obtaining a second measured value as the initial reference threshold voltage provides a traceable reference point for subsequent calculations, avoiding reference drift caused by batch differences in storage media. Calculating the difference between the first and second measured values ​​converts the absolute voltage value into a relative change, eliminating the influence of external interference factors such as ambient temperature on a single measured value. When calling a preset fitting curve, the voltage change is mapped to a precise time dimension parameter by generating a function relationship from multi-period retention test data of the same type of calibration data blocks, realizing mathematical modeling between the charge leakage process and the time decay law. Querying the fitting curve based on the first measured value allows for dynamic adaptation to the aging rate of different storage cells, so that the determination of data retention time no longer depends on a fixed time threshold, but is adaptively adjusted based on the actual changes in physical state. This method improves the accuracy of data retention time calculation, adapts to the aging characteristics of storage media under different process batches or ambient temperatures, thereby more accurately triggering data refresh maintenance and improving the data reliability and lifespan of NAND FLASH memory.

[0127] Based on the first embodiment, a fourth embodiment of the data protection method of this application is proposed. Please refer to [link to previous document]. Figure 4 , Figure 4 A flowchart illustrating the fourth embodiment of the data storage protection method provided in this application.

[0128] In this embodiment, step S30 of the data storage protection method includes steps S31 to S32:

[0129] Step S31: Perform a data storage scan on the NAND FLASH memory to locate risky data blocks;

[0130] Among them, the risk data block is the data block where the threshold voltage measurement value is lower than the preset normal threshold voltage range, or the threshold voltage change exceeds the preset safe change threshold.

[0131] Step 32: Repair the stored data in the risky data block to protect the stored data in the NAND FLASH memory.

[0132] This application achieves data protection in NAND FLASH memory through a two-step operation, specifically including: performing a comprehensive data storage scan of the NAND FLASH memory, focusing on screening out risky data. The criteria for determining such data blocks are twofold: either the actual measured value of its threshold voltage exceeds the preset normal range, or the change in the threshold voltage during use exceeds the preset safety threshold. Both situations indicate that the data block may be at risk of data storage instability due to aging, erase and write wear, etc. The next step is data repair step S32. After finding the risky data blocks, the data stored in these blocks will be repaired, ultimately achieving the purpose of protecting the data in the NAND FLASH memory and preventing data loss or errors.

[0133] In a preferred embodiment, the step of repairing stored data in a risky data block may include:

[0134] (1) Read the risk storage data in the risk data block and write the risk storage data to the temporary cache area;

[0135] (2) Erase the risky stored data in the temporary buffer to remove residual charge in the risky stored data;

[0136] (3) Return the valid data in the temporary cache area to the risky data block, so that the threshold voltage of the risky data block is restored to the preset normal threshold voltage range, so as to repair the risky stored data.

[0137] The physical isolation structure of the temporary buffer can employ an SRAM cache module or redundant memory cells independent of the memory array, with a storage capacity configured to hold at least one data block at a time. The erase operation can be performed using a voltage pulse sequence, such as applying a negative erase voltage of -15V to -20V for 100-200μs, forcibly releasing residual charge in the floating gate through the field effect. The preset normal threshold voltage range can be set to 3.0V to 3.5V, determined through memory cell reliability testing, and can cover the voltage distribution range of over 99% of normal data blocks.

[0138] The temporary buffer can be a separate storage area physically isolated from the risky data block, such as a spare block or redundant storage space, to avoid charge interference. The erase operation can employ a multi-stage voltage pulse sequence, such as applying an erase voltage of 15-20V and maintaining it for 100 microseconds to ensure complete charge neutralization. When valid data is returned for writing, the programming voltage can be set within ±5% of the reference value, such as 3.3V ± 0.15V, to stabilize the threshold voltage within a preset range. The effectiveness of residual charge removal can be detected by a verification circuit, such as reading the threshold voltage after erasure to see if it is below the 0.5V threshold. The capacity of the temporary buffer can be configured to be 1.2 times the capacity of the risky data block; for example, allocating 614 bytes of buffer when storing 512 bytes of data ensures complete data transfer. The timing control of the erase operation and data reconstruction adopts a staged execution approach, such as completing the buffer erase before initiating data write-back, to avoid residual charge caused by parallel operations.

[0139] Specifically, once the risky data block is located, the risky stored data is transferred to a physically isolated temporary buffer, which uses an independent charge trap structure from the main memory array. During the erase operation in the buffer, a stepped boost pulse is applied to completely remove residual electrons from the floating gate layer. For example, after initially applying 18V for 50 microseconds, a 20V voltage is applied for 30 microseconds after a 10-microsecond interval, ensuring that charges at different depths are cleared. After charge removal, valid data is re-injected into the risky data block via a charge pump circuit with a precisely controlled programming voltage. For example, a closed-loop feedback mechanism is used to calibrate the threshold voltage to the range of 3.3V ± 0.1V. During this process, the isolation characteristics of the temporary buffer block block block the charge return path of the original storage cell, while the multi-stage erase operation eliminates residual charges in different dielectric layers. Through this phased processing, the storage cell of the risky data block undergoes physical charge reconstruction, and the threshold voltage is stably restored to the normal operating range, thus fundamentally avoiding secondary data failure caused by residual charges.

[0140] Specifically, when a risky data block's threshold voltage deviates from the normal range, the risky stored data is first transferred to a temporary buffer via the data bus. This process employs an ECC verification mechanism to ensure data transmission integrity. Subsequently, a specific erase voltage waveform is applied to the temporary buffer, such as a three-stage gradient voltage: an initial stage applies -18V for 50μs to eliminate shallow charges; a middle stage applies -20V for 100μs to clear deep charges; and a final stage applies -15V for 30μs to balance charge distribution. After charge removal, valid data is rewritten into the original data block according to a programming verification mechanism. Incremental step pulse programming is used during programming, with each step voltage increment being 0.2V, until the threshold voltage reaches a reference value of 3.2V. This phased processing mechanism improves the residual charge removal rate, reducing the standard deviation of the threshold voltage after data block reprogramming to within 0.1V, significantly superior to traditional in-situ repair methods.

[0141] When repairing stored data in a risky data block, the risky stored data is first read from the risky data block and written to a temporary buffer. The temporary buffer can be the RAM cache in the NAND FLASH memory controller. Further, an erase operation is performed on the risky stored data in the temporary buffer to remove residual charge. The erase operation can be achieved by applying an erase voltage to the storage cells of the temporary buffer; the erase voltage can be -20V. This effectively removes the residual charge. Specifically, valid data in the temporary buffer is returned and written to the risky data block. For example, the data can be rewritten to the storage cells of the original risky data block through programming operations, restoring the threshold voltage of the risky data block to a preset normal threshold voltage range to repair the risky stored data. As a preferred implementation, the preset normal threshold voltage range can be 2V to 3V.

[0142] Through the above technical solution, this application achieves complete repair of risky data blocks. By transferring the risky stored data to a temporary buffer for processing, secondary charge interference that may be caused by directly manipulating the risky data block is avoided. Erasing the data in the temporary buffer effectively removes residual charge from the storage unit, eliminating the core cause of data errors. Finally, the erased valid data is rewritten into the original risky data block. Through a complete data reprogramming process, the threshold voltage of the storage unit is forcibly adjusted to a preset normal range, restoring data reliability at the physical level. This phased data transfer and charge removal mechanism ensures the thoroughness of risky data block repair, solves the technical defects of incomplete in-situ repair, and improves the data protection capability and reliability of NAND FLASH memory.

[0143] As another preferred embodiment, the specific implementation of the solution in this application includes: when repairing data stored in a risky data block, firstly, reading the risky stored data in the risky data block and writing the risky stored data into a temporary cache. For example, the read command of the NAND FLASH controller can be used to read the data in the risky data block page by page and temporarily store it in the SRAM cache inside the controller.

[0144] Next, the risky stored data in the temporary buffer is erased to remove residual charge. Specifically, an erase command is sent to the temporary buffer to reset all locations in the buffer to their initial state (e.g., all 1s). This step effectively removes residual charge from the storage cells, eliminating threshold voltage drift caused by charge leakage.

[0145] Finally, the valid data in the temporary cache area is returned to the risky data block, restoring the threshold voltage of the risky data block to the preset normal threshold voltage range, thus repairing the risky stored data. This step can be accomplished by using write commands from the NAND FLASH controller to rewrite the processed data to the corresponding location of the original risky data block. During the write process, the controller can adjust the write voltage and time according to the preset normal threshold voltage range to ensure that the threshold voltage of the storage cell returns to the normal range.

[0146] Through the above technical solution, this application can effectively solve the problem of residual charge in stored data within risky data blocks. By temporarily storing the data in a temporary buffer and then erasing it, residual charge in the storage unit can be completely removed, avoiding the risk of data overwriting or charge interference that may occur when operating directly on the original data block. Simultaneously, by rewriting the processed valid data, the threshold voltage of the storage unit is ensured to return to the normal range, thereby achieving effective repair of the risky data block. This method can significantly reduce the risk of incomplete data repair or secondary failure, improving the data reliability and lifespan of the NAND flash memory.

[0147] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the data storage protection method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0148] Please see Figure 5 , Figure 5 This is a schematic diagram of a data storage protection device proposed in this application. Specifically, the data storage protection device 50 includes:

[0149] Reading unit 51 is used to read the threshold voltage measurement value in the calibration data block to obtain the first measurement value;

[0150] The calculation unit 52 is used to calculate the data retention time of the stored data in the NAND FLASH memory based on the first measurement value;

[0151] The protection unit 53 is used to perform data storage scanning and data refresh on the NAND FLASH memory when the data retention time reaches a preset time threshold, so as to protect the stored data in the NAND FLASH memory.

[0152] This application provides an apparatus comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the data protection method described in Embodiment 1 above.

[0153] This application may also provide a storage medium, which may be a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the data protection method of the above embodiments.

[0154] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0155] The embodiments described herein are not intended to limit the scope of this patent application. Any equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of this application.

Claims

1. A method for protecting stored data, characterized in that, The data protection method is applied to the controller of a NAND flash memory, wherein calibration data blocks are defined in the NAND flash memory, and the data protection method includes: Read the threshold voltage measurement value from the calibration data block to obtain the first measurement value; Based on the first measurement value, calculate the data retention time of the stored data in the NAND FLASH memory; When the data retention time reaches a preset time threshold, the NAND FLASH memory is scanned for data storage and refreshed to protect the stored data in the NAND FLASH memory.

2. The method for protecting stored data according to claim 1, characterized in that, The method for protecting the stored data also includes: A calibration data block is defined at a preset location in the NAND FLASH memory. The calibration data block is used to record a threshold voltage, which is positively correlated with the retention time of the data stored in the NAND FLASH memory.

3. The method for protecting stored data according to claim 2, characterized in that, The step of defining a calibration data block at a preset location in the NAND FLASH memory includes: During the mass production testing phase of the NAND FLASH memory, an independent storage area is divided in the physical storage array of the NAND FLASH memory as a candidate calibration data block. The candidate calibration data block and the data block containing the stored data in the NAND FLASH memory use the same storage medium and process parameters. Preset reference data is written into the candidate calibration data block so that the initial threshold voltage in the candidate calibration data block is within the preset reference range; The validity of the candidate calibration data block is verified to determine whether the change pattern of the threshold voltage of the candidate calibration data block over time is consistent with the data stored in the NAND FLASH memory. The candidate calibration data block that passes the verification is defined as a calibration data block.

4. The method for protecting stored data according to claim 1, characterized in that, The step of calculating the data retention time of the stored data in the NAND FLASH memory based on the first measurement value includes: The initial threshold voltage measurement value of the calibration data block is obtained to obtain a second measurement value; wherein, the second measurement value is the reference threshold voltage recorded when the calibration data block is defined; The difference between the first measured value and the second measured value is calculated to obtain the threshold voltage change. The preset fitting curve of threshold voltage change versus storage time is invoked. The fitting curve is a function curve generated by performing retention tests on the same type of calibration data blocks for multiple time periods. The fitting curve is used to reflect the correspondence between threshold voltage change and the retention time of stored data. Based on the first measurement value, the fitted curve is queried to determine the data retention time corresponding to the stored data in the NAND FLASH memory.

5. The method for protecting stored data according to claim 1, characterized in that, The step of performing data storage scanning and data refresh on the NAND FLASH memory to protect the stored data in the NAND FLASH memory includes: A data storage scan is performed on the NAND FLASH memory to locate risky data blocks; wherein, the risky data block is a data block whose threshold voltage measurement value is lower than a preset normal threshold voltage range, or whose threshold voltage change exceeds a preset safe change threshold. Repair the stored data in the risky data block to protect the stored data in the NAND FLASH memory.

6. The method for protecting stored data according to claim 5, characterized in that, The steps for repairing the stored data in the risky data block include: Read the risk storage data from the risk data block and write the risk storage data into a temporary cache area; The risk-stored data in the temporary buffer is erased to remove any residual charge from the risk-stored data. The valid data in the temporary cache area is returned and written to the risk data block, so that the threshold voltage of the risk data block is restored to the preset normal threshold voltage range, thereby repairing the risk stored data.

7. The method for protecting stored data according to claim 1, characterized in that, The method for protecting the stored data also includes: Detect the operating status of the NAND FLASH memory; The step of reading the threshold voltage measurement value in the calibration data block includes: When the NAND FLASH memory is in a power-off state or in a sleep state, the threshold voltage measurement value in the calibration data block is read.

8. A data protection device, characterized in that, The data protection device is applied to the controller of the NAND flash memory, wherein calibration data blocks are defined in the NAND flash memory, and the data protection device includes: A reading unit is used to read the threshold voltage measurement value in the calibration data block to obtain a first measurement value; The calculation unit is used to calculate the data retention time of the stored data in the NAND FLASH memory based on the first measurement value; The protection unit is used to perform data storage scanning and data refresh on the NAND FLASH memory when the data retention time reaches a preset time threshold, so as to protect the stored data in the NAND FLASH memory.

9. A device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the storage data protection method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium stores an executable program for a data protection method, which, when executed, implements the steps of the data protection method as described in any one of claims 1 to 7.

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