Memory with memory-initiated command insertion and related systems, devices, and methods

Abstract

The present disclosure relates to memories with memory-initiated command insertion and related systems, devices, and methods. In one embodiment, a memory device includes a command insertion terminal configured to be operatively connected to a memory controller. The memory device can (i) identify a condition that can be addressed by receiving a command from the memory controller, and (ii) output the command or an indication of the condition via the command insertion terminal to cause the command to be inserted into a command queue of the memory controller. The memory device can include a command terminal via which the memory device can receive the command from the memory controller after the command is inserted in the command queue. In some embodiments, the condition can be that a memory region of the memory device needs a refresh cycle, and the command can be a command to perform a refresh cycle on the memory region.

Description

Technical Field

[0001] This disclosure relates to memory systems, apparatus, and methods. More specifically, this disclosure relates to memory systems having memory-initiated command insertion capabilities, and associated systems, apparatus, and methods. Background Technology

[0002] Memory devices are widely used to store information associated with various electronic devices such as computers, wireless communication devices, cameras, digital displays, and so on. Memory devices are frequently provided as internal, semiconductor integrated circuits, and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory, including static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), may require a power source to maintain its data. In contrast, non-volatile memory retains its stored data even without external power. Non-volatile memory is used in various technologies, including flash memory (e.g., NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM). Improvements to memory devices typically include increasing memory cell density, increasing read / write speeds or otherwise reducing operating latency, improving reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs. Summary of the Invention

[0003] In one aspect, this disclosure provides a memory device including: a command insertion terminal configured to be operatively connected to a memory controller, wherein the memory device is configured to: identify a condition that can be addressed by receiving a command from the memory controller, and output an indication of the command or the condition via the command insertion terminal such that the command is inserted into a command queue of the memory controller.

[0004] In another aspect, this disclosure provides a method of operating a memory device, comprising: identifying a condition that can be addressed by receiving a command from a memory controller, and outputting an indication of the command or the condition via a command insertion terminal of the memory device such that the command is inserted into a command queue of the memory controller.

[0005] In another aspect, this disclosure provides a memory system comprising: a memory controller having a memory command scheduler configured to generate a command queue; a memory device having a command insertion terminal; and a command insertion signal trace operatively connecting the command insertion terminal of the memory device to the memory command scheduler of the memory controller, wherein the memory device is configured to: identify a condition addressable by receiving a command from the memory controller, and output an indication of the command or the condition to the memory command scheduler via the command insertion terminal and the command insertion signal trace, such that the command is inserted into the command queue. Attached Figure Description

[0006] Many aspects of this disclosure can be better understood by referring to the following figures. The components in the figures are not necessarily to scale. The focus is on clearly illustrating the principles of this disclosure. The figures should not be construed as limiting this disclosure to the specific embodiments depicted, but are for explanation and understanding only.

[0007] Figure 1A This is a block diagram illustrating various embodiments of a memory system configured according to the present invention.

[0008] Figure 1B This is a block diagram illustrating various embodiments of a memory system configured according to the present invention.

[0009] Figure 2 This is a flowchart illustrating various embodiments of the present invention for inserting commands into the command queue of a memory controller.

[0010] Figure 3 This is a flowchart illustrating various embodiments of the invention for inserting refresh operations and / or cycles into the command queue of a memory controller.

[0011] Figure 4 This is a schematic diagram of a system comprising various embodiments of a memory device or system configured according to the technology of the present invention. Detailed Implementation

[0012] As discussed in more detail below, the technology disclosed herein relates to memories with memory-initiated command insertion and associated systems, apparatus, and methods. In some embodiments, the memory system includes a command insertion signal trace that operatively connects a memory controller (e.g., a memory command scheduler of the memory controller) to a command insertion terminal of the memory device. In operation, the memory device may (a) identify a condition that can be addressed by receiving a command from the memory controller, and / or (b) issue the command to the memory controller (via the command insertion terminal and the command insertion signal trace) for insertion into a command queue of the memory controller. The memory controller may then issue the command to one or more memory devices of the memory system, for example, via a command / address and / or data bus operatively connected to one or more memory devices. In response to receiving the command from the memory controller, the memory device may proceed to execute the command (e.g., to address the identified condition). Those skilled in the art will understand that the technology may have additional embodiments and may be described without further reference. Figure 1A-4 The described embodiments are practiced in several details.

[0013] In the embodiments described below, memory devices and systems are primarily described in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the invention may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash memory (e.g., NAND and / or NOR) storage media.

[0014] A. Overview

[0015] Many memory systems employ a controller- or processor-centric architecture, meaning that the controller or processor initiates communication between itself and one or more memory devices operatively connected to it. For example, in many memory systems, the memory controller sends commands to the memory devices via a command / address bus, and the memory devices respond by executing those commands. Therefore, memory devices mostly respond to communication received from the memory controller via the command / address bus. In other words, the memory controller may primarily use the command / address bus to initiate communication with the memory devices. Conversely, the ability of a memory device to initiate communication with the memory controller via the command / address bus may be limited.

[0016] In some memory systems, memory devices can communicate with a memory controller, but this communication can be restricted. For example, some memory systems may program a mode register to transmit information to the memory controller. The memory controller can then read the information from the programmed memory register. However, to read the programmed mode register, the memory controller needs all lines of the command / address bus and / or data bus to be idle until the memory controller can read the mode register and determine how to respond to the communication. Because the command / address bus and / or data bus must be idle for the memory controller to read the mode register, communication via the mode register consumes a significant amount of valuable system bandwidth by occupying these buses.

[0017] To address these issues, the memory system and apparatus of the present invention may include a command insertion signal trace that operatively connects an external command insertion pin of the memory device to a memory controller (e.g., a memory command scheduler of the memory controller). When the memory device recognizes a condition that can be addressed by receiving a command from the memory controller, the memory device may transmit the command or indication of the condition to the memory controller (via the command insertion terminal and the command insertion signal trace) to insert the command into the command queue of the memory controller. The memory controller may then send the command to one or more memory devices in the memory system, for example, via a command / address and / or data bus operatively connected to one or more memory devices. In response to receiving the command from the memory controller, the memory device may proceed to execute the command (e.g., to address the recognized condition).

[0018] Embodiments of the present invention thus offer several advantages over other memory systems. For example, a memory system configured according to embodiments of the present invention enables a memory device to initiate communication with a memory controller (e.g., addressing a condition that will appear at the memory device) rather than waiting for the memory controller to initiate communication and / or identify the condition. Furthermore, the memory device in the memory system of the present invention can communicate with the memory controller without significantly impacting system bandwidth via the command / address bus and / or data DQ bus. For example, the memory device of the present invention can communicate with the memory controller by transmitting a condition and / or one or more corresponding commands (e.g., as background operations of the memory device) to insert the corresponding commands into the command queue of the memory controller in a manner other than programming a mode register and waiting for the memory controller to read the programmed mode register and determine how to respond. Moreover, by providing the memory device with a means of communication with the memory controller, the memory system configured according to the present invention meets the industry's shift toward improved communication between memory devices and memory controllers and / or less controller-centric technologies and protocols (e.g., Compute High-Speed ​​Link (CXL), Generation 3 High-Bandwidth Memory (HBM3), DDR6 discovery, etc.).

[0019] Embodiments of the present invention can provide additional advantages via other memory systems, particularly with respect to refresh operations. For example, in various memory systems, the total number of memory rows requiring Row Hammer Refresh (RHR) at any given time is unknown. Therefore, these memory systems use statistical sampling techniques to identify potential victims or hammered memory rows. However, statistical sampling techniques typically result in more memory rows receiving RHR refreshes than theoretically required. For example, assuming a refresh period of 32ms, a memory refresh period of 50ns, or a cyclic tRFC, and an activation (e.g., hammer) threshold of 2,000 active rows before an adjacent memory row requires an RHR refresh, the theoretical number of hammered memory rows requiring RHR refresh is 320 rows (e.g., 32ms / 50ns / 2,000). However, memory devices using statistical sampling techniques perform significantly more (e.g., almost an order of magnitude) RHR refreshes than this theoretical number of hammered memory rows. Performing RHR refreshes on memory rows that do not require RHR attenuation / service results in wasted power.

[0020] Furthermore, the duration tRFC of the memory refresh period acts as a bandwidth limiter. For example, as the duration tRFC of the memory refresh period increases (e.g., to allow the memory device to perform RHR reduction / servicing on the victim memory row after the memory device executes a refresh command received from the memory controller), the system bandwidth decreases because the memory device is not available to the memory controller for access commands before the memory refresh period tRFC has elapsed. Additionally, as the number of victim memory regions receiving RHR refreshes increases, the timing margin for performing RHR reduction / servicing within the memory refresh period tRFC becomes tighter. Utilizing additional memory row parallelism to perform RHR refreshes on a larger number of victim memory regions simultaneously can alleviate the rejection RHR threshold at future process nodes, but the added parallelism (i) can increase the power required by the memory device from the power supply, (ii) can cause problems for the power delivery network of the memory device, and / or (iii) can increase the amount of noise injected into the peripheral circuitry of the memory device.

[0021] To address these issues, the memory systems and apparatus of the present invention can be configured to implement a deterministic solution for RHR operation rather than using statistical sampling techniques to identify potential victim memory regions. Specifically, the memory systems and apparatus of the present invention can track the number of times a memory region is activated and use that count to identify aggressor (e.g., seed) and / or victim memory regions. This deterministic solution is expected to reduce the number of memory regions identified for row RHR refresh compared to the number identified using statistical sampling techniques. Consequently, the memory device is expected to operate and / or consume or require less power for RHR operation within a shorter memory refresh period tRFC, because fewer memory regions are expected to receive RHR fading / servicing. Furthermore, because fewer memory regions are expected to receive RHR refreshes, parallel activation of memory regions (e.g., parallel activation of memory rows) during RHR operation can be reduced. Therefore, the memory systems and / or apparatus of the present invention are expected to achieve (i) reduced power requirements on the power supply, (ii) reduced strain or concurrency on the power delivery network of the memory device and / or memory system, and / or (iii) reduced noise injected into the peripheral circuitry of the memory device.

[0022] Alternatively or concurrently, memory systems and apparatuses configured according to the present invention can perform all or part of the RHR reduction / servicing outside the memory refresh period tRFC, which can improve system bandwidth and achieve a looser refresh timing specification. For example, as discussed in more detail below, the memory systems and apparatuses of the present invention can track the number of activations of memory regions, compare the number of activations with a threshold to determine whether the number of activations meets or exceeds the threshold, and / or identify one or more adjacent (e.g., victim) memory regions within or outside the memory refresh period tRFC. When an adjacent memory region is identified, a refresh cycle for that memory region can be inserted into the command queue of the memory controller. In some embodiments, the memory device can insert a refresh cycle into the command queue within or outside the memory refresh period tRFC. The memory controller can then send one or more commands corresponding to the inserted refresh cycle to the memory device to instruct the memory device to refresh the adjacent memory region. Therefore, the memory device of the present invention (i) can remove the RHR cycle from the tRFC budget, and / or (ii) can perform RHR reduction / servicing on an adjacent memory region in response to a command received from the memory controller, the command specifically instructing the memory device to refresh that adjacent memory region.

[0023] Therefore, it is desirable that the total time required for the memory system and apparatus of the present invention to refresh the memory area and / or perform RHR reduction / servicing in response to a refresh command is less than the total time required for other memory systems and apparatuses to (i) refresh the memory area in response to receiving a refresh command from the memory controller and (ii) perform RHR reduction / servicing at the end of the corresponding memory refresh time period tRFC. Therefore, the duration of the memory refresh time period tRFC of the memory system and apparatus of the present invention can be less than the duration of the memory refresh time period tRFC of other memory systems and apparatuses. The reduction in the duration of the memory refresh time period tRFC can be translated as (i) an increase in the amount of time available to the memory controller for access operations (which can be translated as an increase in system bandwidth), (ii) a looser timing specification for performing refresh and / or other operations, and / or (iii) greater command scheduling flexibility.

[0024] B. Selected embodiments of memory systems and associated apparatus and methods

[0025] Figure 1A This is a block diagram schematically illustrating a memory system 190 configured according to various embodiments of the present invention. In one embodiment, the memory system 190 is a dual in-line memory module (DIMM). In these and other embodiments, in Figure 1A This describes the individual modules or levels of the memory device 100. (Already from...) Figure 1AWell-known components of the memory system 190 are omitted and will not be described in detail below to avoid unnecessarily obscuring aspects of the invention.

[0026] like Figure 1A As shown, the memory system 190 may include one or more memory devices 100, which may be connected to an electronic device or component thereof capable of temporarily or permanently storing information using the memory. For example, the memory device 100 may be operatively connected to a host device 108 and / or a memory controller 101. The host device 108 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device 108 may be a network connectivity device (e.g., a switch, router, etc.); a recorder of digital images, audio, and / or video; a vehicle; an electrical appliance; a toy; or any of a number of other products. In one embodiment, the host device 108 may be directly connected to the memory device 100 (e.g., via a communication bus (not shown) with signal traces). Alternatively, the host device 108 may be indirectly connected to the memory device 100 (e.g., via a network connection or through an intermediate device, such as through the memory controller 101 and / or through the communication bus 117 via the signal trace).

[0027] The memory device 100 of the memory system 190 is operatively connected to the memory controller 101 via a command / address (CMD / ADDR) bus 118 and a data (DQ) bus 119. (See below for more details.) Figure 1B In more detail, the CMD / ADDR bus 118 and DQ bus 119 are available for the memory controller 101 to transmit commands, memory addresses, and / or data to the memory device 100. In response, the memory device 100 can execute commands received from the memory controller 101. For example, upon receiving a write command from the memory controller 101 via the CMD / ADDR bus 118, the memory device 100 can receive data from the memory controller 101 via the data DQ bus 118 and can write the data to the memory cell corresponding to the memory address received from the memory controller 101 via the CMD / ADDR bus 118. As another example, upon receiving a read command from the memory controller 101 via the CMD / ADDR bus 118, the memory device 100 can output data from the memory cell corresponding to the memory address received from the memory controller 101 via the data DQ bus 118 to the memory controller 101.

[0028] exist Figure 1A In the illustrated embodiment, one of the memory devices 100 is operatively connected to the memory controller 101 via one or more command insertion signal traces 120. More specifically, the command insertion signal trace 120 operatively connects one or more external command insertion pins or terminals CI of the memory device 100 to the command queue 103 of the memory command scheduler 102 of the memory controller 101. The command insertion signal trace 120 is separate from and / or different from the CMD / ADDR bus 118 and / or the DQ bus 119. As described in more detail below, the memory device 100 may transmit conditions and / or commands to the memory controller 101 via the command insertion terminal CI and the command insertion signal trace 120. The commands may then be inserted into the command queue 103 of the scheduler 102. Subsequently, the memory controller 101 may send the inserted commands to one or more memory devices 100 of the memory system 190 via, for example, the CMD / ADDR bus 118, the DQ bus 119, and / or another signaling bus or trace of the memory system 190.

[0029] Figure 1A The memory device 100 shown, operatively connected to the memory controller 101 via command insertion signal trace 120, may be the master memory device 100 of the memory system 190. In some embodiments, only the master memory device 100 of the memory system 190 may transmit conditions and / or corresponding commands directly to the memory controller 101 (e.g., without sending the conditions and / or corresponding commands to other memory devices 100 of the memory system 190) for inserting the corresponding commands into the command queue 103 of the scheduler 102 on the memory controller 101. In these and other embodiments, other memory devices 100 of the memory system 190 may transmit conditions and / or corresponding commands to the master memory device 100. Subsequently, the master memory device 100 may transmit conditions and / or corresponding commands directly to the memory controller 101 via the command insertion terminal CI and the corresponding command insertion signal trace 120 of the master memory device 100.

[0030] In some embodiments, only the master memory device 100 or a subset of the memory devices 100 of the memory system 190 includes one or more command insertion terminals CI. In other embodiments, each of the memory devices 100 of the memory system 190 may include one or more command insertion terminals CI. While each of the memory devices 100 of the memory system 190 may include a command insertion terminal CI, in some embodiments, only the command insertion terminal CI of the master memory device 100 may be operatively connected directly to the memory controller (e.g., without intermediate memory devices 100) via command insertion signal trace 120.

[0031] In other embodiments, command insertion terminals CI of more than one (e.g., all or more) memory devices 100 of memory system 190 may be operatively directly connected to memory controller 101 via one or more command insertion signal traces 120 (e.g., without intermediate memory devices 100). In these embodiments, any of the memory devices 100 operatively connected to memory controller 101 via command insertion signal traces 120 may transmit conditions and / or corresponding commands directly to memory controller 101 (e.g., without sending conditions and / or corresponding commands to other memory devices 100 of memory system 190) for insertion of the corresponding command into command queue 103 of scheduler 102. Command insertion signal traces 120 operatively connecting the command insertion terminals CI of memory devices 100 to memory controller 101 may be common or shared among memory devices 100. In these and other embodiments, command insertion signal traces 120 may be dedicated to individual memory devices 100.

[0032] Figure 1B yes Figure 1A A block diagram of a memory device 100 configured according to various embodiments of the present invention. As shown, the memory device 100 may employ multiple external terminals. The external terminals may include those operatively connected to a CMD / ADDR bus 118. Figure 1A The external terminals may include a command terminal for receiving the command signal CMD and an address terminal for receiving the address signal ADDR, respectively. Additional external terminals may include a chip select terminal for receiving the chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, and data terminals DQ, RDQS, DBI, and DMI (e.g., operatively connected to...). Figure 1A The DQ bus 119) and power supply terminal V DD V SS and V DDQ .

[0033] The memory device 100 may additionally include one or more command insertion terminals CI, which are configured, for example, via one or more corresponding command insertion signal traces (e.g., Figure 1AThe command insertion signal trace 120 is operatively connected to the memory controller (e.g., the memory command scheduler of the memory controller). In embodiments where a single command insertion signal trace 120 is used to operatively connect the memory device 100 directly to the memory controller, the memory device 100 may include a single command insertion terminal CI. As another example, in embodiments where multiple command insertion signal traces 120 are used to operatively connect the memory device 100 directly to the memory controller, the memory device 100 may include multiple command insertion terminals CI. As discussed in more detail below, when operatively connected to the memory controller 101 ( Figure 1A When conditions are met, the memory device 100 may transmit the conditions and / or corresponding commands to the memory controller 101 for inserting the corresponding commands into the command queue 103 of the memory controller 101. Figure 1A In this context, the memory controller 101 sends a corresponding command to another memory device 100 of the memory device 100 and / or the memory system 190. The memory controller 101 may issue the corresponding command via the CMD / ADDR bus 118, DQ bus 119 and / or another bus or signal trace that are operatively connected to (b) the memory controller 101 of the memory device 100 and / or the other memory device 100 of the memory system 190.

[0034] Alternatively or concurrently, the command insertion terminal CI of memory device 100 may be configured to be operatively connected to the command insertion terminal CI of another memory device 100 in memory system 190. For example, the command insertion terminal CI of the first memory device 100 may be operatively connected to the command insertion terminal CI of the master memory device 100 in memory system 190. Continuing this example, one or more other command insertion terminals CI of the master memory device 100 may be operatively directly connected to memory controller 101. In operation, the first memory device 100 may transmit conditions and / or corresponding commands to the master memory device 100 via the command insertion terminal CI operatively connected to the first memory device 100. The master memory device 100 may then transmit the conditions and / or corresponding commands to memory controller 101 for inserting the corresponding commands into the command queue 103 of memory controller 101.

[0035] A power potential V can be supplied to the power supply terminals of the memory device 100. DD and V SS These power supply potentials V DD and V SS It can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can be based on the power supply potential V. DD and V SSThis generates various internal potentials V PP V OD V ARY V PERI Wait a minute. Internal potential V PP It can be used in the line decoder 140, with an internal potential V. OD and V ARY It can be used in the sensing amplifier included in the memory array 150 of the memory device 100, and the internal potential V PERI It can be used in many other circuit blocks.

[0036] It can also supply a power potential V to the power terminals. DDQ The power supply potential V can be... DDQ Together with the power supply potential V SS Together, they are supplied to the input / output (I / O) circuit 160. In an embodiment of the present invention, the power supply potential V DDQ It can be related to the power supply potential V DD The same potential. In another embodiment of the invention, the power supply potential V... DDQ It can be related to the power supply potential V DD Different potentials. However, the potential V of a dedicated power supply. DDQ It can be used in I / O circuit 160 to prevent power supply noise generated by I / O circuit 160 from propagating to other circuit blocks.

[0037] External clock signals and / or complementary external clock signals can be supplied to clock terminals, data clock terminals, and / or additional clock terminals. External clock signals CK, CKF, WCK, and / or WCKF can be supplied to clock input circuit 133. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. Complementary clock signals can simultaneously have relative clock levels and transitions between relative clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0038] An input buffer included in clock input circuit 133 can receive an external clock signal. For example, when enabled by a CKE signal from command decoder 115, the input buffer can receive CK and CKF signals and / or WCK and WCKF signals. Clock input circuit 133 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can provide various phase and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from command decoder 115. For example, internal clock circuit 130 may include a clock path that receives the internal clock signal ICLK and provides various clock signals (not shown) to command decoder 115. Figure 1B (Not shown in the image). Internal clock circuit 130 may additionally provide input / output (I / O) clock signals. The I / O clock signals may be supplied to I / O circuit 160 and may be used as timing signals to, for example, determine the timing of input / output (I / O) clocks via DQ bus 119. Figure 1A The output timing and / or input timing of the transmitted data and / or the signal trace inserted in the command 120 ( Figure 1A The condition / command is transmitted via the command insertion terminal CI. Multiple clock frequencies can be provided for the I / O clock signal, allowing data to be output from and input to the memory device 100 at different data rates. A higher clock frequency may be desirable when high memory speed is required. A lower clock frequency may be desirable when lower power consumption and / or a looser timing margin are required. The internal clock signal ICLK can also be supplied to the timing generator 135, thus generating various internal clock signals that can be used by the command decoder 115, column decoder 145, I / O circuitry 160, and / or other components of the memory device 100.

[0039] Memory device 100 may include an array of memory cells, such as memory array 150. The memory cells of memory array 150 may be arranged in multiple memory regions, and each memory region may include multiple word lines (WLs), multiple bit lines (BLs), and multiple memory cells arranged at the intersections of word lines and bit lines. In some embodiments, the memory region may be one or more memory groups or another arrangement of memory cells (e.g., half a memory group, a subarray within a memory group, etc.). In these and other embodiments, the memory region of memory array 150 may be arranged in one or more groups (e.g., one or more groups of memory groups, one or more logical memory columns, or dies, etc.). The memory cells in memory array 150 may include any of a variety of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase-changing, etc. The selection of word lines WLs may be performed by row decoder 140, and the selection of bit lines BLs may be performed by column decoder 145. A sense amplifier (SAMP) can be provided for the corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which can then be coupled to at least one corresponding primary I / O line pair (MIOT / B) via a transmission gate (TG), which can act as a switch. The memory array 150 may also include board lines and corresponding circuitry for managing its operation.

[0040] Address signals and group address signals can be supplied from outside the memory device 100 to the command and address terminals. The address signals and group address signals supplied to the address terminals can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive the address signals and supply the decoded row address signal (XADD) to the row decoder 140, and supply the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive the group address signal (BADD) and supply the group address signal to both the row decoder 140 and the column decoder 145.

[0041] Command signals CMD, address signals ADDR, and chip select signals CS can be supplied to command and address terminals (e.g., from memory controller 101 and / or host device 108). Command signals can represent various memory commands (e.g., access commands, which may include read and write commands). The select signal CS can be used to select memory device 100 to respond to commands and addresses provided to the command and address terminals. When an active CS signal is provided to memory device 100, commands and addresses can be decoded, and memory operations can be performed. Command signals CMD can be provided as internal command signals ICMD to command decoder 115 via command / address input circuitry 105. Command decoder 115 may include circuitry for decoding internal command signals ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. Internal command signals may also include output and input activation commands, such as timing commands (not shown) to command decoder 115. Command decoder 115 may additionally include one or more registers 128 that track various counts or values ​​(e.g., the number of times a memory region (e.g., a memory row) has been activated).

[0042] When a read command is issued and the read command is promptly supplied to the row and column addresses, read data can be read from the memory cells in memory array 150 identified by these row and column addresses. The read command can be received by command decoder 115, which can provide internal commands to I / O circuitry 160, enabling read data to be output from data terminals DQ, RDQS, DBI, and DMI via read / write (RW) amplifier 155 and I / O circuitry 160 according to the RDQS clock signal. The read data can be generated by a programmable register in memory device 100, for example, a mode register. Figure 1B The read data is provided at the time defined by the read delay information RL (not shown in the diagram). The read delay information RL can be defined in terms of the clock cycles of the CK clock signal. For example, the read delay information RL can be the number of clock cycles of the CK signal after the read command is received by the memory device 100 when the associated read data is provided.

[0043] When a write command is issued and the command is supplied to the row and column addresses in a timely manner, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by the command decoder 115, which can provide an internal command to the I / O circuit 160 so that the write data can be received by the data receiver in the I / O circuit 160 and supplied to the memory array 150 via the I / O circuit 160 and the RW amplifier 155. The write data can be written to the memory cell specified by the row and column addresses. The write data can be supplied to the data terminals at a time defined by the write delay WL information. The write delay WL information is programmable in the memory device 100, for example, programmed in the mode register ( Figure 1B (Not shown in the image). The write delay WL information can be defined in terms of the clock cycles of the CK clock signal. For example, the write delay information WL can be the number of clock cycles of the CK signal after the write command is received by the memory device 100 when the associated write data is received.

[0044] As discussed in more detail below, the memory device 100 may additionally or alternatively be connected via command insertion terminal CI and / or corresponding command insertion signal trace 120. Figure 1A Send the conditions and / or corresponding commands to the memory controller 101. Figure 1A ) and / or another memory device 100 of memory system 190 Figure 1A In some embodiments, memory device 100 may directly issue conditions and / or corresponding commands to memory controller 101 for inserting the corresponding commands into command queue 103 of memory command scheduler 102 of memory controller. For example, memory device 100 may directly insert (e.g., add) the corresponding commands into command queue 103. As another example, memory device 100 may transmit conditions and / or corresponding commands to memory controller 101 (e.g., memory command scheduler 102 of memory controller 101), and memory controller 101 (e.g., memory command scheduler 102) may (i) process the conditions (e.g., to identify the corresponding command), (ii) process the corresponding commands, and / or (iii) insert (e.g., add) the corresponding commands into command queue 103. In any instance, the corresponding commands may be inserted into command queue 103 of memory controller 101 such that memory controller 101 issues the corresponding commands to memory device 100 and / or one or more other memory devices 100 of memory system 190.

[0045] In these and other embodiments, memory device 100 may transmit conditions and / or corresponding commands to another memory device 100 of memory system 190. The other memory device 100 may then (i) receive the conditions and / or corresponding commands, (ii) process the conditions (e.g., to identify the corresponding commands), (iii) process the corresponding commands, and / or (iv) transmit the conditions and / or corresponding commands to memory controller 101 for insertion into command queue 103 of memory controller 101. The corresponding commands may be inserted into command queue 103 such that memory controller 101 sends the corresponding commands to one or more of the memory devices 100 that transmitted the conditions and / or corresponding commands directly to memory controller 101, to the memory device 100 that first transmitted the conditions and / or corresponding commands, and / or to other memory devices 100 of memory system 190.

[0046] In some embodiments, background operation of the memory device 100 can be performed via command insertion terminal CI and / or via corresponding signal trace 120 to transmit conditions and / or corresponding commands. Therefore, in these embodiments (e.g., CMD / ADDR bus 118...), Figure 1A On the DQ bus 119 ( Figure 1A The system bandwidth on another bus or signal trace of the memory system 190 may be unaffected or impeded by the transmission of conditions and / or corresponding commands via command insertion terminal CI and / or corresponding signal trace 120.

[0047] Figure 2 This is a flowchart of routine 250 for inserting commands into a command queue of a memory controller, according to various embodiments of the present invention. Routine 250 is illustrated as a set of steps or blocks 251-254. All or a subset of one or more of blocks 251-254 may be generated by a memory system (e.g., Figure 1A The memory system 190) is executed by a component or device. For example, all or a subset of one or more of blocks 251-254 may be performed by (i) a memory device (e.g., Figure 1A and 1B (i) memory device 100) and / or (ii) memory controller (e.g., Figure 1A The memory controller 101) executes.

[0048] Routine 250 begins at block 251, where the memory device identifies the conditions for receiving one or more commands from the memory controller. The memory device may be the master memory device of the memory system. In these and other embodiments, the memory device may be any memory device of the memory system and / or a memory device other than the master memory device of the memory system.

[0049] The conditions for receiving commands may include any conditions addressable by receiving commands from the memory controller via the memory device. For example, the conditions for receiving commands from the memory controller may include (e.g., at the memory device) conditions that allow (i) sending one or more commands (e.g., one or more multi-purpose commands (MPCs)) to the memory device via the memory controller and / or (ii) executing one or more commands via the memory device. In some embodiments, the conditions may include (a) the memory device determining (e.g., specific) that the transfer of data from the memory device to the memory controller is appropriate, and / or (b) the memory device determining (e.g., specific) that the transfer of data from the memory controller to the memory device is appropriate. For example, the memory device may determine that it is appropriate to transfer reliability (e.g., error checking and erasing (ECS) data), alert type information, and / or other data to the memory controller. In these and other embodiments, the conditions may include the memory device determining that training operations between the memory controller and the memory device are appropriate. For example, the memory device may determine that read latency or write latency no longer focuses read or write data on the read or write data DQS strobe. This can indicate that various data transfer parameters (e.g., latency on the memory device, latency on the data channel, etc.) have changed since the last training operation between the memory controller and the memory device was performed and the data transfer parameters were calibrated. In these and other embodiments, the condition may include the memory device determining that an initialization operation is appropriate (e.g., to reset the mode register of the memory device). In these and other embodiments, the condition may include the memory device determining a refresh (e.g., performing a hammer refresh operation, as described below). Figure 3 (Discussed in more detail) or other operations are appropriate (e.g., to serve the memory area of ​​its memory array, reset the memory device, etc.).

[0050] At block 252, the memory device transmits the condition and / or one or more corresponding commands to the memory controller for inserting the corresponding commands into the command queue of the memory controller. Transmitting the condition and / or corresponding commands to the memory controller may include issuing the condition and / or corresponding commands to the memory controller (e.g., the memory controller's memory command scheduler) via (i) one or more command insertion terminals of the memory device and / or (ii) operatively connecting the command insertion terminals of the memory device to one or more corresponding command insertion signal traces of the memory controller. A memory device that transmits the condition and / or corresponding commands directly to the memory controller may be a memory device that identifies the condition at block 251. In these and other embodiments, a memory device that transmits the condition and / or corresponding commands directly to the memory controller may be the master memory device of the memory system. For example, a first memory device may identify the condition at block 251 and may transmit the condition and / or corresponding commands to the master memory device (e.g., via one or more signal traces operatively connecting the first memory device to the master memory device). Based at least in part on receiving the condition and / or corresponding command from the first memory device, the master memory device may (i) process the condition (e.g., to identify the corresponding command), (ii) process the corresponding command, and / or (iii) send the condition and / or corresponding command to the memory controller for insertion into the command queue of the memory controller.

[0051] In the aforementioned scenario, the condition identified at block 251 is that the memory device determines (e.g., a specific) that the transfer of data from the memory device to the memory controller is appropriate. The memory device and / or another memory device may transmit the condition and / or one or more corresponding commands (e.g., a read command and / or another appropriate command) to the memory controller at block 252 to insert the corresponding command into the memory controller's command queue. The transmission of the condition and / or the corresponding command may specify or indicate (e.g., via an identifier of the memory device) which memory device the data will be transferred to the memory controller, such that the memory controller can indicate that when the memory controller issues a corresponding command, the corresponding command is intended for that memory device.

[0052] Similarly, in the aforementioned case, the condition identified at block 251 is that the memory device determines (e.g., a specific) that the transfer of data from the memory controller to the memory device is appropriate. The memory device and / or another memory device may transmit the condition and / or one or more corresponding commands (e.g., a write command and / or another appropriate command) to the memory controller at block 252 to insert the corresponding command into the memory controller's command queue. The transmission of the condition and / or the corresponding command may specify or indicate (e.g., via an identifier of the memory device) which memory device the data will be transferred to the memory controller, such that the memory controller can indicate that the corresponding command and / or the requested data are intended for that memory device when the memory controller issues the corresponding command and / or transmits the requested data.

[0053] In the stated case, the condition identified at block 251 is that the memory device determines the training and / or initialization operation is appropriate. The memory device and / or another memory device may transmit the condition and / or one or more corresponding commands to the memory controller at block 252 to insert the corresponding commands into the command queue of the memory controller. In some embodiments, the corresponding commands may include a Mode Register Setting (MRS) command, a ZQ calibration command, and a V... ref DQ calibration commands, read training commands, and / or write training commands. The transmission of conditions and / or corresponding commands can specify which memory device is requesting training and / or initialization so that the memory controller can indicate which memory device the corresponding command is intended for when the memory controller issues the corresponding command.

[0054] In the aforementioned case, the condition identified at box 251 is that the memory device determines a refresh operation (e.g., a row hammer refresh operation) is appropriate. The memory device and / or another memory device may transmit the condition and / or one or more corresponding commands (e.g., one or more refresh commands and / or loops, such as an activation command along with a precharge command) to the memory controller at box 252 to insert the corresponding commands into the memory controller's command queue. The transmission of the condition and / or corresponding commands (i) may specify which memory device will perform the refresh operation and / or (ii) may specify one or more addresses of one or more memory regions to be refreshed. Subsequently, when the memory controller issues the corresponding command, the memory controller may issue instructions to (a) the memory device that identified the condition at box 251, (b) the memory device that transmitted the condition and / or corresponding commands to the memory controller at box 252, and / or (c) another memory device in the memory system that will refresh a memory region, for example, corresponding to the memory region at the memory address specified in the transmission from the memory device to the controller at box 252. (The following section discusses...) Figure 3 The refresh operation will be discussed in more detail.

[0055] In some embodiments, the memory device may directly insert one or more commands corresponding to the conditions identified at block 251 into the command queue of the memory controller. In these and other embodiments, the memory device may transmit the conditions and / or one or more corresponding commands to the memory controller (e.g., the memory command scheduler of the memory controller). The memory controller may then (i) process the conditions received from the memory device (e.g., to identify one or more corresponding commands), (ii) process the one or more corresponding commands received from the memory device, and / or (iii) insert one or more corresponding commands into its command queue.

[0056] In some embodiments, the corresponding command can be inserted at any position in the command queue of the memory controller. For example, the corresponding command can be inserted at the end of the command queue so that the memory controller then issues the corresponding command. As another example, the corresponding command can be inserted at the beginning of the command queue so that the corresponding command is the next command issued by the memory controller. As yet another example, the corresponding command can be inserted at any position between the beginning and the end of the command queue.

[0057] At block 253, the memory device receives a corresponding command from the memory controller. The memory device receiving the corresponding command at block 253 may be the same memory device that identifies the condition at block 251. In these and other embodiments, the memory device receiving the corresponding command at block 253 may be the same memory device that directly transmits the condition and / or the corresponding command to the memory controller at block 252 for inserting the corresponding command into the command queue of the memory controller. In these and other embodiments, the memory device receiving the corresponding command at block 253 may be any of the memory devices in the memory system.

[0058] In some embodiments, when a command has been initiated via the memory controller or the host device (as opposed to the memory device itself), the memory device receives the corresponding command in the same or similar manner as the memory device would normally receive a command. For example, when the memory controller issues a corresponding command that has been inserted into its command queue at block 252, the memory controller may issue the corresponding command via the command / addressing CMD / ADDR bus, the data DQ bus, and / or another bus or signal trace that operatively connects the memory controller to the memory device in the same or similar manner as the memory controller issued the command, provided that the command has been inserted into its command queue under the guidance of the memory controller and / or the host device (as opposed to the memory device itself).

[0059] At block 254, the memory device executes the corresponding command received from the memory controller at block 253. In some embodiments, the memory device may be the memory device that identifies the condition at block 251. In these and other embodiments, the memory device may be the memory device that transmits the condition and / or the corresponding command directly to the memory controller at block 252. In these and other embodiments, the memory device may be any of the memory devices in the memory system, such as the memory device identified by the memory controller when it issues one of the corresponding commands. For example, the memory controller may issue a memory device (e.g., chip) selection signal along with the corresponding command. The memory device selection signal may indicate which of the memory devices will execute the corresponding command. Therefore, the memory device executing the command at block 254 may be the memory device corresponding to the memory device selection signal issued by the memory controller. In some embodiments, where a command has been initiated via the memory controller or a host device (as opposed to via the memory device), the memory device executes the corresponding command at block 254 in the same or similar manner as the memory device would normally execute the command.

[0060] Although boxes 251-254 of routine 250 are discussed and explained in a specific order, Figure 2 The routine 250 described herein is not limited thereto. In other embodiments, routine 250 may be executed in a different order. In these and other embodiments, any one of blocks 251-254 of routine 250 may be executed before, during, and / or after any other block 251-254 of routine 250. Furthermore, those skilled in the art will recognize that the described routine 250 may be modified while remaining within these and other embodiments of the present invention. For example, in some embodiments, routines may be omitted and / or repeated. Figure 2 One or more blocks 251-254 of routine 250 described herein.

[0061] Embodiments of the present invention thus provide several advantages over other memory systems. For example, a memory system configured according to embodiments of the present invention enables a memory device to initiate communication with a memory controller (e.g., for conditional addressing that will occur at the memory device) rather than waiting for the memory controller to initiate communication and / or identify conditions. Furthermore, memory devices in the memory system of the present invention can communicate with the memory controller without significantly impacting system bandwidth on the command / address bus and / or data DQ bus. For example, a memory device of the present invention can communicate with a memory controller by transmitting conditions and / or one or more corresponding commands (e.g., as background operations of the memory device) in a manner other than programming a mode register and waiting for the memory controller to read the programmed mode register and determine how to respond, thereby inserting the corresponding commands into the command queue of the memory controller. The present invention also provides several additional bandwidth, timing, and power reduction benefits, as described below regarding… Figure 3 To elaborate further.

[0062] Figure 3 This is a flowchart illustrating various embodiments of the invention, specifically routine 360 ​​for inserting refresh operations and / or cycles into the command queue of a memory controller. Routine 360 ​​is illustrated as a set of steps or blocks 361-367. All or a subset of one or more of blocks 361-367 may be generated by a memory system (e.g., Figure 1A The memory system 190) is executed by a component or device. For example, all or a subset of one or more of blocks 361-367 may be performed by (i) a memory device (e.g., Figure 1A and 1B (i) memory device 100) and / or (ii) memory controller (e.g., Figure 1A The memory controller 101) executes.

[0063] Figure 3 The advantages offered by the memory system configured according to the invention are discussed in detail below in the context of refresh operations (e.g., row hammer refresh operations) to highlight several advantages provided by the memory system configured according to the invention. At least a portion of routine 360 ​​can be considered as Figure 2 The application routine 250. Therefore, for Figure 2 The arguments in boxes 251-254 of routine 250 may be applied, in whole or in part, to the following discussion on... Figure 3 The discussion of any one or more of the boxes 361-367 in routine 360.

[0064] Routine 360 ​​begins at block 361, whereby the memory device tracks the number of times a memory region of the memory device is activated. In some embodiments, a memory region may be a memory row of the memory device. In these and other embodiments, the memory device may track the number of times all or a subset of memory regions of its memory array are activated. For example, the memory device may store a count or value for each memory region (e.g., each memory row) of the memory device. Each count may represent the number of times the corresponding memory region of the memory device has been activated. Therefore, whenever a memory region corresponding to a count is activated, the memory device may increment the count (e.g., increment by one).

[0065] At box 362, the memory device can compare the number of times a memory region of the memory device has been activated with a threshold. In some embodiments, the threshold can be any number, and / or the threshold can be predetermined and / or preset. For example, the threshold can be set to a value representing the number of activations of memory regions (e.g., 2,000; 10,000; or other thresholds) where activation of memory regions at or below the number of activations is not expected to significantly affect adjacent memory regions (e.g., victim or hammered) (e.g., data retention of the memory regions). In other words, the threshold can be set to a value representing the number of activations of memory regions where activation of memory regions at or above the number of activations is expected to significantly affect adjacent memory regions (e.g., victim) (e.g., data retention of the memory regions). Therefore, when the number of times a memory region of the memory device has been activated meets or exceeds the threshold, the memory device can determine that adjacent memory regions may require a hammer refresh (RHR) operation and / or other operations to serve the adjacent memory regions and thus reduce or mitigate the effect of the number of times the memory region is activated being equal to or greater than the threshold.

[0066] At box 363, the memory device may determine whether the number of times the memory area of ​​the memory device has been activated meets or exceeds a threshold. If the memory device determines that the number of times the memory area of ​​the memory device has been activated does not meet or exceeds the threshold, then routine 360 ​​may return to box 361 or box 362. On the other hand, if the memory device determines that the number of times the memory area of ​​the memory device has been activated meets or exceeds the threshold, then routine 360 ​​may go to box 364.

[0067] At box 364, the memory device identifies one or more memory regions adjacent to the memory region corresponding to the activation count. For example, in an embodiment where the memory region is a memory row, the adjacent memory region may comprise one or more memory rows (e.g., adjacent to, immediately adjacent to, or within a specific number of memory rows from the memory region) in a memory array of the neighboring memory device. Identifying one or more adjacent memory regions may include identifying the memory address corresponding to one or more adjacent memory regions.

[0068] At box 365, routine 360 ​​continues to the memory device transmitting (i) a condition that an adjacent memory region requires one or more refresh cycles (e.g., RHR decay / servicing) and / or (ii) one or more commands corresponding to the refresh cycle. The memory device may transmit the condition and / or one or more corresponding commands to a memory controller operatively connected to the memory device for inserting the corresponding commands into the command queue of the memory controller. The one or more commands corresponding to the refresh cycle may include an activation (ACT) command, a precharge (PRE) command, and / or one or more other commands. For example, the execution of an activation operation and a precharge operation on a memory region may together define a refresh cycle for the memory region. Continuing this example, the commands corresponding to the refresh cycle may therefore include (i) an activation command and a precharge command, and / or an activation-precharge (e.g., combined) command (ii).

[0069] In some embodiments, the memory device may additionally transmit the memory address corresponding to an adjacent memory region (to the memory controller) at block 365. Transmitting the memory address of the adjacent memory region enables the memory controller to instruct the memory device to perform a refresh cycle on that particular adjacent memory region when the memory controller issues one or more corresponding commands that have been inserted into the command queue.

[0070] Memory devices can be related to the above-mentioned Figure 2 The conditions, corresponding commands, and / or memory addresses of adjacent memory regions are transmitted to the memory controller in a manner consistent with the discussion of block 252 of routine 250. In some embodiments, the memory device may transmit the conditions, corresponding commands, and / or memory addresses to the memory controller via (i) a command insertion terminal CI of the memory device and (ii) a corresponding command insertion signal trace operatively connecting the command insertion terminal CI of the memory device to the command queue of the memory controller. In these and other embodiments, the memory device may transmit the conditions, corresponding commands, and / or memory addresses of adjacent memory regions to another memory device in the memory system (e.g., the master memory device). The other memory device may then issue the conditions, corresponding commands, and / or memory addresses of adjacent memory regions to the memory controller for inserting the corresponding command into the command queue of the memory controller.

[0071] In some embodiments, the number of refresh cycles communicated to the memory controller and / or the number of corresponding commands inserted into the command queue may correspond to the number of adjacent memory regions identified at block 364. For example, refresh cycles and / or corresponding commands for each adjacent memory region identified at block 364 may be communicated to the memory controller and / or inserted into the command queue.

[0072] At box 366, the memory device receives from the memory controller a command corresponding to a refresh cycle inserted into the command queue of the memory controller at box 365. For example, the memory device may receive an ACT command, a PRE command, and / or a memory address corresponding to an adjacent memory region identified at box 364. Continuing this example, the memory device may receive the ACT command, PRE command, and / or the memory address of the corresponding adjacent memory region via a command / address bus that operatively connects the memory device to the memory controller. In cases where a refresh cycle has been initiated by the memory controller or by the host device (as opposed to by the memory device), the memory device may receive the ACT command, PRE command, and / or memory address from the memory controller in the same or similar manner as the memory device receives the ACT command, PRE command, and / or memory address from the memory controller. In some embodiments, the memory device may receive the ACT command, PRE command, and / or memory address as described above. Figure 2 The routine 250 and block 253 discuss the manner in which commands are received from the memory controller.

[0073] At block 367, routine 360 ​​continues to the memory device executing the corresponding command received from the memory controller at block 366. In some embodiments, the memory device may be related to the above-mentioned... Figure 2 The corresponding command is executed in a manner consistent with the discussion of block 254 of routine 250. For example, in response to receiving an ACT command and / or a memory address corresponding to an adjacent memory region from the memory controller, the memory device may activate the adjacent memory region. Continuing this example, in response to receiving a PRE command and / or a memory address corresponding to an adjacent memory region from the memory controller, the memory device may precharge the adjacent memory region. Activating and precharging the adjacent memory region may serve the adjacent memory region to reduce and / or mitigate the effect that the number of times the memory regions of blocks 361-363 are activated meets or exceeds the thresholds of blocks 362 and 363 (e.g., similar to a row hammer refresh operation). In some embodiments, after performing a refresh cycle on the adjacent memory region, the memory device may reset the count or value corresponding to the number of times the memory regions of blocks 361-363 have been activated.

[0074] Although boxes 361-367 of routine 360 ​​are discussed and explained in a specific order, Figure 3The routine 360 ​​described herein is not limited thereto. In other embodiments, routine 360 ​​may be executed in a different order. In these and other embodiments, any one of blocks 361-367 of routine 360 ​​may be executed before, during, and / or after any one of the other blocks 361-367 of routine 360. Furthermore, those skilled in the art will recognize that the described routine 360 ​​may be modified while remaining within these and other embodiments of the present invention. For example, in some embodiments, [specific details may be omitted and / or repeated]. Figure 3 The example 360 ​​described herein includes one or more boxes 361-367.

[0075] Embodiments of the present invention thus offer several advantages over other memory systems. For example, instead of using statistical sampling techniques to identify potential victim memory regions for row hammer refresh operations, a memory system configured according to embodiments of the present invention can implement a deterministic solution for RHR operations. Specifically, the memory system of the present invention can track the number of times a memory region is activated and use that count to identify aggressor (e.g., seed) and / or victim memory regions. This deterministic solution is expected to reduce the number of memory regions identified for RHR fading / servicing compared to the number of memory regions identified using statistical sampling techniques. Consequently, it is expected that the memory device consumes or requires less power for RHR operations because fewer memory regions are expected to receive RHR fading / servicing. Moreover, because fewer memory regions are expected to receive RHR fading / servicing, parallel activation of memory regions (e.g., parallel activation of memory rows) can be reduced during RHR operations. Therefore, it is expected that the memory system and / or device of the present invention achieves (i) reduced power demand, (ii) reduced strain or concurrency on the power delivery network of the memory device and / or memory system, and / or (iii) reduced noise injected into the peripheral circuitry of the memory device.

[0076] Alternatively, memory systems and apparatuses configured according to the present invention can perform all or part of the RHR reduction / servicing outside the memory refresh period or the cycle tRFC, which can improve system bandwidth and achieve a looser refresh timing specification. For example, as discussed above, various memory systems are configured to (i) perform RHR reduction / servicing after refreshing the memory region in response to receiving a refresh command and (ii) at the end of the corresponding memory refresh period tRFC. Therefore, these memory systems require a relatively long memory refresh period tRFC to ensure adequate timing margin for performing RHR operations after executing the refresh command. System bandwidth decreases as the length of the memory refresh period tRFC increases because the memory device is unavailable for access operations by the memory controller during the duration of the memory refresh period tRFC.

[0077] In contrast, the memory system and apparatus of the present invention can perform all or part of the RHR reduction / servicing outside the memory refresh period tRFC. For example, the memory system and apparatus of the present invention can perform... Figure 3 The routine 360 ​​may be performed in whole or in part. More specifically, the memory system and apparatus may perform RHR shaving / servicing outside the memory refresh period tRFC by responding to a command (e.g., an activation and / or precharge command) received from the memory controller instructing the memory device to specifically refresh a memory region identified as a victim memory region, thereby executing boxes 366 and 367. In these and other embodiments, the memory system and apparatus of the present invention may track the number of memory region activations within the memory refresh period tRFC (box 361), compare the number of activations with a threshold (box 362), determine whether the number of activations meets or exceeds the threshold (box 363), identify one or more adjacent memory regions (box 364), and / or insert refresh cycles for one or more adjacent memory regions into the command queue of the memory controller (box 365).

[0078] Therefore, it is desirable for the memory system and apparatus of the present invention to refresh the memory area and / or perform operations in response to a refresh command. Figure 3 The total time required for one or more of blocks 361-365 in routine 360 ​​is less than the total time required for other memory systems and devices to (i) refresh the memory region in response to receiving a refresh command and (ii) perform RHR reduction / servicing at the end of the corresponding memory refresh period tRFC. Therefore, the duration of the memory refresh period tRFC in the memory systems and devices of the present invention can be less than the duration of the memory refresh period tRFC in other memory systems and devices. The reduction in the duration of the memory refresh period tRFC can be translated as (i) an increase in the amount of time available to the memory controller (which can be translated as an increase in system bandwidth), (ii) a looser timing specification for performing refresh and / or other operations, and / or (iii) greater command scheduling flexibility.

[0079] The above references Figure 1A-3 Any of the memory systems, devices, and / or methods described above can be incorporated into any of a large number of larger and / or more complex systems, a representative example of which is... Figure 4 System 490 is schematically shown in the diagram. System 490 may include a semiconductor device assembly 400, a power supply 492, a driver 494, a processor 496, and / or other subsystems and components 498. Semiconductor device assembly 400 may include components generally similar to those described in the reference above. Figure 1A-3The characteristics of those features of the described memory system, apparatus, and / or method. The resulting system 490 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 490 may, without limitation, include handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 490 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 490 may also include remote devices and any of a variety of computer-readable media.

[0080] C. in conclusion

[0081] The above detailed description of embodiments of this technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. As those skilled in the art will recognize, although specific embodiments and examples of this technology have been described above for illustrative purposes, various equivalent modifications can be made within the scope of this technology. For example, while steps are presented and / or discussed in a given order, alternative embodiments may perform the steps in a different order. Furthermore, various embodiments described herein may be combined to provide other embodiments.

[0082] Based on the foregoing, it should be understood that specific embodiments of the present technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the present technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, unless the word “or” is explicitly limited to referring only to a single item exclusive to other items in a list referring to two or more items, the use of “or” in this list may be understood to include: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, as used herein, the phrase “and / or” in phrases such as “A and / or B” means only A, only B, and both A and B. Moreover, the terms “comprising,” “including,” “having,” and “with” are used throughout to mean at least one or more of the described features, such that any larger number of identical features and / or other features of additional types are not excluded.

[0083] Based on the foregoing, it should also be understood that various modifications can be made without departing from the present technology. For example, the various components of the present technology may be further divided into sub-components, or the various components and functions of the present technology may be combined and / or integrated. Furthermore, although advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also present these advantages, and not all embodiments are required to present these advantages to fall within the scope of the present technology. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A memory device comprising: The command insertion terminal is configured to be operatively connected to the memory controller. The memory device is configured to: Identify the conditions under which addressing can be performed by receiving commands from the memory controller, and The command or indication of the condition is output via the command insertion terminal so that the command is inserted into the command queue of the memory controller. The conditions include (i) the memory device determining that the memory device needs training, and / or (ii) the memory device determining that the memory device needs initialization.

2. The memory device according to claim 1, wherein: The memory device further includes a command terminal; and The memory device is further configured to receive the command from the memory controller via the command terminal after outputting the command or indication of the condition via the command insertion terminal.

3. The memory device according to claim 1, wherein: The command insertion terminal is the first command insertion terminal; and The memory device further includes a second command insertion terminal configured to be operatively connected to another memory device.

4. The memory device of claim 1, wherein the condition further comprises (iii) the memory device determining to output first data from the memory device to the memory controller, (iv) the memory device determining to receive second data from the memory controller, and / or (v) the memory device determining that a memory area of ​​the memory device needs to be refreshed.

5. The memory device of claim 4, wherein the memory device is further configured to output the memory address of the memory region via the command insertion terminal, such that the memory device performs a refresh cycle or operation on the memory region in response to receiving the command from the memory controller.

6. The memory device of claim 1, wherein the memory device is further configured to output an identifier of the memory device via the command insertion terminal, such that commands in the command queue target the memory device based on the identifier.

7. The memory device of claim 1, wherein the memory device is further configured to store a value representing the number of times a memory region of the memory device is activated.

8. The memory device according to claim 7, wherein: The memory area is the first memory area; The memory device is further configured to: Determine whether the value meets or exceeds the threshold. The memory address of the second memory region of the memory device is identified, and In response to receiving the command from the memory controller, a refresh cycle or operation is performed on the second memory region; and In the memory array of the memory device, the second memory region is adjacent to the first memory region.

9. A method of operating a memory device, comprising: Identify the conditions under which addressing can be achieved by receiving commands from the memory controller, and The command or indication of the condition is output via the command insertion terminal of the memory device so that the command is inserted into the command queue of the memory controller. The conditions include (i) the memory device determining that the memory device needs training, and / or (ii) the memory device determining that the memory device needs initialization.

10. The method of claim 9, further comprising inserting the command into the command queue of the memory controller.

11. The method of claim 9, further comprising receiving the command from the memory controller after outputting the instruction of the command or the condition.

12. The method of claim 11, further comprising: Before receiving the command from the memory controller, the identifier of the memory device is output via the command insertion terminal; or Before receiving the command from the memory controller, the memory address of the memory region is output via the command insertion terminal.

13. The method of claim 11, further comprising executing the command in response to receiving the command from the memory controller.

14. The method of claim 9, further comprising storing a value representing the number of times a memory region of the memory device has been activated.

15. The method of claim 14, wherein: The memory area is the first memory area; The method further includes: Determine that the value meets or exceeds the threshold, and The memory address of the second memory region of the memory device is identified; and In the memory array of the memory device, the second memory region is adjacent to the first memory region.

16. The method of claim 15, wherein: The conditions further include that the second memory region needs to be refreshed in a cycle or operation; and The method further includes: After outputting the command or the indication of the condition, the command is received from the memory controller, and In response to receiving the command from the memory controller, the second memory area is refreshed.

17. A memory system comprising: A memory controller having a memory command scheduler configured to generate command queues; A memory device having a command insertion terminal; and A command insertion signal trace operatively connects the command insertion terminal of the memory device to the memory command scheduler of the memory controller. The memory device is configured to: Identify the conditions under which addressing can be performed by receiving commands from the memory controller, and The command or condition indication is output to the memory command scheduler via the command insertion terminal and the command insertion signal trace, so that the command is inserted into the command queue. The conditions include (i) the memory device determining that the memory device needs training, and / or (ii) the memory device determining that the memory device needs initialization.

18. The memory system of claim 17, wherein the command insertion terminal of the memory device is operatively connected directly to the memory command scheduler of the memory controller via the command insertion signal trace.

19. The memory system according to claim 17, wherein: The memory system further includes a command / address bus that operatively connects the memory device to the memory controller; The memory controller is configured to send the command to the memory device via the command / address bus after the command is inserted into the command queue; and The memory device is further configured to execute the command in response to receiving the command from the memory controller via the command / address bus.

20. The memory system of claim 17, wherein: The memory device includes a memory array having a first memory region and a second memory region adjacent to the first memory region; and The memory device is further configured to: The storage represents a value indicating the number of times the first memory area has been activated. Determine whether the value meets or exceeds the threshold. Identify the memory address of the second memory region. After the command is inserted into the command queue, the command is received from the memory controller, and The command is executed in response to receiving the command from the memory controller to refresh the second memory area.

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