A method and apparatus for processing a consistent data monitoring request

Abstract

The application provides a processing method and device of a consistent data monitoring request, including obtaining a consistent request, a consistent monitoring request, and a processing load state of a consistent data monitoring stash request, and determining a processing mode of the stash request. When the load of a cache unit is low, a standard processing mode is used to perform a directed cache operation, high-frequency data is stored in a specified cache unit, the data access path is shortened, and the cache hit rate is improved. When the load of the cache unit is high, a degraded processing mode is used to avoid resource occupation by the stash operation, prevent blocking of regular data reading and writing and cache line state maintenance, and balance the performance of a multi-core consistent cache system. Based on the existing request processing logic of the cache unit, the consistent data monitoring stash request in the degraded processing mode is reused in the processing procedure of the consistent monitoring request, and the hardware resource occupation is reduced.

Description

Technical Field

[0001] This application relates to the fields of computer architecture and program compilation technology, and in particular to a method and apparatus for processing consistent data monitoring requests. Background Technology

[0002] The caching stashing mechanism is a mechanism that proactively stores data from a specified cache line into a target cache (which can be a local cache, an upper-level cache, or another core cache) based on cache unit requirements or software settings, while maintaining data consistency. With the increasing demands for large-scale applications and large data volume access, the number of chip cores is increasing, and the requirements for data access latency are becoming more stringent. Therefore, improving the speed at which chip cores acquire data and extending the retention time of data in the caching system has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this application is to at least partially solve one of the technical problems in the related art.

[0004] Therefore, the first objective of this application is to propose a method for processing consistent data listening requests.

[0005] The second objective of this application is to provide a processing apparatus for a consistent data monitoring request.

[0006] The third objective of this application is to propose an electronic device.

[0007] The fourth objective of this application is to provide a computer-readable storage medium.

[0008] The fifth objective of this application is to provide a computer program product.

[0009] The sixth objective of this application is to propose a chip.

[0010] To achieve the above objectives, a first aspect of this application proposes a method for processing consistent data monitoring requests, applied to a multi-core consistent caching system. The caching system includes multiple cache units, each of which implements data interaction and routing requests based on an interconnect bus bridge. The method for processing consistent data monitoring requests includes:

[0011] Receive various requests initiated or forwarded by peripherals, including consistency requests, consistency listening requests, and consistency data listening stash requests;

[0012] Process the consistency request to complete data reading, data writing, or state change operations; process the consistency monitoring request to complete the state maintenance operation of cache lines;

[0013] For the consistency data listening stash request, the processing load status of the cache unit is obtained. The load status reflects at least the current workload of processing the consistency request, the current workload of processing the consistency listening request, and the current workload of processing the consistency data listening stash request.

[0014] Based on the processing load status, it is determined whether the consistent data listening stash request should be processed in a standard processing mode or a degraded processing mode. In the standard processing mode, the data is stored in a specified cache unit. In the degraded processing mode, the consistent data listening stash request is processed as a consistent listening request.

[0015] To achieve the above objectives, a second aspect of this application provides a processing apparatus for a consistent data monitoring request, applied to a multi-core consistent caching system. The caching system includes multiple cache units, each of which implements data interaction and routing requests based on an interconnect bus bridge. The processing apparatus for the consistent data monitoring request is configured to implement the steps of the consistent data monitoring request processing method proposed in the first aspect of this application.

[0016] To achieve the above objectives, a third aspect of this application provides an electronic device, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the steps of the processing method for a consistent data monitoring request proposed in the first aspect of this application.

[0017] To achieve the above objectives, a fourth aspect of this application provides a computer-readable storage medium that, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the steps of the processing method for a consistent data monitoring request proposed in the first aspect of this application.

[0018] To achieve the above objectives, a fifth aspect of this application provides a computer program product, including a computer program that, when executed by a processor in a communication device, implements the steps of the processing method for a consistent data monitoring request proposed in the first aspect of this application.

[0019] To achieve the above objectives, a sixth aspect of this application provides a chip including one or more interface circuits and one or more processors; the interface circuits are used to receive signals and send the signals to the processors, the signals including computer instructions; when the processor executes the computer instructions, the chip performs the steps of the processing method for a consistent data monitoring request proposed in the first aspect of this application.

[0020] In this embodiment, the processing mode of a stash request is dynamically determined by acquiring the processing load status of consistency requests, consistency listening requests, and consistency data listening stash requests. When the load on the cache unit is low, the standard processing mode is used to perform targeted caching operations, storing high-frequency data in designated cache units, shortening subsequent data access paths, improving cache hit rate, and reducing data access latency. When the load on the cache unit is high, a degraded processing mode is adopted to avoid stash operations from preempting resources and to prevent basic operations such as regular data read / write and cache line status maintenance from being blocked, thus achieving a balance in the performance of the multi-core consistency caching system. Based on the existing request processing logic of the cache unit, the processing flow of the consistency listening request is reused for the consistency data listening stash request in the degraded processing mode, eliminating the need to design additional response logic for failed stash operations. At the same time, through the load status determination mechanism, the blind expansion of hardware queues to adapt to stash functionality is avoided, achieving efficient reuse of functional logic, reducing hardware resource consumption and code complexity, and lowering the R&D and deployment costs of the cache unit.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 A flowchart illustrating a method for processing a consistency data monitoring request provided in an embodiment of this application;

[0024] Figure 2 This is a schematic diagram of the interconnect structure of a multi-core coherent cache system provided according to an embodiment of this application;

[0025] Figure 3 This is a schematic diagram illustrating the interaction between various functional modules within the cache unit provided according to an embodiment of this application;

[0026] Figure 4 This is a functional diagram illustrating the consistency request processing provided according to an embodiment of this application;

[0027] Figure 5 This is a functional diagram illustrating the consistency monitoring request provided according to an embodiment of this application;

[0028] Figure 6 This is a functional diagram illustrating the consistent data monitoring stash request provided according to an embodiment of this application.

[0029] Figure 7This is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0030] Figure 8 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0032] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a” and “the” as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0033] It should be understood that although the terms first, second, third, etc., may be used to describe various information in the embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words "if" and "suppose" as used herein can be interpreted as "when," "when," or "in response to a determination."

[0034] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0035] The cache stash mechanism is a highly proactive and precisely targeted intelligent cache management strategy. Its core logic lies in proactively and accurately storing target data for a specified cache line to a pre-defined target cache node based on the real-time operational needs of the cache unit or pre-configured software layers. This target cache node can flexibly adapt to the complex architecture of multi-core systems. It can be a local core private cache initiating the request, an upper-layer cache used for data sharing, or a private cache of other collaborating cores. Throughout the entire data migration and storage process, it strictly adheres to multi-core cache consistency protocols (such as MESI and MOESI), ensuring data consistency among cache nodes through precise maintenance of cache line status (such as invalidated old data copies and synchronized data versions), thus avoiding data access errors caused by multi-copy conflicts.

[0036] As the demand for high computing power and high concurrency continues to rise, large-scale application scenarios (such as artificial intelligence training, real-time decision-making for autonomous driving, and data center computing) and the demand for large-scale data access (such as high-definition video stream processing and log analysis) are becoming increasingly popular. This directly drives the evolution of chip design towards multi-core and even many-core architectures. That is, the number of chip cores has gradually increased from the initial dual-core and quad-core to dozens or hundreds of cores, and the collaboration and data interaction between cores are more frequent.

[0037] However, data access latency has become a key bottleneck restricting the overall performance of caching systems. In a multi-core architecture, if a core frequently retrieves data from memory or a remote cache, its access latency can be tens or even hundreds of times that of the local cache, severely slowing down the core's computing efficiency. In scenarios involving large amounts of data access, the high frequency of data reading and writing further exacerbates the latency problem, and the core often needs to spend a lot of time waiting for data transmission instead of performing core computing tasks.

[0038] In some scenarios, existing caching mechanisms are ill-suited to current technological requirements. Most existing caching mechanisms employ a "passive caching" model, meaning data is only loaded from upper-level storage when the kernel initiates a data access request and misses the cache. Because the kernel's access requests cannot be predicted in advance, the first access to frequently accessed data suffers from high latency. Furthermore, the replacement strategies of existing caching mechanisms (such as Least Recently Used (LRU) and First-In-First-Out (FIFO) algorithms lack specificity. Frequently accessed critical data may be replaced by infrequently accessed temporary data, shortening the retention time of valid data in the cache system. This forces the kernel to repeatedly load the same data from the remote storage, further exacerbating the performance degradation of the caching system.

[0039] Against this backdrop, how to effectively improve the speed at which the chip core acquires data, shorten the data access path, and extend the retention time of critical data in the cache system and improve the cache hit rate by optimizing caching strategies has become an urgent technical problem to be solved in the field of multi-core cache system design.

[0040] The following describes a method and apparatus for processing consistency data monitoring requests according to embodiments of this application, with reference to the accompanying drawings.

[0041] Figure 1 This is a flowchart illustrating a method for processing a consistency data monitoring request, as provided in an embodiment of this application.

[0042] like Figure 1 As shown, the method for processing consistent data listening requests is applied to a multi-core consistent caching system. The caching system includes multiple cache units, each of which implements data interaction and routing requests based on an interconnect bus bridge. The method for processing consistent data listening requests includes, but is not limited to, the following steps:

[0043] S101 receives various requests initiated or forwarded by peripherals, including consistency requests, consistency listening requests, and consistency data listening stash requests.

[0044] In one feasible implementation, Figure 2 This is a schematic diagram of the interconnection structure of a multi-core coherent cache system provided according to an embodiment of this application. Figure 2 As shown, the peripherals initiating the request include, but are not limited to, Direct Memory Access (DMA) controllers, I / O devices (such as storage controllers and network interface cards), and external computing units. The peripherals establish a communication connection with the cache system's interconnect bus bridge via the system bus.

[0045] In one feasible implementation, such as Figure 2 As shown, peripherals generate corresponding request messages based on business needs (such as DMA data transfer, I / O device data write requests). These request messages include a request type identifier (distinguishing between consistency requests, consistency monitoring requests, and consistency data monitoring stash requests), the target address, and operation parameters (e.g., consistency data monitoring stash requests require the target cache unit ID). The peripherals send these request messages to the cache system's interconnect bus bridge via a pre-defined bus interface protocol (such as AXI or AHB), triggering the cache system's request receiving process. The interconnect bus bridge performs preliminary parsing of the received peripheral requests, verifying the validity of the request messages (e.g., checking the address range and the validity of the request type identifier). Valid requests proceed to the routing process, while invalid requests directly return an error response.

[0046] In some embodiments, such as Figure 2As shown, the peripheral device initiates a stash-type consistency request `req_stash`, specifying cache unit 2 to perform the data stash. `req_stash` enters the interconnect bus bridge 1 and is routed to cache unit 4 based on the target cache unit ID. Cache unit 4 processes `req_stash`, generating a corresponding consistency data listening stash request `snpstash_req` based on the request type and the target cache unit ID, and then sends `snpstash_req`. `snpstash_req` enters the interconnect bus bridge 1 and is routed to cache unit 2 based on the target cache unit ID. Cache unit 2 receives `snpstash_req`, processes it accordingly, and returns a response to cache unit 4. Cache unit 4 determines whether it needs to provide data to cache unit 2 based on the received response. If no data needs to be provided to cache unit 2, cache unit 4 can complete `snpstash_req`. If data needs to be provided to cache unit 2, cache unit 4, after obtaining the data, will transmit the data to cache unit 2 and wait for cache unit 2 to return a completion response indicating that the data has been received. Only then can cache unit 4 complete snpstash_req. Finally, cache unit 4 completes the req_stash response interaction with the peripheral device.

[0047] In one feasible implementation, the peripheral device acts as a request forwarding intermediary, forwarding requests initiated by other entities (such as the outer core, remote cache, and external storage device) to the interconnect bus bridge of the cache system, whereby the request type is ultimately received and processed by the target cache unit in the cache system.

[0048] In one feasible implementation, Figure 3 This is a schematic diagram illustrating the interaction between various functional modules within the cache unit provided according to an embodiment of this application.

[0049] like Figure 3 As shown, the consistency request buffer module is responsible for buffering consistency requests, including consistent read requests (DataNeed Request), consistent write requests (Write Request), and consistent no-data operation requests (DataLess Request, such as cache line status queries and permission change requests). Upon receiving a consistency request, the consistency request buffer module first checks its address relevance with the currently executing request (e.g., whether it accesses the same cache line). If a relevance exists, the consistency request is cached and executed only after the currently executing request has been processed. If resources are sufficient and there is no relevance, the consistency request is sent to the consistency request processing module of the cache unit.

[0050] like Figure 3As shown, the consistency listener request buffer module is responsible for buffering and temporarily storing consistency listener requests and consistency data listener stash requests. When the consistency listener request module is busy, this module will automatically cache the pending consistency listener requests into a queue, and schedule them for execution after the resources are released, so as to avoid request loss or blocking of the system bus.

[0051] like Figure 3 As shown, the consistency request processing module is responsible for handling various consistency requests, including consistent read requests (DataNeed Request), consistent write requests (Write Request), and consistent no-data operation requests (DataLess Request). This module also summarizes the currently processed request load information in real time and synchronizes it to the stash monitor, providing core data support for dynamically scheduling stash requests.

[0052] like Figure 3 As shown, the consistency monitoring request processing module is responsible for handling non-stash consistency monitoring requests and performing consistency assurance operations such as cache line state maintenance. This module summarizes the currently processed request load information in real time and synchronizes it to the stash monitor, providing key data support for dynamically scheduling stash requests.

[0053] like Figure 3 As shown, the stash monitor monitors the running status and load of the cache unit in real time, and dynamically determines whether to perform a stash data operation based on preset threshold conditions. When the conditions are met, stash-type consistency monitoring requests in the consistency monitoring request buffer module are scheduled to the consistency data monitoring stash request processing module to perform targeted caching operations; when the conditions are not met, the requests are forwarded to the consistency monitoring request processing module and processed in non-stash mode, thereby achieving dynamic optimization of cache performance while ensuring core business operations.

[0054] like Figure 3 As shown, the consistency data monitoring stash request processing module is responsible for handling stash-type consistency monitoring requests. After responding to such requests, it reuses the DataNeed Request processing flow from the consistency request processing module to achieve targeted storage of stash data. Simultaneously, this module aggregates the processing load information of the current requests in real time and synchronizes it to the stash monitor, providing data support for its dynamic scheduling decisions.

[0055] For example, the consistency request processing module is implemented using a queue architecture, with a total of 32 processing queues. Each execution queue has a 1-bit `req_valid_reg` register to indicate whether the current queue resource is occupied. This module summarizes the resource occupancy information of all queues, generates a `total_req_status_reg` register, and synchronizes the value of this register to the stash monitor. Similarly, the queue resource management and information summarization mechanisms of the consistency listening request processing module and the consistency data listening stash request processing module adopt the same logic as described above. Specifically, the consistency listening request processing module is configured with 16 processing queues, and the consistency data listening stash request processing module is configured with 8 processing queues. Both modules respectively generate `total_snp_status_reg` and `total_snpstash_status_reg` registers, and synchronize their respective register values ​​to the stash monitor, providing data support for its scheduling decisions.

[0056] S102 handles consistency requests to complete data reading, data writing, or state change operations; it also handles consistency listener requests to complete state maintenance operations on cache lines.

[0057] In one feasible implementation, Figure 4 This is a functional diagram illustrating the consistency request processing provided according to an embodiment of this application. Figure 4 As shown, after a consistent read request enters the consistent request processing module, it is processed step by step according to the following functional pipeline:

[0058] At the req_s0 level, read the local consistent directory information and obtain the local directory query results;

[0059] At the req_s1 level, the determination is made based on the local directory query results to clarify the data storage ownership scenario, which is specifically divided into three categories: hitting the local cache unit, hitting the upper-level cache unit, and missing both the local cache and the upper-level cache unit.

[0060] At the `req_s2` level, if a local cache unit is hit: directly read the local cache data, obtain the response data, and wait to enter the `req_s6` level; if an upper-level cache unit is hit: based on the consistency request type, convert it into the corresponding consistency listening request and initiate the consistency listening request to the upper-level cache unit; if neither the local nor the upper-level cache unit is hit: first determine whether the request needs to allocate a local cache unit. If no allocation is needed, wait to enter the `req_s4` level; if allocation is needed, further determine whether a local cache unit replacement operation needs to be performed to free up storage space. If replacement is needed, enter the `req_s3` level; otherwise, enter the `req_s4` level.

[0061] At the req_s3 level, if it is a scenario where the upper-level cache unit is hit: wait for the upper-level cache unit to return the status response and data response, and complete the response processing of the consistency listening request initiated by the local cache unit; if it is a scenario where the local cache unit is replaced: send a consistency replacement request reqB to the lower-level cache unit, and complete the reqB response interaction with the lower-level cache unit at this level.

[0062] At the req_s4 level, a consistent read request reqA is initiated to the lower-level cache unit to request the target data;

[0063] At the req_s5 level, wait for the target data to be returned from the lower-level cache unit, and complete the response interaction with the lower-level cache unit at this level;

[0064] At level req_s6, a response is provided to the current consistent read request req_read;

[0065] At the req_s7 level, wait for the upper-level cache unit to issue a termination response for the request, and synchronously modify the local consistency directory; if local data needs to be updated, complete the local data write operation at this level.

[0066] In one feasible implementation, Figure 5 This is a functional diagram illustrating the consistency monitoring request provided according to an embodiment of this application. Figure 5 As shown, after the consistency listener request (SNP) enters the consistency listener request processing module, it is processed step by step according to the following functional pipeline:

[0067] At the SNP_S0 level, read the local consistent directory information and obtain the local directory query results;

[0068] At the SNP_S1 level, the determination is based on the local directory query results to clarify the data storage ownership scenario, which is specifically divided into three categories: hitting the local cache unit, hitting the upper-level cache unit, and missing both the local cache unit and the upper-level cache unit.

[0069] At the SNP_S2 level, if it is determined that the upper-level cache unit has been hit, a consistency listening request snpA consistent with the current request type is sent to the upper-level cache unit.

[0070] At the snp_s3 level, wait for and receive the status response and data response returned by the upper-level cache unit to complete the processing loop of snpA request;

[0071] At the SNP_S4 level, if it is determined that a local cache unit is hit, or neither the local cache unit nor the upper-level cache unit is hit, then the corresponding processing operation is executed according to the specific type of the current consistency monitoring request and the local directory query result. After returning the response, the entire processing flow of this consistency monitoring request SNP is completed.

[0072] During the process of handling consistency listener requests (SNPs) by the consistency listener request processing module, the stash monitor uses multiple built-in registers to implement function control and status recording, as detailed below:

[0073] In the stash monitor, the stash_mode_config register is used to allocate independent physical addresses. It is readable and writable, supports dynamic software modification, and has a default value of 0. When the register value is 0, all consistency data listener stash requests determine whether to perform a data stash operation based on the system status; when the register value is 1, all consistency data listener stash requests force a data stash operation.

[0074] In the stash monitor, configure the `total_stash_num` and `actual_stash_num` registers and assign corresponding physical addresses. These registers are readable and writable, allowing software modification of their values. The default value is 0 upon reset. The `total_stash_num` register records the total number of consistency data listener stash requests received by the current cache unit; the `actual_stash_num` register records the number of requests that actually perform data stash operations.

[0075] In the stash monitor, configure the `req_disable_stash_num`, `snp_disable_stash_num`, and `snpstash_disable_stash_num` registers and assign them corresponding physical addresses. These registers are read-only and not writable, with a default reset value of 0. `req_disable_stash_num` records the number of requests that could not perform data stash operations due to insufficient resources in the consistency request processing queue; `snp_disable_stash_num` records the number of requests that could not perform data stash operations due to insufficient resources in the consistency listener queue; and `snpstash_disable_stash_num` records the number of requests that could not perform data stash operations due to insufficient resources in the consistency data listener stash queue.

[0076] In the stash monitor, set the consistency request register req_status_reg, the consistency listener request register snp_status_reg, and the consistency data listener stash request register snpstash_status_reg; these three registers are used internally by the monitor registers and are allocated physical addresses, and the register attributes are readable but not writable. The `req_status_reg` register records the number of ongoing consistency requests. Its bit width is the same as `total_req_status_reg` in the consistency request module, and its value comes from `total_req_status_reg`. Similarly, `snp_status_reg` records the number of ongoing consistency listener requests. Its bit width is the same as `total_snp_status_reg` in the consistency request module, and its value comes from `total_snp_status_reg`. Finally, `snpstash_status_reg` records the number of ongoing consistency data listener stash requests. Its bit width is the same as `total_snpstash_status_reg` in the consistency request module, and its value comes from `total_snpstash_status_reg`.

[0077] In the stash monitor, set the threshold registers `req_threshold_reg`, `snp_threshold_reg`, and `snpstash_threshold_reg` and assign corresponding physical addresses. These registers are readable and writable, allowing software modification of their configurations. The configuration range for all three registers is 0-9 (meaning 0%-90%), with a default value of 9. Specifically, when `req_threshold_reg` = 9 and the `req_status_reg` register has a 5-bit width, the currently recordable value is greater than 32. At 90%, data stash operations are paused; the value of 32 is determined by the maximum bit width of `req_status_reg`. When `snp_threshold_reg` = 5, the `snp_status_reg` register has a bit width of 4 bits, and the current record value is greater than 16. At 50%, data stash operations are paused. The value of 16 is determined by the maximum bit width of snpstash_status_reg. When snpstash_threshold_reg=0, the snpstash_status_reg register has a bit width of 3 bits, and the current record value is greater than 8. At 0%, data stash operations are paused. The value of 8 is determined by the maximum bit width of snpstash_status_reg. The threshold register also has the function of pausing data stash operations.

[0078] For example, when snpstash_threshold_reg=0, the snpstash_status_reg register has a bit width of 3 bits, so the current record value is greater than 8. At 0%, data stash operations are paused. The value of 8 is determined by the maximum bit width of snpstash_status_reg. The threshold register also has the function of pausing data stash operations.

[0079] In the stash monitor, the `stash_enable` flag is set, and the final decision on whether to perform a data stash operation is based on the specific register configurations mentioned above. When `stash_mode_config` is configured to 1, `stash_enable` is 1, and the values ​​of the resource monitoring register and threshold register are ignored. When `stash_mode_config` is configured to 0, `stash_enable` is determined by the logical AND result of `req_enable`, `snp_enable`, and `snpstash_enable`, as follows:

[0080] req_enable: req_threshold_reg The maximum allowed number of requests (req) is 32, which is 90%. 32 = 28.8, rounded up to 29. When the value of req_status_reg is greater than 29, then req_enable = 0; otherwise, req_enable = 1.

[0081] snp_enable: snp_threshold_reg The maximum number of SNPs allowed to process is 16, which is 90%. 16 = 14.4, rounded up to 15. When the value of snp_status_reg in the system is greater than 15, then snp_enable = 0; otherwise, snp_enable = 1.

[0082] snpstash_enable: snpstash_threshold_reg Snpstash allows a maximum of 8 processes, which is 90%. 8 = 7.2, rounded up to 8. When the snpstash_status_reg value in the system is greater than 8, then snpstash_enable = 0; otherwise, snpstash_enable = 1. This means that the snpstash queue is allowed to be fully used at this time.

[0083] `stash_enable=req_enable&&snp_enable&&snpstash_enable`. If `stash_enable` is 1, the data stashing operation is performed, and the consistency data listener stashing request will be processed by the consistency data listener stashing processing module. If `stash_enable` is 0, the data stashing operation is not performed, and the consistency data listener stashing request will be treated as a normal SNP request and processed by the consistency listener processing module.

[0084] When `req_enable` is 0, data stash operations are stopped, and `req_disable_stash_num` is incremented by 1 to record this. Similarly, when `snp_enable` is 0, `snp_disable_stash_num` is incremented by 1; when `snpstash_enable` is 0, `snpstash_disable_stash_num` is incremented by 1.

[0085] If multiple enable values ​​(including req_enable, snp_enable, and snpstash_enable) are all 0, the priority rule for incrementing by 1 is: snpstash_disable_stash_num > snp_disable_stash_num > req_disable_stash_num.

[0086] For example, in a DMA data transfer program, when stash_mode_config is configured to 0, reading total_stash_num and actual_stash_num yields the following data:

[0087] When total_stash_num equals actual_stash_num, it indicates that the internal executable queue resources are sufficient. By configuring the corresponding threshold register, a maximum queue configuration value for consistency requests, consistency listener requests, and consistency data listener stash requests can be found, allowing for reasonable adjustment of hardware resources.

[0088] When total_stash_num is greater than actual_stash_num, it indicates that some data stash operations failed to be executed. In this case, by reading req_disable_stash_num, snp_disable_stash_num, and snpstash_disable_stash_num, the specific reason why the data stash request was not executed can be obtained. If req_disable_stash_num is greater than snp_disable_stash_num and snpstash_disable_stash_num, it means that the number of consistency request queue items is likely insufficient. In this case, the situation of being disabled can be alleviated by increasing the number of consistency request queue items.

[0089] S103, for consistent data listening stash requests, obtain the processing load status of the cache unit. The load status reflects at least the current workload of processing consistent requests, the current workload of processing consistent listening requests, and the current workload of processing consistent data listening stash requests.

[0090] In one feasible implementation, the corresponding load quantization data is collected through the first type of resource monitoring register (i.e., the total_req_status_reg register), the second type of resource monitoring register (i.e., the total_snp_status_reg register), and the third type of resource monitoring register (i.e., the total_snpstash_status_reg register) built into the cache unit, respectively, wherein:

[0091] The first type of resource monitoring register records the number of consistency requests currently being executed in the cache unit. The bit width of the first type of resource monitoring register matches the total number of items in the consistency request queue. The second type of resource monitoring register records the number of consistency listening requests currently being executed in the cache unit. The bit width of the second type of resource monitoring register matches the total number of items in the consistency listening request queue. The third type of resource monitoring register records the number of consistency data listening stash requests currently being executed in the cache unit. The bit width of the third type of resource monitoring register matches the total number of items in the consistency data listening stash request queue. The current values ​​of the first, second, and third type of resource monitoring registers are used as quantitative indicators of the cache unit's processing load status.

[0092] In one feasible implementation, the cache unit's load status processing also includes the cache unit's queue resource occupancy ratio, which is obtained by: reading the total number of corresponding queue items for each type of request in multiple requests, determining the current value of each type of resource monitoring register (including the first type of resource monitoring register, the second type of resource monitoring register, and the third type of resource monitoring register), and determining the ratio of the current value to the total number of corresponding queue items.

[0093] In one feasible implementation, if the ratio of any current value to the total number of items in the corresponding queue exceeds a preset ratio (for example, the preset ratio is 90%), the current load state of the cache unit is marked as abnormal, and the corresponding abnormal count is triggered. The abnormal count is a readable but not writable attribute that supports software reading for performance debugging of multi-core consistent cache systems.

[0094] S104. Based on the processing load status, determine whether to use the standard processing mode or the degraded processing mode for the consistency data listening stash request. In the standard processing mode, the data is stored in the specified cache unit. In the degraded processing mode, the consistency data listening stash request is processed as a consistency listening request.

[0095] In one feasible implementation, the current workload for processing consistency requests is compared with a first preset threshold; the current workload for processing consistency monitoring requests is compared with a second preset threshold; the current workload for processing consistency data monitoring stash requests is compared with a third preset threshold; if the current workload for processing consistency requests is less than the first preset threshold, the current workload for processing consistency monitoring requests is less than the second preset threshold, and the current workload for processing consistency data monitoring stash requests is less than the third preset threshold, it is determined that the standard processing mode is adopted for consistency data monitoring stash requests; otherwise, it is determined that the degraded processing mode is adopted for consistency data monitoring stash requests.

[0096] In some embodiments, Figure 6 This is a functional diagram illustrating the consistent data monitoring stash request provided according to an embodiment of this application. Figure 6 As shown, when a consistent data listener stash request is entered into the consistent listener request processing module, it is processed step by step according to the following functional pipeline:

[0097] At snpstash_s0 ​​level, read local consistent directory information and obtain local directory results;

[0098] At snpstash_s1 level, the corresponding function is executed based on the obtained directory results. The result information is divided into three categories: hit local cache unit, hit upper cache unit, and miss both local cache unit and upper cache unit.

[0099] At snpstash_s2 level, a consistency listener request snpB is initiated to the upper-layer cache unit to obtain data and perform invalidation operations. The purpose is to transfer the hit data of the upper-layer cache unit to the local cache unit.

[0100] At snpstash_s3 level, wait to receive the response from snpB, call req_s2 and req_s3 levels to complete the update of the snpB local cache;

[0101] At snpstash_s4 level, listen for stash requests for current consistent data and return responses to notify the lower-level cache unit that it needs to provide the target data.

[0102] At the snpstash_s5 level, the function pipeline is invoked according to different hit conditions. Specifically: when the local directory result hits the local cache unit, the req_s5 and req_s7 levels are invoked, and the function pipeline completes the subsequent data stash operation; when the local directory result hits the upper-level cache unit, the req_s5 and req_s7 levels are invoked to complete the subsequent data stash operation; when the local directory result misses both the local cache unit and the upper-level cache unit, the req_s2, req_s3, req_s5, and req_s7 levels are invoked to complete the subsequent data stash operation.

[0103] In one feasible implementation, the method for processing consistent data listening requests further includes:

[0104] A mandatory standard mode is provided, which is activated by setting the value of the configuration register in the cache unit. When the mandatory standard mode is activated, the processing load state of the cache unit is ignored, and the standard processing mode is adopted for all received consistency data listener stash requests. In the degraded processing mode, for consistency data listener stash requests processed as consistency listener requests, the cache line invalidation operation or state degradation operation is performed without triggering data acquisition and storage.

[0105] In summary, the consistency data monitoring request processing method provided in this application dynamically determines the processing mode of the stash request by acquiring the processing load status of the consistency request, the consistency monitoring request, and the consistency data monitoring stash request. When the load of the cache unit is low, the standard processing mode is used to perform targeted caching operations, storing high-frequency data in the designated cache unit, shortening the subsequent data access path, improving the cache hit rate, and reducing data access latency. When the load of the cache unit is high, the degradation processing mode is adopted to avoid stash operations from preempting resources and to prevent basic operations such as regular data reading and writing and cache line status maintenance from being blocked, thus achieving a balance in the performance of the multi-core consistency caching system. Based on the existing request processing logic of the cache unit, the consistency data monitoring stash request in the degradation processing mode reuses the processing flow of the consistency monitoring request, eliminating the need to design additional response logic for failed stash operations. At the same time, through the load status determination mechanism, the blind expansion of the hardware queue to adapt to the stash function is avoided, achieving efficient reuse of functional logic, reducing hardware resource consumption and code complexity, and lowering the R&D and deployment costs of the cache unit.

[0106] Corresponding to the above-described method for processing consistency data monitoring requests, this application also provides an apparatus for processing consistency data monitoring requests. Since the embodiments of the apparatus for processing consistency data monitoring requests in this application correspond to the embodiments of the method for processing consistency data monitoring requests described above, details not disclosed in the embodiments of the apparatus for processing consistency data monitoring requests can be found in the embodiments of the method for processing consistency data monitoring requests, and will not be repeated here.

[0107] In one feasible implementation, the processing device for the consistency data monitoring request of the multi-core processor performs the steps of the consistency data monitoring request processing method provided in the embodiments of this application. In some embodiments, the consistency data monitoring request processing device has specific functional modules, algorithms, or logic, and can apply a standard processing mode or a degraded processing mode to the consistency data monitoring stash request according to a series of steps, rules, and strategies of the consistency data monitoring request processing method described in the embodiments of this application. In some embodiments, by writing specific program code, the consistency data monitoring request processing method is transformed into instructions that the consistency data monitoring request processing device can understand and execute. This code may include logic such as condition judgment, loop control, and data processing, and applies a standard processing mode or a degraded processing mode to the consistency data monitoring stash request.

[0108] The methods and apparatus provided in the embodiments of this application have been described above. To achieve the functions of the methods provided in the embodiments of this application, the methods and apparatus can be further refined using electronic devices.

[0109] Figure 7 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Figure 7 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0110] like Figure 7 As shown, the electronic device 700 includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a memory 706 into a random access memory (RAM) 703. The RAM 703 also stores various programs and data required for the operation of the electronic device 700. The processor 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0111] The following components are connected to I / O interface 705: memory 706 including hard disk; and communication section 707 including network interface card such as LAN (Local Area Network) card, modem, etc., communication section 707 performs communication processing via a network such as the Internet; drive 708 is also connected to I / O interface 705 as needed.

[0112] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via the communication section 707. When the computer program is executed by the processor 701, it performs the functions defined in the methods of this application.

[0113] In an exemplary embodiment, a storage medium including instructions is also provided, such as a memory including instructions, which can be executed by a processor 701 of an electronic device 700 to perform the above-described method. Optionally, the storage medium may be a non-transitory computer-readable storage medium, such as a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device.

[0114] In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0115] In this embodiment of the disclosure, a computer program product is also provided, including a computer program that, when executed by a processor, implements the method disclosed in the above embodiments.

[0116] For cases where the corresponding electronic device can be a chip or a chip system, please refer to [reference needed]. Figure 8 The diagram shows the result of the chip. Figure 7 The chip shown includes one or more interface circuits 802 and one or more central processing units 801; the interface circuits 802 are used to receive signals from the memory of the electronic device and send signals to the processor 801, the signals including computer instructions stored in the memory device 803, when the processor 801 executes the computer instructions, causing the electronic device to execute the multi-core processor consistency verification method proposed in the embodiments of this application.

[0117] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0118] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for processing consistent data monitoring requests, applied to a multi-core consistent caching system, wherein the caching system includes multiple caching units, and each caching unit implements data interaction and routing requests based on an interconnect bus bridge, characterized in that... include: Receive various requests initiated or forwarded by peripherals, including consistency requests, consistency listening requests, and consistency data listening stash requests; Process the consistency request to complete data reading, data writing, or state change operations; process the consistency monitoring request to complete the state maintenance operation of cache lines; For the consistency data listening stash request, the processing load status of the cache unit is obtained. The load status reflects at least the current workload of processing the consistency request, the current workload of processing the consistency listening request, and the current workload of processing the consistency data listening stash request. Based on the processing load status, it is determined whether the consistent data listening stash request is processed in a standard processing mode or a degraded processing mode. In the standard processing mode, the data is stored in a specified cache unit. In the degraded processing mode, the consistent data listening stash request is processed as a consistent listening request. The process load status of the cache unit is obtained, wherein the cache unit processing load status includes the queue resource utilization ratio of the cache unit, and the queue resource utilization ratio is obtained through the following method: The load quantization data is collected through the first type of resource monitoring register, the second type of resource monitoring register, and the third type of resource monitoring register built into the cache unit, respectively. The first type of resource monitoring register records the number of consistency requests currently being executed in the cache unit, and the bit width of the first type of resource monitoring register matches the total number of items in the consistency request queue; The second type of resource monitoring register records the number of consistency monitoring requests currently being executed in the cache unit, and the bit width of the second type of resource monitoring register matches the total number of items in the consistency monitoring request queue; The third type of resource monitoring register records the number of consistency data listening stash requests currently being executed in the current cache unit, and the bit width of the third type of resource monitoring register matches the total number of items in the queue of consistency data listening stash requests; The current values ​​of the first type of resource monitoring register, the second type of resource monitoring register, and the third type of resource monitoring register are used as quantitative indicators of the load status of the cache unit; the total number of corresponding queues for each type of request in multiple requests is read, the current value of each type of resource monitoring register is determined, and the ratio of the current value to the total number of corresponding queues is determined.

2. The method according to claim 1, characterized in that, The step of obtaining the processing load status of the cache unit also includes: If the ratio of any of the current values ​​to the total number of items in the corresponding queue exceeds a preset ratio, the current load status of the cache unit is marked as abnormal, and the corresponding abnormal count is triggered. The abnormal count is a readable but not writable attribute that supports software reading for performance debugging of multi-core consistent cache systems.

3. The method according to claim 1, characterized in that, The step of determining whether to use a standard processing mode or a degraded processing mode for the consistent data listening stash request based on the processing load status includes: The current workload for processing consistency requests is compared with a first preset threshold; the current workload for processing consistency monitoring requests is compared with a second preset threshold; the current workload for processing consistency data monitoring stash requests is compared with a third preset threshold. If the current workload of processing the consistency request is less than the first preset threshold, the current workload of processing the consistency monitoring request is less than the second preset threshold, and the current workload of processing the consistency data monitoring stash request is less than the third preset threshold, it is determined that the standard processing mode is adopted for the consistency data monitoring stash request. Otherwise, the stash request for the consistency data monitoring is determined to be processed in a degraded mode.

4. The method according to claim 1, characterized in that, The method further includes: A forced standard mode is provided, which is activated by setting the value of the configuration register in the cache unit; When the mandatory standard mode is activated, the processing load status of the cache unit is ignored, and the standard processing mode is determined for all received consistent data listening stash requests.

5. The method according to claim 1, characterized in that, Also includes: In the degradation processing mode, for the consistency data listening stash request processed as a consistency listening request, invalidation operation or state degradation operation of cache line is performed, without triggering data acquisition and storage.

6. A processing apparatus for consistent data monitoring requests, applied to a multi-core consistent caching system, the caching system comprising multiple caching units, each caching unit implementing data interaction and routing requests based on an interconnect bus bridge, characterized in that... The steps are configured to implement the method of any one of claims 1 to 5.

7. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps of the method according to any one of claims 1 to 5.

8. A chip, characterized in that, The chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the method according to any one of claims 1 to 5.

Images