A dual-band power amplifier with band-pass filtering characteristics

Abstract

The application discloses a dual-frequency power amplifier with band-pass filtering characteristics, wherein the power amplifier comprises an input matching network, a gate bias circuit, a stabilizing circuit, a transistor, a harmonic control network, a drain bias circuit and an output matching network; the input matching network adopts a matching circuit structure with band-stop filtering characteristics, aims to generate transmission zero points with high suppression between passbands, and provides good inter-band suppression; the output matching network adopts a dual-frequency structure with band-pass filtering characteristics, aims to realize matching in target frequency bands, and provides good out-of-band suppression; and good dual-frequency filtering effect is realized through cooperation of the input and the output. The application can realize good dual-frequency filtering effect, realize wider passband bandwidth at two frequencies than traditional design, and realize high-efficiency output in dual-frequency bands.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and specifically to a dual-frequency power amplifier with bandpass filtering characteristics. Background Technology

[0002] The rapid development of wireless communication technology and the mobile internet has drastically changed people's production and lifestyles, while also placing higher demands on radio frequency (RF) front-ends, requiring them to meet diverse industrial application standards. With the advent of the 5G era, mobile communication needs to be compatible with 2G, 3G, 4G, and multiple dispersed 5G frequency bands, leading to severe challenges for RF front-ends in terms of multi-band and multi-mode operation. This places higher demands on the multi-frequency operating capabilities of power amplifiers and the multi-frequency filtering performance of filters, including but not limited to good out-of-band rejection, inter-passband rejection, and wider passband bandwidth.

[0003] Typically, power amplifiers and filters in the RF links of communication or radar systems need to be designed separately based on a 50Ω system and cascaded to achieve signal filtering and amplification. This design method not only makes the design process cumbersome, but also introduces additional insertion loss to the link, which in turn leads to reduced system performance and increased overall circuit size.

[0004] To address the aforementioned issues, it is crucial to deeply integrate filtering and power amplification functions at the circuit level, designing a dual-band power amplifier with high out-of-band rejection, wider bandwidth, and filtering capabilities. The core innovation of this invention, addressing these application requirements, lies in a circuit design that integrates an input matching circuit with band-stop filtering characteristics with a dual-band output matching circuit with band-pass filtering characteristics. This embeds the filtering structure within the power amplifier's matching network, effectively resolving the aforementioned key technical problems. Summary of the Invention

[0005] To solve the above problems, the technical solution of the present invention is: a dual-frequency power amplifier with bandpass filtering characteristics, comprising an input matching network, a gate bias circuit, a stabilizing circuit, a transistor, a drain bias circuit, a harmonic control network, and an output matching network;

[0006] The input terminal of the input matching network serves as the power input terminal, and the output terminal is connected to the stabilizing circuit. The stabilizing circuit is connected in series between the input matching network and the transistor, and the output terminal is connected to the gate of the transistor.

[0007] The gate bias circuit is connected in parallel between the input matching network and the stabilization circuit, and its end is connected in parallel to ground through a decoupling capacitor Cg.

[0008] The drain of the transistor is connected to the input terminal of the harmonic control network, the harmonic control network is connected to the output matching network, the output terminal of the output matching network serves as the power output terminal, the drain bias circuit is connected in parallel in the harmonic control network, and the end is connected in parallel to ground through the decoupling capacitor Cd.

[0009] Preferably, the input matching network adopts a matching circuit with band-stop filtering characteristics, which is composed of a DC blocking capacitor C1 and microstrip lines TL1 to TL8. The specific connection relationship is as follows: one end of microstrip line TL1 is connected to the RF signal input terminal, and the other end is connected to one end of DC blocking capacitor C1; the other end of DC blocking capacitor C1 is connected in series through microstrip lines TL2, TL4, TL6, and TL8 in sequence, and the end of the series path is connected to the subsequent circuit; at the series node of microstrip lines TL2 and TL4, a microstrip line TL3 with its other end in an open circuit state is connected in parallel; at the series node of microstrip lines TL4 and TL6, a microstrip line TL5 with its other end in an open circuit state is connected in parallel; at the series node of microstrip lines TL6 and TL8, a microstrip line TL7 with its other end in an open circuit state is connected in parallel.

[0010] Preferably, the gate bias circuit includes a microstrip line TL9 and a decoupling capacitor Cg. The microstrip line TL9 is connected in parallel at the node of microstrip lines TL8 and TL10. The decoupling capacitor Cg is connected between the non-parallel terminal of the microstrip line TL9 and ground. The bias voltage of the gate bias circuit is VG.

[0011] Preferably, the stabilizing circuit includes microstrip line TL10, a parallel circuit of C2 and R1, and microstrip line TL11, wherein one end of microstrip line TL10 is connected in series with microstrip line TL8, and the other end is connected in series with the parallel circuit of C2 and R1 and microstrip line TL11 in sequence, and the other end of TL11 is connected to the gate terminal of the transistor.

[0012] Preferably, the harmonic control network includes microstrip lines TL12, TL13, TL14, and TL15, wherein one end of microstrip line TL12 is connected to the drain of the transistor, and the other end of microstrip line TL15 is connected in series with the output matching network; at the connection node of microstrip lines TL12 and TL15, microstrip lines TL13 and TL14 are also connected in parallel, and the other ends of TL13 and TL14 are both set to open circuit.

[0013] Preferably, the output matching network employs a dual-frequency matching circuit with bandpass filtering characteristics, including microstrip lines TL17 to TL25 and a DC blocking capacitor C3; the complex impedance is converted to a real impedance through microstrip lines TL17 and TL18, and a bandpass filter impedance converter is designed through microstrip lines TL19 to TL24, wherein one end of microstrip line TL25 is connected to the output terminal, and the other end of microstrip line TL25 is connected to one end of the DC blocking capacitor C3; the other end of the DC blocking capacitor C3 is sequentially connected to microstrip lines TL24, TL17 to TL25, and TL18 to TL25. L22, TL21, and TL19 form a series path, the end of which is connected to the harmonic control network via microstrip line TL17; at the series node of microstrip lines TL24 and TL22, microstrip line TL23 with its other end open is connected in parallel; at the series node of microstrip lines TL22 and TL21, microstrip line TL20 with its other end open is connected in parallel; at the series node of microstrip lines TL21 and TL19, microstrip line TL18 with its other end open is connected in parallel.

[0014] To achieve the above objectives, the present invention provides a dual-frequency power amplifier with bandpass filtering characteristics, comprising the following steps:

[0015] S10: In high-frequency circuit simulation software, source-pull and load-pull are performed on the transistor at target frequencies f1 and f2. After multiple iterations, the midpoint of the line connecting the maximum efficiency point and the maximum power point is selected as the optimal load impedance value Z. L,f1 and Z L,f2 With the optimal source impedance value Z S,f1 and Z S,f2 ;

[0016] S20: Design bias and stabilization circuits to ensure normal circuit operation;

[0017] S30: Design a harmonic control network to achieve harmonic suppression by setting a λ / 4 open stub at the second harmonic frequency;

[0018] S40: Design an output matching network that converts complex impedance to real impedance through a three-segment matching structure and uses a bandpass filter impedance converter to achieve dual-frequency real impedance matching.

[0019] S50: Design the input matching network, using an input matching circuit structure with band-stop filtering characteristics;

[0020] S60: Circuit simulation is performed using high-frequency circuit simulation software to optimize various performance indicators.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] This invention successfully designed and implemented a high-performance dual-band filtered power amplifier. Its core advantages lie in achieving a balance between high efficiency and high integration. It effectively solves the problems of coexistence interference and spurious radiation in multi-frequency systems, eliminates the need for external filters, and provides an integrated solution for compact wireless communication front-ends. At the same time, this dual-band filtered power amplifier has excellent out-of-band and inter-band filtering characteristics. In addition, this dual-band filtered power amplifier has a wider bandwidth compared to traditional dual-band power amplifiers. Attached Figure Description

[0023] Figure 1 This is a topology diagram of a dual-frequency power amplifier with bandpass filtering characteristics provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the overall circuit structure of a dual-frequency power amplifier with bandpass filtering characteristics provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the output matching section circuit of a dual-frequency power amplifier with bandpass filtering characteristics provided in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the input matching section circuit of a dual-frequency power amplifier with bandpass filtering characteristics provided in an embodiment of the present invention.

[0027] Figure 5 This is an S-parameter diagram of the overall circuit of a dual-frequency power amplifier with bandpass filtering characteristics provided in an embodiment of the present invention;

[0028] Figure 6 This is a curve showing the power-added efficiency as a function of frequency for a dual-frequency power amplifier with bandpass filtering characteristics provided in an embodiment of the present invention.

[0029] Figure 7 This is a curve showing the output power of a dual-frequency power amplifier with bandpass filtering characteristics as a function of frequency, provided in an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0031] Conversely, this invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the invention as defined in the claims. Furthermore, to provide a better understanding of the invention, certain specific details are described in detail below. However, those skilled in the art will fully understand the invention even without these detailed descriptions.

[0032] In response to the shortcomings of existing technologies, the applicant has conducted in-depth research on the structure of traditional dual-frequency filtering high-efficiency power amplifiers in the prior art. The applicant found in the research that the existing traditional dual-frequency filtering high-efficiency power amplifiers have a relatively simple mode, a relatively complex structure, are difficult to implement, have a large overall circuit size, and have relatively high costs.

[0033] To overcome the shortcomings of existing technologies, see Figure 1 The diagram shown is a block diagram of the power amplifier structure of the present invention, including an input matching network 21, an RC stabilization circuit 27, a gate bias circuit 35, a transistor 42, a harmonic control network 51, a drain bias circuit 55, and an output matching network 61.

[0034] For the transistor, the Cree CGH40010F was selected, which has a small-signal gain of 14-16dB, a saturation gain of 10dB, and a saturation output power exceeding 10W. According to the datasheet, it was operated in Class AB mode, with a gate bias set to -2.8V and a drain bias set to 28V. This example aims to achieve high-efficiency output at 1.8GHz and 3.0GHz frequencies, increasing bandwidth at each frequency point, while also providing filtering functionality.

[0035] The present invention provides a dual-frequency power amplifier with bandpass filtering characteristics, comprising the following steps:

[0036] S10: In high-frequency circuit simulation software, source-pull and load-pull are performed on the transistor at target frequencies f1 and f2. After multiple iterations, the midpoint of the line connecting the maximum efficiency point and the maximum power point is selected as the optimal load impedance value Z to be matched later. L,f1 and Z L,f2 With the optimal source impedance value Z S,f1 and Z S,f2 Z L,f1 =R a +jX a Z L,f2 =R b +jX b Z S,f1 =R c +jX c Z S,f2 =R d +jX d , where Ra R b R c R d and X a X b X c X d These are the real and imaginary parts of the optimal impedance values ​​at the two frequencies obtained by load traction, respectively.

[0037] S20: Design bias and stabilization circuits to ensure normal circuit operation;

[0038] like Figure 1 As shown, the bias circuit includes drain bias and gate bias circuits, both of which are constructed by connecting a quarter-wavelength microstrip line with a frequency of (f1+f2) / 2 in series and a 100pF grounding capacitor in parallel. Its function is to provide DC power to the entire power amplifier.

[0039] like Figure 2 As shown, the stabilization circuit includes a microstrip line TL10, a parallel circuit of C2 and R1, a microstrip line TL11, a parallel circuit consisting of microstrip line TL10, C2=5.6pF and R1=15Ω, and microstrip line TL11 connected in series. This ensures that the stability factor of the power amplifier is greater than 1 throughout the entire operating frequency band.

[0040] S30: Design a harmonic control network to achieve harmonic suppression by setting a λ / 4 open stub at the second harmonic frequency;

[0041] like Figure 2 The harmonic control network shown includes microstrip lines TL12, TL13, TL14, and TL15. Microstrip line TL13 has an electrical length of 90° at a frequency of 2f1, thus short-circuiting the signal at 2f1. Microstrip line TL14 also has an electrical length of 90° at a frequency of 2f2, thus also short-circuiting the signal at 2f2. Microstrip lines TL12 and TL15 primarily serve a tuning function; their values ​​can be obtained through tuning.

[0042] S40: Design an output matching network that converts complex impedance to real impedance through a three-segment matching structure and uses a bandpass filter impedance converter to achieve dual-frequency real impedance matching.

[0043] like Figure 3 As shown, the dual-frequency output matching circuit consists of microstrip lines TL17, TL18, TL19, TL20, TL21, TL22, TL23, TL24, TL25 and DC blocking capacitor C3. The matching process is divided into three steps: First, microstrip line TL17 is used to connect the complex impedance Z at point A at the two frequencies. L,f1 and Z L,f2 Transformed into a pair of conjugate complex admittances Y(f1)=G B+jB B and Y(f2)=G B -jB B The second step involves using a microstrip line TL18 to cancel the imaginary part B at two frequencies. B We obtained Z at two frequencies. inB The design obtains the actual impedance input; finally, a bandpass filter impedance matching converter is used to complete the matching between the actual impedances of the two frequencies. The dual-frequency output matching circuit proposed in this design can achieve out-of-band suppression for both frequencies.

[0044] (1)

[0045] (2)

[0046] Where m = f2 / f1 is the ratio of the two operating frequencies, n is any integer, and Z1 and θ1 are the characteristic impedance and electrical length of the microstrip line TL17.

[0047] The characteristic impedance Z1 and electrical length θ1 of the microstrip line TL17 can be obtained in the first step according to formulas (1) and (2).

[0048] (3)

[0049] (4)

[0050] The second step, based on formulas (3) and (4), yields the characteristic impedance Z2 and electrical length θ2 of the microstrip line TL18. Furthermore, Z2 can be obtained. inB =20Ω.

[0051] The third step consists of a bandpass filter impedance matching structure. The matrix elements of the complete ABCD matrix topology can be represented by the following formula:

[0052] (5)

[0053] Where a i b i c i and d i It is a polynomial containing the characteristic impedances of cascaded microstrip lines and parallel stubs, A T B T C T D T The ABCD matrix parameters describe the overall transmission characteristics of the bandpass filter impedance matching structure. Then, the S-parameters of the two-port symmetrical lossless structure can be derived.

[0054] (6)

[0055] Z LThis is the load impedance of the structure, which is 50Ω. Assume Z... inB / Z L =k is the impedance transformation ratio, and then we can obtain the following equation:

[0056] (7a)

[0057] (7b)

[0058] Where m = 0, 2, 4, n = 1, 3, 5, and F Structure It is the characteristic function of this topology. The theoretical Chebyshev transit number is given by formula (8a).

[0059] (8a)

[0060] (8b)

[0061] Where ε is the in-band equal ripple factor, l1, l3, and l5 are the values ​​containing θ. C polynomial (θ) C (This represents the bandwidth for transmitting this topology). To achieve the same Chebyshev reaction, the following equation (9) needs to be established.

[0062] (9)

[0063] (10)

[0064] refer to Figure 2 Where θ = 90° is taken as the variable bandwidth θ C Under the condition of 60°, based on the above design closed equation (5)-(10), Z3, Z4, Z5, Z6, and Z can be obtained. S1 Z S2 The value is then determined. Then, the DC blocking capacitor C3 = 10pF, the microstrip line TL25 acts as a tuner, the characteristic impedance Z7 = 50Ω, and the electrical length is determined by the tuner. This completes the output matching design.

[0065] S50: Design the input matching network and use a circuit structure with band-stop filtering characteristics to achieve dual-frequency matching;

[0066] like Figure 4 As shown, the input matching structure consists of microstrip lines TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8 and DC blocking capacitor C1. It is composed of two matching parts, and the source pull obtains the optimal impedance value for the two frequencies.

[0067] (11)

[0068] (12)

[0069] Where m = f2 / f1 is the ratio of the two operating frequencies, and n is any integer.

[0070] First, the characteristic impedance Z7 and electrical length θ7 of the microstrip line TL18 can be obtained according to formulas (11) and (12), and then... Figure 4 The complex impedance Z at two frequencies is obtained at point D. inD,f1 Z inD,f2 .

[0071] The matrix elements of a complete ABCD matrix topology can be represented by the following formula:

[0072] (13)

[0073] in It can be expressed by the following formula:

[0074] (14)

[0075] Z inD Then it can be calculated using formula (15), where Z L =50Ω.

[0076] (15)

[0077] Combining formulas (13)-(15), we can obtain formula (16).

[0078] (16)

[0079] in This is expressed by the following formula (17):

[0080] (17)

[0081] The aforementioned formulas (13)-(17) contain five parameters to be optimized (Z8, Z9, Z...). S3 Z S4 Z S5 Since the objective function is nonlinear and has multiple local optima, a genetic algorithm is used for global optimization. The fitness function is defined as the performance index shown in formula (18).

[0082] (18)

[0083] Where, θ a θ b and θ cThese represent the electrical lengths of the microstrip line at frequencies f1 = 1.8 GHz, f2 = 3.0 GHz, and (f1 + f2) / 2 = 2.4 GHz, respectively. It is the reflection coefficient at the corresponding frequency point.

[0084] Combining the above formulas (13)-(18), under the condition that all microstrip lines have a power length of 90° at the center frequency, Z8, Z9, and Z can be calculated. S3 Z S4 Z S5 The value of the DC blocking capacitor C1 = 10pF. Microstrip lines TL1 and TL2 mainly function as tuners, and their characteristic impedance Z... 10 and electric length θ 10 This can be achieved through tuning. At this point, the input matching design is complete.

[0085] S60: Circuit simulation is performed using high-frequency circuit simulation software, and various performance indicators are optimized by tuning the overall circuit parameters.

[0086] Based on the power amplifier designed as described above, circuit simulation was performed using high-frequency circuit simulation software, and the S-parameter results are as follows: Figure 5 As shown, the advantages of its simulation results are: (1) The designed power amplifier has an S21 > 14.8dB in the frequency ranges of 1.6-2.0GHz and 2.8-3.2GHz, and the maximum values ​​reach 15.7dB and 15.8dB respectively, with low gain flatness. (2) The power amplifier has extremely high inter-band rejection: in the 2.4-2.6 GHz band, it achieves a maximum deep rejection of 80 dB (S21 < -50dB). This characteristic can effectively prevent mutual interference between the transmit and receive bands of the dual-band system. Good out-of-band rejection: at the far ends of both sides of the passband (below 1.3GHz and above 3.5 GHz), the rejection reaches 58.5dB and 53.4dB respectively. This shows that the structure can effectively suppress far-end interference signals and reduce electromagnetic interference to other external communication systems. (3) As Figure 6 As shown, the power-added efficiency (PAE) reaches over 60% in the 1.6-2.0 GHz range and over 56% in the 2.8-3.2 GHz range, with PAE reaching 65% and 68% respectively at the center frequency. Figure 7 As shown, the output power (Pout) reaches over 39.6dBm in the 1.6-2.0GHz range and over 39.2dBm in the 2.8-3.2GHz range. At the center frequency, Pout is 41.6dBm and 39.8dBm respectively. This indicates that the designed power amplifier can achieve high-efficiency output at 1.8 and 3.0GHz frequencies, with bandwidths exceeding 400MHz, meeting the wideband requirements of modern wireless communication.

Claims

1. A dual-frequency power amplifier with bandpass filtering characteristics, characterized in that, The amplifier circuit includes, in sequence: The input matching network employs a band-stop impedance converter to achieve band-stop filtering characteristics, used for dual-frequency impedance matching and suppression of inter-band interference signals. Its input terminal constitutes the RF signal input port of the amplifier. The input matching network consists of a DC blocking capacitor C1 and microstrip lines TL1 to TL8, specifically connected as follows: one end of microstrip line TL1 is connected to the RF signal input terminal, and the other end is connected to one end of the DC blocking capacitor C1; the other end of the DC blocking capacitor C1 is connected in series through microstrip lines TL2, TL4, TL6, and TL8, and the end of this series path serves as the output terminal of the input matching network; at the series node of microstrip lines TL2 and TL4, a microstrip line TL3 with its other end open is connected in parallel; at the series node of microstrip lines TL4 and TL6, a microstrip line TL5 with its other end open is connected in parallel; at the series node of microstrip lines TL6 and TL8, a microstrip line TL7 with its other end open is connected in parallel. A stabilizing circuit, whose input terminal is connected to the output terminal of the input matching network, is used to ensure that the amplifier operates stably within the dual-frequency operating band. A transistor, whose gate is connected to the output of the stabilizing circuit, is used to provide power amplification for radio frequency signals; A gate bias circuit, which is connected to the node between the input matching network and the stabilization circuit and grounded through a decoupling capacitor Cg, is used to provide a gate bias voltage for the transistor. A harmonic control network, whose input is connected to the drain of the transistor, is used to suppress the dual-frequency second harmonic signal generated by the transistor. The output matching network employs a three-segment structure to achieve bandpass filtering characteristics, used for dual-frequency impedance matching, bandpass selection, and out-of-band rejection. Its input is connected to the output of the harmonic control network, and its output constitutes the RF signal output port of the amplifier. The output matching network consists of microstrip lines TL17 to TL25 and a DC blocking capacitor C3. One end of microstrip line TL17 serves as the input of the output matching network and is connected to the output of the harmonic control network. One end of the DC blocking capacitor C3 is connected to one end of microstrip line TL25, and the other end of microstrip line TL25 serves as the output of the output matching network. The other end of the DC blocking capacitor C3 is connected in series via microstrip lines TL24, TL22, TL21, and TL19. The end of this series path away from the DC blocking capacitor C3 is connected to the other end of microstrip line TL17. At the series node of microstrip lines TL24 and TL22, microstrip line TL23 with its other end open is connected in parallel. At the series node of microstrip lines TL22 and TL21, microstrip line TL20 with its other end open is connected in parallel. At the series node of microstrip lines TL21 and TL19, microstrip line TL18 with its other end open is connected in parallel. A drain bias circuit is connected in parallel to the connection node of the harmonic control network and the output matching network, and grounded through a decoupling capacitor Cd, which is used to provide a drain bias voltage for the transistor. The input matching network and the output matching network work together to achieve impedance matching and overall bandpass filtering characteristics of the amplifier in the dual-frequency operating band, thus completing the integrated processing of filtering and power amplification of dual-frequency signals.

2. A dual-frequency power amplifier with bandpass filtering characteristics according to claim 1, characterized in that, The gate bias circuit includes a microstrip line TL9 and a decoupling capacitor Cg. One end of the microstrip line TL9 is connected in parallel to the node between the input matching network and the stabilization circuit, and the other end is grounded through the decoupling capacitor Cg. The bias voltage of the gate bias circuit is VG.

3. A dual-frequency power amplifier with bandpass filtering characteristics according to claim 1, characterized in that, The stabilization circuit includes a microstrip line TL10, a parallel circuit consisting of a capacitor C2 and a resistor R1 connected in parallel, and a microstrip line TL11. One end of the microstrip line TL10 is connected to the output terminal of the input matching network, and the other end is connected to one end of the parallel circuit. The other end of the parallel circuit is connected to one end of the microstrip line TL11, and the other end of the microstrip line TL11 is connected to the gate terminal of the transistor.

4. A dual-frequency power amplifier with bandpass filtering characteristics according to claim 1, characterized in that, The harmonic control network includes microstrip lines TL12, TL13, TL14, and TL15. One end of microstrip line TL12 is connected to the drain of the transistor, and the other end is connected to one end of microstrip line TL15. Microstrip lines TL13 and TL14 are also connected in parallel at this connection node. The other ends of microstrip lines TL13 and TL14 are both set to open circuit. The other end of microstrip line TL15 serves as the output terminal of the harmonic control network and is connected to the input terminal of the output matching network.

5. A dual-frequency power amplifier with bandpass filtering characteristics according to claim 1, characterized in that, The drain bias circuit includes a microstrip line TL16 and a decoupling capacitor Cd. One end of the microstrip line TL16 is connected in parallel to the connection node between the harmonic control network and the output matching network, and the other end is grounded through the decoupling capacitor Cd. The bias voltage of the drain bias circuit is VD.

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