Display device and electronic device

Abstract

The invention discloses a display device and an electronic device. The display device includes: a display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver supplying a gate scan signal to the plurality of pixels in units of horizontal lines, in which each of the plurality of pixels includes: a first transistor connected between a driving voltage line and a second node; a sixth transistor connected between the second node and a common voltage line; a light emitting element connected between the sixth transistor and the common voltage line; and a fourth transistor connected between the second node and the initialization voltage line, and the gate driver generates another gate scan signal by delaying a phase of one of the gate scan signals and supplies the other gate scan signal to the plurality of pixels.

Description

Technical Field

[0001] This disclosure relates to a display device and an electronic device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light-emitting diode (OLED) display device. Among these flat panel display devices, the OLED display device includes a light-emitting element (e.g., an organic light-emitting diode) in which the brightness of each pixel varies with the current. Accordingly, the OLED display device can display images without a separate backlight unit that supplies light to the display panel. Summary of the Invention

[0004] This disclosure provides a display device capable of reducing leakage current and flicker per pixel of a display panel and accurately representing an image corresponding to black grayscale.

[0005] This disclosure also provides a display device capable of improving the transistor arrangement structure of the pixel circuitry for each pixel and modulating the delay period and phase of one of the gate scan signals supplied to the pixel circuitry as a modulated gate scan signal to supply another gate scan signal.

[0006] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0007] According to embodiments of this disclosure, a display device may include: a display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver that supplies gate scan signals to the plurality of pixels in units of horizontal lines. Each of the plurality of pixels may include: a first transistor connected between a driving voltage line and a second node; a sixth transistor connected between the second node and a common voltage line; a light-emitting element connected between the sixth transistor and the common voltage line; and a fourth transistor connected between the second node and an initialization voltage line. The gate driver can generate another gate scan signal by delaying the phase of one of the gate scan signals and supply the other gate scan signal to the plurality of pixels.

[0008] According to embodiments of this disclosure, each of the plurality of pixels may further include: a second transistor connected between the data line and the first node; a third transistor connected between the third node and the second node; a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between the bias voltage line and the first node; and an eighth transistor connected between the anode electrode of the light-emitting element and the light-emitting initialization line. The first transistor may be connected between the first node and the second node, and the gate electrode of the first transistor may be connected to the third node.

[0009] According to embodiments of this disclosure, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor may be p-type transistors, and the third transistor may be an n-type transistor.

[0010] According to embodiments of this disclosure, multiple pixels may each be connected to: a write gate line connected to the gate electrode of a second transistor; a compensation gate line connected to the gate electrode of a third transistor; an initialization gate line connected to the gate electrode of a fourth transistor; a light emission line connected to the gate electrodes of a fifth transistor and a sixth transistor; and a bias gate line connected to the gate electrodes of a seventh transistor and an eighth transistor. Furthermore, the multiple pixels may include a capacitor connected between a drive voltage line and a third node.

[0011] According to embodiments of this disclosure, the gate driver can transmit a write gate signal to a write gate line, a compensation gate signal to a compensation gate line, a bias gate signal to a bias gate line, and a light emission signal to a light emission line, and delay the phase of the bias gate signal by a time period and supply the phase-delayed bias gate signal as an initialization gate signal to the initialization gate line.

[0012] According to embodiments of this disclosure, the gate driver can generate and transmit a compensation gate signal and a bias gate signal at an effective level in a first time period during a time period for driving multiple pixels, generate and transmit an initialization gate signal and a compensation gate signal at an effective level in a second time period, generate and transmit a compensation gate signal and a write gate signal at an effective level in a third time period, generate and transmit a bias gate signal at an effective level in a fourth time period, generate and transmit an initialization gate signal at an effective level in a fifth time period, and generate and transmit a light emission signal at an effective level in a sixth time period.

[0013] According to embodiments of this disclosure, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor may be p-type transistors, and the third transistor and the fourth transistor may be n-type transistors.

[0014] According to embodiments of this disclosure, multiple pixels may each be connected to: a write gate line connected to the gate electrode of a second transistor; a compensation gate line connected to the gate electrode of a third transistor; an initialization gate line connected to the gate electrode of a fourth transistor; a light emission line connected to the gate electrodes of a fifth transistor and a sixth transistor; and a bias gate line connected to the gate electrodes of a seventh transistor and an eighth transistor. Furthermore, the multiple pixels may include a capacitor connected between a drive voltage line and a third node.

[0015] According to embodiments of this disclosure, a gate driver can transmit a write gate signal to a write gate line, a compensation gate signal to a compensation gate line, a bias gate signal to a bias gate line, and a light emission signal to a light emission line. The phase of the bias gate signal is delayed by a time period, the phase of the phase-delayed bias gate signal is inverted, and the phase-delayed and inverted bias gate signal is supplied to the initialization gate line as an initialization gate signal.

[0016] According to embodiments of this disclosure, the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor may be p-type transistors, and the third transistor, the fourth transistor, and the eighth transistor may be n-type transistors.

[0017] According to embodiments of this disclosure, multiple pixels may each be connected to: a write gate line connected to the gate electrode of a second transistor; a compensation gate line connected to the gate electrode of a third transistor; an initialization gate line connected to the gate electrode of a fourth transistor; a light-emitting line connected to the gate electrodes of a fifth transistor and a sixth transistor; a bias gate line connected to the gate electrode of a seventh transistor; and an inverted bias gate line connected to the gate electrode of an eighth transistor. Furthermore, the multiple pixels may include a capacitor connected between a drive voltage line and a third node.

[0018] According to embodiments of this disclosure, a gate driver can transmit a write gate signal to a write gate line, a compensation gate signal to a compensation gate line, a bias gate signal to a bias gate line, a light emission signal to a light emission line, invert the phase of the bias gate signal and transmit the phase-inverted bias gate signal to an inverted bias gate line, delay the phase of the bias gate signal by a time period, invert the phase of the phase-delayed bias gate signal, and supply the phase-delayed and inverted bias gate signal as an initialization gate signal to the initialization gate line.

[0019] According to another embodiment of this disclosure, the display device may include: a display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver that supplies gate scan signals to the plurality of pixels in units of horizontal lines. The gate driver can generate another gate scan signal by delaying the phase of one of the gate scan signals, and supplies the phase-delayed other gate scan signal to the plurality of pixels. Each of the plurality of pixels may include: a first transistor connected between a drive voltage line and a second node; a second transistor connected between a data line and the first node; a third transistor connected between a third node and the second node; a fourth transistor connected between the second node and an initialization voltage line; a fifth transistor connected between a drive voltage line and the first node; a sixth transistor connected between the second node and a common voltage line; a seventh transistor connected between a bias voltage line and the first node; an eighth transistor connected between the anode electrode of a light-emitting element and a light-emitting initialization line; and a light-emitting element connected between the sixth transistor and the common voltage line.

[0020] According to embodiments of this disclosure, multiple pixels may each be connected to: a write gate line connected to the gate electrode of a second transistor; a compensation gate line connected to the gate electrode of a third transistor; an initialization gate line connected to the gate electrode of a fourth transistor; a light emission line connected to the gate electrodes of a fifth transistor and a sixth transistor; and a bias gate line connected to the gate electrodes of a seventh transistor and an eighth transistor. Furthermore, the multiple pixels may include a capacitor connected between a drive voltage line and a third node.

[0021] According to embodiments of this disclosure, the gate driver can transmit a write gate signal to a write gate line, a compensation gate signal to a compensation gate line, a bias gate signal to a bias gate line, and a light emission signal to a light emission line, and delay the phase of the bias gate signal by a time period and supply the phase-delayed bias gate signal as an initialization gate signal to the initialization gate line.

[0022] According to embodiments of this disclosure, a gate driver can transmit a write gate signal to a write gate line, a compensation gate signal to a compensation gate line, a bias gate signal to a bias gate line, and a light emission signal to a light emission line. The phase of the bias gate signal is delayed by a time period, the phase of the phase-delayed bias gate signal is inverted, and the phase-delayed and inverted bias gate signal is supplied to the initialization gate line as an initialization gate signal.

[0023] According to embodiments of this disclosure, multiple pixels may each be connected to: a write gate line connected to the gate electrode of a second transistor; a compensation gate line connected to the gate electrode of a third transistor; an initialization gate line connected to the gate electrode of a fourth transistor; a light-emitting line connected to the gate electrodes of a fifth transistor and a sixth transistor; a bias gate line connected to the gate electrode of a seventh transistor; and an inverted bias gate line connected to the gate electrode of an eighth transistor. Furthermore, the multiple pixels may include a capacitor connected between a drive voltage line and a third node.

[0024] According to embodiments of this disclosure, a gate driver can transmit a write gate signal to a write gate line, a compensation gate signal to a compensation gate line, a bias gate signal to a bias gate line, and a light emission signal to a light emission line. The phase of the bias gate signal is delayed by a time period, the phase of the phase-delayed bias gate signal is inverted, and the phase-delayed and inverted bias gate signal is supplied to the initialization gate line as an initialization gate signal.

[0025] According to embodiments of this disclosure, an electronic device including a display apparatus may include: a display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver that supplies gate scan signals to the plurality of pixels in units of horizontal lines. Each of the plurality of pixels may each include: a first transistor connected between a driving voltage line and a second node; a sixth transistor connected between the second node and a common voltage line; a light-emitting element connected between the sixth transistor and the common voltage line; and a fourth transistor connected between the second node and an initialization voltage line. The gate driver can generate another gate scan signal by delaying the phase of one of the gate scan signals and supply the other gate scan signal to the plurality of pixels.

[0026] According to the embodiments, leakage current and flicker of each pixel of the display panel can be minimized, and the effect of reducing the power consumption of the display device can be improved.

[0027] Furthermore, according to the embodiments, even if the brightness of the image changes rapidly from white grayscale to black grayscale, the image corresponding to the black grayscale can be accurately represented.

[0028] Furthermore, according to the embodiments, the circuit structure of the gate driver can be simplified, and the size and layout area of ​​the gate driver can be reduced.

[0029] However, the effects of the embodiments are not limited to those set forth herein. The above and other effects of the embodiments will become more apparent to those skilled in the art upon which they pertain by referring to the claims. Attached Figure Description

[0030] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a perspective view of a display device according to an embodiment;

[0032] Figure 2 This is a schematic cross-sectional view of a display device according to an embodiment;

[0033] Figure 3 This is a plan view of the display panel of a display device according to an embodiment;

[0034] Figure 4 This is a schematic block diagram illustrating a display panel and a display driver according to an embodiment;

[0035] Figure 5 This is a schematic diagram of the equivalent circuit of a pixel of the display device according to the first embodiment;

[0036] Figure 6 yes Figure 5 A schematic timing diagram of the emission signal, compensation gate signal, write gate signal, bias gate signal and modulated initialization gate signal;

[0037] Figure 7 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operations during the first time period;

[0038] Figure 8 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operations during the second time period;

[0039] Figure 9 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operations during the third time period;

[0040] Figure 10 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operations in the fourth time period;

[0041] Figure 11 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operations in the fifth time period;

[0042] Figure 12 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operations in the sixth time period;

[0043] Figure 13 This is a schematic diagram of the equivalent circuit of a pixel of the display device according to the second embodiment;

[0044] Figure 14 yes Figure 13 A schematic timing diagram of the emission signal, compensation gate signal, write gate signal, bias gate signal and modulated initialization gate signal;

[0045] Figure 15 This is a schematic diagram of the equivalent circuit of a pixel of the display device according to the third embodiment; and

[0046] Figure 16 yes Figure 15 A schematic timing diagram of the emission signal, compensation gate signal, write gate signal, bias gate signal, modulated bias gate signal, and modulated initialization gate signal. Detailed Implementation

[0047] The present disclosure will now be described more fully below with reference to the accompanying drawings, which illustrate embodiments thereof. However, the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0048] When a component or layer is referred to as being "on," "connected to," or "coupled to" another component or layer, the component or layer may be directly on, directly connected to, or coupled to the other component or layer, or an intermediary component or layer may be present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another component or layer, an intermediary component or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary component. Additionally, when a component is referred to as being "in contact" or "in contact with" another component, the component may be in "electrical contact" or "physical contact" with the other component, or in "indirect contact" or "direct contact" with the other component. Throughout this specification, the same reference numerals denote the same parts.

[0049] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “above,” “above,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another(s) as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features would then be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or oriented in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a” and “the (described)” as used herein are intended to include the plural forms as well. Furthermore, when used in this specification, the terms “comprising” and variations thereof and / or “including” and variations thereof indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] In the specification and claims, the phrase "at least one" is intended, for the purposes of its meaning and interpretation, to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, the term "and / or" is intended, for the purposes of its meaning and interpretation, to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood as equivalent to "and / or".

[0052] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. Similarly, the second element may also be referred to as the first element.

[0053] Each of the features of the various embodiments of this disclosure can be combined, in part or in whole, or combined with one another, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other, or can be implemented together in combination.

[0054] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0055] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0056] Figure 1 This is a perspective view of a display device according to an embodiment.

[0057] refer to Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). For example, the display device 10 can be applied to the display units of televisions, laptop computers, monitors, billboards, or Internet of Things (IoT) devices. For example, the display device 10 can be applied to wearable devices such as smartwatches, smartwatch phones, glasses displays, and head-mounted displays (HMDs).

[0058] The display device 10 can be formed into a planar shape similar to a quadrilateral. For example, the display device 10 can have a planar shape similar to a quadrilateral having a short side in the first direction DR1 and a long side in the second direction DR2. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be rounded to have a certain curvature, or they can be formed as right angles. The planar shape of the display device 10 is not limited to a quadrilateral, and can be formed similarly to other polygons, circles, or ellipses.

[0059] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, a touch driver 400, and a power supply unit 500.

[0060] The display panel 100 may include a main area MA and a sub-area SBA.

[0061] The main area MA may include a display area DA containing pixels for displaying an image and a non-display area NDA disposed adjacent to the display area DA. The display area DA may emit light from multiple light-emitting areas or multiple opening areas. For example, the display panel 100 may include pixel circuitry containing switching elements, a pixel defining layer defining the light-emitting area or the opening area, and self-emissive elements.

[0062] For example, a self-emissive element may include at least one of an organic light-emitting diode (LED) containing an organic light-emitting layer, a quantum dot LED containing a quantum dot light-emitting layer, an inorganic LED containing an inorganic semiconductor, and a micro LED, but this disclosure is not limited thereto.

[0063] The non-display area NDA can be the area outside the display area DA. The non-display area NDA can be defined as the edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include the gate driver that supplies gate signals to the gate lines and the fan-out line that connects the display driver 200 and the display area DA.

[0064] The sub-region SBA can extend from one side of the main region MA. The sub-region SBA can include a flexible material that can be bent, folded, or rolled. For example, when the sub-region SBA is bent, it can overlap with the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA can include pad portions connected to the display driver 200 and the circuit board 300. In another embodiment, the sub-region SBA can be omitted, and the display driver 200 and the pad portions can be located in the non-display area NDA.

[0065] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to data lines. The display driver 200 can supply voltages to power lines and can supply gate control signals to the gate driver. The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic welding method. For example, the display driver 200 can be disposed in a sub-region SBA and can overlap with the main region MA in the thickness direction (e.g., third direction DR3) by bending the sub-region SBA. In another embodiment, the display driver 200 can be mounted on a circuit board 300.

[0066] The circuit board 300 can be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip-on-film.

[0067] The touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 can supply touch drive signals to multiple touch electrodes of the touch sensing unit and can sense the capacitance changes between the touch electrodes. For example, the touch drive signal can be a pulse signal with a frequency. The touch driver 400 can calculate whether an input is performed and the input coordinates based on the capacitance changes between the touch electrodes. The touch driver 400 can be formed as an integrated circuit (IC).

[0068] The power supply unit 500 can be mounted on the circuit board 300 and can supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 can generate a driving voltage to supply to the driving voltage line, an initialization voltage to supply to the initialization voltage line, a bias voltage to supply to the bias voltage line, and a common voltage to supply to the common voltage line. The common voltage of the common voltage line can be supplied to the cathode electrode shared by the light-emitting elements of multiple pixels. The driving voltage can be a high-potential voltage used to drive the light-emitting elements, and the common voltage can be a low-potential voltage used to drive the light-emitting elements.

[0069] Figure 2 This is a schematic cross-sectional view illustrating a display device according to an embodiment.

[0070] refer to Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light-emitting element layer EMTL, and an encapsulation layer ENC.

[0071] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB can include a polymer resin containing polyimide, but this disclosure is not limited thereto. In another embodiment, the substrate SUB can include a glass material or a metal material.

[0072] A thin-film transistor layer (TFTL) can be disposed on a substrate SUB. The TFTL may include multiple thin-film transistors constituting pixel circuitry. The TFTL may further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 and the data lines, and leads connecting the display driver 200 and the pad portion. Each of the thin-film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, if the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin-film transistor.

[0073] The thin-film transistor layer (TFTL) can be disposed in the display area (DA), the non-display area (NDA), and the sub-area (SBA). The gate lines, data lines, power lines, and thin-film transistors of each pixel in the TFTL can be disposed in the display area (DA). The gate control lines and fan-out lines of the TFTL can be disposed in the non-display area (NDA). The leads of the TFTL can be disposed in the sub-area (SBA).

[0074] The light-emitting element layer (EMTL) can be disposed on the thin-film transistor layer (TFTL). The EMTL may include a plurality of light-emitting elements in which a first electrode (hereinafter referred to as the anode electrode), a light-emitting layer, and a second electrode (hereinafter referred to as the cathode electrode) are sequentially stacked to emit light, and a pixel defining layer defining pixels. The light-emitting elements of the EMTL can be disposed in the display area (DA).

[0075] For example, the light-emitting layer can be an organic light-emitting layer comprising organic materials. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the anode electrode receives voltage through the thin-film transistor (TFTL) of the TFTL and the cathode electrode receives a common voltage, holes and electrons can move to the organic light-emitting layer through the hole transport layer and electron transport layer, respectively, and recombine within the organic light-emitting layer to emit light.

[0076] In another embodiment, the light-emitting element may include a quantum dot light-emitting diode containing a quantum dot light-emitting layer, an inorganic light-emitting diode containing an inorganic semiconductor, or a micro light-emitting diode.

[0077] The encapsulation layer ENC can cover the top and side surfaces of the light-emitting element layer EMTL and protect the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the light-emitting element layer EMTL.

[0078] The touch sensing unit (TSU) can be disposed on the encapsulation layer (ENC). The TSU may include multiple touch electrodes for sensing the user's touch using a capacitive method, and touch lines connecting the touch electrodes and the touch driver 400. For example, the TSU may sense the user's touch using a mutual capacitance method or a self-capacitance method.

[0079] In another embodiment, the touch sensing unit TSU may be disposed on a separate substrate, which is disposed on the display unit DU. The substrate supporting the touch sensing unit TSU may be a base member that encapsulates the display unit DU.

[0080] The touch electrodes of the touch sensing unit (TSU) can be located in the touch sensor area within the display area (DA). The touch lines of the touch sensing unit (TSU) can be located in the touch peripheral area within the non-display area (NDA).

[0081] A color filter layer (CFL) can be disposed on the touch sensing unit (TSU). The CFL can include multiple color filters corresponding to each of the light-emitting areas. Each color filter selectively transmits light of a certain wavelength and blocks or absorbs light of other wavelengths. The CFL can absorb a portion of the light introduced from the outside of the display device 10 to reduce reflected light caused by external light. Therefore, the CFL can prevent color distortion caused by the reflection of external light.

[0082] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 does not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively reduced.

[0083] The sub-region SBA of the display panel 100 may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, or rolled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA may include pad portions that are electrically connected to the display driver 200 and the circuit board 300.

[0084] Figure 3 This is a plan view of the display panel of a display device according to an embodiment. Figure 4 This is a schematic block diagram illustrating a display panel and a display driver according to an embodiment.

[0085] refer to Figure 3 and Figure 4 The display panel 100 may include a display area DA and a non-display area NDA.

[0086] The display area DA may include multiple pixels PX and multiple driving voltage lines VDL, multiple gate lines GL, and multiple common voltage lines connected to the pixels PX. Figure 5 It includes VSL, multiple light-emitting lines EML, and multiple data lines DL.

[0087] Each pixel PX can be connected to a gate line GL, a data line DL, a light-emitting line EML, a drive voltage line VDL, and a common voltage line VSL. Each pixel PX may include a light-emitting element, a capacitor, and at least one transistor.

[0088] The gate lines GL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects the first direction DR1. The gate lines GL can be arranged along the second direction DR2. The gate lines GL can sequentially supply gate signals to the pixels PX.

[0089] The light-emitting lines EML can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The light-emitting lines EML can be arranged along the second direction DR2. The light-emitting lines EML can sequentially supply light-emitting signals to the pixels PX.

[0090] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can be arranged along the first direction DR1. Data lines DL can supply data voltage to pixels PX. The data voltage determines the brightness of each pixel PX.

[0091] The driving voltage lines VDL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The driving voltage lines VDL can be arranged along the first direction DR1. The driving voltage lines VDL can supply driving voltage to the pixel PX. The driving voltage can be a high potential voltage used to drive the light-emitting element.

[0092] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, a transmit control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0093] The fan-out line FL can extend from the display driver 200 to the display area DA. The fan-out line FL can supply the data voltage received from the display driver 200 to the data line DL.

[0094] The first gate control line GSL1 can extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 can supply the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0095] The second gate control line GSL2 can extend from the display driver 200 to the transmit control driver 620. The second gate control line GSL2 can supply the transmit control signal ECS received from the display driver 200 to the transmit control driver 620.

[0096] The sub-region SBA can extend from one side of the non-display area NDA. The sub-region SBA may include a pad portion DP connected to the display driver 200. The pad portion DP may be positioned at the edge closer to the sub-region SBA than the display driver 200. The pad portion DP can be electrically connected to the circuit board 300 via an anisotropic conductive film (ACF).

[0097] Display driver 200 may include timing controller 210 and data driver 220.

[0098] The timing controller 210 can receive digital video data DATA and timing signals input from the circuit board 300. Based on the timing signals, the timing controller 210 can control the operation timing of the data driver 220 by generating a data control signal DCS, control the operation timing of the gate driver 610 by generating a gate control signal GCS, and control the operation timing of the transmit control driver 620 by generating a transmit control signal ECS. The timing controller 210 can supply the gate control signal GCS to the gate driver 610 through the first gate control line GSL1. The timing controller 210 can supply the transmit control signal ECS to the transmit control driver 620 through the second gate control line GSL2. The timing controller 210 can supply digital video data DATA and data control signal DCS to the data driver 220.

[0099] Data driver 220 converts digital video data DATA into analog data voltage and supplies the analog data voltage to data line DL via fan-out line FL. The gate signal of gate driver 610 selects the pixel PX to which the data voltage is supplied, and the selected pixel PX can receive the data voltage via data line DL.

[0100] The power supply unit 500 can be disposed on the circuit board 300 and can supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 can generate a driving voltage to supply the driving voltage line VDL, generate an initialization voltage to supply the initialization voltage line, and generate a common voltage to supply the common cathode electrode of the light-emitting elements of the pixel PX.

[0101] The gate driver 610 can be disposed on the outside of one side of the display area DA or on the side of the non-display area NDA, and the emitter control driver 620 can be disposed on the outside of the other side of the display area DA or on the other side of the non-display area NDA, but this disclosure is not limited thereto. In another embodiment, the gate driver 610 and the emitter control driver 620 can be disposed on one side or the other side of the non-display area NDA. In embodiments, the gate driver 610 and the emitter control driver 620 can be integrated with each other. For example, the gate driver 610 and the emitter control driver 620 can be formed into a single chip type.

[0102] Gate driver 610 may include multiple transistors that generate gate signals based on gate control signal GCS. Emit control driver 620 may include multiple transistors that generate light emission signals based on emitt control signal ECS. For example, the transistors of gate driver 610, emitt control driver 620, and each of the transistors in pixel PX may be formed on the same layer. Gate driver 610 can supply gate signals to gate line GL, and emitt control driver 620 can supply light emission signals to emitt line EML.

[0103] Figure 5 This is a schematic diagram of the equivalent circuit of a pixel of the display device according to the first embodiment.

[0104] like Figure 5 As shown, pixel PX can be connected to (or may include) write gate line GWL, compensation gate line GCL, initialization gate line SGL, bias gate line GBL, light emission line EML, data line DL, drive voltage line VDL, common voltage line VSL, initialization voltage line VIL, light emission initialization line VAIL, and bias voltage line VBL.

[0105] A pixel PX may include a pixel circuit PC and a light-emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor Cst.

[0106] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 can control the source-drain current (hereinafter referred to as the drive current) based on the data voltage applied to its gate electrode. The drive current flowing through the channel region of the first transistor T1 (e.g., Isd) can be proportional to the square of the difference between the voltage (Vsg) between the source and gate electrodes of the first transistor T1 and the threshold voltage (Vth) (Isd = k × (Vsg – Vth)). 2 k can be a scaling factor determined by the structural and physical characteristics of the first transistor T1, Vsg can be the source-gate voltage of the first transistor T1, and Vth can be the threshold voltage of the first transistor T1.

[0107] An LED emits light by receiving a driving current Isd. The amount of light emitted by the LED, or the brightness of the LED, is proportional to the amount of the driving current Isd.

[0108] The light-emitting element (ED) can be an organic light-emitting diode (OLED) comprising an anode electrode, a cathode electrode, and an organic light-emitting layer disposed between these electrodes (i.e., the anode electrode and the cathode electrode). In another embodiment, the ED can be an inorganic light-emitting element comprising an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between these electrodes (i.e., the anode electrode and the cathode electrode). In another embodiment, the ED can be a quantum dot light-emitting element comprising an anode electrode, a cathode electrode, and a quantum dot light-emitting layer disposed between these electrodes (i.e., the anode electrode and the cathode electrode). In yet another embodiment, the ED can be a micro-LED.

[0109] The anode of the light-emitting element (ED) can be electrically connected to the second node N2. The anode of the light-emitting element (ED) can be connected to the second node N2 via a sixth transistor T6. The cathode of the light-emitting element (ED) can be connected to the common voltage line VSL. The cathode of the light-emitting element (ED) can receive a common voltage ELVSS (e.g., a low-potential voltage) from the common voltage line VSL.

[0110] The second transistor T2 can be turned on by the write gate signal GW from the write gate line GWL to electrically connect the data line DL and the first node N1 connected to the source electrode of the first transistor T1. The second transistor T2 can be turned on by the write gate signal GW, thereby supplying a data voltage to the first node N1. The gate electrode of the second transistor T2 can be electrically connected to the write gate line GWL, the source electrode of the second transistor T2 can be electrically connected to the data line DL, and the drain electrode of the second transistor T2 can be electrically connected to the first node N1.

[0111] The third transistor T3 can be turned on by the compensation gate signal GC from the compensation gate line GCL to electrically connect the second node N2, which is connected to the drain electrode of the first transistor T1, and the third node N3, which is connected to the gate electrode of the first transistor T1. The third transistor T3 can be connected between the third node N3 and the second node N2. For example, the gate electrode of the third transistor T3 can be electrically connected to the compensation gate line GCL, the source electrode of the third transistor T3 can be electrically connected to the third node N3, and the drain electrode of the third transistor T3 can be electrically connected to the second node N2. The third transistor T3 can be turned on by the compensation gate signal GC from the compensation gate line GCL to electrically connect the first transistor T1 in the form of a diode. The third transistor T3 can be a dual-gate transistor with two gate electrodes (e.g., a gate electrode and a counter gate electrode). The gate electrode and the counter gate electrode can face each other in different layers.

[0112] The fourth transistor T4 can be turned on by the initialization gate signal SGB from the initialization gate line SGL to electrically connect the second node N2 and the initialization voltage line VIL. The fourth transistor T4 can be electrically connected between the second node N2 and the initialization voltage line VIL. For example, the gate electrode of the fourth transistor T4 can be electrically connected to the initialization gate line SGL, the drain electrode of the fourth transistor T4 can be electrically connected to the second node N2, and the source electrode of the fourth transistor T4 can be electrically connected to the initialization voltage line VIL. The fourth transistor T4 can also be a dual-gate transistor. The initialization voltage line VIL can carry the initialization voltage VINT.

[0113] The fifth transistor T5 can be turned on by the light-emitting signal EM from the light-emitting line EML to electrically connect the drive voltage line VDL and the first node N1 connected to the source electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be electrically connected to the light-emitting line EML, the source electrode of the fifth transistor T5 can be electrically connected to the drive voltage line VDL, and the drain electrode of the fifth transistor T5 can be electrically connected to the first node N1.

[0114] The sixth transistor T6 can be turned on by the light-emitting signal EM from the light-emitting line EML, thereby electrically connecting the second node N2, which is connected to the drain electrode of the first transistor T1, and the anode electrode of the light-emitting element ED. The gate electrode of the sixth transistor T6 can be electrically connected to the light-emitting line EML, the drain electrode of the sixth transistor T6 can be electrically connected to the second node N2, and the source electrode of the sixth transistor T6 can be electrically connected to the anode electrode of the light-emitting element ED. When the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all turned on, the drive current Isd can be supplied to the light-emitting element ED.

[0115] The seventh transistor T7 can be turned on by the bias gate signal GB from the bias gate line GBL to electrically connect the bias voltage line VBL and the first node N1 connected to the source electrode of the first transistor T1. The seventh transistor T7 can be turned on by the bias gate signal GB, thereby supplying the bias voltage VB to the first node N1. The seventh transistor T7 can improve the hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1. The gate electrode of the seventh transistor T7 can be electrically connected to the bias gate line GBL, the source electrode of the seventh transistor T7 can be electrically connected to the bias voltage line VBL, and the drain electrode of the seventh transistor T7 can be electrically connected to the first node N1.

[0116] The eighth transistor T8 can be turned on by the bias gate signal GB from the bias gate line GBL to electrically connect the anode of the light-emitting element ED and the light-emitting initialization line VAIL. The gate electrode of the eighth transistor T8 can be electrically connected to the bias gate line GBL, the source electrode of the eighth transistor T8 can be electrically connected to the light-emitting initialization line VAIL, and the drain electrode of the eighth transistor T8 can be electrically connected to the anode of the light-emitting element ED. The eighth transistor T8 can be turned on by the bias gate signal GB, thereby allowing current from the anode of the light-emitting element ED to flow to the light-emitting initialization line VAIL. The eighth transistor T8 can be a dual-gate transistor. The light-emitting initialization line VAIL can be supplied with the light-emitting initialization voltage VAINT.

[0117] Each of the first transistor T1, the second transistor T2, and the fourth transistors T4 through T8 may include a silicon-based active layer. For example, each of the first transistor T1, the second transistor T2, and the fourth transistors T4 through T8 may be a p-type transistor including an active layer made of low-temperature polycrystalline silicon (LTPS). The active layer made of LTPS can have high electron mobility and excellent conduction characteristics. Therefore, the display device 10 can stably and efficiently drive the pixel PX by including transistors with excellent conduction characteristics. Each of the first transistor T1, the second transistor T2, and the fourth transistors T4 through T8 can output the current flowing into its source electrode to its drain electrode based on a gate low voltage applied to its gate electrode.

[0118] The third transistor T3 can be an n-type transistor including an oxide-based active layer. The transistor including the oxide-based active layer can have a coplanar structure in which a gate electrode is disposed thereon. The transistor including the oxide-based active layer can output current flowing into its drain electrode to its source electrode based on a gate high voltage applied to its gate electrode.

[0119] A capacitor Cst can be connected between the third node N3, which is connected to the gate electrode of the first transistor T1, and the drive voltage line VDL. For example, the first electrode of the capacitor Cst can be electrically connected to the third node N3, and the second electrode of the capacitor Cst can be electrically connected to the drive voltage line VDL, thereby maintaining the potential difference between the drive voltage line VDL and the gate electrode of the first transistor T1.

[0120] The bias voltage VB can be greater than the drive voltage ELVDD, the drive voltage ELVDD can be greater than the common voltage ELVSS, and the common voltage ELVSS can be greater than the initialization voltage VINT and the light-emitting initialization voltage VAINT. However, this disclosure is not limited thereto, and in another embodiment, the common voltage ELVSS can be equal to or less than the initialization voltage VINT. The light-emitting initialization voltage VAINT can be less than or equal to the initialization voltage VINT. The bias voltage VB can be a voltage close to black grayscale (e.g., 5V). Figure 3 and Figure 4 Each pixel PX can be Figure 5 The circuit structure shown in the diagram is formed.

[0121] Figure 6 yes Figure 5 A schematic timing diagram of the emission signal, compensation gate signal, write gate signal, bias gate signal and modulated initialization gate signal.

[0122] For example, Figure 6 yes Figure 5 A schematic timing diagram of the light emission signal EM, the compensation gate signal GC, the write gate signal GW, the bias gate signal GB, and the modulated initialization gate signal SGB.

[0123] The gate driver 610 can generate a gate scan signal including a compensation gate signal GC, a bias gate signal GB, and a modulated initialization gate signal SGB based on the gate control signal GCS input from the timing controller 210.

[0124] The gate driver 610 may include a first shift register that sequentially generates a compensation gate signal GC in response to a gate control signal GCS and outputs the compensation gate signal GC to each compensation gate line GCL. The gate driver 610 may further include a second shift register that sequentially generates a bias gate signal GB in response to the gate control signal GCS and outputs the bias gate signal GB to each bias gate line GBL. The gate driver 610 may further include a delay circuit that sequentially delays the bias gate signal GB output from the second shift register (e.g., delays the phase of the bias gate signal GB) and outputs the delayed bias gate signal as an initialization gate signal SGB to the initialization gate line SGL.

[0125] The gate driver 610 can generate the initialization gate signal SGB independently based on the gate control signal GCS, instead of sequentially delaying the bias gate signal GB output from the second shift register and outputting the delayed bias gate signal as the initialization gate signal SGB. Accordingly, by forming and using a delay circuit with a simple circuit structure instead of a shift register with a complex structure, the internal circuit structure of the gate driver 610 can be simplified, and its size and forming area can be reduced. For this purpose, the fourth transistor T4, which operates in response to the initialization gate signal SGB, can be formed as a p-type transistor in the same manner as the seventh transistor T7, which operates in response to the bias gate signal GB. For example, each of the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 can be formed as a p-type transistor including an active layer of low-temperature polysilicon type.

[0126] On the other hand, the transmit control driver 620 can generate a light-emitting scan signal including a write gate signal GW and a light-emitting signal EM based on the transmit control signal ECS input from the timing controller 210.

[0127] refer to Figure 6 The pixels PX of the display device 10 can be operated according to the operation periods including the first time period P1, the second time period P2, the third time period P3, the fourth time period P4, the fifth time period P5 and the sixth time period P6.

[0128] The light-emitting signal EM, the compensation gate signal GC, the write gate signal GW, the bias gate signal GB, and the modulated initialization gate signal SGB can each be changed to an active or inactive level during each of the aforementioned time periods P1, P2, P3, P4, P5, and P6. The active level of each of the signals EM, GC, GW, GB, and SGB can be a voltage level that enables the corresponding transistor to conduct. In other words, the active level signal can have a value greater than the threshold voltage of the corresponding transistor. For example, in the case of an n-type transistor, the active level of the signal applied to the gate electrode of the corresponding transistor can be a high level (e.g., a positive level or a high voltage level).

[0129] The inactive level of each of the signals EM, GC, GW, GB, and SGB can be a voltage level that can turn off the corresponding transistor. In other words, the inactive level of the signal can have a value less than the threshold voltage of the corresponding transistor. For example, in the case of an n-type transistor, the inactive level of the signal applied to the gate electrode of the corresponding transistor can be a low level (e.g., a negative level or a low voltage level).

[0130] In contrast, when the corresponding transistor is a p-type transistor, the effective level of the signal applied to the gate electrode of the corresponding transistor can be a low level (e.g., a negative level or a low voltage level), and the ineffective level of the signal applied to the gate electrode of the corresponding transistor can be a high level (e.g., a positive level or a high voltage level).

[0131] During the first time period P1, the compensation gate signal GC and the bias gate signal GB may each have an active level. During the first time period P1, the emission signal EM, the initialization gate signal SGB, and the write gate signal GW may each have an inactive level. The first time period P1 may be, for example, a time period used to improve the hysteresis of the first transistor T1.

[0132] During the second time period P2, the initialization gate signal SGB and the compensation gate signal GC can each have an active level. During the second time period P2, the emission signal EM, the write gate signal GW, and the bias gate signal GB can each have an inactive level. The second time period P2 can be, for example, a period used to initialize the voltage of the gate electrode of the first transistor T1.

[0133] In the third time period P3, the compensation gate signal GC and the write gate signal GW can each have an active level. In the third time period P3, the emission signal EM, the initialization gate signal SGB, and the bias gate signal GB can each have an inactive level. In the third time period P3, the data voltage can be supplied to the pixel circuit PC. The third time period P3 can be, for example, a period used to supply the data voltage to the pixel circuit PC and to detect and compensate the threshold voltage of the first transistor T1.

[0134] In the fourth time period P4, the bias gate signal GB may have an active level. In the fourth time period P4, the light emission signal EM, the initialization gate signal SGB, the compensation gate signal GC, and the write gate signal GW may each have an inactive level. The fourth time period P4 may be, for example, a time period used to improve black-grayscale performance by discharging the voltage at the drain electrode of the first transistor T1 and the anode electrode of the light emission element ED.

[0135] In the fifth time period P5, the initialization gate signal SGB can have an active level. In the fifth time period P5, the emission signal EM, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can each have an inactive level. The fifth time period P5 can, for example, be a time period used to further improve the hysteresis of the first transistor T1.

[0136] In the sixth time period P6, the emission signal EM can have an active level. In the sixth time period P6, the initialization gate signal SGB, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can each have an inactive level. The sixth time period P6 can be, for example, a time period used for emitting light from the light-emitting element ED.

[0137] The operation of the display device 10 according to the embodiment will be referred to Figures 7 to 12 The description is as follows. Figures 7 to 12 The transistor surrounded by the dashed circle can be a conducting transistor, and the transistors other than those surrounded by the dashed circle can be cut-off transistors.

[0138] Figure 7 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operation in the first time period.

[0139] First, the operation of pixel PX in the first time period P1 will refer to Figure 6 and Figure 7 The description is as follows.

[0140] like Figure 6 As shown, during the first time period P1, the compensation gate signal GC and the bias gate signal GB can each have an active level. During the first time period P1, the write gate signal GW, the emission signal EM, and the initialization gate signal SGB generated by the delayed bias gate signal GB can each be inactive.

[0141] An effective level compensation gate signal GC can be applied to the gate electrode of the third transistor T3 through the compensation gate line GCL. Accordingly, the third transistor T3 can be turned on.

[0142] An effective bias gate signal GB can be applied to the gate electrodes of the seventh transistor T7 and the eighth transistor T8 via the bias gate line GBL. Accordingly, the seventh transistor T7 and the eighth transistor T8 can be turned on.

[0143] A non-active write gate signal GW can be applied to the gate electrode of the second transistor T2 via the write gate line GWL. Accordingly, the second transistor T2 can be turned off.

[0144] A non-active level initialization gate signal SGB can be applied to the gate electrode of the fourth transistor T4 via the initialization gate line SGL. Accordingly, the fourth transistor T4 can be turned off.

[0145] A non-active level light emission signal EM can be applied to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 respectively through the light emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0146] As described above, when the seventh transistor T7 is turned on, the bias voltage VB from the bias voltage line VBL can be applied to the source electrode of the first transistor T1 (e.g., the first node N1) through the turned-on seventh transistor T7. The voltage difference between the gate electrode and the source electrode of the first transistor T1 (hereinafter referred to as the gate-source voltage) can become greater than the threshold voltage of the first transistor T1, and the first transistor T1 can be turned on.

[0147] When the third transistor T3 is turned on by the effective level compensation gate signal GC, the gate electrode (e.g., third node N3) and drain electrode (e.g., second node N2) of the first transistor T1 can be electrically connected to each other. In other words, the first transistor T1 can be connected in the form of a diode. Accordingly, a current can be generated flowing from the bias voltage line VBL through the turned-on first transistor T1 in the direction towards the drain electrode (e.g., second node N2) and gate electrode (e.g., third node N3) of the first transistor T1. Accordingly, the first transistor T1 can be turned off when the voltage at the source electrode (e.g., first node N1) of the first transistor T1 increases and the gate-source voltage of the first transistor T1 becomes equal to the threshold voltage of the first transistor T1.

[0148] As described above, when the first transistor T1, the third transistor T3, and the seventh transistor T7 are each turned on, the bias voltage VB from the bias voltage line VBL can be applied to the first node N1, the second node N2, and the third node N3 respectively through the turned-on first transistor T1, third transistor T3, and seventh transistor T7. Therefore, the hysteresis of the first transistor T1 can be improved during the first time period P1. During the first time period P1, the voltage at the source electrode of the first transistor T1 can be initialized to the bias voltage VB.

[0149] When the eighth transistor T8 is turned on by the effective level bias gate signal GB, the voltage of the anode electrode of the light-emitting element ED can be initialized to the light-emitting initialization voltage VAINT of the light-emitting initialization line VAIL.

[0150] Figure 8 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operation in the second time period.

[0151] like Figure 6 As shown, during the second time period P2, the initialization gate signal SGB and the compensation gate signal GC can each be supplied at an active level. During the second time period P2, the emission signal EM, the write gate signal GW, and the bias gate signal GB can each be kept at an inactive level.

[0152] An effective level compensation gate signal GC can be applied to the gate electrode of the third transistor T3 through the compensation gate line GCL. Accordingly, the third transistor T3 can be turned on.

[0153] An active-level initialization gate signal SGB can be applied to the gate electrode of the fourth transistor T4 via the initialization gate line SGL. Accordingly, the fourth transistor T4 can be turned on.

[0154] A non-active level light emission signal EM can be applied to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 respectively through the light emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0155] A non-active bias gate signal GB can be applied to the gate electrodes of the seventh transistor T7 and the eighth transistor T8 via the bias gate line GBL. Accordingly, the seventh transistor T7 and the eighth transistor T8 can be turned off.

[0156] As described above, when the third transistor T3 is turned on, the gate electrode (e.g., the third node N3) and drain electrode (e.g., the second node N2) of the first transistor T1 can be electrically connected to each other. The first transistor T1 can remain in the off state during the second time period P2.

[0157] As described above, when the third transistor T3 and the fourth transistor T4 are each turned on, the initialization voltage VINT from the initialization voltage line VIL can be applied to the second node N2 and the third node N3 respectively through the turned-on third transistor T3 and fourth transistor T4. Therefore, in the second time period P2, the voltage of the gate electrode of the first transistor T1 and the voltage of the drain electrode of the first transistor T1 can each be initialized to the initialization voltage VINT.

[0158] The operation of pixel PX in the third time period P3 will refer to Figure 6 and Figure 9 The description is as follows.

[0159] Figure 9 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operation in the third time period.

[0160] like Figure 6 As shown, in the third time period P3, the compensation gate signal GC and the write gate signal GW can each have an active level. In the third time period P3, the emission signal EM, the initialization gate signal SGB, and the bias gate signal GB can each have an inactive level. In the third time period P3, the data voltage can be supplied to the pixel circuit PC.

[0161] An active write gate signal GW can be applied to the gate electrode of the second transistor T2 via the write gate line GWL. Accordingly, the second transistor T2 can be turned on.

[0162] An effective level compensation gate signal GC can be applied to the gate electrode of the third transistor T3 through the compensation gate line GCL. Accordingly, the third transistor T3 can be turned on.

[0163] A non-active level initialization gate signal SGB can be applied to the gate electrode of the fourth transistor T4 via the initialization gate line SGL. Accordingly, the fourth transistor T4 can be turned off.

[0164] A non-active level light emission signal EM can be applied to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 respectively through the light emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0165] A non-active bias gate signal GB can be applied to the gate electrode of the seventh transistor T7 via the bias gate line GBL. Accordingly, the seventh transistor T7 can be turned off.

[0166] As described above, when the third transistor T3 is turned on, the gate electrode (e.g., the third node N3) and drain electrode (e.g., the second node N2) of the first transistor T1 can be electrically connected to each other. In other words, the first transistor T1 can be connected in the form of a diode.

[0167] As described above, when the second transistor T2 is turned on, the data voltage from the data line DL can be applied to the source electrode of the first transistor T1 (e.g., the first node N1) through the turned-on second transistor T2. The voltage at the source electrode of the first transistor T1 can be maintained at the data voltage, while the voltage at the gate electrode of the first transistor T1 (e.g., the third node N3) can gradually increase. In other words, when the current generated by the data voltage applied to the first node N1 is supplied to the second node N2 and the third node N3 through the turned-on first transistor T1, the voltage at the gate electrode of the first transistor T1 can gradually increase. As the voltage at the gate electrode of the first transistor T1 gradually increases, the gate-source voltage of the first transistor T1 can gradually decrease. In this way, at the point when the gate-source voltage of the first transistor T1 decreases and reaches the threshold voltage of the first transistor T1, the first transistor T1 can be turned off. Therefore, at the point when the first transistor T1 is turned off, the threshold voltage of the first transistor T1 can be detected, and the detected threshold voltage can be reflected in the third node N3. For example, at the point when the first transistor T1 is turned off, the voltage of the third node N3 can be obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The voltage of the third node N3 (e.g., data voltage - threshold voltage of the first transistor T1) can be stored in a capacitor Cst and maintained for a specific time period. Therefore, in the third time period P3, a data voltage can be applied, and the threshold voltage of the first transistor T1 can be detected and maintained. Thus, in the third time period P3, the voltage of the third node N3 can include the threshold voltage of the first transistor T1.

[0168] The operation of pixel PX in the fourth time period P4 will refer to Figure 6 and Figure 10 The description is as follows.

[0169] Figure 10 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operation in the fourth time period.

[0170] like Figure 6 As shown, in the fourth time period P4, the bias gate signal GB can have an active level. In the fourth time period P4, the emission signal EM, the initialization gate signal SGB, the compensation gate signal GC, and the write gate signal GW can each have an inactive level.

[0171] An effective bias gate signal GB can be applied to the gate electrodes of the seventh transistor T7 and the eighth transistor T8 via the bias gate line GBL. Accordingly, the seventh transistor T7 and the eighth transistor T8 can be turned on.

[0172] A non-active write gate signal GW can be applied to the gate electrode of the second transistor T2 via the write gate line GWL. Accordingly, the second transistor T2 can be turned off.

[0173] A non-active level compensation gate signal GC can be applied to the gate electrode of the third transistor T3 via the compensation gate line GCL. Accordingly, the third transistor T3 can be turned off.

[0174] A non-active level initialization gate signal SGB can be applied to the gate electrode of the fourth transistor T4 via the initialization gate line SGL. Accordingly, the fourth transistor T4 can be turned off.

[0175] A non-active level light emission signal EM can be applied to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 respectively through the light emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0176] As described above, when the seventh transistor T7 is turned on, the bias voltage VB from the bias voltage line VBL can be applied to the source electrode of the first transistor T1 (e.g., the first node N1) through the turned-on seventh transistor T7. Accordingly, the voltage at the source electrode of the first transistor T1 can gradually increase, and the gate-source voltage of the first transistor T1 can become greater than the threshold voltage of the first transistor T1, thus turning on the first transistor T1. The bias voltage VB from the bias voltage line VBL can be applied to the first node N1 and the second node N2 through the turned-on first transistor T1. The voltage at the second node N2 can be the difference voltage obtained by subtracting the threshold voltage of the first transistor T1 from the bias voltage VB. Accordingly, the hysteresis of the first transistor T1 can be improved during the fourth time period P4. Therefore, even when the scan rate of the display device 10 changes rapidly, the deviation of the drive current Isd flowing through the first transistor T1 can be minimized, thereby improving the image quality of the display device 10.

[0177] When the eighth transistor T8 is turned on by the effective level bias gate signal GB, the voltage of the anode electrode of the light-emitting element ED can be initialized to the light-emitting initialization voltage VAINT of the light-emitting initialization line VAIL. Since the voltage of the anode electrode of the light-emitting element ED remains at the low light-emitting initialization voltage VAINT during the fourth time period P4, the light-emitting element ED can be turned off quickly enough even when the grayscale of the data voltage rapidly changes from white grayscale to black grayscale. Therefore, even when the image rapidly changes from white grayscale to black grayscale, the image corresponding to the black grayscale can be accurately represented. Therefore, the fourth time period P4 can be a period used to improve the representation of black grayscale by discharging the voltage on the drain electrode of the first transistor T1 and the anode electrode of the light-emitting element ED.

[0178] The operation of pixel PX in the fifth time period P5 will refer to Figure 6 and Figure 11 The description is as follows.

[0179] Figure 11 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operation in the fifth time period.

[0180] like Figure 6 As shown, in the fifth time period P5, the initialization gate signal SGB can be supplied at an active level. In the fifth time period P5, the emission signal EM, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can each be supplied at an inactive level.

[0181] An active-level initialization gate signal SGB can be applied to the gate electrode of the fourth transistor T4 via the initialization gate line SGL. Accordingly, the fourth transistor T4 can be turned on.

[0182] A non-active write gate signal GW can be applied to the gate electrode of the second transistor T2 via the write gate line GWL. Accordingly, the second transistor T2 can be turned off.

[0183] A non-active level compensation gate signal GC can be applied to the gate electrode of the third transistor T3 via the compensation gate line GCL. Accordingly, the third transistor T3 can be turned off.

[0184] A non-active level light emission signal EM can be applied to the gate electrodes of the fifth transistor T5 and the sixth transistor T6 respectively through the light emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0185] A non-active bias gate signal GB can be applied to the gate electrodes of the seventh transistor T7 and the eighth transistor T8 via the bias gate line GBL. Accordingly, the seventh transistor T7 and the eighth transistor T8 can be turned off.

[0186] As described above, when the fourth transistor T4 is turned on, the initialization voltage VINT from the initialization voltage line VIL can be applied to the drain electrode of the first transistor T1 (e.g., the second node N2) through the turned-on fourth transistor T4. Accordingly, the voltage at the drain electrode of the first transistor T1 can be discharged to the initialization voltage VINT. Consequently, in the fifth time period P5, the voltage of the second node N2 can be maintained at a low voltage. Since the voltage of the second node N2 remains at the low initialization voltage VINT in the fifth time period P5, even if the grayscale of the data voltage rapidly changes from white grayscale to black grayscale, the light-emitting element ED can be turned off sufficiently quickly in the next time period (e.g., the sixth time period P6). Therefore, even if the image rapidly changes from white grayscale to black grayscale, the image corresponding to the black grayscale can be accurately represented.

[0187] In other words, the second node N2 can be kept at a high voltage (e.g., the bias voltage – the threshold voltage of the first transistor T1) in the previous time period (e.g., the fourth time period P4) to improve the hysteresis of the first transistor T1, and in this case, it may be difficult to properly represent black grayscale when changing from white grayscale. To solve the above problem, in the fifth time period P5 before the light-emitting period (e.g., the sixth time period P6), the voltage of the second node N2 can be pre-discharged to a low voltage (e.g., the initialization voltage VINT).

[0188] The operation of pixel PX in the sixth time period P6 will refer to Figure 6 and Figure 12 The description is as follows.

[0189] Figure 12 It is used to describe Figure 5 pixels in Figure 6 A schematic diagram of the operation in the sixth time period.

[0190] like Figure 6 As shown, in the sixth time period P6, the emission signal EM can be supplied at an active level through the emission line EML. In the sixth time period P6, the initialization gate signal SGB, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can each be supplied at an inactive level.

[0191] An effective level light emission signal EM can be applied to the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 through the light emission line EML. Accordingly, the fifth transistor T5 and the sixth transistor T6 can be turned on.

[0192] A non-active write gate signal GW can be applied to the gate electrode of the second transistor T2 via the write gate line GWL. Accordingly, the second transistor T2 can be turned off.

[0193] A non-active level compensation gate signal GC can be applied to the gate electrode of the third transistor T3 via the compensation gate line GCL. Accordingly, the third transistor T3 can be turned off.

[0194] A non-active level initialization gate signal SGB can be applied to the gate electrode of the fourth transistor T4 via the initialization gate line SGL. Accordingly, the fourth transistor T4 can be turned off.

[0195] A non-active bias gate signal GB can be applied to the gate electrode of the seventh transistor T7 via the bias gate line GBL. Accordingly, the seventh transistor T7 can be turned off.

[0196] The first transistor T1 can be kept in the on state by the gate-source voltage held by the capacitor Cst.

[0197] In the sixth time period P6, since the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are each turned on, the drive current Isd can be supplied to the light-emitting element ED through the turned-on first transistor T1, fifth transistor T5, and sixth transistor T6. Therefore, the light-emitting element ED can emit light according to the drive current Isd. The gate-source voltage held by the capacitor Cst can include the threshold voltage of the first transistor T1, and the magnitude of the drive current Isd flowing to the light-emitting element ED through the turned-on first transistor T1 can be determined based on the data voltage and the threshold voltage of the first transistor T1. Therefore, the drive current Isd supplied to the light-emitting element ED can accurately reflect the magnitude of the data voltage. In this way, since the threshold voltage of the first transistor T1 of each pixel PX is compensated to determine the drive current Isd of each pixel PX, the brightness deviation between pixels PX caused by the deviation in the threshold voltage between the first transistor T1 of each pixel PX can be minimized. Therefore, the image quality of the display device 10 can be improved.

[0198] According to the embodiment, since the voltage of the second node N2 is discharged to the initialization voltage VINT and maintained at a low voltage in the previous time period (e.g., the fifth time period P5), the voltage difference between the anode electrode of the light-emitting element ED (e.g., the anode electrode connected to the source electrode of the sixth transistor T6) and the cathode electrode of the light-emitting element ED can be kept small in the sixth time period P6. In other words, the voltage of the anode electrode of the light-emitting element ED can be kept sufficiently low in the sixth time period P6. Therefore, as described above, since the voltage of the anode electrode of the light-emitting element ED can be reduced rapidly, even if the grayscale of the data voltage changes rapidly from white grayscale to black grayscale in adjacent frame time periods, the image of black grayscale can be accurately represented.

[0199] Since the first transistor T1 is already turned on when changing from black grayscale to white grayscale, a large amount of current can flow due to the data voltage of the white grayscale. Therefore, even if the voltage of the second node N2 is discharged to a low voltage such as the initialization voltage VINT, the voltage of the anode electrode of the light-emitting element ED can rise from black grayscale to a large voltage corresponding to white grayscale in a sufficiently short time. Therefore, the image quality of the display device 10 can be improved. Because black grayscale can be improved in this way, the swing range of the data voltage can be reduced, and thus the power consumption of the display device 10 can be improved.

[0200] According to the embodiment, since the fourth transistor T4 is disposed between the drain electrode of the first transistor T1 and the initialization voltage line VIL, the voltage difference between the drain electrode voltage of the first transistor T1 and the initialization voltage VINT can be low, and therefore the leakage current (e.g., cutoff leakage current) of the fourth transistor T4 can be minimized. Accordingly, even when the display device 10 is driven at a low frequency, an image can be displayed without flicker.

[0201] Figure 13 This is a schematic diagram of the equivalent circuit of a pixel of the display device according to the second embodiment.

[0202] refer to Figure 13 Pixel PX may include pixel circuit PC and light-emitting element ED, and pixel circuit PC may include first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8 and capacitor Cst.

[0203] Figure 13 The connection structure of the first transistor T1 to the third transistor T3 and the fifth transistor T5 to the eighth transistor T8 in the pixel circuit PC shown in the figure can be compared with... Figure 5 The connection structures of transistors T1 to T3 and transistors T5 to T8 shown in the diagram are identical. Therefore, the description of the arrangement and connection structure characteristics of transistors T1 to T3 and transistors T5 to T8 will be provided using... Figure 5 The description is replaced with [the description].

[0204] However, similar to the third transistor T3, Figure 13 The fourth transistor T4 shown in the diagram can be an n-type transistor including an oxide-based active layer. The fourth transistor T4 including an oxide-based active layer can output the current flowing into its drain electrode to its source electrode based on the gate high voltage applied to its gate electrode.

[0205] Figure 14 yes Figure 13A schematic timing diagram of the emission signal, compensation gate signal, write gate signal, bias gate signal and modulated initialization gate signal.

[0206] refer to Figure 13 and Figure 14 The fourth transistor T4 can be configured as an n-type transistor and outputs the current flowing into its drain electrode to its source electrode based on the gate high voltage. Accordingly, the gate driver 610 can generate an initialization gate signal SGB' such that the gate high voltage is generated as an effective voltage, and supply the initialization gate signal SGB' to the initialization gate line SGL'. For this purpose, the gate driver 610 can use at least one delay circuit and at least one inverting gate circuit to generate the initialization gate signal SGB'.

[0207] For example, gate driver 610 can use a second shift register to sequentially generate bias gate signals GB according to the gate control signal GCS, and sequentially output the bias gate signals GB to each bias gate line GBL. Accordingly, gate driver 610 can sequentially delay the bias gate signals GB using at least one delay circuit connected in parallel to each bias gate line GBL. Gate driver 610 can use at least one inverting gate circuit connected in series to each delay circuit to invert the phase of the sequentially delayed bias gate signals GB, and output the phase-inverted bias gate signals GB as initialization gate signals SGB' to initialization gate line SGL'.

[0208] refer to Figure 14 The pixels PX of the display device 10 can operate according to operation periods including a first time period P1, a second time period P2, a third time period P3, a fourth time period P4, a fifth time period P5, and a sixth time period P6. However, the operation sequence of the pixels PX within each time period will be determined by... Figures 6 to 12 The description is replaced with [the description].

[0209] Figure 15 This is a schematic diagram of the equivalent circuit of a pixel of a display device according to the third embodiment.

[0210] refer to Figure 15 Pixel PX may include pixel circuit PC and light-emitting element ED, and pixel circuit PC may include first transistor T1 to eighth transistor T8 and capacitor Cst.

[0211] Figure 15 The connection structure of the first transistor T1 to the third transistor T3 and the fifth transistor T5 to the seventh transistor T7 in the pixel circuit PC shown in the figure can be compared with... Figure 5The connection structures of transistors T1 to T3 and transistors T5 to T7 shown in the diagram are identical. Therefore, the description of the arrangement and connection structure characteristics of transistors T1 to T3 and transistors T5 to T7 will be provided using... Figure 5 The description is replaced with [the description].

[0212] However, similar to the third transistor T3, Figure 15 The fourth transistor T4 and the eighth transistor T8 shown in the diagram can be n-type transistors including oxide-based active layers. Each of the fourth transistor T4 and the eighth transistor T8, which includes oxide-based active layers, can output current flowing into its drain electrode to its source electrode based on a gate high voltage applied to its gate electrode.

[0213] Figure 16 yes Figure 15 A schematic timing diagram of the emission signal, compensation gate signal, write gate signal, bias gate signal, modulated bias gate signal, and modulated initialization gate signal.

[0214] refer to Figure 15 and Figure 16 Each of the fourth transistor T4 and the eighth transistor T8 can be configured as an n-type transistor and outputs the current flowing into its drain electrode to its source electrode based on the gate high voltage. Accordingly, the gate driver 610 can generate an initialization gate signal SGB' such that the gate high voltage is generated as an effective voltage, and supply the initialization gate signal SGB' to the initialization gate line SGL'. The gate driver 610 can also generate a bias gate signal GB' such that the gate high voltage is generated as an effective voltage, and supply the bias gate signal GB' to the inverted bias gate line GBL' connected to the eighth transistor T8. For this purpose, the gate driver 610 can use at least one delay circuit and at least one inverting gate circuit to generate the initialization gate signal SGB'.

[0215] For example, gate driver 610 can use a second shift register to sequentially generate bias gate signals GB according to the gate control signal GCS, and sequentially output the bias gate signals GB to each bias gate line GBL. Accordingly, gate driver 610 can sequentially delay the bias gate signals GB using at least one delay circuit connected in parallel to each bias gate line GBL. Gate driver 610 can use at least one inverting gate circuit connected in series to each delay circuit to invert the phase of the sequentially delayed bias gate signals GB, and output the phase-inverted bias gate signals GB as initialization gate signals SGB' to initialization gate line SGL'.

[0216] The gate driver 610 can invert the phase of the bias gate signal GB using at least one inverting gate circuit connected in parallel to each bias gate line GBL. The bias gate signal GB' can be supplied to the inverting bias gate line GBL' connected to the eighth transistor T8.

[0217] refer to Figure 16 The pixels PX of the display device 10 can operate according to operation periods including a first time period P1, a second time period P2, a third time period P3, a fourth time period P4, a fifth time period P5, and a sixth time period P6. However, the operation sequence of the pixels PX within each time period will be determined by... Figures 6 to 12 The description is replaced with [the description].

[0218] The above description is an example of the technical features of this disclosure, and those skilled in the art to which this disclosure pertains will be able to make various modifications and changes. Therefore, the embodiments of this disclosure described above can be implemented individually or in combination with each other.

[0219] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but rather to describe it, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the claims, and should be construed as including all technical spirit within the equivalent scope within the scope of this disclosure.

Claims

1. A display device, comprising: A display panel in which multiple pixels are arranged in a display area to display an image; as well as A gate driver supplies gate scan signals to the plurality of pixels in units of horizontal lines, wherein... Each of the plurality of pixels includes: The first transistor is connected between the drive voltage line and the second node; The sixth transistor is connected between the second node and the common voltage line; A light-emitting element is connected between the sixth transistor and the common voltage line; and The fourth transistor is connected between the second node and the initialization voltage line, and The gate driver generates another gate scan signal by delaying the phase of one of the gate scan signals, and supplies the other gate scan signal to the plurality of pixels.

2. The display device according to claim 1, wherein, Each of the plurality of pixels further includes: The second transistor is connected between the data line and the first node; The third transistor is connected between the third node and the second node; The fifth transistor is connected between the driving voltage line and the first node; A seventh transistor is connected between the bias voltage line and the first node; and The eighth transistor is connected between the anode electrode of the light-emitting element and the light-emitting initialization line. The first transistor is connected between the first node and the second node, and The gate electrode of the first transistor is connected to the third node.

3. The display device according to claim 2, wherein, The first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are p-type transistors, and The third transistor is an n-type transistor.

4. The display device according to claim 2, wherein, Each of the plurality of pixels is connected to: Write a gate line, the write gate line being connected to the gate electrode of the second transistor; A compensation gate line, the compensation gate line being connected to the gate electrode of the third transistor; Initialize the gate line, which is connected to the gate electrode of the fourth transistor; A light-emitting line, the light-emitting line being connected to the gate electrode of the fifth transistor and the gate electrode of the sixth transistor; as well as A bias gate line is provided, which is connected to the gate electrode of the seventh transistor and the gate electrode of the eighth transistor. The plurality of pixels further includes: A capacitor is connected between the drive voltage line and the third node.

5. The display device according to claim 4, wherein, The gate driver: The write gate signal is transmitted to the write gate line; The compensation gate signal is transmitted to the compensation gate line; The bias gate signal is transmitted to the bias gate line; The light-emitting signal is transmitted to the light-emitting line; and The phase of the bias gate signal is delayed by a time period, and the phase-delayed bias gate signal is supplied to the initialization gate line as the initialization gate signal.

6. The display device according to claim 5, wherein, The gate driver: In the first time period of the time period used to drive the plurality of pixels, the compensation gate signal and the bias gate signal are generated and transmitted at an active level; During the second time period, the initialization gate signal and the compensation gate signal at the active level are generated and transmitted. During the third time period, the compensation gate signal at the effective level and the write gate signal at the effective level are generated and transmitted. During the fourth time period, the bias gate signal at the effective level is generated and transmitted; During the fifth time period, the initialization gate signal at the effective level is generated and transmitted; and During the sixth time period, the light-emitting signal at an effective level is generated and transmitted.

7. The display device according to claim 2, wherein, The first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are p-type transistors, and The third transistor and the fourth transistor are n-type transistors.

8. The display device according to claim 7, wherein, Each of the plurality of pixels is connected to: Write a gate line, the write gate line being connected to the gate electrode of the second transistor; A compensation gate line, the compensation gate line being connected to the gate electrode of the third transistor; Initialize the gate line, which is connected to the gate electrode of the fourth transistor; A light-emitting line, the light-emitting line being connected to the gate electrode of the fifth transistor and the gate electrode of the sixth transistor; as well as A bias gate line is provided, which is connected to the gate electrode of the seventh transistor and the gate electrode of the eighth transistor. The plurality of pixels further includes: A capacitor is connected between the drive voltage line and the third node.

9. The display device according to claim 8, wherein, The gate driver: The write gate signal is transmitted to the write gate line; The compensation gate signal is transmitted to the compensation gate line; The bias gate signal is transmitted to the bias gate line; The light-emitting signal is transmitted to the light-emitting line; and The phase of the bias gate signal is delayed by a certain time period, the phase of the phase-delayed bias gate signal is reversed, and the phase-delayed and reversed bias gate signal is supplied to the initialization gate line as an initialization gate signal.

10. The display device according to claim 2, wherein, The first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor are p-type transistors, and The third transistor, the fourth transistor, and the eighth transistor are n-type transistors.

11. The display device according to claim 10, wherein, Each of the plurality of pixels is connected to: Write a gate line, the write gate line being connected to the gate electrode of the second transistor; A compensation gate line, the compensation gate line being connected to the gate electrode of the third transistor; Initialize the gate line, which is connected to the gate electrode of the fourth transistor; A light-emitting line, the light-emitting line being connected to the gate electrode of the fifth transistor and the gate electrode of the sixth transistor; A bias gate line, the bias gate line being connected to the gate electrode of the seventh transistor; as well as A reverse bias gate line is connected to the gate electrode of the eighth transistor, and The plurality of pixels further includes: A capacitor is connected between the drive voltage line and the third node.

12. The display device according to claim 11, wherein, The gate driver: The write gate signal is transmitted to the write gate line; The compensation gate signal is transmitted to the compensation gate line; The bias gate signal is transmitted to the bias gate line; The light-emitting signal is transmitted to the light-emitting line; The phase of the bias gate signal is reversed, and the phase-reversed bias gate signal is transmitted to the inverted bias gate line; and The phase of the bias gate signal is delayed by a certain time period, the phase of the phase-delayed bias gate signal is reversed, and the phase-delayed and reversed bias gate signal is supplied to the initialization gate line as an initialization gate signal.

13. A display device, comprising: A display panel in which multiple pixels are arranged in a display area to display an image; as well as A gate driver supplies gate scan signals to the plurality of pixels in units of horizontal lines, wherein... The gate driver generates another gate scan signal by delaying the phase of one of the gate scan signals, and supplies the other gate scan signal to the plurality of pixels. Each of the plurality of pixels includes: The first transistor is connected between the drive voltage line and the second node; The second transistor is connected between the data line and the first node; The third transistor is connected between the third node and the second node; The fourth transistor is connected between the second node and the initialization voltage line; The fifth transistor is connected between the driving voltage line and the first node; The sixth transistor is connected between the second node and the common voltage line; The seventh transistor is connected between the bias voltage line and the first node; The eighth transistor is connected between the anode electrode of the light-emitting element and the light-emitting initialization line; and The light-emitting element is connected between the sixth transistor and the common voltage line.

14. An electronic device comprising a display device according to any one of claims 1 to 13.

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