Liquid crystal display panel, driving method and display device

Abstract

The invention provides a liquid crystal display panel, a driving method and a display device. The liquid crystal display panel comprises a source electrode driving chip, a first data line, a second data line, a first thin film transistor and a second thin film transistor. The source electrode driving chip is connected with the first data line and the second data line, the first data line is further connected with the first thin film transistor, and the second data line is further connected with the second thin film transistor; the source electrode driving chip is used for outputting data voltage to the first thin film transistor through the first data line; the balance voltage is used for balancing charges, coupled to a common electrode through a parasitic capacitor between the first data line and the common electrode in the liquid crystal display panel, of the data voltage. According to the technical scheme, the display effect of the liquid crystal display panel can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a liquid crystal display panel, a driving method, and a display device. Background Technology

[0002] Liquid crystal display (LCD) panels have many advantages such as thinness, energy saving, and no radiation, and are widely used in electronic devices such as LCD TVs, mobile phones, digital cameras, computer screens, or laptop screens.

[0003] Liquid crystal display panels typically use a dual-gate + zigzag (Z) inversion architecture for driving. However, in practical applications, this driving method suffers from a problem where the changes in the positive and negative data voltages output by the data lines during the charging time of one line are not perfectly matched (1:1). This results in the parasitic capacitance between the data lines and the common electrode coupling charges onto the common electrode failing to cancel each other out, leading to crosstalk in the liquid crystal display panel.

[0004] Therefore, how to reduce the parasitic coupling between the data lines and the common electrode in the liquid crystal display panel under this driving method to improve the display effect has become a technical problem that needs to be solved. Summary of the Invention

[0005] This application provides a liquid crystal display panel, a driving method, and a display device to improve the display effect of the liquid crystal display panel.

[0006] In a first aspect, this application provides a liquid crystal display panel, comprising: a source driver chip, a first data line and a second data line, a first thin-film transistor and a second thin-film transistor; the source driver chip is connected to the first data line and the second data line respectively, the first data line is also connected to the first thin-film transistor, and the second data line is also connected to the second thin-film transistor; the source driver chip is configured to output a data voltage to the first thin-film transistor through the first data line; and is also configured to output a balancing voltage to the second thin-film transistor through the second data line, the balancing voltage being used to balance the charge coupled to the common electrode by the parasitic capacitance between the data voltage and the common electrode in the liquid crystal display panel.

[0007] In conjunction with the first aspect, in one possible implementation, both the first thin-film transistor and the second thin-film transistor are located in the display area of ​​the liquid crystal display panel, and the pixel unit corresponding to the second thin-film transistor has no color resist.

[0008] In conjunction with the first aspect, in one possible implementation, the first thin-film transistor is located in the display area of ​​the liquid crystal display panel, and the second thin-film transistor is located in the non-display area of ​​the liquid crystal display panel.

[0009] In conjunction with the first aspect, in one possible implementation, during the charging time of the Pth row, the first target voltage and the second target voltage have the same amplitude but opposite polarities. The first target voltage is the sum of the changes in the data voltage output by the first data line to the first thin-film transistor in the Pth row, and the second target voltage is the sum of the changes in the balance voltage output by the second data line to the second thin-film transistor in the Pth row. P is a positive integer less than or equal to Q, and Q is the row number of the first thin-film transistor and the second thin-film transistor.

[0010] In conjunction with the first aspect, in one possible implementation, the number of the second data lines is related to the charge coupled to the common electrode by the parasitic capacitance.

[0011] In conjunction with the first aspect, in one possible implementation, the source driver chip includes: a first buffer and a second buffer; the first buffer is used to store and output the data voltage; the second buffer is used to store and output the balanced voltage.

[0012] Secondly, this application provides a driving method that can be applied to a liquid crystal display panel described in the first aspect or any possible implementation thereof. The method includes: acquiring a data voltage output to a first thin-film transistor via a first data line when crosstalk exists in the liquid crystal display panel; determining a balance voltage based on the data voltage, the balance voltage being used to balance the charge coupled to the common electrode by the parasitic capacitance between the data voltage and the common electrode in the liquid crystal display panel via the first data line; and outputting the balance voltage to a second thin-film transistor via a second data line.

[0013] In conjunction with the second aspect, in one possible implementation, both the first thin-film transistor and the second thin-film transistor are located in the display area of ​​the liquid crystal display panel, and the pixel unit corresponding to the second thin-film transistor has no color resist.

[0014] In conjunction with the second aspect, in one possible implementation, during the charging time of the Pth row, the first target voltage and the second target voltage have the same amplitude but opposite polarities. The first target voltage is the sum of the changes in the data voltage output by the first data line to the first thin-film transistor in the Pth row, and the second target voltage is the sum of the changes in the balance voltage output by the second data line to the second thin-film transistor in the Pth row. P is a positive integer less than or equal to Q, and Q is the row number of the first thin-film transistor and the second thin-film transistor.

[0015] Thirdly, this application provides a display device that may include the liquid crystal display panel shown in the first aspect or any possible implementation of the first aspect.

[0016] This application provides a liquid crystal display panel, a driving method, and a display device. The technical solution provided in this application outputs a balanced voltage by providing at least one second data line in the liquid crystal display panel. This counteracts the charge coupled to the common electrode by the parasitic capacitance between the data voltage and the common electrode in the liquid crystal display panel through the first data line, thereby maintaining the stability of the common electrode voltage and solving the crosstalk phenomenon of the liquid crystal display panel. The technical solution provided in this application can effectively improve the crosstalk phenomenon of the liquid crystal display panel without changing the original driving architecture and without affecting its display performance, thus improving the display effect of the liquid crystal display panel. Attached Figure Description

[0017] Figure 1 This is a schematic structural diagram of a driving circuit for a liquid crystal display panel; Figure 2 This is a schematic waveform diagram of the data line under a driving mode of a dual-gate + zigzag inverting architecture; Figure 3 This is a schematic diagram illustrating crosstalk in a liquid crystal display panel. Figure 4 This is a schematic waveform diagram showing the coupling of a common electrode in a liquid crystal display panel. Figure 5 A schematic structural diagram of a liquid crystal display panel provided in this application; Figure 6 A schematic waveform diagram of a data voltage and a balance voltage provided in this application; Figure 7 A schematic structural diagram of a source driver chip provided in this application; Figure 8 This is a schematic flowchart illustrating a driving method for a liquid crystal display panel provided in this application. Detailed Implementation

[0018] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] First, combine Figures 1 to 4 This application explains the technical problems that need to be solved.

[0020] Liquid crystal display (LCD) panels typically use a dual-gate + zigzag inversion (Z) architecture for driving, such as... Figure 1 As shown.

[0021] The driving circuit of the liquid crystal display panel includes scan lines (gatelines) arranged horizontally in parallel and data lines (source lines) arranged vertically in parallel. Scan lines are as follows... Figure 1 Data cables from G1 to G8 are as follows: Figure 1 S1 to S10. It can be seen that the scan lines and data lines are arranged perpendicularly, forming pixel areas at the intersections. Each pixel unit comprises three subpixels: a red subpixel, a green subpixel, and a blue subpixel, as shown below. Figure 1 The image contains R, G, and B pixels. Each sub-pixel includes a TFT and a capacitor unit. The capacitor unit includes a pixel capacitor and a storage capacitor connected in parallel. The TFT includes a gate, a source, and a drain. The gate of the TFT is connected to the scan line, the source of the TFT is connected to the data line, the drain of the TFT is connected to one end of the capacitor unit, and the other end of the capacitor unit is connected to the common electrode (Vcom). Figure 1 The driving circuit in the image is a dual-gate architecture, so each row of pixel units is controlled by two scan lines.

[0022] Liquid crystal display (LCD) panels typically display images using a line-by-line scanning method. For example, during the first line's charging time of 1 hour, the scan lines output a gate high voltage (VGH) to the gate of the first row's TFT, turning on the first row's TFT and allowing the data lines to output a data voltage to the source of the corresponding sub-pixel's TFT in the first row. Similarly, during the second line's charging time of 2 hours, the scan lines output a high level to the gate of the second row's TFT, turning on the second row's TFT and allowing the data lines to output a data voltage to the source of the corresponding sub-pixel's TFT in the second row. This process continues until one frame of data is scanned, at which point the focus returns to scanning the first row for the second frame. It should be noted that the data voltage is applied to the corresponding pixel capacitor through the TFT's drain to control the orientation of the liquid crystal molecules, thereby controlling the display of the image.

[0023] Meanwhile, to reduce the impact of DC blocking effect and DC residual phenomenon on liquid crystal molecules, a polarity reversal driving method is usually used to drive the liquid crystal display panel, such as... Figure 1 The LCD employs a zigzag reversal driving method. Therefore, the data voltage has both positive and negative polarities. These polarities are based on the common electrode voltage; for example, a data voltage higher than the common electrode voltage can be considered positive, and a data voltage lower than the common electrode voltage can be considered negative. The positive data voltage can be described as a positive driving voltage (voltagehigh, VH), used to control the deflection of liquid crystal molecules to the corresponding grayscale state. The negative data voltage can be described as a negative driving voltage (voltage low, VL), used to alternate with VH to achieve polarity reversal. Therefore, the driving process of the LCD panel can be understood as continuously charging the voltage on the sub-pixels from positive to negative polarity, and then from negative to positive polarity. The voltage on the sub-pixel can be understood as the data voltage received by the source electrode of the corresponding TFT.

[0024] However, this driving method has a problem where the changes in VH and VL output by the data line during a single line of charging are not matched 1:1. This causes the parasitic capacitance between the data line and the common electrode to couple to the common electrode, resulting in the inability to cancel each other out. This leads to crosstalk in the LCD panel. It should be noted that the rise in VH and the fall in VL during the same line of charging must be matched 1:1 to ensure that the charges coupled to the common electrode through the parasitic capacitance between the data line and the common electrode cancel each other out, thus ensuring the stability of the common electrode voltage. The common electrode is the common reference electrode for all pixel units in the display panel. If the voltage of the common electrode fluctuates, the voltage on the pixel unit will deviate from the target voltage, causing changes in the brightness or color of adjacent areas in the displayed image, which is the crosstalk phenomenon. Crosstalk refers to the abnormal signal of one pixel unit or area affecting neighboring pixels or areas, causing image distortion, such as stripes or shadows on a solid color background, or changes in the brightness or color of adjacent areas.

[0025] Figure 2 A schematic waveform diagram of the data line is shown under a driving mode of a dual-gate + zigzag inverting architecture. It should be noted that... Figure 1 In the LCD panel, six data lines form a group that constitutes a data line functional unit. The VH / VL output logic, sub-pixel and data line connection relationships of each data line functional unit can be arranged repeatedly in a standardized pattern within the data line area of ​​the LCD panel. Figure 2 The following explanation uses the waveform diagram of the data line in the first data line functional unit as an example.

[0026] like Figure 2 As shown, during the fifth row charging time, the data line function unit outputs VL twice and VH once; during the sixth row charging time, the data line function unit outputs VH twice; and during the seventh row charging time, the data line function unit outputs VL twice and VH once. In other words, under this driving method, the changes in VH and VL output by the data line function unit are inconsistent during the charging time from the fifth to the seventh row, which can lead to crosstalk in the LCD panel. Figure 3 As shown.

[0027] Figure 4 A schematic waveform diagram illustrating the coupling between parasitic capacitance and a common electrode in a liquid crystal display panel is shown. Figure 4As shown, waveform 1 represents the data voltage output by the data line during the charging time of one row, or it can be understood as the data voltage received by the source of the TFT in that row during the charging time. It can be seen that the VH change of this data voltage is inconsistent with the VL change. The coupling voltage of the common electrode is 86 millivolts (mV) at microsecond a (μs) and 150 mV at microsecond b.

[0028] Therefore, how to reduce the parasitic coupling between the data lines and the common electrode in the liquid crystal display panel under this driving method to improve the display effect has become a technical problem that needs to be solved.

[0029] Currently, crosstalk in LCD panels can be mitigated by adjusting the polarity inversion method. However, this method only addresses crosstalk caused by the polarity inversion itself, and has limitations. Furthermore, adjusting the polarity inversion method may introduce other display problems, such as increasing the risk of screen flicker.

[0030] In view of this, this application provides a liquid crystal display panel, a driving method, and a display device. The technical solution provided in this application includes at least one independent second data line in the liquid crystal display panel, and a balanced voltage is output through the second data line to cancel the charge coupled to the common electrode by the parasitic capacitance between the data voltage and the common electrode in the liquid crystal display panel through the first data line, thereby maintaining the stability of the common electrode voltage and solving the crosstalk phenomenon of the liquid crystal display panel. The second data line can be newly added or a reused existing data line; this application does not limit this. The technical solution provided in this application can effectively improve the crosstalk phenomenon of the liquid crystal display panel without changing the original driving architecture of the liquid crystal display panel or affecting its display performance. In other words, the technical solution provided in this application can be applied to various driving architectures, not limited to the dual-gate + zigzag inversion driving architecture, and has high compatibility.

[0031] The following is combined Figures 5 to 8 This application provides a detailed description of the technical solution provided.

[0032] Figure 5 This is a schematic structural diagram of a liquid crystal display panel provided in this application. Figure 5 The liquid crystal display panel shown includes: a source driver chip, a first data line and a second data line, a first thin-film transistor (TFT), and a second TFT. The source driver chip is connected to both the first and second data lines. The first data line is also connected to the first TFT, and the second data line is also connected to the second TFT. The first data lines are S1 to S10 as shown in the figure, and the second data line is SR as shown in the figure. Both the first and second TFTs are located within a pixel area.

[0033] It should be understood that the liquid crystal display panel may also include a gate driver chip, a timing controller (TCON), etc., and this application does not impose specific limitations on this.

[0034] In this application, the source driver chip is used to output a data voltage to the first thin-film transistor via a first data line, so as to control the deflection of the liquid crystal molecules by controlling the voltage across the liquid crystal molecules, thereby realizing the display of the image; it is also used to output a balancing voltage to the second thin-film transistor via a second data line, the balancing voltage being used to balance the charge coupled to the common electrode by the parasitic capacitance between the data voltage and the common electrode in the liquid crystal display panel through the first data line.

[0035] In one possible implementation, both the first and second thin-film transistors can be located in the active area (AA) of the liquid crystal display panel, and the pixel unit corresponding to the second thin-film transistor has no color resist. It should be understood that... Figure 5 The liquid crystal display panel in the middle adopts the dual gate + zigzag inversion (dual gate + Z) driving method. Therefore, the pixel unit corresponding to the second thin film transistor has no color resistance, which can be understood as the sub-pixel corresponding to the second thin film transistor having no color resistance.

[0036] This implementation eliminates color resistance in the second thin-film transistor, allowing the balancing voltage output from the second data line to be used solely to balance the charge coupled to the common electrode by parasitic capacitance, without participating in the display function of the liquid crystal display panel. It should be noted that pixel units without color resistance cannot filter out specific colors of light and therefore do not participate in image display. Furthermore, this implementation does not occupy the non-active area (NAA) of the liquid crystal display panel, meeting the design requirements of narrow bezel panels.

[0037] In one possible implementation, the first thin-film transistor (TFT) can be located in the display area of ​​the liquid crystal display panel to enable normal display of the image. The second TFT can be located in the non-display area of ​​the liquid crystal display panel, thereby reducing the impact on the displayed image and improving the display effect of the liquid crystal display panel when balancing the charge coupled to the common electrode by balancing the voltage to resolve crosstalk. Furthermore, this implementation does not require occupying pixel units in the display area, thus not affecting the resolution of the liquid crystal display panel.

[0038] In one possible implementation, during the charging time of the Pth row, the first target voltage and the second target voltage have the same amplitude but opposite polarities. The first target voltage is the sum of the changes in the data voltage output from the first data line to the first thin-film transistor in the Pth row, and the second target voltage is the sum of the changes in the balance voltage output from the second data line to the second thin-film transistor in the Pth row, where P is a positive integer less than or equal to Q, and Q is the row number of the first and second thin-film transistors. It should be understood that the first target voltage can also be understood as the sum of the changes in the data voltage received by the first thin-film transistor in the Pth row, and the second target voltage can also be understood as the sum of the changes in the data voltage received by the second thin-film transistor in the Pth row.

[0039] Figure 6 A schematic waveform diagram of a data voltage and a balance voltage provided in this application. Figure 6 The following example illustrates the concept of a single data line functional unit with the first data line as the basis and a single second data line. Figure 6 As shown, during the fifth row charging time, the first target voltage is a VL signal with an amplitude of Q, and the second target voltage is a VH signal with an amplitude of Q; during the sixth row charging time, the first target voltage is a VH signal with an amplitude of 2Q, and the second target voltage is a VL signal with an amplitude of 2Q; during the seventh row charging time, the first target voltage is a VL signal with an amplitude of Q, and the second target voltage is a VH signal with an amplitude of Q.

[0040] In the technical solution provided in this application, by ensuring that the amplitude of the first target voltage and the second target voltage are the same but their polarities are opposite during each row charging time, the charge coupled to the common electrode by the balance voltage through the second parasitic capacitance during each row charging time can cancel out the charge coupled to the common electrode by the data voltage through the first parasitic capacitance, thereby maintaining the stability of the common electrode voltage and solving the crosstalk phenomenon of the liquid crystal display panel. The first parasitic capacitance refers to the parasitic capacitance between the first data line and the common electrode. The second parasitic capacitance refers to the parasitic capacitance between the second data line and the common electrode. In the technical solution provided in this application, the balance voltage is determined based on the sum of the changes in the data voltage of each row during each charging time, thereby achieving precise balance of the coupled charge on the common electrode.

[0041] In this application, the number of second data lines is related to the charge coupled to the common electrode by the first parasitic capacitance. For example, when the charge coupled to the common electrode by the first parasitic capacitance is less than or equal to a preset value, the number of second data lines can be 1; when the charge coupled to the common electrode by the second parasitic capacitance is greater than the preset value, the number of second data lines can be multiple. The specific number can be set according to actual needs and is not limited here.

[0042] In this application, to achieve independent control of the data voltage and the balancing voltage and reduce interference between them, a buffer for storing the balancing voltage can be added to the source driver chip, such as... Figure 7 As shown.

[0043] like Figure 7 As shown, the source driver chip may include: a control unit, a first buffer, and a second buffer. The control unit is connected to both the first and second buffers. The first buffer is also connected to a first data line via a first pin, and the second buffer is also connected to a second data line via a second pin. Figure 7 The number of the second data lines is 2.

[0044] The first buffer is used to store the data voltage output by the control unit and transmit the stored data voltage to the first data line through the first pin, thereby outputting the data voltage to the first thin-film transistor.

[0045] The second buffer is used to store the balanced voltage output by the control unit and transmit the stored balanced voltage to the second data line through the second pin, thereby outputting the balanced voltage to the second thin-film transistor.

[0046] The following is combined Figure 8 The driving method for the liquid crystal display panel provided in this application will be described. For example... Figure 8 As shown, the driving method includes S810 to S830.

[0047] As an example, this driving method can be executed by the source driver chip, for example, by hardware and / or software modules in the source driver chip.

[0048] S810, in the event of crosstalk in the liquid crystal display panel, acquires the data voltage output to the first thin-film transistor through the first data line.

[0049] This application does not impose specific restrictions on the detection method for crosstalk in liquid crystal display panels.

[0050] S820 determines a balance voltage based on the data voltage. The balance voltage is used to balance the charge coupled to the common electrode by the parasitic capacitance between the data voltage and the common electrode in the liquid crystal display panel through the first data line.

[0051] The specific implementation method for determining the balance voltage based on the data voltage can be found in the relevant description in the foregoing embodiments, and will not be repeated here.

[0052] S830 outputs a balanced voltage to the second thin-film transistor via the second data line.

[0053] After determining the balance voltage, the balance voltage can be output to the second thin-film transistor through the second data line, and the crosstalk phenomenon of the liquid crystal display panel can be detected. If not, S810 to S830 are repeated until the crosstalk phenomenon is improved.

[0054] Optionally, when crosstalk occurs in the liquid crystal display panel, the causes of the crosstalk can be analyzed to further optimize the driving method of the liquid crystal display panel. Causes of crosstalk include dual-gate driving and / or polarity reversal methods. For example, if the crosstalk is caused by the polarity reversal method, it can be improved by adjusting the reversal period or reversal type of the polarity reversal method, which has the advantages of low cost and no need for additional hardware. If adjusting the polarity reversal method still cannot effectively improve the crosstalk, a driving method that outputs a balanced voltage can be used to cancel the parasitic capacitive coupling charge of the common electrode, thereby improving the crosstalk.

[0055] This application also provides a display device, which may include the liquid crystal display panel described in the foregoing embodiments.

[0056] The term "multiple" in this document refers to two or more. The character " / " generally indicates an "or" relationship between related objects; in formulas, " / " indicates a "division" relationship between related objects. Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0057] It is understood that, in the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0058] It should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A liquid crystal display panel, characterized in that, include: Source driver chip, first data line and second data line, first thin-film transistor and second thin-film transistor; The source driver chip is connected to the first data line and the second data line respectively. The first data line is also connected to the first thin-film transistor, and the second data line is also connected to the second thin-film transistor. The source driver chip is used to output a data voltage to the first thin-film transistor through the first data line; it is also used to output a balancing voltage to the second thin-film transistor through the second data line, the balancing voltage being used to balance the charge coupled to the common electrode by the parasitic capacitance between the data voltage and the common electrode in the liquid crystal display panel through the first data line.

2. The liquid crystal display panel according to claim 1, characterized in that, Both the first thin-film transistor and the second thin-film transistor are located in the display area of ​​the liquid crystal display panel, and the pixel unit corresponding to the second thin-film transistor has no color resist.

3. The liquid crystal display panel according to claim 1, characterized in that, The first thin-film transistor is located in the display area of ​​the liquid crystal display panel, and the second thin-film transistor is located in the non-display area of ​​the liquid crystal display panel.

4. The liquid crystal display panel according to claim 2 or 3, characterized in that, During the charging time of the Pth row, the first target voltage and the second target voltage have the same amplitude but opposite polarity. The first target voltage is the sum of the changes in the data voltage output by the first thin-film transistor from the first data line to the Pth row, and the second target voltage is the sum of the changes in the balance voltage output by the second thin-film transistor from the second data line to the Pth row. P is a positive integer less than or equal to Q, and Q is the row number of the first thin-film transistor and the second thin-film transistor.

5. The liquid crystal display panel according to claim 4, characterized in that, The number of the second data lines is related to the charge coupled to the common electrode by the parasitic capacitance.

6. The liquid crystal display panel according to claim 5, characterized in that, The source driver chip includes: a first buffer and a second buffer; The first buffer is used to store and output the data voltage; The second buffer is used to store and output the balanced voltage.

7. A driving method, characterized in that, The liquid crystal display panel used in any one of claims 1 to 6 comprises: In the event of crosstalk in the liquid crystal display panel, the data voltage output to the first thin-film transistor via the first data line is obtained; A balance voltage is determined based on the data voltage. The balance voltage is used to balance the charge that is coupled to the common electrode by the parasitic capacitance between the data voltage and the common electrode in the liquid crystal display panel through the first data line. The balanced voltage is output to the second thin-film transistor via the second data line.

8. The driving method according to claim 7, characterized in that, Both the first thin-film transistor and the second thin-film transistor are located in the display area of ​​the liquid crystal display panel, and the pixel unit corresponding to the second thin-film transistor has no color resist.

9. The driving method according to claim 7 or 8, characterized in that, During the charging time of the Pth row, the first target voltage and the second target voltage have the same amplitude but opposite polarity. The first target voltage is the sum of the changes in the data voltage output by the first thin-film transistor from the first data line to the Pth row, and the second target voltage is the sum of the changes in the balance voltage output by the second thin-film transistor from the second data line to the Pth row. P is a positive integer less than or equal to Q, and Q is the row number of the first thin-film transistor and the second thin-film transistor.

10. A display device, characterized in that, Including the liquid crystal display panel as described in any one of claims 1 to 6.

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