Memory system and method of processing read command for target address
By introducing buffers and linked list management mechanisms into the memory system, the problem of long processing time for multiple read commands is solved, resulting in faster command response and higher processing efficiency.
Patent Information
- Application Number
- CN202510075294.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-16
- Filing Date
- 2025-01-17
- Publication Date
- 2026-03-03
AI Technical Summary
Existing memory systems suffer from low efficiency due to long processing times when handling multiple read commands targeting the same address.
By introducing a buffer in the controller to store read data and using a linked list to manage multiple read commands, repeated access to the memory medium is avoided, and response messages are generated quickly.
It improves the processing speed of multiple read commands to the target address, reduces the number of accesses to the memory medium, and enhances processing efficiency.
Smart Images
Figure CN121600980A_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This application claims priority to Korean Patent Application No. 10-2024-0109636, filed with the Korean Intellectual Property Office on August 16, 2024, which is incorporated herein by reference in its entirety. Technical Field
[0003] Embodiments of this disclosure relate to memory systems and methods for processing multiple read commands for a target address. Background Technology
[0004] Memory systems can store data and can be implemented using volatile or non-volatile memory. In volatile memory (e.g., SRAM or DRAM), the stored data is lost when the power is turned off, while in non-volatile memory (e.g., NAND flash memory, PRAM, or MRAM), the stored data is retained and maintained even when the power is turned off.
[0005] The memory system can receive read commands from the host requesting data to be read. While the memory system is processing a read command for a specific address, it can additionally receive subsequent read commands for the same address. Summary of the Invention
[0006] Various embodiments of this disclosure are intended to provide a memory system and method that improves the processing time of multiple read commands targeting the same destination address.
[0007] In one aspect, a memory system may include: a memory medium; and a controller configured to receive a read command from a host, read data from the memory medium according to the read command, and generate a response message to the read command based on the data read from the memory medium.
[0008] The controller may include a buffer that stores data read from a memory medium. The controller may receive a first read command from a host for target data stored at a target address in the memory medium; read the target data from the memory medium; store the read target data in the buffer; generate a first response message to the first read command based on the read target data; and wherein, after receiving the first read command, the controller receives a second read command from the host for the target data stored at the target address, and generates a second response message to the second read command based on the target data stored in the buffer.
[0009] In another aspect, a method of operating a memory system may include: receiving a first read command from a host, the first read command requesting to read target data stored at a target address in a memory medium; reading the target data from the memory medium; storing the target data in a buffer; receiving a second read command from the host after receiving the first read command, the second read command requesting to read the target data stored at the target address; and generating a first response message to the first read command and a second response message to the second read command.
[0010] Generating a first response message and a second response message may include generating a first response message based on target data read from a memory medium and generating a second response message based on target data stored in a buffer.
[0011] According to embodiments of this disclosure, multiple read commands targeting a target address can be processed more quickly. Attached Figure Description
[0012] Figure 1 This is a schematic configuration diagram of a memory system according to an embodiment of the present disclosure.
[0013] Figure 2 This is a diagram illustrating the operation of a memory system processing a first read command according to an embodiment of the present disclosure.
[0014] Figure 3 This is a diagram illustrating the operation of a memory system processing a second read command according to an embodiment of the present disclosure.
[0015] Figure 4 This is a diagram illustrating a linked list according to an embodiment of the present disclosure.
[0016] Figure 5 This is a diagram illustrating the operation of inserting and deleting a first node and a second node in a linked list in a memory system according to an embodiment of the present disclosure.
[0017] Figure 6 This is a diagram illustrating the operation of a memory system processing a write command according to an embodiment of the present disclosure.
[0018] Figure 7 This is a diagram illustrating a method of operating a memory system according to an embodiment of the present disclosure. Detailed Implementation
[0019] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, references to "embodiment," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to such phrases are not necessarily limited to the same embodiment(s). When used herein, the term "embodiment" does not necessarily refer to all embodiments within the scope of this disclosure.
[0020] Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and variations and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the contents of the disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various figures and embodiments.
[0021] The methods, processes, and / or operations described herein can be executed by code or instructions that will run on a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of these method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.
[0022] When implemented at least in part as software, controllers, processors, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions that will be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.
[0023] Figure 1 This is a schematic configuration diagram of a memory system according to an embodiment of the present disclosure.
[0024] Reference Figure 1 The memory system 100 may include a memory medium 110 and a controller 120.
[0025] The memory medium 110 can store target data TGT_DATA. The target data TGT_DATA can be stored in the target address TGT_ADDR of the memory medium 110. That is, the region in the memory medium 110 where the target data TGT_DATA is stored can be identified by the target address TGT_ADDR.
[0026] The memory medium 110 can be implemented in various ways.
[0027] For example, memory medium 110 may be implemented as a random access memory medium. Memory medium 110 may include multiple banks, in which data can be stored and read from the multiple banks.
[0028] The memory medium 110 can perform periodic refresh operations to maintain the stored data. When the power supply to the memory medium 110 is cut off, the data stored in the memory medium 110 is lost.
[0029] In another example, memory medium 110 may be implemented using a non-volatile memory medium (e.g., NAND flash, PRAM, or MRAM).
[0030] Controller 120 can receive read commands from the host. Controller 120 can read data requested by the read command from the memory medium 110, and then generate a response message to the read command based on the read data. Controller 120 can send the generated response message to the host.
[0031] Before the controller 120 sends a response message to the host for the received read command, the controller 120 may store the received read command in the controller 120.
[0032] The controller 120 may include a buffer 121 that stores data read from the memory medium 110.
[0033] The controller 120 and the buffer 121 can be implemented in various ways.
[0034] For example, controller 120 may be implemented by an integrated circuit that includes logic gates for performing the operations described above. Controller 120 may be implemented by an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
[0035] In another example, controller 120 may include a processor that performs calculations to control the processing of multiple operation requests and controls a working memory that stores data required to process the multiple operation requests.
[0036] For example, a processor can control the operation of controller 120 by running firmware. The processor can drive the firmware to control the overall operation of controller 120 and perform logical calculations. As a program running in controller 120 to drive controller 120, the firmware may include binary data in which code for performing the aforementioned overall operation and logical calculations is defined.
[0037] Firmware can be stored in storage space (e.g., working memory, ROM, flash memory) located inside or outside the controller 120. The processor can load all or part of the firmware stored in the storage space.
[0038] The working memory can store data (e.g., multiple operation requests or firmware) required by the controller 120 to process multiple operation requests. For example, the working memory may include a separate volatile memory (e.g., SRAM).
[0039] For example, buffer 121 may be implemented by a separate register, volatile memory (e.g., SRAM), non-volatile memory (e.g., NAND flash, NOR flash, PRAM, or MRAM), etc.
[0040] In another example, when controller 120 includes working memory, buffer 121 can be implemented by working memory.
[0041] Figure 2 This is a diagram illustrating the operation of a memory system processing a first read command according to an embodiment of the present disclosure.
[0042] Reference Figure 2 The host can send the first read command RD_CMD_1 to the controller 120 of the memory system 100 (S210). The first read command RD_CMD_1 is a command requesting to read the target data TGT_DATA stored at the target address TGT_ADDR of the memory medium 110.
[0043] After receiving the first read command RD_CMD_1, the controller 120 can use the target address TGT_ADDR to access the memory medium 110 (S220) and read the target data TGT_DATA (S230).
[0044] The controller 120 can store the read target data TGT_DATA in the buffer 121 (S240).
[0045] The controller 120 can generate a first response message RESP_MSG_1 based on the target data TGT_DATA read. The first response message RESP_MSG_1 is a response message to the first read command RD_CMD_1 (S250).
[0046] From the time the first read command RD_CMD_1 is received to the time the first response message RESP_MSG_1 is generated, the controller 120 may additionally receive another command from the host. This will be explained in the following reference. Figure 3 Detailed description.
[0047] Figure 3 This is a diagram illustrating the operation of the memory system in processing the second read command.
[0048] As mentioned above Figure 2The host can send the first read command RD_CMD_1 to the controller 120 of the memory system 100 (S210).
[0049] The host can send the second read command RD_CMD_2 to the controller 120 (S310). The host can send the second read command RD_CMD_2 to the controller 120 after sending the first read command RD_CMD_1.
[0050] Similar to the first read command RD_CMD_1, the second read command RD_CMD_2 is a command that requests to read the target data TGT_DATA stored at the target address TGT_ADDR of the memory medium 110. In other words, the first read command RD_CMD_1 and the second read command RD_CMD_2 are read commands that need to access the same address.
[0051] Subsequently, controller 120 can generate a second response message RESP_MSG_2 based on the target data TGT_DATA stored in buffer 121. The second response message RESP_MSG_2 is a response message to the second read command RD_CMD_2 (S320). Step S320 can be referred to above. Figure 2 The described step S240 is executed afterward.
[0052] Although the controller 120 must access the memory medium 110 to generate the first response message RESP_MSG_1, the controller 120 does not access the memory medium 110 separately during the generation of the second response message RESP_MSG_2. This is because the target data TGT_DATA is already stored in the buffer 121, so the second response message RESP_MSG_2 can be generated without accessing the memory medium 110.
[0053] Therefore, by preventing the same target data TGT_DATA from being read repeatedly from the memory medium 110, the controller 120 can process multiple read commands for the same target address TGT_ADDR more quickly.
[0054] During this process, the controller 120 needs to manage the first read command RD_CMD_1 and the second read command RD_CMD_2 as commands to read the target data TGT_DATA stored at the same target address TGT_ADDR.
[0055] The following describes how the controller 120 manages the first read command RD_CMD_1 and the second read command RD_CMD_2.
[0056] Figure 4 This is a diagram illustrating a linked list according to an embodiment of the present disclosure.
[0057] Reference Figure 4 The controller 120 can generate a linked list LINK_LIST, which stores information associated with read commands used to read target data TGT_DATA.
[0058] The linked list LINK_LIST may include one or more nodes. Each node may correspond to a specific read command and may include information about the corresponding read command (e.g., the read command, the storage location of the read command, the index of the read command, and the address of the data requested by the read command in the memory medium 110).
[0059] In addition, each node may further include a pointer to a subsequent node. The nodes included in the linked list LINK_LIST can be linked to each other individually via pointers to subsequent nodes.
[0060] Therefore, by traversing the nodes included in the linked list LINK_LIST, the controller 120 can access information about each read command requesting to read the target data TGT_DATA.
[0061] The currently processed read command can correspond to a node in the linked list LINK_LIST, and the next read command to be processed will correspond to the node following the node corresponding to the currently processed read command. When there are no subsequent nodes, the controller 120 can determine that there are no further read commands to process.
[0062] Therefore, controller 120 can determine whether a next read command exists by searching subsequent nodes in the linked list LINK_LIST. This allows the controller to generate a response to the next subsequent read command more quickly.
[0063] The target data TGT_DATA stored in buffer 121 can be used to generate response messages for read commands corresponding to all nodes in the linked list LINK_LIST except for the first inserted node. Therefore, controller 120 can determine more quickly whether to generate response messages for read commands using the target data TGT_DATA stored in buffer 121.
[0064] After generating the linked list LINK_LIST, the controller 120 can insert a first node NODE_1 into the linked list LINK_LIST. The first node NODE_1 includes information associated with the first read command RD_CMD_1. The first node NODE_1 can be the first node inserted into the linked list LINK_LIST.
[0065] After inserting the first node NODE_1 into the linked list LINK_LIST, the controller 120 can insert the second node NODE_2 into the linked list LINK_LIST. The second node NODE_2 includes information about the second read command RD_CMD_2.
[0066] Since the first read command RD_CMD_1 is received before the second read command RD_CMD_2, the controller 120 can insert the first node NODE_1 into the linked list LINK_LIST before the second node NODE_2.
[0067] In addition to the first read command RD_CMD_1 and the second read command RD_CMD_2, nodes corresponding to other read commands that request the reading of target data TGT_DATA can also be similarly inserted into the linked list LINK_LIST.
[0068] Among the nodes inserted into the LINK_LIST list, the node corresponding to the read command for which a response message has been sent to the host can be removed from the LINK_LIST list. The controller 120 may retain only the nodes corresponding to read commands for which a response message has not yet been sent to the host in the LINK_LIST list. This will be explained in the following reference. Figure 5 Detailed description.
[0069] Figure 5 This is a diagram illustrating the operation of inserting and deleting a first node NODE_1 and a second node NODE_2 in a linked list in a memory system according to an embodiment of the present disclosure.
[0070] As described above, the controller 120 of the memory system 100 can receive a first read command RD_CMD_1 from the host (S210). Afterwards, the controller 120 can insert a first node NODE_1, including information associated with the first read command RD_CMD_1, into the linked list LINK_LIST (S510).
[0071] Controller 120 can receive a second read command RD_CMD_2 (S310) from the host. Figure 5 In this embodiment, step S510 is performed before step S310, but in other embodiments, step S510 may be performed after step S310.
[0072] The controller 120 can insert a second node NODE_2, which includes information related to the second read command RD_CMD_2, into the linked list LINK_LIST (S520).
[0073] Then, controller 120 may send a first response message RESP_MSG_1 to the host in response to the first read command RD_CMD_1 (S530). Next, controller 120 may delete the first node NODE_1 from the linked list LINK_LIST (S540).
[0074] Controller 120 may send a second response message RESP_MSG_2 to the host (S550) in response to the second read command RD_CMD_2. Figure 5 In this embodiment, step S550 is performed after steps S530 and S540. However, in other embodiments, step S550 may be performed before at least one of steps S530 and S540.
[0075] Afterwards, controller 120 can delete the second node NODE_2 from the linked list LINK_LIST (S560).
[0076] While the memory system 100 is processing the first read command RD_CMD_1 and the second read command RD_CMD_2, the memory system 100 may pause processing the write command for the target address TGT_ADDR. This will be explained below. Figure 6 Detailed description.
[0077] Figure 6 This is a diagram illustrating the operation of a memory system processing a write command according to an embodiment of the present disclosure.
[0078] From the time the linked list LINK_LIST is generated until the time the linked list LINK_LIST becomes empty, the controller 120 of the memory system 100 can pause the processing of the write command WR_CMD.
[0079] The linked list LINK_LIST is an empty list when it does not contain any nodes.
[0080] When the linked list LINK_LIST is not empty, in order to prevent errors from occurring due to the write command WR_CMD when the controller 120 is processing the read command for the target data TGT_DATA, the controller 120 can pause the processing of the write command WR_CMD.
[0081] The write command WR_CMD is a command that requests that new data, different from the target data TGT_DATA, be written to the target address TGT_ADDR.
[0082] The write command WR_CMD is received from the host after the controller 120 receives the first read command RD_CMD_1 and the second read command RD_CMD_2.
[0083] In response to a read command received prior to the write command WR_CMD for the target address TGT_ADDR, the controller 120 should send the target data TGT_DATA previously stored in the target address TGT_ADDR—not the new data associated with the write command WR_CMD—to the host.
[0084] When the read command for the target address TGT_ADDR received before the write command WR_CMD is processed, the linked list LINK_LIST becomes empty. Therefore, the controller 120 can pause the processing of the write command WR_CMD before the linked list LINK_LIST becomes empty, thereby preventing any errors from occurring due to the processing of the write command WR_CMD.
[0085] After the linked list LINK_LIST becomes empty, the controller 120 can process the write command WR_CMD and delete the linked list LINK_LIST.
[0086] Figure 7 This is a diagram illustrating a method of operating a memory system according to an embodiment of the present disclosure.
[0087] Reference Figure 7 A method of operating a memory system 100 may include step S710 of receiving a first read command RD_CMD_1 from a host, the first read command RD_CMD_1 requesting target data TGT_DATA stored in a target address TGT_ADDR of the memory medium 110.
[0088] The method of operating the memory system 100 may include step S720 of reading target data TGT_DATA from memory medium 110.
[0089] The method of operating the memory system 100 may include step S730 of storing the read target data TGT_DATA in buffer 121.
[0090] The method of operating the memory system 100 may include step S740 of receiving a second read command RD_CMD_2 from the host after receiving a first read command RD_CMD_1, wherein the second read command RD_CMD_2 requests target data TGT_DATA stored in the target address TGT_ADDR.
[0091] The method of operating the memory system 100 may include step S750 of generating a first response message RESP_MSG_1 to a first read command RD_CMD_1 and a second response message RESP_MSG_2 to a second read command RD_CMD_2.
[0092] In step S750, the first response message RESP_MSG_1 is generated based on the target data TGT_DATA read from the memory medium 110, but the second response message RESP_MSG_2 is generated based on the target data TGT_DATA stored in the buffer 121.
[0093] The method of operating the memory system 100 may further include the following steps: generating a linked list LINK_LIST, which stores information associated with a read command requesting to read target data TGT_DATA; after receiving a first read command RD_CMD_1, inserting a first node NODE_1, which includes information about the first read command RD_CMD_1, into the linked list LINK_LIST; and after receiving a second read command RD_CMD_2, inserting a second node NODE_2, which includes information about the second read command RD_CMD_2, into the linked list LINK_LIST.
[0094] The method of operating the memory system 100 may further include the steps of: deleting a first node NODE_1 from the linked list LINK_LIST after sending a first response message RESP_MSG_1 to the host; and deleting a second node NODE_2 from the linked list LINK_LIST after sending a second response message RESP_MSG_2 to the host.
[0095] The method of operating the memory system 100 may further include the following steps: from the time when the linked list LINK_LIST is generated to the time when the linked list LINK_LIST becomes an empty list, suspend the processing of the write command WR_CMD for the target address TGT_ADDR.
[0096] The write command WR_CMD is a command requesting that data different from the target data TGT_DATA be written to the target address TGT_ADDR. After receiving the first read command RD_CMD_1 and the second read command RD_CMD_2, the controller 120 can receive the WR_CMD command from the host.
[0097] The method of operating the memory system 100 may further include the step of deleting the linked list LINK_LIST when processing the write command WR_CMD or after processing is complete.
[0098] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered merely descriptive and not limiting of the scope of the technology. The technical scope of this disclosure is not limited to the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted in conjunction with the appended claims and cover all equivalents falling within the scope of the appended claims.
Claims
1. A memory system, comprising: Memory medium; as well as The controller receives a read command from the host, reads data from the memory medium according to the read command, and generates a response message to the read command based on the data read from the memory medium. in, The controller includes a buffer that stores data read from the memory medium. The controller receives a first read command from the host for target data stored at a target address in the memory medium, reads the target data from the memory medium, stores the read target data in the buffer, and generates a first response message to the first read command based on the read target data. After receiving the first read command, the controller receives a second read command from the host for the target data stored at the target address, and generates a second response message to the second read command based on the target data stored in the buffer.
2. The memory system according to claim 1, wherein, The controller generates a linked list that stores information associated with read commands that read the target data. Insert a first node into the linked list, the first node including information associated with the first read command; After the first node is inserted into the linked list, a second node is inserted into the linked list, the second node including information associated with the second read command.
3. The memory system according to claim 2, wherein, After sending the first response message to the host, the controller removes the first node from the linked list, and after sending the second response message to the host, removes the second node from the linked list.
4. The memory system according to claim 3, wherein, From the time the linked list is generated until the time the linked list becomes empty, the controller pauses processing write commands, and The write command is a command that requests that new data be written to the target address, and the write command is received from the host after the first read command and the second read command.
5. The memory system according to claim 4, wherein, When processing the write command, the controller deletes the linked list.
6. A method for operating a memory system, comprising: Receive a first read command from the host, the first read command requesting to read target data stored in the target address of the memory medium; Read the target data from the memory medium; The target data is stored in a buffer; After receiving the first read command, a second read command is received from the host, the second read command requesting to read the target data stored in the target address; Based on the target data read from the memory medium, a first response message to the first read command is generated; as well as Based on the target data stored in the buffer, a second response message is generated in response to the second read command.
7. The method of claim 6, further comprising: Generate a linked list that stores information about read commands that request to read the target data; Upon receiving the first read command, a first node is inserted into the linked list, the first node including information about the first read command; as well as Upon receiving the second read command, a second node is inserted into the linked list, the second node including information about the second read command.
8. The method of claim 7, further comprising: After the first response message is sent to the host, the first node is removed from the linked list; as well as After the second response message is sent to the host, the second node is removed from the linked list.
9. The method of claim 8, further comprising: From the time the linked list is created until the time the linked list becomes empty, processing of write commands to the target address is paused. in, The write command is a command that requests that new data be written to the target address, and The write command is received from the host after the first read command and the second read command.
10. The method of claim 9, further comprising: When processing the write command, the linked list is deleted.