High-frequency low-noise phase-locked loop circuit and infrared detector

Abstract

The invention discloses a high-frequency low-noise phase-locked loop circuit and an infrared detector, and relates to the technical field of infrared focal plane reading circuits, and the phase-locked loop circuit comprises a phase frequency detection circuit which is used for receiving an external reference clock signal and a feedback frequency division signal, carrying out phase frequency comparison, forming closed-loop locking, and generating a control signal; the charge pump circuit is used for generating a differential pulse current signal according to the control signal; the loop filter circuit is used for integrating and filtering the differential pulse current signal to generate a continuous control voltage signal; the voltage-controlled oscillator bias circuit is used for converting the continuous control voltage signal into a bias current signal; the annular voltage-controlled oscillator circuit is used for generating a high-frequency oscillation signal according to the bias current signal; and the frequency dividing circuit is used for performing integer frequency division on the high-frequency oscillation signal to generate a feedback frequency division signal. The invention has the characteristics of high frequency stability, low phase noise, small area, low power consumption and the like.

Description

Technical Field

[0001] This invention relates to the field of infrared focal plane readout circuit technology, and in particular to a high-frequency, low-noise phase-locked loop circuit and an infrared detector. Background Technology

[0002] In long-wave (8~14μm) applications such as early warning, monitoring, aerospace remote sensing and high-precision temperature measurement, infrared detection technology places higher demands on the sensitivity, anti-interference and signal restoration capabilities of infrared focal plane detectors in infrared detection systems due to the extremely weak signals in the long-wave infrared band.

[0003] In traditional infrared detector readout circuit architectures, analog signals, after being output from the pixel array, require amplification and analog-to-digital conversion through column-level or output-level circuits. This results in limitations in sampling accuracy, noise accumulation, and increased interference. To overcome these problems, pixel-level digital readout circuit architectures have gradually become a research hotspot. By directly integrating the analog-to-digital converter (ADC) circuit within the pixel unit, the transmission path from the analog signal to the ADC is shortened, enabling the detector to output digital signals and significantly improving the detector's anti-interference capability, sensitivity, and resolution.

[0004] However, the realization of pixel-level digitization places more stringent requirements on the clock circuit: on the one hand, a high-frequency, low-phase-noise, and low-jitter clock signal must be provided to drive the analog-to-digital converter circuit; on the other hand, to ensure the timing consistency of each unit in the pixel array during large-scale parallel sampling, the phase-locked loop (PLL) needs to have extremely high stability and phase consistency, while also possessing a certain degree of adjustment capability to adapt to different operating modes or application requirements. The PLL design needs to be small in size, low in power consumption, easy to integrate, and able to stably output the target frequency for a long time to meet the acquisition requirements of weak signals by long-wavelength detectors. Summary of the Invention

[0005] This invention provides a high-frequency, low-noise phase-locked loop circuit and an infrared detector.

[0006] In a first aspect, a high-frequency, low-noise phase-locked loop circuit is provided, comprising: A phase frequency detection circuit, including a PFD, generates control signals for a charge pump circuit. A charge pump circuit, whose input is connected to the output of the phase frequency detection circuit, is used to generate a differential pulse current signal for driving the control voltage change of the filter circuit according to the control signal; the differential pulse current signal has different polarities in the time domain. A loop filter circuit, whose input terminal is connected to the output terminal of the charge pump circuit, is used to integrate and filter the differential pulse current signal to generate a continuous control voltage signal for controlling the output frequency of the voltage-controlled oscillator bias circuit. A voltage-controlled oscillator bias circuit, whose input terminal is connected to the output terminal of the loop filter circuit, is used to convert the continuous control voltage signal into an adjustable bias current signal. A ring voltage-controlled oscillator circuit, wherein the bias terminal is connected to the output terminal of the voltage-controlled oscillator bias circuit, is used to generate a high-frequency oscillation signal according to the bias current signal; A frequency divider circuit, whose input terminal is connected to the output terminal of the ring voltage-controlled oscillator circuit, is used to perform integer frequency division on the high-frequency oscillation signal to generate a frequency-divided signal for feedback to the phase frequency detection circuit; The phase-frequency detection circuit is used to receive an external reference clock signal and the feedback frequency division signal, and to perform phase-frequency comparison to form a closed-loop lock and generate the control signal including phase difference and frequency difference.

[0007] Furthermore, the input terminal of the phase frequency detection circuit is connected to a clock signal circuit, which includes a frequency divider, a D flip-flop, and a multiplexer. The external reference clock signal is output through the frequency divider, one path of which is directly fed into one input terminal of the multiplexer; the other path is fed into the other input terminal of the multiplexer after passing through the D flip-flop. The output path of the multiplexer is selected by the MODE signal.

[0008] Furthermore, the loop filter circuit uses a second-order filter with a passive RC network structure for integration processing.

[0009] Furthermore, the ring voltage-controlled oscillator adopts a multi-stage ring structure, including multiple cascaded differential delay units with capacitor adjustment function; it uses multi-stage complementary delay units to form a loop oscillation, and changes the transmission delay of each stage by the current of the differential pair, thereby realizing the adjustable output frequency of the high-frequency clock signal in the phase-locked loop.

[0010] Furthermore, the ring voltage-controlled oscillator circuit also includes a differential delay unit, which forms a loop oscillation by using multiple complementary delay units. The transmission delay of each stage is changed by the current of the differential pair, thereby realizing the adjustable output frequency of the high-frequency clock signal in the phase-locked loop.

[0011] Furthermore, the frequency divider circuit includes a counter and a logic controller, which are used to select different division ratios through an external configuration signal, so that the division signal fed back to the phase frequency detection circuit is the set frequency, thereby achieving closed-loop locking.

[0012] Furthermore, the external reference clock signal fref is set to 2 MHz; The frequency division signal fed back to the phase frequency detection circuit is 2MHz.

[0013] Secondly, an infrared detector is provided, comprising: The high-frequency, low-noise phase-locked loop circuit described in the first aspect. Attached Figure Description

[0014] Figure 1 A schematic diagram of a high-frequency, low-noise phase-locked loop circuit provided in an embodiment of this application; Figure 2 A circuit diagram of a high-frequency, low-noise phase-locked loop circuit provided in an embodiment of this application. Detailed Implementation

[0015] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the technical solutions in the embodiments of this application are clearly described. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0016] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0017] The steps described in the specification and the flowcharts in the accompanying drawings of this invention are not necessarily strictly executed according to the step numbers; the execution order of the method steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.

[0018] This specification provides a high-frequency, low-noise phase-locked loop circuit and also relates to an infrared detector. The following detailed description is provided in conjunction with the accompanying drawings and preferred embodiments.

[0019] Please see Figure 1-2 This application provides a high-frequency, low-noise phase-locked loop circuit, such as... Figure 1-2 As shown, it includes: The phase frequency detection circuit, including the PFD (Phase Frequency Detector), generates control signals (UP / DN) for the charge pump circuit. A charge pump circuit, whose input is connected to the output of the phase frequency detection circuit, is used to generate a differential pulse current (ICP) signal for driving the control voltage change of the filter circuit according to the control signal; the differential pulse current (ICP) signal has different polarities in the time domain. A loop filter circuit, whose input is connected to the output of the charge pump circuit, is used to integrate and filter the differential pulse current (ICP) signal to generate a continuous control voltage signal for controlling the output frequency of the voltage-controlled oscillator bias circuit. A voltage-controlled oscillator bias circuit, whose input terminal is connected to the output terminal of the loop filter circuit, is used to convert the continuous control voltage signal into an adjustable bias current signal. A ring voltage-controlled oscillator circuit, the bias terminal of which is connected to the output terminal of the voltage-controlled oscillator bias circuit, is used to generate a high-frequency oscillation signal (fvco) based on the bias current signal. A frequency divider circuit, whose input terminal is connected to the output terminal of the ring voltage-controlled oscillator circuit, is used to perform integer frequency division on the high-frequency oscillation signal (fvco) to generate a frequency-divided signal (fdiv) for feedback to the phase frequency detection circuit. The phase-frequency detection circuit is used to receive an external reference clock signal (fref) and the feedback frequency division signal (fdiv), and to perform phase-frequency comparison to form a closed-loop lock and generate the control signal including phase difference and frequency difference.

[0020] In the specific implementation process, see Figure 1The phase-frequency detection circuit (phase detector) compares the phase and frequency of the input reference clock signal fref with the output clock signal fdiv of the frequency divider circuit (DIV). In this stage, the charge pump phase-locked loop system typically outputs two control signals. Then, the output signal pulses, containing both phase and frequency differences, control the switching of the charging and discharging current sources in the charge pump circuit (CP), controlling the opening and closing of the upper and lower current paths. This allows the charge pump output to produce a current ICP of different polarities in the time domain. Next, ICP flows through a loop filter circuit (low-pass filter, LPF), which filters out high-frequency signals and retains low-frequency signals. The LPF then converts the current signal ICP into a real-time voltage signal, which controls the output frequency of the ring voltage-controlled oscillator (VCO). Finally, the frequency divider circuit (DIV) divides the VCO output signal fvco to obtain a lower frequency signal fdiv, which is then compared with the input reference clock signal fref. This cycle achieves the frequency and phase tracking function of the charge pump phase-locked loop's output signal. In this negative feedback system, when the phases of fref and fdiv are unequal, the capacitor in the LPF continuously charges and discharges, thereby adjusting the output frequency of the VCO. When the phase-locked loop is locked, there is no phase difference between the input clock signal fref and the divider output signal fdiv; the input and output signals are in phase. Therefore, by coordinating the optimization of loop parameters (including the phase comparator, charge pump, voltage-controlled oscillator, and filter), the stability and frequency output range of the output clock signal are effectively improved. This gives the phase-locked loop (PLL) circuit the characteristics of fast locking, low phase noise, and high frequency stability. This structure can continuously provide a low-phase-noise, high-bandwidth clock signal in the context of wide dynamic range infrared image acquisition. Compared with traditional PLL structures, this invention has a higher frequency range, lower power consumption, and better noise performance. It can be adapted to pixel-level ADC architectures and supports the construction of a high-precision clock platform in long-wave infrared detectors, fully leveraging the advantage of the large photocurrent of long-wave devices.

[0021] Furthermore, the input terminal of the phase frequency detection circuit is connected to a clock signal circuit, which includes: a frequency divider (PLL_FDIV5), a D flip-flop (DFFRK1), and a multiplexer (M2X1). The external reference clock signal (fref) is output through the frequency divider, one path is directly fed into one input terminal (A terminal) of the multiplexer; the other path is fed into the other input terminal (B terminal) of the multiplexer after passing through the D flip-flop. The output path of the multiplexer is selected by the MODE signal.

[0022] More specifically, two input clock signals can be selected at the input terminal: 10 MHz and 20 MHz. Preferably, the external reference clock signal fref is set to 2 MHz and input to the PFD. Its phase and frequency are compared with the feedback signal output from the VCO and processed by the frequency divider to generate the UP / DN control signal. Thus, the overall PLL structure supports two input clock modes: MODE=0 corresponds to a 10 MHz input, and MODE=1 corresponds to a 20 MHz input. Stable locking can be achieved in both operating modes, and a high-frequency, low-noise local oscillator clock source can be output, adapting to the precise sampling control of pixel-level ADCs.

[0023] In some possible implementations, the phase frequency detection circuit further includes a differential buffer circuit to buffer, differentially convert, or shape the input signal to ensure good signal integrity of the reference clock fref and feedback signal fdiv received by the PFD.

[0024] Furthermore, the charge pump circuit is composed of a source follower structure and a current mirror, with symmetrical matching of pull-up and pull-down branches. The charge pump gain Kp = 5μA / 2π is used to generate differential pulse current based on the UP / DN (DOWN) control signal output by the PFD, thereby driving the filter control voltage change.

[0025] Furthermore, the loop filter circuit employs a second-order filter with a passive RC network structure for integration processing to generate a continuously adjustable control voltage, improving phase margin and response speed, enabling the system to quickly enter the locked state, and enhancing system stability and anti-interference capability. Its preferred bandwidth is approximately 80kHz, pole frequency is 343kHz, and loop settling time is approximately 50μs.

[0026] Furthermore, the ring voltage-controlled oscillator adopts a multi-stage ring structure, consisting of multiple cascaded differential delay units (DLY_CELL) with capacitor adjustment function. It utilizes multiple complementary delay units to form a loop oscillation, and changes the propagation delay of each stage by altering the current of the differential pairs, thus achieving an adjustable output frequency of the high-frequency clock signal in the phase-locked loop. It features a wide tuning range and high frequency gain, with an output frequency range of 564MHz to 1.28GHz and a gain of Kvco≈1.02GHz. Finally, the differential signal is converted and output through a signal conversion unit (PLL_D2S).

[0027] Furthermore, the frequency divider circuit includes a counter and a logic controller, which are used to select different division ratios through an external configuration signal, so that the division signal fdiv fed back to the phase frequency detection circuit is 2MHz, thereby achieving closed-loop locking.

[0028] The following provides a specific implementation process.

[0029] First, a phase-frequency detection circuit is designed, consisting of a PFD and a differential buffer. Two input clock signals can be selected at the input terminal: 10 MHz and 20 MHz. The reference clock fref is set to 2 MHz and input to the PFD. Its phase-frequency is compared with the feedback signal output from the VCO and processed by a frequency divider to generate the UP / DN control signal, as shown below. Figure 1 As shown.

[0030] Then, the UP / DN control signal is input to the charge pump circuit, which outputs a current signal, which is then sent to a second-order filter for integration to generate a continuously adjustable control voltage. The loop filter adopts a passive RC network structure, designed to improve phase margin and response speed, enabling the system to quickly enter the locked state. The typical bandwidth is approximately 80kHz, the pole frequency is 343kHz, and the loop settling time is approximately 50μs.

[0031] Subsequently, the control voltage output from the filter is fed into the VCO bias circuit to drive the bias current adjustment of the voltage-controlled oscillator. To provide a stable bias for the VCO, this module needs to be placed close to the Ring VCO to reduce parasitic interference and phase disturbances caused by connection traces. The voltage-controlled oscillator adopts a three-stage ring structure, composed of multiple cascaded delay units, and has a wide tuning range and high frequency gain (Kvco≈1.02GHz), achieving an output frequency range of 564MHz~1.28GHz. The VCO output signal is divided and fed back to the PFD to form a closed loop, allowing the system to operate stably under a low-voltage supply condition of VDD=1.2V.

[0032] Finally, the remaining circuit design of the PLL was completed, forming a complete module, and the layout was implemented and verified on the tape-out. The overall PLL structure supports two input clock modes: MODE=0 corresponds to a 10MHz input, and MODE=1 corresponds to a 20MHz input. Stable locking can be achieved in both operating modes, and a high-frequency, low-noise local oscillator clock source is output, which is suitable for the precise sampling control of pixel-level ADCs.

[0033] In summary, this implementation method optimizes the collaborative design of the PFD, charge pump, filter, and VCO modules, and combines multiple operating mode control mechanisms to achieve stable operation of the high-frequency phase-locked loop in the infrared pixel-level circuit while ensuring low power consumption and small-area integration. This provides a reliable clock foundation for subsequent image sampling and digital processing.

[0034] Corresponding to the above-described high-frequency low-noise phase-locked loop circuit embodiments, this application provides an infrared detector, including: the above-described high-frequency low-noise phase-locked loop circuit.

[0035] The infrared detector described above achieves the same technical effect as the high-frequency low-noise phase-locked loop circuit embodiment described above, and will not be repeated here to avoid repetition.

[0036] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0037] It is understood that the embodiments of this application have been described above in conjunction with the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. As those skilled in the art will know, various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, those skilled in the art, under the guidance or instruction of this application, can modify these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this invention.

Claims

1. A high-frequency, low-noise phase-locked loop circuit, characterized in that, include: A phase frequency detection circuit, including a PFD, generates control signals for the charge pump circuit. A charge pump circuit, whose input is connected to the output of the phase frequency detection circuit, is used to generate a differential pulse current signal for driving the control voltage change of the filter circuit according to the control signal; the differential pulse current signal has different polarities in the time domain. A loop filter circuit, whose input terminal is connected to the output terminal of the charge pump circuit, is used to integrate and filter the differential pulse current signal to generate a continuous control voltage signal for controlling the output frequency of the voltage-controlled oscillator bias circuit. A voltage-controlled oscillator bias circuit, whose input terminal is connected to the output terminal of the loop filter circuit, is used to convert the continuous control voltage signal into an adjustable bias current signal. A ring voltage-controlled oscillator circuit, wherein the bias terminal is connected to the output terminal of the voltage-controlled oscillator bias circuit, is used to generate a high-frequency oscillation signal according to the bias current signal; A frequency divider circuit, whose input terminal is connected to the output terminal of the ring voltage-controlled oscillator circuit, is used to perform integer frequency division on the high-frequency oscillation signal to generate a frequency-divided signal for feedback to the phase frequency detection circuit; The phase-frequency detection circuit is used to receive an external reference clock signal and the feedback frequency division signal, and to perform phase-frequency comparison to form a closed-loop lock and generate the control signal including phase difference and frequency difference.

2. The high-frequency, low-noise phase-locked loop circuit according to claim 1, characterized in that, The phase frequency detection circuit is connected to a clock signal circuit at its input, which includes a frequency divider, a D flip-flop, and a multiplexer. An external reference clock signal is output from the frequency divider, one path of which is directly fed into one input of the multiplexer; the other path is fed into the other input of the multiplexer after passing through the D flip-flop. The output path of the multiplexer is selected by the MODE signal.

3. The high-frequency, low-noise phase-locked loop circuit according to claim 1, characterized in that, The loop filter circuit uses a second-order filter with a passive RC network structure for integration processing.

4. The high-frequency, low-noise phase-locked loop circuit according to claim 1, characterized in that, The ring voltage-controlled oscillator adopts a multi-stage ring structure, including multiple cascaded differential delay units with capacitor adjustment function; it uses multi-stage complementary delay units to form a loop oscillation, and changes the transmission delay of each stage by the current of the differential pair to realize the adjustable output frequency of the high-frequency clock signal in the phase-locked loop.

5. The high-frequency, low-noise phase-locked loop circuit according to claim 1, characterized in that, The frequency divider circuit includes a counter and a logic controller, which are used to select different division ratios through external configuration signals so that the division signal fed back to the phase frequency detection circuit is the set frequency, thereby achieving closed-loop locking.

6. The high-frequency, low-noise phase-locked loop circuit according to claim 1, characterized in that, The external reference clock signal is set to 2 MHz; The frequency division signal fed back to the phase frequency detection circuit is 2MHz.

7. An infrared detector, characterized in that, include: The high-frequency, low-noise phase-locked loop circuit as described in claim 1.

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