A method and device for on-board interference avoidance based on hierarchical dynamic coordination

Abstract

The application discloses a layered dynamic coordination-based on-board interference avoidance method and device. The method divides the interference avoidance task into interference avoidance in a multi-core processor and interference avoidance between multi-core processors. For the interference avoidance between multi-core processors, a high-layer scheduling controller performs interference avoidance according to the user density of adjacent spatial resource division units between the multi-core processors; for the interference avoidance in the multi-core processor, a media access control layer in the multi-core processor at a bottom layer is internally provided with a scheduling advance amount of each thread, so that different time points of adjacent threads on a pipeline correspond to the same time point of scheduling, resource allocation is performed at the same time point, a subsequent thread perceives a scheduling result of a previous thread, and interference avoidance is performed. The application reduces the calculation complexity of a single decision point, meets the real-time requirement of on-board scheduling, and significantly improves scheduling flexibility and interference response speed.

Description

Technical Field

[0001] This invention relates to the field of wireless communication management, specifically to a method and apparatus for avoiding on-board interference based on hierarchical dynamic coordination. It can be applied to satellite communication, especially in low-Earth orbit constellations and other systems employing large-scale co-frequency multi-beam systems, to avoid co-frequency interference between beams in real time. Background Technology

[0002] In 6G-oriented space-ground converged communication scenarios, large-scale phased array antennas have become a core technological support. They can generate dozens or even hundreds of beams to achieve continuous, wide-area coverage of the ground, which is also a key means to improve the capacity of communication systems. Due to the scarcity of spectrum resources, in order to overcome spectrum bottlenecks and maximize resource utilization, it is necessary to reuse the same frequencies among massive beams. However, this also brings extremely complex inter-beam co-frequency interference problems, becoming a core bottleneck restricting the performance improvement of on-board communication systems.

[0003] In existing technologies, the main approach to address co-channel interference between multiple beams on satellites is a single-level centralized decision-making architecture. Typically, this architecture includes static beam hopping scheduling schemes based on offline computation and dynamic beam hopping scheduling schemes that rely on a central processing unit for real-time optimization. However, both schemes rely on a single decision node to directly generate the final beam scheduling instructions at the network layer in an attempt to avoid co-channel interference between beams.

[0004] However, with the continuous surge in beam size of communication systems such as low-Earth orbit satellites, and the highly dynamic and random nature of terrestrial services, a single-level centralized scheduling approach is ill-suited to practical application needs. Specifically: First, there is a fundamental conflict between high-level global optimization and low-level real-time scheduling: high-level global optimization requires comprehensive consideration of long-term service statistical characteristics and complex inter-beam interference relationships, resulting in complex calculation processes and long cycles; while low-level real-time scheduling requires extremely low processing latency and extremely high parallel throughput, which a single decision node cannot simultaneously meet. Second, scheduling flexibility is severely limited: spaceborne base stations typically use multiple multi-core processors to collaboratively complete multi-beam scheduling tasks, but the decision point in a single architecture is far from the multi-core processor that performs low-level scheduling, making it impossible for the decision node to dynamically and quickly respond to instantaneous interference changes within the chip, and difficult to adjust the scheduling strategy in real time. Finally, system performance is limited by the computing power of a single decision point: when the number of beams increases significantly, the number of interference relationships and scheduling combinations that the decision node needs to handle explodes, and its computing power gradually becomes a bottleneck for improving system performance, ultimately leading to excessive scheduling latency and an inability to further increase system capacity.

[0005] Therefore, existing interference avoidance schemes based on centralized decision-making at a single level can no longer meet the application requirements of large-scale co-frequency multi-beam on-board communication systems. How to solve the problems of insufficient scheduling flexibility, low efficiency, and computational complexity in existing large-scale co-frequency multi-beam systems has become a technical problem that needs to be solved urgently. Summary of the Invention

[0006] The purpose of this invention is to propose an on-board interference avoidance method and device based on hierarchical dynamic collaboration. The interference avoidance task is divided into interference avoidance within a multi-core processor and interference avoidance between multi-core processors. This avoids problems such as insufficient scheduling flexibility, low efficiency, and computational complexity caused by centralized decision-making at a single level, and achieves efficient interference avoidance for on-board multi-beam systems.

[0007] To achieve this objective, the present invention adopts the following technical solution:

[0008] A hierarchical dynamic collaborative on-board interference avoidance method is applied to a low-Earth orbit satellite multi-beam co-frequency communication system. The communication system includes a scheduling controller and at least two multi-core processors, with the scheduling controller communicatively connected to each multi-core processor. The method includes:

[0009] Scheduling controller avoidance steps:

[0010] The system senses the user access status of the spatial resource allocation units responsible for each multi-core processor and obtains the user density of adjacent spatial resource allocation units between multi-core processors.

[0011] Based on the user density of adjacent spatial resource partitioning units among the multi-core processors, a corresponding scheduling time slot is allocated to each multi-core processor within a preset interference avoidance period, and the multiple multi-core processors are notified. The multi-core processors then perform scheduling based on the scheduling time slots.

[0012] Multi-core processors perform internal interference avoidance steps:

[0013] The system sets up information sharing and transmission between threads in the Media Access Control (MAC) layer of a multi-core processor, as well as scheduling lead time for multiple scheduling threads. This ensures that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread executes sequentially according to a preset order, obtains the scheduling results of the preceding thread, filters priorities, avoids interference from the space resource partitioning units within the multi-core processor, performs interference avoidance, and completes scheduling.

[0014] Optionally, the step of sensing the user access status of the spatial resource allocation units managed by each multi-core processor and obtaining the user density of adjacent spatial resource allocation units between multi-core processors includes:

[0015] The space resource allocation units are initialized. Based on the satellite coverage area, the space resource allocation units responsible for each multi-core processor are divided, and the adjacency of the space resource allocation units between the multi-core processors is determined.

[0016] Define an interference avoidance period and, within each interference avoidance period, count the proportion of users in adjacent spatial resource partitioning units of multi-core processors.

[0017] Optionally, based on the user density of adjacent spatial resource partitioning units among the multi-core processors, corresponding scheduling time slots are allocated to each multi-core processor within a preset interference avoidance period, and multiple multi-core processors are notified. The multi-core processors then perform scheduling based on the scheduling time slots, specifically as follows:

[0018] Based on the user ratio, a corresponding proportion of scheduling time slots is provided for adjacent spatial resource partitioning units between each multi-core processor. The allocated scheduling time slots for adjacent wavelengths are notified to each multi-core processor through a message interface. Within the notification period, the multi-core processor schedules adjacent spatial resource partitioning units according to the scheduling time slots notified by the scheduling controller.

[0019] Optionally, the avoidance period can be determined according to the specific business scenario; and / or,

[0020] The allocation ratio of the scheduling time slots is consistent with the user ratio of adjacent spatial resource allocation units.

[0021] Optionally, the setting of information sharing and transmission between threads in the Media Access Control (MAC) layer of the multi-core processor, and the scheduling lead of multiple scheduling threads, so that different times of adjacent threads on the pipeline correspond to the same scheduling time, and each scheduling thread executes sequentially in a preset order to obtain the scheduling result of the preceding thread, including:

[0022] The information sharing and transmission method between threads in the Media Access Control (MAC) layer of a multi-core processor is set, and the scheduling lead of multiple scheduling threads is set so that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread is executed in a preset order, and each thread can obtain the scheduling result of the preceding thread at the corresponding scheduling time.

[0023] Optionally, the filtering priority, to avoid interference from the space resource allocation units within the multi-core processor, performs interference avoidance, and completes scheduling, includes:

[0024] Extract the priority of the spatial resource partitioning units, sort them as scheduling priorities, and share the sorting results among scheduling threads;

[0025] Scheduling begins according to the sorting results. If the spatial resource partitioning unit has already been scheduled or is subject to interference, it will not be scheduled until the next interference-free spatial resource partitioning unit is reached. Scheduling and avoidance will then begin, and the scheduling results will be shared for use in avoiding interference in the next thread scheduling.

[0026] Optionally, the scheduling lead should be set so that multiple threads are aligned to the same physical moment of scheduling; and / or,

[0027] The spatial resource partitioning unit is subject to interference because adjacent spatial resource partitioning units have already been scheduled in the preceding thread.

[0028] Optionally, the spatial resource partitioning unit is a wave position or a narrow beam.

[0029] Optionally, information sharing and passing between threads can be achieved through shared memory, message queues, pipes, or global variables.

[0030] This invention further discloses an on-board interference avoidance device based on hierarchical dynamic coordination, comprising: a scheduling controller and at least two multi-core processors, wherein the scheduling controller is communicatively connected to each multi-core processor module.

[0031] The scheduling controller is used to sense the user access status of the spatial resource allocation unit responsible for each multi-core processor, obtain the user density of adjacent spatial resource allocation units between multi-core processors, allocate corresponding scheduling time slots to each multi-core processor within a preset interference avoidance period based on the user density of adjacent spatial resource allocation units between multi-core processors, and notify the corresponding multi-core processor.

[0032] The multi-core processor module is used to set the information sharing and transmission between threads of the Media Access Control (MAC) layer within the multi-core processor, as well as the scheduling lead of multiple scheduling threads, so that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread executes in a preset order, obtains the scheduling results of the preceding thread, filters priorities, avoids interference from the space resource partitioning units within the multi-core processor, performs interference avoidance, and completes the scheduling.

[0033] In summary, the present invention has the following advantages:

[0034] 1. Layered collaborative architecture to resolve the inherent contradictions of centralized decision-making:

[0035] This invention pioneers a two-tier dynamic collaborative architecture of "system-multi-core processor," decoupling the centralized decision-making traditionally undertaken by a single node into macro-level coordination by a high-level scheduling controller and micro-level execution by a low-level chip scheduler. The high-level controller focuses only on coordinating interference between adjacent spatial resource allocation units among multi-core processors, without needing to intervene in fine-grained scheduling within the chip. This significantly reduces the computational complexity of a single decision point, completely overcoming the demand conflicts inherent in traditional centralized architectures, while also avoiding the explosive growth in computational load caused by a surge in beam size.

[0036] 2. Streamline scheduling + real-time result sharing enables accurate prediction and efficient avoidance of interference:

[0037] By employing a pipelined scheduling and real-time sharing strategy of decision results at the MAC layer within the multi-core processor, subsequent threads can proactively and with low latency acquire the scheduling results of preceding threads, accurately identify occupied beam positions and adjacent interfering beam positions, and achieve "early detection and proactive avoidance" of interference. This design not only solves the beam conflict problem caused by traditional thread isolation scheduling, but also retains the high efficiency of multi-threaded parallel processing through the logic of "staggered start + alignment at the same physical moment," without additional synchronization overhead, thus meeting the real-time requirements of on-board scheduling.

[0038] 3. Inter-thread coordination mechanism to improve on-chip scheduling flexibility and response speed:

[0039] By leveraging inter-thread information sharing and scheduling interference identification mechanisms, threads within a multi-core processor can dynamically adapt to instantaneous interference changes within the chip. When a sudden increase in users or temporary interference occurs at a certain wave position, the local thread can adjust its scheduling strategy directly based on previous results without relying on upper-layer instructions, quickly selecting a conflict-free wave position. This significantly improves scheduling flexibility and interference response speed, perfectly adapting to the dynamic nature of business operations and the randomness of interference.

[0040] 4. The architecture is scalable and easy to implement, adapting to future evolution needs:

[0041] The layered design strategy transforms static interference planning into two-level dynamic sensing and scheduling, giving the system extremely strong flexibility and scalability. The distributed architecture supports beam size expansion by adding processing units, and upper and lower layer modules can be upgraded independently, adapting to future network evolution and algorithm optimization without overall reconstruction. At the same time, this invention is implemented through software-level logical design, eliminating the need for additional hardware modules, reducing the integration cost and implementation difficulty of on-board equipment, and improving engineering practicality. Attached Figure Description

[0042] Figure 1 This is an architecture diagram of a layered dynamic collaborative on-board interference avoidance system according to a specific embodiment of the present invention;

[0043] Figure 2This is a flowchart of a hierarchical dynamic cooperative on-board interference avoidance method according to a specific embodiment of the present invention;

[0044] Figure 3 This is a flowchart of the interference avoidance steps of the scheduling controller according to a specific embodiment of the present invention;

[0045] Figure 4 This is a flowchart of the MAC layer scheduling thread interference avoidance steps according to a specific embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram of beam scheduling according to a specific embodiment of the present invention. Detailed Implementation

[0047] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0048] The main feature of this invention is that it divides the interference avoidance task into interference avoidance within a multi-core processor and interference avoidance between multi-core processors. For interference avoidance between multi-core processors, the higher-level scheduling controller performs interference avoidance based on the user density of adjacent spatial resource allocation units (e.g., beamwidth or narrow beam) between multi-core processors. For interference avoidance within a multi-core processor, the lower-level Media Access Control (MAC) layer within the multi-core processor sets the scheduling lead for each thread, so that different times of adjacent threads on the pipeline correspond to the same scheduling time, so that resources are allocated at the same time. Subsequent threads perceive the scheduling results of the preceding threads and perform interference avoidance in sequence according to the geographical location of the terminal scheduling.

[0049] For details, see Figure 1 This illustrates an architecture diagram of hierarchical dynamic collaborative on-board interference avoidance according to a specific embodiment of the present invention. See [link / reference]. Figure 2 The flowchart illustrates a hierarchical dynamic cooperative on-board interference avoidance method according to a specific embodiment of the present invention.

[0050] A hierarchical dynamic cooperative on-board interference avoidance method is applied to a low-Earth orbit satellite multi-beam co-frequency communication system. This system includes a scheduling controller and at least two multi-core processors. The scheduling controller and each multi-core processor are communicatively connected, for example, through a message interface. The method includes:

[0051] The scheduler avoidance step is primarily used by the scheduler to perform interference avoidance between multi-core processors.

[0052] The system senses the user access status of the spatial resource allocation units responsible for each multi-core processor and obtains the user density of adjacent spatial resource allocation units between multi-core processors.

[0053] Based on the user density of adjacent spatial resource partitioning units among multi-core processors, a corresponding scheduling time slot is allocated to each multi-core processor within a preset interference avoidance period, and multiple multi-core processors are notified, and the multi-core processors perform scheduling based on the scheduling time slot.

[0054] The spatial resource allocation unit can be a beam or a narrow beam; the beam is used as an example below. Both a beam and a narrow beam essentially represent the directional coverage area generated by the phased array antenna of a low-Earth orbit satellite.

[0055] Once the user terminal (UE) connects, it uses location information to determine which wavelength it is on. The scheduling controller can then detect the number of users on each wavelength among the adjacent wavelengths of the multi-core processor.

[0056] Beam skipping is performed by using the user density of adjacent positions over a relatively wide time range. For example, if the user density is 1:1, then the time division relationship of adjacent positions is also 1:1. That is, at time 1, position 0 of the adjacent positions gets a scheduling opportunity, and at time 2, position 2 of the adjacent positions gets a scheduling opportunity.

[0057] The multi-core processor executes an internal interference avoidance step, which is mainly used for interference avoidance steps in the space resource partitioning unit within the multi-core processor:

[0058] The system sets up information sharing and transmission between threads in the Media Access Control (MAC) layer of a multi-core processor, as well as scheduling lead time for multiple scheduling threads, so that different times of adjacent threads on the pipeline correspond to the same scheduling time, and each scheduling thread executes in a preset order; it obtains the scheduling results of the preceding thread, filters priorities, avoids interference from the space resource partitioning units inside the multi-core processor, performs interference avoidance, and completes scheduling.

[0059] In this invention, the spatial resource partitioning unit inside a multi-core processor refers to the spatial resource partitioning unit managed by a single multi-core processor, and each multi-core processor avoids interference with the spatial resource partitioning unit managed by its own processor.

[0060] In this step, the spatial resource division unit will be explained using wave position as an example.

[0061] First, the pipeline scheduling mode of the MAC layer of the multi-core processor is set, and the scheduling advance of each thread is initialized so that different times of adjacent threads in the pipeline correspond to the same scheduling time, so that resources can be allocated at the same time, as shown in Table 1:

[0062] Table 1: Scheduling table for each thread at different times

[0063]

[0064] As shown in Table 1, by setting scheduling lead times for threads 1, 2, and 3, although the current times of adjacent threads 1, 2, and 3 are not the same, thread 1's time 0, thread 2's time 1, and thread 3's time 2 are all scheduled at the same time. This means that the scheduling result of thread 1 can be perceived by thread 2. For example, each thread can share memory, thereby perceiving the scheduling results of the aforementioned threads. Consequently, thread 2 can use the scheduling result of thread 1 to perform interference calculations and avoid interference at the scheduling level.

[0065] Secondly, interference avoidance within the multi-core processor is implemented.

[0066] like Figure 5 As shown, the current thread 1 beam scheduler has selected beam position 19. The beam positions adjacent to beam position 19 (14, 15, 18, 20, 22, 23) may all be subject to interference. Therefore, when thread 2 schedules, it only selects the other uninterrupted beam positions other than the adjacent beam positions (14, 15, 18, 20, 22, 23) for scheduling.

[0067] That is, based on the result of the previous thread scheduling, avoidance is performed, and an undisturbed wave position is selected.

[0068] In the above example, information sharing between threads is set to shared memory, but the present invention is not limited to this. Information sharing between threads can also be achieved through message queues, pipes, global variables, etc.

[0069] Further, see Figure 3 The flowchart illustrates the interference avoidance steps of the scheduling controller according to a specific embodiment of the present invention.

[0070] like Figure 1 As shown, if n is 4, the spatial resource allocation unit is a beam with a quantity of 64, then the 64 beams are evenly distributed to 4 multi-core processors, each processor is responsible for scheduling 16 beams, and the scheduling controller is responsible for beam interference coordination among the multi-core processors.

[0071] The process of sensing user access status in the spatial resource allocation units managed by each multi-core processor and obtaining user density in adjacent spatial resource allocation units between multi-core processors specifically involves:

[0072] The spatial resource allocation units are initialized. Based on the satellite coverage area, the spatial resource allocation units responsible for each multi-core processor are divided, such as wave positions, and the adjacency of spatial resource allocation units between multi-core processors (such as the adjacency of wave positions) is determined.

[0073] Define an interference avoidance period, such as 1 second or longer, depending on the specific business scenario. Within each interference avoidance period, count the proportion of users in adjacent spatial resource partitioning units of multi-core processors.

[0074] Based on the user density of adjacent spatial resource partitioning units among multi-core processors, corresponding scheduling time slots are allocated to each multi-core processor within a preset interference avoidance period, and multiple multi-core processors are notified. The multi-core processors then perform scheduling based on the scheduling time slots, specifically as follows:

[0075] Based on the user ratio, a corresponding proportion of scheduling time slots is provided for the adjacent spatial resource partitioning units of each multi-core processor. The allocated scheduling time slots of adjacent wavelengths are notified to each multi-core processor through the message interface. Within the notification period, the multi-core processor schedules the adjacent spatial resource partitioning units according to the scheduling time slots notified by the scheduling controller.

[0076] In this step, the allocation ratio of scheduling time slots is consistent with the user ratio of adjacent spatial resource partitioning units.

[0077] Therefore, the interference avoidance steps of the scheduling controller, through hierarchical decision-making, dynamic adaptation, and lightweight collaboration, avoid interference between adjacent spatial resource partitioning units between multi-core processors. This not only solves the computing power and flexibility problems of traditional centralized architecture, but also provides stable upper-level constraints for interference avoidance within the underlying chip, and is the core support of the entire hierarchical dynamic collaboration system.

[0078] See Figure 4 The flowchart illustrates the internal interference avoidance steps performed by a multi-core processor.

[0079] The aforementioned settings for information sharing and transmission between threads in the Media Access Control (MAC) layer of a multi-core processor, as well as the scheduling lead time for multiple scheduling threads, ensure that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread executes sequentially according to a preset order, obtaining the scheduling results of the preceding thread. Specifically:

[0080] The information sharing and transmission method between threads in the Media Access Control (MAC) layer of a multi-core processor is set, and the scheduling lead of multiple scheduling threads is set so that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread is executed in a preset order, and each thread can obtain the scheduling result of the preceding thread at the corresponding scheduling time.

[0081] The scheduling lead setting should ensure that multiple threads are aligned to the same physical moment of scheduling.

[0082] The filtering priority avoids interference from spatial resource allocation units, performs interference avoidance, and completes scheduling, specifically as follows:

[0083] Extract the priority of spatial resource partitioning units (e.g., wave positions), sort them as scheduling priorities, and share the sorting results among scheduling threads;

[0084] Scheduling begins according to the sorting results. If the spatial resource partitioning unit has already been scheduled or is subject to interference, it will not be scheduled until the next interference-free spatial resource partitioning unit (e.g., wave position) is reached, at which point scheduling and avoidance will begin. The scheduling results will be shared for use in avoiding interference in the next thread scheduling.

[0085] The interference between the spatial resource partitioning units is that adjacent spatial resource partitioning units have already been scheduled in the preceding thread.

[0086] Therefore, this step utilizes pipelined scheduling, with results shared among threads. Subsequent threads can directly obtain the scheduling results of preceding threads, accurately identifying occupied beam positions and adjacent interfering beam positions, thus avoiding conflicts at the source. By proactively sensing interference, interference avoidance shifts from "passive response" to "active prediction," significantly reducing the probability of beam collisions within the chip.

[0087] Furthermore, this invention also discloses an on-board interference avoidance device based on hierarchical dynamic coordination, comprising: a scheduling controller and at least two multi-core processors.

[0088] The scheduling controller can communicate with each multi-core processor module;

[0089] The scheduling controller is used to sense the user access status of the spatial resource allocation unit responsible for each multi-core processor, obtain the user density of adjacent spatial resource allocation units between multi-core processors, allocate corresponding scheduling time slots to each multi-core processor within a preset interference avoidance period based on the user density of adjacent spatial resource allocation units between multi-core processors, and notify the corresponding multi-core processor.

[0090] The multi-core processor module is used to set the information sharing and transmission between threads of the Media Access Control (MAC) layer within the multi-core processor, as well as the scheduling lead of multiple scheduling threads, so that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread executes in a preset order, obtains the scheduling results of the preceding thread, filters priorities, avoids interference from the space resource partitioning units within the multi-core processor, performs interference avoidance, and completes the scheduling.

[0091] Specifically, the scheduling controller initializes the spatial resource allocation units, divides the spatial resource allocation units responsible for each multi-core processor according to the satellite coverage area, such as wave positions, and determines the adjacency of spatial resource allocation units between multi-core processors (such as the adjacency of wave positions).

[0092] Define the interference avoidance period, such as 1 second or longer, depending on the specific business scenario. Within each interference avoidance period, count the proportion of users in adjacent spatial resource partitioning units of multi-core processors.

[0093] Based on the user ratio, a corresponding proportion of scheduling time slots is provided for adjacent spatial resource partitioning units between each multi-core processor. The allocated scheduling time slots for adjacent wavelengths are notified to each multi-core processor through a message interface. Within the notification period, the multi-core processor schedules adjacent spatial resource partitioning units according to the scheduling time slots notified by the scheduling controller.

[0094] The allocation ratio of scheduling time slots is consistent with the user ratio of adjacent spatial resource allocation units.

[0095] The multi-core processor sets the information sharing and transmission mode between threads of the Media Access Control (MAC) layer, and sets the scheduling advance of multiple scheduling threads so that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread is executed in a preset order, and each thread can obtain the scheduling result of the preceding thread at the corresponding scheduling time.

[0096] Extract the priority of spatial resource partitioning units (e.g., wave positions), sort them as scheduling priorities, and share the sorting results among scheduling threads;

[0097] Scheduling begins according to the sorting results. If the spatial resource partitioning unit has already been scheduled or is subject to interference, it will not be scheduled until the next interference-free spatial resource partitioning unit (e.g., wave position) is reached, at which point scheduling and avoidance will begin. The scheduling results will be shared for use in avoiding interference in the next thread scheduling.

[0098] The spatial resource allocation unit can be a beam position or a narrow beam. Those skilled in the art will understand that a beam position or a narrow beam essentially represents the directional coverage area generated by a low-Earth orbit satellite phased array antenna.

[0099] Information sharing between threads is achieved through shared memory, but this invention is not limited to this; message queues, pipes, global variables, and other methods can also be used for information sharing between threads.

[0100] In summary, the present invention has the following advantages:

[0101] 1. Layered collaborative architecture to resolve the inherent contradictions of centralized decision-making:

[0102] This invention pioneers a two-tier dynamic collaborative architecture of "system-multi-core processor," decoupling the centralized decision-making traditionally undertaken by a single node into macro-level coordination by a high-level scheduling controller and micro-level execution by a low-level chip scheduler. The high-level controller focuses only on coordinating interference between adjacent spatial resource allocation units among multi-core processors, without needing to intervene in fine-grained scheduling within the chip. This significantly reduces the computational complexity of a single decision point, completely overcoming the demand conflicts inherent in traditional centralized architectures, while also avoiding the explosive growth in computational load caused by a surge in beam size.

[0103] 2. Streamline scheduling + real-time result sharing enables accurate prediction and efficient avoidance of interference:

[0104] By employing a pipelined scheduling and real-time sharing strategy of decision results at the MAC layer within the multi-core processor, subsequent threads can proactively and with low latency acquire the scheduling results of preceding threads, accurately identify occupied beam positions and adjacent interfering beam positions, and achieve "early detection and proactive avoidance" of interference. This design not only solves the beam conflict problem caused by traditional thread isolation scheduling, but also retains the high efficiency of multi-threaded parallel processing through the logic of "staggered start + alignment at the same physical moment," without additional synchronization overhead, thus meeting the real-time requirements of on-board scheduling.

[0105] 3. Inter-thread coordination mechanism to improve on-chip scheduling flexibility and response speed:

[0106] By leveraging inter-thread information sharing and scheduling interference identification mechanisms, threads within a multi-core processor can dynamically adapt to instantaneous interference changes within the chip. When a sudden increase in users or temporary interference occurs at a certain wave position, the local thread can adjust its scheduling strategy directly based on previous results without relying on upper-layer instructions, quickly selecting a conflict-free wave position. This significantly improves scheduling flexibility and interference response speed, perfectly adapting to the dynamic nature of business operations and the randomness of interference.

[0107] 4. The architecture is scalable and easy to implement, adapting to future evolution needs:

[0108] The layered design strategy transforms static interference planning into two-level dynamic sensing and scheduling, giving the system extremely strong flexibility and scalability. The distributed architecture supports beam size expansion by adding processing units, and upper and lower layer modules can be upgraded independently, adapting to future network evolution and algorithm optimization without overall reconstruction. At the same time, this invention is implemented through software-level logical design, eliminating the need for additional hardware modules, reducing the integration cost and implementation difficulty of on-board equipment, and improving engineering practicality.

[0109] Obviously, those skilled in the art will understand that the various units or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device, or alternatively, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by the computing device. Alternatively, they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0110] The above description is a further detailed explanation of the present invention in conjunction with specific preferred embodiments. It should not be considered that the specific embodiments of the present invention are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all such deductions or substitutions should be considered to fall within the scope of protection of the present invention as defined by the submitted claims.

Claims

1. A hierarchical dynamic cooperative on-board interference avoidance method, applied to a low-Earth orbit satellite multi-beam co-frequency communication system, the communication system comprising a scheduling controller and at least two multi-core processors, wherein the scheduling controller is communicatively connected to each multi-core processor, the method comprising: Scheduling controller avoidance steps: The system senses the user access status of the spatial resource allocation units responsible for each multi-core processor and obtains the user density of adjacent spatial resource allocation units between multi-core processors. Based on the user density of adjacent spatial resource partitioning units among the multi-core processors, a corresponding scheduling time slot is allocated to each multi-core processor within a preset interference avoidance period, and the multiple multi-core processors are notified. The multi-core processors then perform scheduling based on the scheduling time slots. Multi-core processors perform internal interference avoidance steps: The system sets up information sharing and transmission between threads in the Media Access Control (MAC) layer of a multi-core processor, as well as scheduling lead time for multiple scheduling threads. This ensures that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread executes sequentially according to a preset order, obtains the scheduling results of the preceding thread, filters priorities, avoids interference from the space resource partitioning units within the multi-core processor, performs interference avoidance, and completes scheduling.

2. The on-board interference avoidance method according to claim 1, characterized in that: The process of sensing user access status in the spatial resource allocation units managed by each multi-core processor and obtaining user density in adjacent spatial resource allocation units between multi-core processors includes: The space resource allocation units are initialized. Based on the satellite coverage area, the space resource allocation units responsible for each multi-core processor are divided, and the adjacency of the space resource allocation units between the multi-core processors is determined. Define an interference avoidance period and, within each interference avoidance period, count the proportion of users in adjacent spatial resource partitioning units of multi-core processors.

3. The on-board interference avoidance method according to claim 2, characterized in that: Based on the user density of adjacent spatial resource partitioning units among the multi-core processors, the system allocates corresponding scheduling time slots to each multi-core processor within a preset interference avoidance period, and notifies multiple multi-core processors. The multi-core processors then perform scheduling based on the scheduling time slots, including: Based on the user ratio, a corresponding proportion of scheduling time slots is provided for adjacent spatial resource partitioning units between each multi-core processor. The allocated scheduling time slots for adjacent wavelengths are notified to each multi-core processor through a message interface. Within the notification period, the multi-core processor schedules adjacent spatial resource partitioning units according to the scheduling time slots notified by the scheduling controller.

4. The on-board interference avoidance method according to claim 3, characterized in that: The avoidance period can be determined based on specific business scenarios; and / or, The allocation ratio of the scheduling time slots is consistent with the user ratio of adjacent spatial resource allocation units.

5. The on-board interference avoidance method according to claim 1, characterized in that: The configuration of information sharing and transmission between threads in the Media Access Control (MAC) layer of the multi-core processor, and the scheduling lead time of the multi-scheduled threads, ensures that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduled thread executes sequentially according to a preset order, obtaining the scheduling results of the preceding thread, including: The information sharing and transmission method between threads in the Media Access Control (MAC) layer of a multi-core processor is set, and the scheduling lead of multiple scheduling threads is set so that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread is executed in a preset order, and each thread can obtain the scheduling result of the preceding thread at the corresponding scheduling time.

6. The on-board interference avoidance method according to claim 5, characterized in that: The filtering priority avoids interference from the space resource allocation units within the multi-core processor, performs interference avoidance, and completes scheduling, including: Extract the priority of the spatial resource partitioning units, sort them as scheduling priorities, and share the sorting results among scheduling threads; Scheduling begins according to the sorting results. If the spatial resource partitioning unit has already been scheduled or is subject to interference, it will not be scheduled until the next interference-free spatial resource partitioning unit is reached. Scheduling and avoidance will then begin, and the scheduling results will be shared for use in avoiding interference in the next thread scheduling.

7. The on-board interference avoidance method according to claim 6, characterized in that: The scheduling lead should be set so that multiple threads are aligned to the same physical time of scheduling; and / or, The interference of the spatial resource partitioning unit is that the spatial resource partitioning unit has already been scheduled in the preceding thread.

8. The on-board interference avoidance method according to any one of claims 1-7, characterized in that: The spatial resource allocation unit is a wave position or a narrow beam.

9. The on-board interference avoidance method according to any one of claims 1-7, characterized in that: Information sharing and transmission between threads can be achieved through shared memory, message queues, pipes, or global variables.

10. An on-board interference avoidance device based on hierarchical dynamic coordination, comprising: A scheduling controller and at least two multi-core processors, wherein the scheduling controller is communicatively connected to each multi-core processor module, characterized in that: The scheduling controller is used to sense the user access status of the spatial resource allocation unit responsible for each multi-core processor, obtain the user density of adjacent spatial resource allocation units between multi-core processors, allocate corresponding scheduling time slots to each multi-core processor within a preset interference avoidance period based on the user density of adjacent spatial resource allocation units between multi-core processors, and notify the corresponding multi-core processor. The multi-core processor module is used to set the information sharing and transmission between threads of the Media Access Control (MAC) layer within the multi-core processor, as well as the scheduling lead of multiple scheduling threads, so that different times of adjacent threads on the pipeline correspond to the same scheduling time. Each scheduling thread executes in a preset order, obtains the scheduling results of the preceding thread, filters priorities, avoids interference from the space resource partitioning units within the multi-core processor, performs interference avoidance, and completes the scheduling.

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