Integrated well tap cell design to address power supply noise reduction by using decap diffusion length transistors

Abstract

The present disclosure provides an integrated circuit device and associated methods of manufacture and operation having a standard well tap cell disposed over a semiconductor substrate having first and second regions, where the standard well tap cell includes a first tie-rod transistor disposed between a first plurality of LOD protection transistors in the first region, and a second tie-rod transistor disposed between a second plurality of LOD protection transistors in the second region. And a second tie bar transistor disposed between a second plurality of LOD protection transistors in the second region, wherein the first plurality of LOD protection transistors and the second plurality of LOD protection transistors include a first transistor connected as a first decoupling capacitor between a first voltage source and a second voltage source, a second transistor connected as a second decoupling capacitor between the first voltage source and the second voltage source, and a plurality of further dummy transistors, each having a gate, a source, and a drain terminal commonly connected to the supply voltage.

Description

Technical Field

[0001] This disclosure is generally directed to integrated circuits (ICs). In one aspect, this disclosure generally relates to an improved trap tap cell design for integrated circuits. Background Technology

[0002] Integrated circuit designs typically include numerous well tap cells uniformly distributed across a large number of gate regions to provide well and substrate bias, where the spacing and distribution of the well tap cells depend on the manufacturing technology node. At sub-nanometer technology nodes, IC designs apply the diffusion length (LOD) rule, which defines the minimum distance from the edge of the shallow trench isolation (STI) oxide layer to the n-channel or p-channel of the FET device. The reason for the LOD rule is that the STI region generates mechanical stress in the substrate region of diffusion discontinuity, and these stresses can negatively impact device performance and the functionality of functional transistors placed too close to the discontinuous diffusion edge. To meet the LOD rule in FinFET technology nodes (e.g., 16nm, 5nm), IC designers typically include a number of dummy transistors within the well tap cells, ensuring that all functional transistors within the well tap cell have uniform performance and functionality. However, including dummy transistors presents significant design challenges and trade-offs because they increase the size of the well tap cells, consuming considerable space in the design. As can be seen from the foregoing, existing solutions for preventing the effects of mechanical stress that could negatively impact the device performance of functional transistors in the well tap unit are extremely difficult to implement in practice due to the difficulty in balancing cost, complexity, and circuit area requirements. Summary of the Invention

[0003] An integrated circuit device having a compact standard well tap cell and associated operation and manufacturing methods are provided. The integrated circuit device includes a semiconductor substrate having a first region doped with a first type of dopant and a second region doped with a second type of dopant different from the first type of dopant. In a selected embodiment, the first type of dopant is n-type and the second type of dopant is p-type. In the disclosed standard well tap cell, a first tie transistor is disposed between a first plurality of diffusion length (LOD) protection transistors in the first region of the semiconductor substrate. Additionally, a second tie transistor is disposed between a second plurality of LOD protection transistors in the second region of the semiconductor substrate. The disclosed first and second plurality of LOD protection transistors include a first transistor connected as a first decoupling capacitor between a first voltage source and a second voltage source. Additionally, the disclosed first and second plurality of LOD protection transistors include a second transistor connected as a second decoupling capacitor between the first voltage source and the second voltage source. The disclosed first and second plurality of LOD protection transistors also include a plurality of additional dummy transistors, each additional dummy transistor having a gate, source, and drain terminals commonly connected to the first and second voltage sources. In selected embodiments, the first and second tie transistors, the first plurality of LOD protection transistors, and the second plurality of LOD protection transistors are each formed as FinFET devices. In these embodiments, the first tie transistor may be embodied as a first FinFET device, comprising (1) a body well region formed in a first region of a semiconductor substrate, and (2) shorted gate, source, and drain regions connected to a first power supply voltage. Alternatively, the second tie transistor may be embodied as a second FinFET device, comprising (1) a body well region formed in a second region of a semiconductor substrate, and (2) shorted gate, source, and drain regions connected to a second power supply voltage. Alternatively, the first transistor may be embodied as a first decap FinFET device, comprising (1) a gate connected to one of the first or second power supply voltages, and (2) shorted source and drain regions connected to the other of the first or second power supply voltages. Additionally, the plurality of additional dummy transistors may include a first dummy FinFET device having a shorted gate, source, and drain region connected to either the first or second power supply voltage. In a selected embodiment, the first tie transistor may be embodied as an n-FinFET formed in a first region of the semiconductor substrate, the second tie transistor may be embodied as a p-FinFET formed in a second region of the semiconductor substrate, the first transistor connected as a first decoupling capacitor may be embodied as a p-FinFET formed in the first region of the semiconductor substrate, and the second transistor connected as a second decoupling capacitor may be embodied as an n-FinFET formed in the second region of the semiconductor substrate.In addition, each of the plurality of additional dummy transistors may be embodied as a p-FinFET formed in a first region of the semiconductor substrate or an n-FinFET formed in a second region of the semiconductor substrate.

[0004] In another form, an integrated circuit device and a method of manufacturing and operating are provided, wherein a plurality of standard well tap units are connected to a first power supply voltage and a second power supply voltage. As disclosed, each standard well tap unit has a set of layout characteristics including first and second semiconductor substrate regions extending across the standard well tap unit, wherein the first semiconductor substrate region is doped with a first type of dopant, wherein the second semiconductor substrate region is doped with a second type of dopant different from the first type of dopant, and wherein the first and second semiconductor substrate regions are formed adjacent to each other in a semiconductor substrate. The layout characteristics also include a first tie transistor disposed between a first plurality of diffusion length (LOD) protection transistors in the first semiconductor substrate region, wherein the first tie transistor has a gate, source, and drain terminals commonly connected to the first power supply voltage. In a selected embodiment, the first tie transistor is a FinFET device comprising (1) an n-type body well region formed in the first semiconductor substrate region of the semiconductor substrate, and (2) shorted gate, source, and drain regions connected to the first power supply voltage. Additionally, the layout features include a second tie transistor disposed between a second plurality of LOD protection transistors in a second semiconductor substrate region, wherein the second tie transistor has a gate, source, and drain terminals commonly connected to a second power supply voltage. In a selected embodiment, the second tie transistor is a FinFET device comprising (1) a p-type body well region formed in a second semiconductor region of the semiconductor substrate, and (2) a shorted gate, source, and drain region connected to the second power supply voltage. In a selected embodiment, the first tie transistor is an n-well tie transistor located in a central segment of a first semiconductor substrate region, the first semiconductor substrate region being an n-well region connected to the first power supply voltage via the n-well tie transistor, and the second tie transistor is a p-well tie transistor located in a central segment of a second semiconductor substrate region, the second semiconductor substrate region being a p-well region connected to the second power supply voltage via the p-well tie transistor. In the disclosed layout features, the first plurality of LOD protection transistors and the second plurality of LOD protection transistors collectively include at least one decap transistor connected as a decoupling capacitor between the first power supply voltage and the second power supply voltage, and further include a plurality of additional dummy transistors, each of which has a gate, source, and drain terminals commonly connected to the first power supply voltage or the second power supply voltage. In a selected embodiment, the at least one decap transistor is a FinFET device comprising (1) a body well region formed in a first or second semiconductor substrate region of a semiconductor substrate, (2) shorted source and drain regions connected to one of the first or second power supply voltages, and (3) a gate connected to the other of the first or second power supply voltages.In selected embodiments, each of the first tether transistor, the second tether transistor, the first plurality of LOD protection transistors, and the second plurality of LOD protection transistors may be a FinFET device formed in a first semiconductor substrate region or a second semiconductor substrate region of the semiconductor substrate. In selected embodiments, the first plurality of LOD protection transistors and the second plurality of LOD protection transistors collectively include at least two decap transistors connected as decoupling capacitors between the first power supply voltage and the second power supply voltage. In selected embodiments, the first tether transistor is an n-FinFET formed in a first semiconductor substrate region of the semiconductor substrate, the second tether transistor is a p-FinFET formed in a second semiconductor substrate region of the semiconductor substrate, and the at least one decap transistor connected as a decoupling capacitor is a p-FinFET formed in a first semiconductor substrate region of the semiconductor substrate and / or an n-FinFET formed in a second semiconductor substrate region of the semiconductor substrate. Additionally, each of the plurality of additional dummy transistors may be a p-FinFET formed in a first semiconductor substrate region of the semiconductor substrate or an n-FinFET formed in a second semiconductor substrate region of the semiconductor substrate.

[0005] In another embodiment, an integrated circuit device and a method of manufacturing and operating the same are provided. The manufacturing method includes receiving a standard well tap cell design for a well tap circuit used to connect a first power supply voltage to an n-type semiconductor substrate region and a p-type semiconductor substrate region, respectively. Furthermore, the manufacturing method includes forming the standard well tap cell design into an integrated circuit having a set of layout characteristics using a sequence of manufacturing steps. As formed, the layout characteristics include an n-well link located in the n-type semiconductor substrate region for connecting the n-type semiconductor substrate region to the first power supply voltage. The layout characteristics also include a first plurality of diffusion length (LOD) protection transistors located in the n-type semiconductor substrate region to protect the n-well link. Furthermore, the layout characteristics include a p-well link located in the p-type semiconductor substrate region for connecting the p-type semiconductor substrate region to the second power supply voltage. The layout characteristics also include a second plurality of LOD protection transistors located in the p-type semiconductor substrate region to protect the p-well link. As formed, the first plurality of LOD protection transistors and the second plurality of LOD protection transistors collectively include (1) at least one decap transistor connected as a decoupling capacitor between the first power supply voltage and the second power supply voltage, and (2) a plurality of additional dummy transistors, wherein each additional dummy transistor has a gate, source, and drain terminals commonly connected to the first power supply voltage or the second power supply voltage. In one embodiment, three decap transistors and one dummy transistor may be included. And in another embodiment, one decap transistor and three dummy transistors may be included. In a selected embodiment, the sequence of manufacturing steps for forming a standard well tap cell design includes obtaining a semiconductor substrate and selectively implanting the semiconductor substrate to form n-type semiconductor substrate regions and p-type semiconductor substrate regions adjacent to each other. The sequence of manufacturing steps also includes selectively forming a plurality of semiconductor fins extending upward from the n-type semiconductor substrate regions and the p-type semiconductor substrate regions on the semiconductor substrate. As formed, the plurality of semiconductor fins includes P+-doped semiconductor fins formed over an n-type semiconductor substrate region in one or more defined diffusion length (LOD) protection regions; N+-doped semiconductor fins formed over an n-type semiconductor substrate region in one or more defined n-tap regions; N+-doped semiconductor fins formed over a p-type semiconductor substrate region in one or more defined LOD protection regions; and P+-doped semiconductor fins formed over a p-type semiconductor substrate region in one or more defined p-tap regions. Additionally, the sequence of manufacturing steps includes selectively forming one or more gate electrodes aligned perpendicularly to the plurality of semiconductor fins to define a first plurality of LOD protection transistors in the n-type semiconductor substrate region and a second plurality of LOD protection transistors in the p-type semiconductor substrate region.Finally, the sequence of manufacturing steps includes selectively forming one or more metal interconnect layers over a semiconductor substrate to connect the first plurality of LOD protection transistors and the second plurality of LOD protection transistors to form (1) at least one decap FinFET device connected between the first voltage source and the second voltage source as a first decoupling capacitor, and (2) a plurality of additional dummy FinFET devices, wherein each additional dummy FinFET device has a gate, source and drain terminals commonly connected to the first voltage source or the second voltage source. Attached Figure Description

[0006] The invention can be understood and its many objectives, features and advantages can be obtained when the following detailed description of preferred embodiments is considered in conjunction with the following figures.

[0007] Figure 1 This is a simplified planar diagram of the layout structure of a conventional well tap unit design. The conventional well tap unit design uses a dummy polymer on oxide diffusion edge (PODE) transistor layout pattern to overcome diffusion length (LOD) regularity errors.

[0008] Figure 2 It is along Figure 1 The simplified cross-sectional view of a conventional well tap unit design, shown by the cross-sectional path, illustrates the electrical connections of the well tap transistor and the dummy PODE transistor that form the conventional well tap unit.

[0009] Figure 3 This is a simplified plan view of the layout structure of a first CMOS well tap unit designed according to a selected embodiment of the present disclosure, wherein the first CMOS well tap unit is designed to employ a pair of decap coupled transistors in the first layout structure.

[0010] Figure 4 It is along Figure 3 The simplified cross-sectional view of the first CMOS well tap unit design, taken from the cross-sectional path shown, illustrates the electrical connection between the well tap transistor and the decap coupling transistor forming the first CMOS well tap unit.

[0011] Figure 5 This is a simplified plan view of the layout structure of a second CMOS well tap unit designed according to a selected embodiment of the present disclosure, wherein the second CMOS well tap unit is designed in a second layout structure using a pair of decap coupled transistors.

[0012] Figure 6 It is along Figure 5The simplified cross-sectional view of the second CMOS well tap unit design, taken from the cross-sectional path shown, illustrates the electrical connection between the well tap transistor and the decap coupling transistor forming the second CMOS well tap unit.

[0013] Figure 7 This is a simplified plan view of the layout structure of a third PMOS well tap unit designed according to a selected embodiment of the present disclosure, wherein the third PMOS well tap unit design employs a pair of decap coupled transistors in a third layout structure.

[0014] Figure 8 It is along Figure 7 The simplified cross-sectional view of the third PMOS well tap unit design, taken from the cross-sectional path shown, illustrates the electrical connection between the well tap transistor and the decap coupling transistor that form the third PMOS well tap unit.

[0015] Figure 9 This is a simplified plan view of the layout structure of a fourth NMOS well tap unit designed according to a selected embodiment of the present disclosure, wherein the fourth NMOS well tap unit design employs a pair of decap coupled transistors in a fourth layout structure.

[0016] Figure 10 It is along Figure 9 The simplified cross-sectional view of the fourth NMOS well tap unit design, taken from the cross-sectional path shown, illustrates the electrical connection between the well tap transistor and the decap coupling transistor forming the fourth NMOS well tap unit.

[0017] Figure 11 This is a simplified plan view of the layout structure of a fifth CMOS well tap unit designed according to a selected embodiment of the present disclosure, wherein the fifth CMOS well tap unit is designed to employ a pair of decap coupled transistors in a fifth layout structure.

[0018] Figure 12 It is along Figure 11 The simplified cross-sectional view of the fifth CMOS well tap unit design, taken from the cross-sectional path shown, illustrates the electrical connection between the well tap transistor and the decap coupling transistor forming the fifth CMOS well tap unit.

[0019] Figure 13 This is a simplified plan view of the layout structure of the sixth CMOS well tap unit designed according to a selected embodiment of the present disclosure, wherein the sixth CMOS well tap unit is designed in a sixth layout structure using a pair of decap coupled transistors.

[0020] Figure 14 It is along Figure 13The simplified cross-sectional view of the sixth CMOS well tap unit design, taken from the cross-sectional path shown, illustrates the electrical connection between the well tap transistor and the decap coupling transistor forming the sixth CMOS well tap unit.

[0021] Figure 15 A perspective view depicting an n-well tap cell with a decap-coupled PMOS FinFET and a dummy PMOS FinFET formed on opposite sides of a centrally positioned n-well tie rod according to a selected embodiment of the present disclosure.

[0022] Figure 16 A perspective view depicting a p-well tap cell, according to a selected embodiment of the present disclosure, having a decap-coupled NMOS FinFET and a dummy NMOS FinFET formed on opposite sides of a centrally located p-well tie rod.

[0023] Figure 17 A flowchart illustrating a method for manufacturing an integrated circuit with a standard well tap cell design according to a selected embodiment of the present disclosure is shown.

[0024] It should be understood that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are exaggerated relative to other elements for the purpose of promoting and improving clarity and understanding. In addition, where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding or similar elements. Detailed Implementation

[0025] A compact standard well tap cell and associated operation and fabrication methods are described for conforming to diffusion length (LOD) design rules by forming a decoupling capacitor (decap) structure using “dummy” n-FinFET and p-FinFET devices. This decoupling capacitor structure is seamlessly integrated within the standard IC well tap cell to protect the n-well and p-well taps. In selected embodiments, an integrated circuit structure is proposed that is compatible with the area footprint of existing well tap cells by converting dummy LOD transistors into decap structures. These decap structures mitigate power supply noise and voltage drop (or IR) issues that become increasingly prominent as lower technology nodes and circuits operate at high frequencies (in the GHz range). To address these dynamic IR issues, the decap structure in each well tap cell acts as a local current source connected between the supply voltage and ground voltage to reduce IR drops between different supply voltages without requiring any wiring overhead resources or silicon area or SoC design methods. Furthermore, by uniformly distributing well tap cells with incorporated decap-coupled dummy transistors on the SoC region, the power grid performance of the SoC is improved without increasing the chip area required for the well tap cells. While selected embodiments of this disclosure are described below with reference to various well tap cell configurations including two decap-coupled dummy transistors in each well tap cell, it should be understood that, according to this disclosure, additional or fewer decap-coupled dummy transistors may be included in each well tap cell, provided that at least one decap-coupled dummy transistor is included in each well tap cell.

[0026] As those skilled in the art will understand, standard design cells are used to design integrated circuits. These standard design cells are generated by system designers using commercially available design tools such as electronic design automation (EDA) and computer-aided design (CAD) tools to integrate different electrical and / or logic functions into an integrated circuit (IC). In the context of this disclosure, a standard well tap cell design may include multiple transistor devices (e.g., complementary FinFETs) for implementing electrical well tapping functions for electrically connecting an n-well to a supply voltage VDD and for connecting a p-well or substrate to a ground voltage VSS. However, a standard well tap cell design may also include additional dummy PODE transistors, along with other transistors, to implement logic functions such as Boolean functions (e.g., AND, OR, NOT, and buffers), storage functions (e.g., flip-flops and latches), and digital combination functions (e.g., multiplexers and demultiplexers). With each standard cell having a predetermined geometry (width and height), the design tools include a library (referred to as a standard cell library) that stores the standard cell definitions selected and placed in rows and columns for these logic functions. After placement is complete, the semiconductor device design is simulated, verified, and then transferred to a chip (i.e., formed in silicon).

[0027] To provide a contextual understanding of this disclosure, reference is now made to Figure 1 , Figure 1 A simplified planar view of a single-row standard cell integrated circuit layout structure for a conventional well tap cell design is shown. Figure 1 The design employs a dummy on-oxide diffusion edge polymer (PODE) transistor layout pattern 11, in which dummy FinFETs 14, 16, 17, 19 are positioned on opposite sides of centrally located n-well and p-well taps 15, 18. The depicted dummy PODE transistor layout pattern 11 includes multiple transistor devices (e.g., complementary FinFETs) 15, 18 for implementing n-well and p-well taps for connecting the supply voltage VDD and ground voltage VSS to the n-well 12 and p-well 13, respectively. Furthermore, the dummy PODE transistor layout pattern 11 includes multiple dummy FinFETs 14 / 16, 17 / 19 positioned on either side of the centrally located n-well and p-well tap FinFETs 15, 18 to overcome diffusion length (LOD) regularity errors. As will be understood, the layout features depicted in the dummy PODE transistor layout pattern 11 do not include each element of the final device (e.g., gate layer or metal interconnect), but rather show the relative positions and placement of dummy and well tap-connected FinFETs 14-19, where P+FinFETs 14, 16 and N+FinFETs 17, 19 are positioned as dummy transistors to protect the N+FinFET 15 and P+FinFET 18, which form the centrally located p-well and n-well taps, from STI stress effects, respectively.

[0028] In the example of the conventional trap tap unit design described, Figure 3 The diagram shows two parallel rows of FinFET devices 34-36 and 37-39; however, it should be understood that additional rows of fins can be formed. Furthermore, design rules will require active region gaps between adjacent FinFET devices and between individual FinFET devices and the peripheral edges of the n-well or p-well regions, but the arrangement, number, and placement of these gaps can vary based on LOD design compliance requirements. Within the depicted conventional well tap cell design, the FinFET gate electrode layer (G) is formed to extend vertically across the cell to overlap with the n-well and p-well fins formed between the P+ and N+ source / drain (S / D) regions, thereby forming dummy p-FinFETs 14, 16 (in n-well region 12) and dummy n-FinFETs 17, 19 (in p-well region 13). These FinFET gate electrode layers are typically placed above the standard cell region in a regular pattern and with constant spacing, and can also be used to electrically isolate the functional FinFET or block from the dummy FinFET if both the functional FinFET or block and the dummy FinFET reside in the same active region. FinFET devices 34-39 can be connected by forming additional metal interconnect layers (not shown) to provide the circuitry required for the well tap cell design. Specifically, the required circuitry for the well tap cell design includes at least a first pair of dummy FinFETs 14 / 16 on opposite sides of the centrally located n-well tap FinFET 15 and a second pair of dummy FinFETs 17 / 19 on opposite sides of the centrally located p-well tap FinFET 18. As will be understood, a dummy device is formed by wiring one or more metal interconnect layers to short the gate, source, and drain terminals of the dummy FinFET 14 / 16 to the power supply voltage VDD and to individually short the gate, source, and drain terminals of the dummy FinFET 17 / 19 to the ground voltage VSS.

[0029] To explain the formation Figure 1 The electrical connections of the LOD-protected well tap transistors 15 and 18 and the dummy PODE transistors 14, 16, 17, and 19 in the conventional well tap unit shown are now referenced. Figure 2 , Figure 2 Depicting along Figure 1 The cross-sectional path shown (indicated as 10) is a simplified cross-section of the dummy PODE transistor layout pattern 21 of a conventional well tap cell design. Figure 2As depicted, the n-well tap FinFET 15 formed above the n-well 12 includes an n-type fin structure extending upward from the n-well 12, sandwiched between the N+ source / drain regions, and controlled by FinFET gate (G) structures formed on the top and sides of the n-type fin structure, wherein the FinFET gate structure includes one or more polysilicon or metal layers formed above the gate dielectric or insulating layer. Additionally, each of the depicted dummy PODE transistors 14, 16 formed above the n-well 12 includes an n-type fin structure extending upward from the n-well 12, sandwiched between the P+ source / drain regions, and controlled by FinFET gate (G) structures formed on the top and sides of the n-type fin structure. As depicted, each of the dummy PODE transistors 14, 16 and the n-well tap FinFET 15 have a power supply voltage VDD connected to the shorted gate, source, and drain regions. In this manner, one or more N+FinFETs 15 form an n-well tap for coupling the n-well region 12 to the first power supply voltage VDD. Additionally, the pair of N+FinFETs 14, 16 form dummy PODE transistors 14, 16, each of which acts as a FinFET dummy device connected between the n-well region 12 and the first power supply voltage VDD.

[0030] Similarly, the p-well tap FinFET 18 formed above p-well 13 includes a p-type fin structure extending upward from p-well 13, sandwiched between the P+ source / drain regions, and controlled by FinFET gate (G) structures formed on the top and sides of the p-type fin structure, wherein the FinFET gate structure includes one or more polysilicon or metal layers formed above the gate dielectric or insulating layer. Furthermore, each of the depicted dummy PODE transistors 17, 19 formed above p-well 13 includes a p-type fin structure extending upward from p-well 13, sandwiched between the N+ source / drain regions, and controlled by FinFET gate (G) structures formed on the top and sides of the p-type fin structure. As depicted, each of the dummy PODE transistors 17, 19 and the p-well tap FinFET 18 has a ground voltage VSS connected to the shorted gate, source, and drain regions. In this manner, one or more P+FinFETs 18 form a p-well tap for coupling the p-well 13 to the second ground voltage VSS. Additionally, the pair of P+FinFETs 17, 19 form dummy PODE transistors 17, 19, each of which acts as a FinFET dummy device connected between the p-well region 13 and the second ground voltage VSS.

[0031] As those skilled in the art will understand, the dummy PODE transistors 14, 16, 17, and 19 are included and positioned to effectively absorb any non-uniform STI stress from outside the conventional well tap cell, such that the FinFET channel regions of the n-well tap FinFET 15 and the p-well tap FinFET 18 will experience uniform STI stress. However, as design technology nodes shrink, more and more other electrical effects arise that affect device performance. For example, there are power supply noise and voltage drop (or IR) issues, which become increasingly prominent as lower technology nodes and circuits operate at high frequencies (in the GHz range).

[0032] To address these drawbacks and shortcomings, as well as other drawbacks and shortcomings from conventional well tap solutions, this paper discloses a compact standard well tap cell design in which several pairs of selected dummy PODE transistor devices are converted into or replaced by decap structures that are seamlessly integrated within a standard IC well tap cell to protect n-well and p-well taps while improving IR performance without requiring wiring resources or increased silicon area. In selected embodiments, each decap structure is implemented using a MOSFET dummy device, wherein the source and drain regions are shorted together to form a first decap plate connected to a first reference voltage, and wherein the gate terminal forms a second decap plate connected to a second reference voltage, thereby providing additional decapacitance between the reference voltages. Such decap structure devices can be placed within a standard cell array, thus providing a significant area benefit compared to using conventional diodes, which would disrupt the alternating well pattern of the standard cell region and would be difficult to integrate.

[0033] To better understand selected embodiments of this disclosure, reference is now made to Figure 3 , Figure 3 A simplified planar view of a single-row standard cell integrated circuit layout structure with a first CMOS decap well tap cell design 31 is depicted. Figure 3The first CMOS decap well tap design 31 employs a pair of decap coupled transistors 34 and 39 and a pair of dummy FinFETs 36 and 37, which are positioned to protect the centrally positioned n-well and p-well taps 35 and 38 from LOD rule errors, while also adding decoupling capacitance between power and ground to help mitigate IR drop issues. The depicted first CMOS decap well tap design 31 includes multiple transistor devices (e.g., complementary FinFETs) 35 and 38 for implementing n-well and p-well taps for connecting the power supply voltage VDD and ground voltage VSS to the n-well 32 and p-well 33, respectively. Furthermore, the first CMOS decap well tap design 31 includes a first decap coupled transistor 34 and a first dummy PODE transistor 36, which are placed on either side of the centrally positioned n-well tap FinFET 35 to protect the N+ FinFET 35. The first CMOS decap tap cell design 31 also includes a second dummy PODE transistor 37 and a second decap coupling transistor 39, which are placed on either side of the centrally positioned p-well tap FinFET 38 to protect the P+FinFET 38.

[0034] To explain Figure 3 The electrical connections of the LOD-protected well tap transistors 35 and 38 in the first CMOS decap tap cell design 31 shown are now referred to. Figure 4 , Figure 4 Depicting along Figure 3 The simplified cross-section of the first CMOS decap well tap cell design 41, shown as a cross-sectional path (indicated by 30), is captured. Figure 4 Aside from electrical connections to the power supply voltage and ground voltage, FinFET 34-39 can be structurally integrated with... Figures 1-2The FinFETs 14-19 shown are identical. As depicted, each of the dummy PODE transistor 36 and the n-well tap-FinFET 35 formed in the n-well region 32 has a power supply voltage VDD connected to the shorted gate, source, and drain regions. Similarly, each of the dummy PODE transistor 37 and the p-well tap-FinFET 38 formed in the p-well region 33 has a ground voltage VSS connected to the shorted gate, source, and drain regions. However, in the case of forming an additional metal interconnect layer 42, the decap-coupled transistor 34 is connected in an open-gate configuration, where the P+ source / drain regions are shorted together and connected to the power supply voltage VDD, and where the gate electrode is connected to the ground voltage VSS, thereby making the decap-coupled transistor 34 act as a "decoupling capacitor" (e.g., by shunting or "decoupling" a specific frequency of a signal to ground). Furthermore, with the formation of an additional metal interconnect layer 43, the decap-coupled transistor 39 is also connected in an open-gate configuration, wherein the N+ source / drain regions are shorted together and connected to the ground voltage VSS, and wherein the gate electrode is connected to the power supply voltage VDD, thereby enabling the decap-coupled transistor 39 to act as a "decoupling capacitor".

[0035] like Figures 3-4 As depicted, the P+ and N+ decap coupled transistors 34 and 39 of the first CMOS decap tap cell design 41 are located in LODE protected areas at opposite ends of the cross-sectional path 30 passing through the n-well region 32 and the p-well region 33. In the n-well region 32, the P+ decap coupled transistor 34 and the dummy PODE transistor 36 combine to protect the n-well tap FinFET 35. Additionally, the N+ decap coupled transistor 39 and the dummy PODE transistor 37 formed in the p-well region 33 combine to protect the p-well tap FinFET 38. The performance and / or functional benefits of positioning the decap coupled transistors 34 and 39 at opposite ends of the cross-sectional path 30 passing through the n-well region 32 and the p-well region 33 include, but are not limited to, providing additional capacitance.

[0036] To better understand selected embodiments of this disclosure, reference is now made to Figure 5 , Figure 5 A simplified planar view of a single-row standard cell integrated circuit layout structure with a second CMOS decap well tap cell design 51 is depicted. Figure 5The second CMOS decap well tap design 51 employs a pair of decap-coupled transistors 56 and 57 and a pair of dummy FinFETs 54 and 59, which are positioned to protect the centrally located n-well and p-well taps 55 and 58 from LOD rule errors, while also adding decoupling capacitance between power and ground to help mitigate IR drop issues. The depicted second CMOS decap well tap design 51 includes multiple transistor devices (e.g., complementary FinFETs) 55 and 58 for implementing n-well and p-well taps for connecting the power supply voltage VDD and ground voltage VSS to the n-well 52 and p-well 53, respectively. Additionally, the second CMOS decap well tap design 51 includes a first dummy PODE transistor 54 and a first decap-coupled transistor 56 placed on either side of the centrally located n-well tap FinFET 55. The second CMOS decap well tap design 51 also includes a second decap-coupled transistor 57 and a second dummy PODE transistor 59 placed on either side of the centrally located p-well tap FinFET 58.

[0037] To explain Figure 5 The electrical connections of LOD protected well tap transistors 55 and 58 in the second CMOS decap tap cell design 51 shown are now referred to. Figure 6 , Figure 6 Depicting along Figure 5 The simplified cross-section of the second CMOS decap well tap cell design 61, shown as a cross-sectional path (indicated as 50), is captured. Figure 6 Aside from electrical connections to the power supply voltage and ground voltage, FinFETs 56-57 can be structurally integrated with... Figures 1-2 The FinFETs 16-17 shown are identical. As depicted, each of the dummy PODE transistor 56 and the n-well tap-connected FinFET 55 formed in the n-well region 52 has a power supply voltage VDD connected to the shorted gate, source, and drain regions. Similarly, each of the dummy PODE transistor 59 and the p-well tap-connected FinFET 58 formed in the p-well region 53 has a ground voltage VSS connected to the shorted gate, source, and drain regions. However, with the additional metal interconnect layer 62 formed, the decap-coupled transistor 56 is connected in an open-gate configuration, where the P+ source / drain regions are shorted together and connected to the power supply voltage VDD, and where the gate electrode is connected to the ground voltage VSS. Additionally, with the additional metal interconnect layer 63 formed, the decap-coupled transistor 57 is also connected in an open-gate configuration, where the N+ source / drain regions are shorted together and connected to the ground voltage VSS, and where the gate electrode is connected to the power supply voltage VDD.

[0038] like Figures 5-6 As depicted, the P+ and N+ decap coupled transistors 56 and 57 of the second CMOS decap tap cell design 61 are located in adjacent LODE protected areas along a cross-sectional path 50 passing through the n-well region 52 and the p-well region 53. In the n-well region 52, a dummy PODE transistor 54 and a P+ decap coupled transistor 56 combine to protect the n-well tap FinFET 55. Additionally, an N+ decap coupled transistor 57 and a dummy PODE transistor 59 formed in the p-well region 53 combine to protect the p-well tap FinFET 58. The performance and / or functional benefits of positioning the decap coupled transistors 56 and 57 along the cross-sectional path 50 passing through the n-well region 52 and the p-well region 53 in adjacent LODE protected areas include, but are not limited to, increased capacitance.

[0039] To better understand selected embodiments of this disclosure, reference is now made to Figure 7 , Figure 7 A simplified planar view of a single-row standard cell integrated circuit layout structure with a third PMOS decap well tap cell design 71 is depicted. Figure 7 The third PMOS decap well tap design 71 employs a pair of decap-coupled transistors 74, 76 and a pair of dummy FinFETs 77, 79, which are positioned to protect the centrally located n-well and p-well taps 75, 78 from LOD rule errors, while also adding decoupling capacitance between power and ground to help mitigate IR drop issues. The depicted third PMOS decap well tap design 71 includes multiple transistor devices (e.g., complementary FinFETs) 75, 78 for implementing n-well and p-well taps for connecting the power supply voltage VDD and ground voltage VSS to the n-well 72 and p-well 73, respectively. Additionally, the third PMOS decap well tap design 71 includes a first decap-coupled transistor 74 and a second decap-coupled transistor 76 placed on either side of the centrally located n-well tap FinFET 75. The third PMOS decap tap unit design 71 also includes a first dummy PODE transistor 77 and a second dummy PODE transistor 79 placed on either side of the centrally positioned p-well tap FinFET 78.

[0040] To explain Figure 7 The electrical connections of the LOD-protected well tap transistors 75 and 78 in the third PMOS decap well tap cell design 71 shown are now referred to. Figure 8 , Figure 8 Depicting along Figure 7 The simplified cross-section of the third PMOS decap well tap cell design 71, shown as 70, is captured by the cross-sectional path (shown as 70). Figure 8Aside from electrical connections to the power supply voltage and ground voltage, FinFET 74-76 can be structurally integrated with... Figures 1-2 The FinFETs 14-16 shown are identical. As depicted, the n-well tap-FinFET 75, formed in the n-well region 72, has a power supply voltage VDD connected to the shorted gate, source, and drain regions. Similarly, each of the first and second dummy PODE transistors 77, 79 and the p-well tap-FinFET 78, formed in the p-well region 73, has a ground voltage VSS connected to the shorted gate, source, and drain regions. However, with the additional metal interconnect layers 82, 83 formed, the first and second decap-coupled transistors 74, 76 are each connected in an open-gate configuration, wherein the P+ source / drain regions are shorted together and connected to the power supply voltage VDD, and wherein the gate electrode is connected to the ground voltage VSS.

[0041] like Figures 7-8 As depicted, the P+ decap coupled transistors 74 and 76 of the third PMOS decap tap cell design 71 are located within the LODE protection zone of the n-well region 72 to protect the n-well tap FinFET 75. Additionally, N+ dummy PODE transistors 77 and 79, formed in the p-well region 73, are combined to protect the p-well tap FinFET 78. The performance and / or functional benefits of positioning the decap coupled transistors 74 and 76 within the LODE protection zone of the n-well region 72 include, but are not limited to, reduced current leakage and increased decoupling capacitance.

[0042] To better understand selected embodiments of this disclosure, reference is now made to Figure 9 , Figure 9 A simplified planar view of a single-row standard cell integrated circuit layout structure with a fourth NMOS decap well tap cell design 91 is depicted. Figure 9The fourth NMOS decap well tap design 91 employs a pair of dummy FinFETs 94, 96 and a pair of decap coupled transistors 97, 99, which are positioned to protect the centrally located n-well and p-well taps 95, 98 from LOD rule errors, while also adding decoupling capacitance between power and ground to help mitigate IR drop issues. The depicted fourth NMOS decap well tap design 91 includes multiple transistor devices (e.g., complementary FinFETs) 95, 98 for implementing n-well and p-well taps for connecting the power supply voltage VDD and ground voltage VSS to the n-well 92 and p-well 93, respectively. Additionally, the fourth NMOS decap well tap design 91 includes a first dummy PODE transistor 94 and a second dummy PODE transistor 96 placed on either side of the centrally located n-well tap FinFET 95. The fourth NMOS decap tap unit design 91 also includes a first decap coupling transistor 97 and a second decap coupling transistor 99 placed on either side of the centrally positioned p-well tap FinFET 98.

[0043] To explain Figure 9 The electrical connections of the LOD-protected well tap transistors 95 and 98 in the fourth NMOS decap tap cell design 91 shown are now referenced. Figure 10 , Figure 10 Depicting along Figure 9 The simplified cross-section of the fourth NMOS decap well tap cell design 91, shown by the cross-sectional path (indicated as 90°). Figure 10 Aside from electrical connections to the power supply voltage and ground voltage, FinFET 97-99 can be structurally integrated with... Figures 1-2 The FinFETs 17-19 shown are identical. As depicted, each of the first dummy PODE transistor 94 and the second dummy PODE transistor 96 and the n-well tap-FinFET 95 formed in the n-well region 92 has a power supply voltage VDD connected to the shorted gate, source, and drain regions. Similarly, the p-well tap-FinFET 98 formed in the p-well region 93 has a ground voltage VSS connected to the shorted gate, source, and drain regions. However, in the case of forming additional metal interconnect layers 102, 103, the first and second decap-coupled transistors 97, 99 are each connected in an open-gate configuration, wherein the N+ source / drain regions are shorted together and connected to the ground voltage VSS, and wherein the gate electrode is connected to the power supply voltage VDD.

[0044] like Figures 9-10As depicted, the N+ decap coupled transistors 97 and 99 of the fourth NMOS decap tap unit design 91 are located in the LODE protection zone of the p-well region 93 to protect the p-well tap FinFET 98. Additionally, P+ dummy PODE transistors 94 and 96 are combined and formed in the n-well region 92 to protect the n-well tap FinFET 95. The performance and / or functional benefits of positioning the decap coupled transistors 97 and 99 in the LODE protection zone of the p-well region 93 include, but are not limited to, increased capacitance.

[0045] To better understand selected embodiments of this disclosure, reference is now made to Figure 11 , Figure 11 A simplified planar view of a single-row standard cell integrated circuit layout structure with a fifth CMOS decap well tap cell design 111 is depicted. Figure 11 The fifth CMOS decap well tap design 111 employs a pair of decap-coupled transistors 114, 117 and a pair of dummy FinFETs 116, 119, which are positioned to protect the centrally located n-well and p-well taps 115, 118 from LOD rule errors, while also adding decoupling capacitance between power and ground to help mitigate IR drop issues. The depicted fifth CMOS decap well tap design 111 includes multiple transistor devices (e.g., complementary FinFETs) 115, 118 for implementing n-well and p-well taps for connecting the power supply voltage VDD and ground voltage VSS to the n-well 112 and p-well 113, respectively. Additionally, the fifth CMOS decap well tap design 111 includes a first decap-coupled transistor 114 and a first dummy PODE transistor 116 placed on either side of the centrally located n-well tap FinFET 115. The fifth CMOS decap tap unit design 111 also includes a second decap coupling transistor 117 and a second dummy PODE transistor 119 placed on either side of the centrally positioned p-well tap FinFET 118.

[0046] To explain Figure 11 The electrical connections of the LOD-protected well tap transistors 115 and 118 in the fifth CMOS decap well tap cell design 111 shown are now referred to. Figure 12 , Figure 12 Depicting along Figure 11 The simplified cross-section of the fifth CMOS decap well tap cell design 111, shown by the cross-sectional path (indicated as 110). Figure 12 Aside from electrical connections to the power supply voltage and ground voltage, the FinFET 114-117 can be structurally integrated with... Figures 1-2The FinFETs 14-17 shown are identical. As depicted, each of the dummy PODE transistor 116 and the n-well tap-FinFET 115 formed in the n-well region 112 has a power supply voltage VDD connected to the shorted gate, source, and drain regions. Similarly, each of the dummy PODE transistor 119 and the p-well tap-FinFET 118 formed in the p-well region 113 has a ground voltage VSS connected to the shorted gate, source, and drain regions. However, with the additional metal interconnect layer 122 formed, the decap-coupled transistor 114 is connected in an open-gate configuration, where the P+ source / drain regions are shorted together and connected to the power supply voltage VDD, and where the gate electrode is connected to the ground voltage VSS. Additionally, with the additional metal interconnect layer 123 formed, the decap-coupled transistor 117 is also connected in an open-gate configuration, where the N+ source / drain regions are shorted together and connected to the ground voltage VSS, and where the gate electrode is connected to the power supply voltage VDD.

[0047] like Figures 11-12 As depicted, the P+ and N+ decap coupled transistors 114, 117 of the fifth CMOS decap tap cell design 111 are located in alternating LODE protected areas along a cross-sectional path 110 passing through the n-well region 112 and the p-well region 113. In the n-well region 112, the P+ decap coupled transistor 114 and the dummy PODE transistor 116 combine to protect the n-well tap FinFET 115. Additionally, the N+ decap coupled transistor 117 and the dummy PODE transistor 119 formed in the p-well region 113 combine to protect the p-well tap FinFET 118. The performance and / or functional benefits of positioning the decap coupled transistors 114, 117 in alternating LODE protected areas along the cross-sectional path 110 passing through the n-well region 112 and the p-well region 113 include, but are not limited to, increased capacitance.

[0048] To better understand selected embodiments of this disclosure, reference is now made to Figure 13 , Figure 13 A simplified planar view of a single-row standard cell integrated circuit layout structure with a sixth CMOS decap well tap cell design 131 is depicted. Figure 13The sixth CMOS decap well tap design 131 employs a pair of decap-coupled transistors 136, 139 and a pair of dummy FinFETs 134, 137, which are positioned to protect the centrally located n-well and p-well taps 135, 138 from LOD rule errors, while also adding decoupling capacitance between power and ground to help mitigate IR drop issues. The depicted sixth CMOS decap well tap design 131 includes multiple transistor devices (e.g., complementary FinFETs) 135, 138 for implementing n-well and p-well taps for connecting the power supply voltage VDD and ground voltage VSS to the n-well 132 and p-well 133, respectively. Additionally, the sixth CMOS decap well tap design 131 includes a first dummy PODE transistor 134 and a first decap-coupled transistor 136 placed on either side of the centrally located n-well tap FinFET 135. The sixth CMOS decap tap unit design 131 also includes a second dummy PODE transistor 137 and a second decap coupling transistor 139 placed on either side of the centrally positioned p-well tap FinFET 138.

[0049] To explain Figure 13 The electrical connections of the LOD-protected well tap transistors 135 and 138 of the sixth CMOS decap tap cell design 131 shown are now referenced. Figure 14 , Figure 14 Depicting along Figure 13 The simplified cross-section of the sixth CMOS decap well tap cell design 141, shown by the cross-sectional path (indicated as 130), is a cut-off line. Figure 14 Aside from electrical connections to the power supply voltage and ground voltage, FinFET 136-139 can be structurally integrated with... Figures 1-2The FinFETs 16-19 shown are identical. As depicted, each of the dummy PODE transistor 134 and the n-well tap-FinFET 135 formed in the n-well region 132 has a power supply voltage VDD connected to the shorted gate, source, and drain regions. Similarly, each of the dummy PODE transistor 137 and the p-well tap-FinFET 138 formed in the p-well region 133 has a ground voltage VSS connected to the shorted gate, source, and drain regions. However, with the additional metal interconnect layer 142 formed, the decap-coupled transistor 136 is connected in an open-gate configuration, where the P+ source / drain regions are shorted together and connected to the power supply voltage VDD, and where the gate electrode is connected to the ground voltage VSS. Additionally, with the additional metal interconnect layer 143 formed, the decap-coupled transistor 139 is also connected in an open-gate configuration, where the N+ source / drain regions are shorted together and connected to the ground voltage VSS, and where the gate electrode is connected to the power supply voltage VDD.

[0050] like Figures 13-14 As depicted, the P+ and N+ decap coupled transistors 136 and 139 of the sixth CMOS decap tap cell design 131 are located in the rightmost LODE protected area of ​​the n-well region 132 and the p-well region 133. In the n-well region 132, the P+ decap coupled transistor 136 and the dummy PODE transistor 134 combine to protect the n-well tap FinFET 135. Additionally, the N+ decap coupled transistor 139 and the dummy PODE transistor 137 formed in the p-well region 133 combine to protect the p-well tap FinFET 138. The performance and / or functional benefits of positioning the decap coupled transistors 136 and 139 in the rightmost LODE protected area along the cross-sectional path 130 through the n-well region 132 and the p-well region 133 include, but are not limited to, higher capacitance per unit area.

[0051] As disclosed herein, the specific placement and spacing of the decap-coupled transistors and well tap transistors in the n-well and p-well regions of a standard well tap cell will depend on the design layout constraints required by the specific cell layout requirements. However, in general, any adjacent rows of N+ decap-coupled transistors (or P+ decap-coupled transistors) should be aligned for connection to form a decoupling capacitor between the ground voltage and the supply voltage. Additionally, the n-well and p-well tap transistors can be located in non-overlapping positions, allowing individual gate electrodes to provide the required reference / supply voltage to each n-well and p-well tap transistor.

[0052] To better understand selected embodiments of this disclosure, reference is now made to Figure 15 , Figure 15A perspective view of an n-well tap unit 15 is depicted, which includes a plurality of N+ / n-well tie-in FinFETs 159 having a plurality of decap-coupled PMOS FinFETs 158A and a plurality of dummy PMOS FinFETs 158B formed in a p-type substrate 151, corresponding to the reference above. Figures 3-4 The configuration connection of the n-well tap in the first CMOS tap cell design is described. Specifically, the plurality of decap-coupled PMOS FinFETs 158A and the plurality of dummy PMOS FinFETs 158B are located on opposite sides of a plurality of centrally positioned N+ / n-well tie-in FinFETs 159.

[0053] The depicted plurality of decap-coupled PMOS FinFETs 158A include a plurality of parallel P+ source / drain regions 154A, 154B formed on a plurality of parallel n-type fin structures aligned in the x-direction to extend upward (in the z-direction) from a lower n-well region 152 formed in a p-substrate 151. As formed, the plurality of parallel P+ source / drain regions 154A, 154B extend over a shallow trench isolation (STI) layer 156 such that they are separated by the STI layer 156 in both the x and y directions. The depicted plurality of decap-coupled PMOS FinFETs 158A also includes one or more metal gate electrode layers 157A that extend vertically in the y-direction to overlap with the plurality of parallel n-type fin structures, thereby forming the P+ fin source / drain regions 154A, 154B. To complete the multiple decap-coupled PMOS FinFETs 158A, one or more source / drain contact / metal / interconnect layers (not shown) can be formed to electrically connect the P+ source / drain regions 154A, 154B to the power supply voltage VDD. Additionally, one or more gate contact / metal / interconnect layers (not shown) can be formed to electrically connect the metal gate electrode layer 157A to the ground voltage VSS. When the P+ source / drain regions 154A, 154B are connected together to form a first decoupling capacitor plate electrically connected to the power supply voltage VDD, and when a second decoupling capacitor plate electrically connected to the ground voltage VSS is formed at the gate electrode, a decoupling capacitor is formed between the ground voltage and the power supply voltage.

[0054] The depicted multiple dummy PMOS FinFETs 158B can be formed on opposite ends of the n-well 152 with the same structure including a metal gate electrode 157D and multiple parallel P+ source / drain regions 154E, 154F. However, the metal gate electrode 157D and the multiple parallel P+ source / drain regions 154E, 154F are all shorted together and connected to a common power supply voltage VDD to form a PFET dummy device. Specifically, one or more source / drain / gate contacts / metal / interconnect layers (not shown) can be formed to electrically connect the P+ source / drain regions 154E, 154F and the metal gate electrode layer 157D to the power supply voltage VDD. Thus, a PFET dummy device is formed having a first end (formed in the n-well region 152) and a second end (formed by the shorted gate 157D and multiple parallel P+ source / drain regions 154E, 154F).

[0055] Between the plurality of decap-coupled PMOS FinFETs 158A and the plurality of dummy PMOS FinFETs 158B, the plurality of N+ / n-well bonded FinFETs 159 can be formed using the same basic structure, but are connected in a different manner via metal interconnect layers. Specifically, the depicted plurality of N+ / n-well bonded FinFETs 159 have a plurality of parallel N+ source / drain regions 154C, 154D, which are aligned in the x-direction to extend upward from the underlying n-well region 152 and protrude over the shallow trench isolation (STI) layer 156, such that they are separated by the STI layer 156 in both the x and y directions. The depicted plurality of N+ / n-well bonded FinFETs 159 may also include one or more metal gate electrode layers 157B, which extend vertically in the y-direction to overlap with the plurality of parallel N+ source / drain regions 154C, 154D. By completing the plurality of N+ / n-well tethered FinFETs 159, one or more source / drain contact layers (not shown) can be formed to electrically connect the N+ source / drain regions 154C, 154D and the metal gate electrode layer 157B to the power supply voltage VDD.

[0056] To better understand selected embodiments of this disclosure, reference is now made to Figure 16 , Figure 16 A perspective view of a p-well tap unit 16 is depicted, which includes a plurality of P+ / p-well tie-in FinFETs 161 having a plurality of dummy NMOS FinFETs 160A and a plurality of decap-coupled NMOS FinFETs 160B formed in a p-type substrate 151, corresponding to the reference above. Figures 3-4The configuration connection of the p-well tap in the first CMOS well tap unit design is described. Specifically, the plurality of dummy NMOS FinFETs 160A and the plurality of decap-coupled NMOS FinFETs 160B are located on opposite sides of a plurality of centrally positioned P+ / P-well tie FinFETs 161.

[0057] As depicted, the plurality of dummy NMOS FinFETs 160A include a plurality of parallel N+ source / drain regions 155A, 155B formed on a plurality of parallel p-type fin structures aligned in the x-direction to extend upward (in the z-direction) from an underlying p-well region 153 formed in a p-substrate 151. As formed, the plurality of parallel N+ source / drain regions 155A, 155B extend over an STI layer 156 such that they are separated by the STI layer 156 in both the x and y directions. The depicted plurality of dummy NMOS FinFETs 160A also includes one or more metal gate electrode layers 157A that extend vertically in the y-direction to overlap with the plurality of parallel p-type fin structures, thereby forming the N+ fin source / drain regions 155A, 155B. To complete the plurality of dummy NMOS FinFETs 160A, one or more source / drain / gate contacts / metal / interconnect layers (not shown) can be formed to electrically connect the N+ source / drain regions 155A, 155B and the metal gate electrode layer 157A to the ground voltage VSS to form an NFET dummy device. The NFET dummy device has a first end (formed in the p-well region 153) and a second end (formed by a shorted gate 157A and a plurality of parallel N+ source / drain regions 155A, 155B).

[0058] The depicted multiple decap-coupled NMOS FinFETs 160B can be formed on opposite ends of the p-well 153 with the same structure including a metal gate electrode 157D and multiple parallel N+ source / drain regions 155E, 155F. However, the metal gate electrode 157D and the multiple parallel N+ source / drain regions 155E, 155F are individually connected to different reference voltages to form decoupling capacitors. Specifically, one or more source / drain contact / metal / interconnect layers (not shown) can be formed to electrically connect the N+ source / drain regions 155E, 155F to the ground voltage VSS. Additionally, one or more gate contact / metal / interconnect layers (not shown) can be formed to electrically connect the metal gate electrode layer 157D to the power supply voltage VDD. In the case where the N+ source / drain regions 155E and 155F are connected together to form a first decoupling capacitor plate electrically connected to the ground voltage VSS, and in the case where the gate electrode 157D forms a second decoupling capacitor plate electrically connected to the power supply voltage VDD, a decoupling capacitor is formed between the ground voltage and the power supply voltage.

[0059] And although Figure 15 and Figure 16 The markings on the metal gate electrode layers 157A and 157D indicate that these may be part of the same gate electrode layer extending above both the n-well tap unit 15 and the p-well tap unit 16, but this is not required in every embodiment. For example, a separate gate electrode layer may be used for the plurality of decap-coupled PMOS FinFETs 158A and the plurality of dummy NMOS FinFETs 160A. Similarly, a separate gate electrode layer may be used for the plurality of dummy NMOS FinFETs 158B and the plurality of decap-coupled NMOS FinFETs 160B.

[0060] Between the plurality of dummy NMOS FinFETs 160A and the plurality of decap-coupled NMOS FinFETs 160B, the plurality of P+ / p-well tie-in FinFETs 161 can be formed using the same basic structure, but connected in a different manner via metal interconnect layers. Specifically, the depicted plurality of P+ / p-well tie-in FinFETs 161 form a plurality of parallel P+ source / drain regions 155C, 155D, which are aligned in the x-direction to extend upward from the underlying p-well region 153 and protrude above the STI layer 156, such that they are separated by the STI layer 156 in both the x and y directions. The depicted plurality of P+ / p-well tie-in FinFETs 161 may also include one or more metal gate electrode layers 157C, which extend vertically in the y-direction to overlap with the plurality of parallel P+ source / drain regions 155C, 155D. By completing the plurality of P+ / p-well tie-in FinFETs 161, one or more source / drain contact layers (not shown) can be formed to electrically connect the P+ source / drain regions 155C, 155D and the metal gate electrode layer 157C to the ground voltage VSS.

[0061] As will be understood, the embodiments disclosed herein are not limited to specific materials used for gate electrodes, resistors, or metal interconnect layers. For example, the gate electrode may be formed over a gate dielectric or insulating layer formed of a high-k dielectric material, such as hafnium-based oxides, hafnium-based oxynitrides, or hafnium-silicon oxynitrides, hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide.

[0062] To further illustrate selected embodiments of this disclosure, reference is now made to... Figure 17 , Figure 17 This is a simplified schematic flowchart 200 illustrating various methods for manufacturing integrated circuits with a standard well tap cell design. In describing manufacturing method 200, the description is intended only to facilitate understanding of various exemplary embodiments and not to be limiting. Unless otherwise indicated, the identified processing steps 201-206 can be implemented using one or more individual manufacturing steps, including but not limited to deposition, growth, masking, development, exposure, patterning, implantation, doping, etching, cleaning, stripping, annealing, and / or polishing performed in any desired order. Figure 17 The steps shown and described below are provided by way of example only, and it should be understood that alternative embodiments of manufacturing method 200 may include additional steps, omit certain steps, substitute or modify certain steps, or be adapted to... Figure 17 The order shown may differ from the order in which certain steps are performed.

[0063] Once the manufacturing process begins (step 201), a standard cell design for the well tap circuit is received. In a selected embodiment, the standard cell design includes LOD-protected n-well tap FinFET links and p-well tap FinFET links, and a plurality of decoupling capacitor-connected FinFETs and a plurality of dummy FinFETs positioned to protect one or more of the n-well and p-well tap FinFET links. According to a selected embodiment, the protective distribution of the decoupling capacitor-connected FinFETs and dummy FinFETs may include one or more decoupling capacitor-connected FinFETs located adjacent to the protected n-well tap FinFET link or p-well tap FinFET link.

[0064] At step 203, a semiconductor substrate is provided or obtained. For example, a semiconductor wafer structure may be provided having a semiconductor substrate structure with a predetermined crystal orientation and thickness (e.g., approximately 0.6 mm for a FinFET technology node). Depending on the type of transistor device being manufactured, the semiconductor substrate structure may be implemented as a bulk silicon substrate, single-crystal silicon (doped or undoped), epitaxial semiconductor material, SOI substrate, or any semiconductor material, including, for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, and other group III-V compound semiconductors or any combination thereof, and may optionally be formed as a bulk processed wafer. As will be understood, the semiconductor substrate structure may be appropriately doped to provide n-type (electron) or p-type (hole) carriers.

[0065] At step 204, a sequence of steps is used to design and fabricate a standard cell in the semiconductor substrate into an integrated circuit having a set of defined layout characteristics, including n-well and p-well regions that can be adjacent to each other and extend across the standard cell. The layout characteristics may also specify that the n-well and p-well regions include LOD-protected n-well and p-well tap-finFET links, centrally positioned and protected by FinFETs and dummy FinFETs connected by decoupling capacitors. In selected embodiments, the n-well tap-finFET link is located in the central segment of the n-well region for connecting the n-well to a first supply voltage (e.g., VDD), and the p-well tap-finFET link is located in the central segment of the p-well region for connecting the p-well to a second supply voltage (e.g., VSS). The layout characteristics also include dummy FinFET layout regions located on one or both sides of the LOD-protected n-well or p-well tap-finFET link. As formed, the dummy FinFET layout region may include one or more p-FinFETs formed in an n-well region and connected as a first dummy device, with their gate, source, and drain regions shorted to a first power supply voltage. Alternatively, the dummy FinFET layout region may include one or more n-FinFETs formed in a p-well region and connected as a second dummy device, with their gate, source, and drain regions shorted to a second power supply voltage. Furthermore, the layout characteristics also include decap FinFET layout regions located on one or both sides of the LOD-protected n-well or p-well tapped FinFET tie. As formed, the decap FinFET layout region may include one or more p-FinFETs formed in an n-well region, with their gates connected to the second power supply voltage and their shorted source and drain regions connected to the first power supply voltage. Alternatively, the decap FinFET layout region may include one or more n-finFETs formed in a p-well region, with their gates connected to the first power supply voltage and their shorted source and drain regions connected to the second power supply voltage.

[0066] When manufacturing standard cells, the sequence of manufacturing steps may include selectively implanting n-well and p-well regions into a single row of standard cell regions on a semiconductor substrate. Additionally, the manufacturing steps may include selectively forming a plurality of semiconductor fins extending upward from the n-well and p-well regions on the semiconductor substrate. Furthermore, the plurality of semiconductor fins may be selectively implanted to form P+-doped source / drain regions over n-well regions in one or more defined P+ active regions of a dummy FinFET layout region (and / or a decap FinFET layout region), N+-doped source / drain regions over n-well regions in a tap region, N+-doped source / drain regions over p-well regions in one or more defined N+ active regions of a dummy FinFET layout region (and / or a decap FinFET layout region), and P+-doped source / drain regions over p-well regions in a tap region. As will be understood, the manufacturing steps may be formed using a combination of epitaxial semiconductor growth and / or selective etching processes. Non-limiting examples of epitaxial growth include ultra-high vacuum chemical vapor deposition (UHV-CVD) at low temperatures (e.g., about 550°C) and / or low-pressure chemical vapor deposition (LP-CVD) at higher temperatures (e.g., about 900°C), as well as other means known in this art. Additionally, the fabrication steps may include selectively forming one or more FinFET gate electrodes, said one or more FinFET gate electrodes being aligned perpendicularly to the plurality of semiconductor fins to define desired p-FinFET and n-FinFET devices in a dummy FinFET layout region and / or a decap FinFET layout region. Finally, the fabrication steps may include selectively forming one or more metal interconnect layers over a substrate to connect p-FinFET and n-FinFET devices in the dummy FinFET layout region, connecting p-FinFET and n-FinFET devices in the decap FinFET layout region as decoupling capacitors, connecting semiconductor fins formed over an n-well region to a first power supply voltage, and connecting semiconductor fins formed over a p-well region to a second power supply voltage.

[0067] At step 205, implantation and back-end processing are performed, and then the manufacturing method ends at step 206. This back-end processing may include applying thermal treatment to the implanted region at some point in the manufacturing sequence to activate the implanted region and otherwise repair implantation damage. Additionally, other circuit features may be formed on a wafer structure (e.g., a transistor device) using one or more of sacrificial oxide formation, stripping, isolation region formation, well region formation, gate dielectric and electrode formation, extension implant, halo implant, spacer formation, source / drain implant, thermally driven or annealed steps, and polishing steps, as well as conventional back-end processing (not depicted). This conventional back-end processing typically includes forming multiple levels of interconnects for connecting transistors in a desired manner to achieve desired functionality. Therefore, the specific sequence of steps used to complete the fabrication of a semiconductor structure can vary depending on process and / or design requirements.

[0068] Therefore, manufacturing method 200 provides an overall process flow sequence for fabricating a standard cell design for a trap tap circuit. It should be understood that certain steps in process flow sequence 200 may be performed in parallel with each other or in parallel with other processes. Furthermore, a specific ordering of process flow sequence 200 may be modified to achieve substantially the same result. Therefore, such modifications are intended to be included within the scope of the subject matter of this invention.

[0069] While the exemplary embodiments described herein relate to well tap cell designs and methods using "dummy" FinFETs connected in combination with decap FinFETs between a supply voltage and a ground voltage, the invention is not necessarily limited to exemplary embodiments illustrating aspects of the invention applicable to a wide variety of circuit designs and operations. For example, this disclosure depicts various well tap cell configurations having a pair of decap-coupled dummy transistors at different locations in each well tap cell, but may include additional or fewer decap-coupled dummy transistors in each well tap cell, provided that at least one decap-coupled dummy transistor is included in each well tap cell. Therefore, the specific embodiments disclosed above are merely illustrative and should not be considered as limiting the invention, as the invention can be modified and practiced in different but equivalent ways, which will be apparent to those skilled in the art who benefit from the teachings herein. Therefore, the identification of circuit designs and layout configurations provided herein is merely illustrative and not limiting, and other circuit arrangements may be used to provide well tap cell functionality with an area-efficient standard cell design. Therefore, the above description is not intended to limit the invention to the specific forms stated, but rather is intended to cover such alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art will understand that various changes, substitutions and alterations may be made without departing from the spirit and scope of the most extensive form of the invention.

[0070] The foregoing only illustrates the principles of certain examples. Therefore, it should be understood that those skilled in the art will be able to design various arrangements, which, while not explicitly described or shown herein, embody the principles and are included within their spirit and scope. Furthermore, all examples and conditional language cited herein are explicitly intended for pedagogical purposes only to aid the reader in understanding the principles and concepts contributed by the inventors to advance the field, and should be understood as not being limited to such specifically cited examples and conditions. Moreover, all statements in this document regarding principles, aspects, and embodiments, as well as their specific examples, are intended to cover both structural and functional equivalents. Furthermore, such equivalents are intended to include both currently known equivalents and those developed in the future, i.e., any element developed that performs the same function, regardless of structure.

[0071] This description of exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are considered part of the entire written description. In this specification, unless otherwise expressly stated, relative terms such as “connection” and “interconnection” with respect to attachment, coupling, etc., refer to a relationship in which structures are directly or indirectly fixed or attached to each other, either directly or indirectly via intermediate structures, and to movable or rigid attachments or relationships.

[0072] The benefits, other advantages, and solutions to the problem have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to the problem, and any elements that may cause any benefit, advantage, or solution to appear or become more apparent should not be construed as essential, necessary, or fundamental features or elements of any or all claims. As used herein, the term "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. An integrated circuit device, characterized in that, The standard well tap unit includes a standard well tapping unit disposed above a semiconductor substrate, the semiconductor substrate comprising a first region doped with a first type of dopant and a second region doped with a second type of dopant different from the first type of dopant, the standard well tapping unit comprising: A first tie transistor is disposed between a first plurality of diffusion length LOD protection transistors in the first region of the semiconductor substrate; and A second tie transistor is disposed between a second plurality of LOD protection transistors in the second region of the semiconductor substrate; The first plurality of LOD protection transistors and the second plurality of LOD protection transistors together include: The first transistor, which acts as a first decoupling capacitor, is connected between the first voltage source and the second voltage source. The second transistor, which acts as a second decoupling capacitor, is connected between the first voltage source and the second voltage source. Multiple additional dummy transistors, each having a gate, source, and drain terminal connected to a first power supply voltage or a second power supply voltage.

2. The integrated circuit device according to claim 1, characterized in that, The first and second tie transistors, the first plurality of LOD protection transistors, and the second plurality of LOD protection transistors each form a FinFET device.

3. The integrated circuit device according to claim 1, characterized in that... The first tie transistor includes an n-FinFET formed in the first region of the semiconductor substrate. The second tie transistor includes a p-FinFET formed in the second region of the semiconductor substrate. The first transistor connected as a first decoupling capacitor includes a p-FinFET formed in the first region of the semiconductor substrate, and The second transistor, connected as a second decoupling capacitor, includes an n-FinFET formed in the second region of the semiconductor substrate.

4. An integrated circuit device, characterized in that, This includes multiple standard well tap units connected to a first power supply voltage and a second power supply voltage. Each standard well tap unit has a set of layout characteristics, which include: First and second semiconductor substrate regions extending across the standard well tap unit, wherein the first semiconductor substrate region is doped with a first type of dopant, wherein the second semiconductor substrate region is doped with a second type of dopant different from the first type of dopant, and wherein the first and second semiconductor substrate regions are formed adjacent to each other in the semiconductor substrate. A first tie transistor is disposed among a plurality of first diffusion length LOD protection transistors in the first semiconductor substrate region, wherein the first tie transistor has a gate, source, and drain terminals commonly connected to the first power supply voltage; and A second tie transistor is disposed among a second plurality of LOD protection transistors in the second semiconductor substrate region, wherein the second tie transistor has a gate, source and drain terminals that are commonly connected to the second power supply voltage; The first plurality of LOD protection transistors and the second plurality of LOD protection transistors together include: At least one decap transistor is connected as a decoupling capacitor between the first power supply voltage and the second power supply voltage, and Multiple additional dummy transistors, each of which has a gate, source, and drain terminals commonly connected to the first power supply voltage or the second power supply voltage.

5. The integrated circuit device according to claim 4, characterized in that, The first tie transistor is an n-well tie transistor located in the central segment of the first semiconductor substrate region, the first semiconductor substrate region being an n-well region connected to the first power supply voltage via the n-well tie transistor, and the second tie transistor is a p-well tie transistor located in the central segment of the second semiconductor substrate region, the second semiconductor substrate region being a p-well region connected to the second power supply voltage via the p-well tie transistor.

6. The integrated circuit device according to claim 4, characterized in that, Each of the first tie transistor, the second tie transistor, the first plurality of LOD protection transistors, and the second plurality of LOD protection transistors includes a FinFET device formed in the first semiconductor substrate region or the second semiconductor substrate region of the semiconductor substrate.

7. The integrated circuit device according to claim 4, characterized in that... The first tie transistor includes an n-FinFET formed in the first semiconductor substrate region of the semiconductor substrate. The second tie transistor includes a p-FinFET formed in the second semiconductor substrate region of the semiconductor substrate. The at least one decap transistor connected as a decoupling capacitor includes a p-FinFET formed in the first semiconductor substrate region of the semiconductor substrate and / or an n-FinFET formed in the second semiconductor substrate region of the semiconductor substrate.

8. The integrated circuit device according to claim 4, characterized in that, Each of the plurality of additional dummy transistors includes a p-FinFET formed in the first semiconductor substrate region of the semiconductor substrate or an n-FinFET formed in the second semiconductor substrate region of the semiconductor substrate.

9. A method for manufacturing an integrated circuit, characterized in that, include: Receive a standard well tap unit design for a well tap circuit, the well tap circuit being used to connect a first power supply voltage and a second power supply voltage to an n-type semiconductor substrate region and a p-type semiconductor substrate region, respectively; as well as The standard well tap cell design is formed in an integrated circuit using a sequence of manufacturing steps to have a set of layout characteristics, which include: An n-well tie rod, located in the n-type semiconductor substrate region, is used to connect the n-type semiconductor substrate region to the first power supply voltage; A first plurality of diffusion length LOD protection transistors are located in the n-type semiconductor substrate region to protect the n-well linkage. A p-well tie rod, located in the p-type semiconductor substrate region, is used to connect the p-type semiconductor substrate region to the second power supply voltage; and A second plurality of LOD protection transistors are located in the p-type semiconductor substrate region to protect the p-well tie rod. The first plurality of LOD protection transistors and the second plurality of LOD protection transistors together include: At least one decap transistor is connected as a decoupling capacitor between the first power supply voltage and the second power supply voltage, and Multiple additional dummy transistors, each of which has a gate, source, and drain terminals commonly connected to the first power supply voltage or the second power supply voltage.

10. The method according to claim 9, characterized in that, The standard sink tap unit design includes: Obtain a semiconductor substrate; The semiconductor substrate is selectively implanted to form the n-type semiconductor substrate region and the p-type semiconductor substrate region that are adjacent to each other; A plurality of semiconductor fins extending upward from the n-type semiconductor substrate region and the p-type semiconductor substrate region are selectively formed on the semiconductor substrate, wherein the plurality of semiconductor fins comprises: P+ doped semiconductor fins are formed over the n-type semiconductor substrate region within one or more defined diffusion length (LOD) protection regions. N+ doped semiconductor fins are formed above the n-type semiconductor substrate region in one or more defined n-tap regions. N+ doped semiconductor fins are formed over the p-type semiconductor substrate region within one or more defined LOD protection regions, and P+ doped semiconductor fins are formed over the p-type semiconductor substrate region in one or more defined p-tap regions; Selectively forming one or more gate electrodes, said one or more gate electrodes being aligned perpendicularly to the plurality of semiconductor fins to define a first plurality of LOD protection transistors in the n-type semiconductor substrate region, and defining a second plurality of LOD protection transistors in the p-type semiconductor substrate region; and One or more metal interconnect layers are selectively formed over the semiconductor substrate to connect the first plurality of LOD protection transistors and the second plurality of LOD protection transistors, including: At least one decap FinFET device is connected as a first decoupling capacitor between the first voltage source and the second voltage source, and Multiple additional dummy FinFET devices, wherein each additional dummy FinFET device has a common gate, source, and drain terminal connected to the first voltage source or the second voltage source.

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