Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes: a substrate including a display area including a corner portion, a connecting portion, and a center portion, and a peripheral area surrounding at least a portion of the display area in a plan view; a first display element in the corner portion; a second display element in the connection portion; a first pixel circuit unit in the corner portion and electrically connected to the first display element; a second pixel circuit unit in the connection portion and electrically connected to the second display element; and a plurality of gate drivers arranged in a line along the first direction, a gate driver of the plurality of gate drivers overlapping at least a portion of the second pixel circuit unit and electrically connected to the first pixel circuit unit in the connection portion.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0109111, filed on August 14, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device. Background Technology

[0003] Display devices visually display data. Display devices can provide images by using light-emitting diodes (LEDs). The uses of display devices have diversified, and various designs have been explored to improve the quality of display devices. Summary of the Invention

[0004] One or more embodiments include a display device.

[0005] Other aspects will be set forth in part in the description which follows, and will also be apparent in part from the description, or may be learned by practicing the disclosed embodiments presented.

[0006] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area, the display area including a corner portion, a connecting portion and a central portion, the peripheral area surrounding at least a portion of the display area in a plan view; a first display element in the corner portion; a second display element in the connecting portion; a first pixel circuit unit in the corner portion and electrically connected to the first display element; a second pixel circuit unit in the connecting portion and electrically connected to the second display element; and a plurality of gate drivers arranged in a line along a first direction, wherein a gate driver of the plurality of gate drivers that is superimposed on at least a portion of the second pixel circuit unit and electrically connected to the first pixel circuit unit is in the connecting portion.

[0007] The first pixel circuit unit and the gate driver may be spaced apart in a second direction that intersects the first direction.

[0008] The gate driver among multiple gate drivers can be closest to the first pixel circuit unit.

[0009] The first pixel circuit unit and the second pixel circuit unit can be located on the layer above the gate driver.

[0010] The first display element can be configured as a plurality of first display elements, including a first-1 display element at the uppermost part of the corner portion.

[0011] The first pixel circuit unit can be configured as a plurality of first pixel circuit units, the plurality of first pixel circuit units including the first-1 pixel circuit unit at the uppermost part of the corner portion and electrically connected to the first-1 display element.

[0012] Multiple gate drivers may include a first gate driver located at the top of the connection portion and electrically connected to the first-1 pixel circuit unit.

[0013] Multiple gate drivers can be aligned in the first direction.

[0014] The display device may also include a clock line stacked with a plurality of gate drivers and extending in a first direction.

[0015] Clock lines can be configured to electrically connect multiple gate drivers to each other.

[0016] The gate driver can be electrically connected to the second pixel circuit unit.

[0017] The connecting portion can be between one corner portion and another corner portion of the display area, wherein the center portion of the display area is inside the corner portion and the connecting portion.

[0018] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area, the display area including a corner portion, a connecting portion and a central portion, the peripheral area surrounding at least a portion of the display area in a plan view; a first display element in the corner portion; a second display element in the connecting portion; a first pixel circuit unit in the corner portion and electrically connected to the first display element; a second pixel circuit unit in the connecting portion and electrically connected to the second display element; and a plurality of gate drivers arranged in a first direction, offset from each other in a direction from the connecting portion toward the corner portion, and including a gate driver in the connecting portion, superimposed with at least a portion of the second pixel circuit unit and electrically connected to the first pixel circuit unit.

[0019] The gate driver among the multiple gate drivers can be closest to the first pixel circuit unit in a second direction that intersects with the first direction.

[0020] The first display element can be configured as a plurality of first display elements, including a first-1 display element at the uppermost part of the corner portion.

[0021] The first pixel circuit unit can be configured as a plurality of first pixel circuit units, the plurality of first pixel circuit units including the first-1 pixel circuit unit at the uppermost part of the corner portion and electrically connected to the first-1 display element.

[0022] Multiple gate drivers may include a first gate driver located at the top of the connection portion and electrically connected to the first-1 pixel circuit unit.

[0023] Multiple gate drivers can be offset relative to the first gate driver in a direction toward the corner portion.

[0024] The display device may also include a clock line, which is stacked with multiple gate drivers and has a stepped shape in a plan view.

[0025] Clock lines can be configured to electrically connect multiple gate drivers to each other.

[0026] According to one or more embodiments, an electronic device includes a display device comprising: a substrate including a display area and a peripheral area, the display area including a corner portion, a connecting portion and a central portion, the peripheral area surrounding at least a portion of the display area in a plan view; a first display element in the corner portion; a second display element in the connecting portion; a first pixel circuit unit in the corner portion and electrically connected to the first display element; a second pixel circuit unit in the connecting portion and electrically connected to the second display element; and a plurality of gate drivers arranged in a line along a first direction, wherein a gate driver of the plurality of gate drivers that is superimposed on at least a portion of the second pixel circuit unit and electrically connected to the first pixel circuit unit is in the connecting portion. Attached Figure Description

[0027] The above and other aspects of certain disclosed embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1A It is a schematic perspective view of a display device according to one or more embodiments; Figure 1B It is a schematic plan view of a display device according to one or more embodiments; Figure 2 and Figure 3 It is an equivalent circuit diagram of pixels that may be included in a display device according to one or more embodiments; Figure 4 It is a schematic cross-sectional view of the display panel in the display device; Figure 5 An enlarged plan view of a portion of the display area of ​​the display device is shown schematically; Figure 6 A portion of the display area of ​​the display device is shown schematically; Figure 7 It is along Figure 5 The line II-II' intercepted Figure 5 A schematic cross-sectional view of the display area of ​​the display device; and Figure 8 An enlarged plan view of a portion of the display area of ​​the display device is shown schematically. Detailed Implementation

[0028] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for a person of ordinary skill in the art to fully understand aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description; therefore, repeated descriptions may be omitted.

[0029] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of “may,” “may,” or “may not” corresponds to one or more embodiments of this disclosure.

[0030] It will be understood by those skilled in the art that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0031] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of description. Furthermore, crosshairs and / or shading are typically provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities and / or any other characteristics, properties, etc., of the elements shown.

[0032] Various embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of examples and / or intermediate structures. Thus, variations in the shapes shown in the drawings will be expected due to, for example, manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes shown for elements, layers, or regions, but will include deviations in shape caused, for example, by manufacturing processes.

[0033] For example, an injection region shown as rectangular will typically have circular or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from the injection region to the non-injection region. Similarly, the buried region formed by injection may result in some injection in the region between the buried region and the surface through which the injection occurs.

[0034] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “higher,” “upper side,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element or feature to another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both the upper and lower orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first component is described as being arranged "on" the second component, this means that the first component is arranged on the upper or lower side of the second component based on the direction of gravity, but not limited to the upper side of the second component based on the direction of gravity.

[0035] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting a portion of the object from the side. The term "overlay" or variations thereof means that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlay" can include stacking, facing or oriented, extending over, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlay" can include meanings such as "spaced apart from," "offset from," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can mean that the first object may be directly or indirectly opposite the second object. Where a third object is located between the first and second objects, the first and second objects, although still facing each other, can be understood as being indirectly opposite each other.

[0036] It will be understood that when an element, layer, region, or component (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operably, functionally, or communicatively) incorporated into" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly incorporated into the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into the other element, layer, region, or component, such that one or more intermediary elements, layers, regions, or components may be present. Additionally, this may collectively mean direct incorporation (or connection) or indirect incorporation (or connection) and integral incorporation (or connection) or non-integral incorporation (or connection). For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, the layer, region, or component may be directly electrically connected or directly bonded to the other layer, region, and / or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the accompanying drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection refers to an electrical connection, and "directly connected / directly bonded" or "directly on" means that one component is directly connected or directly bonded to another component or directly on another component, without an intermediary component.

[0037] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing relationships between components, such as "between," "immediately between," "adjacent to," and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0038] For the purposes of this disclosure, when expressions such as “at least one of…”, “any one of…”, or “one or more of…” follow a list of elements, they modify the entire list of elements without modifying any individual elements within that list. For example, “at least one of X, Y, and Z” and “at least one of the groups consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of…”, “multiple…”, “one of…”, and other prepositional phrases precede (or follow) a list of elements, they modify the entire list of elements, not individual elements within that list. When stated as “C to D”, unless otherwise specified, it means C or greater and D or less.

[0039] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, section, or part from another element, component, assembly, region, area, layer, section, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section. Describing an element as a “first” element may not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or sets of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively mean “first category (or first set),” “second category (or second set),” etc.

[0040] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0041] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It will also be understood that when the terms “comprising” and variations thereof, “having” and variations thereof, and “including” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0042] As used herein, the terms “basic,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent deviations of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “basic” can include a range of + / -5% of the corresponding value. As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that is tolerable by one of ordinary skill in the art. Other expressions may also be expressions from which “basic” has been omitted.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0044] Figure 1A This is a schematic perspective view of a display device 1 according to one or more embodiments. Figure 1B This is a schematic plan view of a display device 1 according to one or more embodiments.

[0045] The display device 1 according to one or more embodiments is a device for displaying moving or still images, and can be used not only as a display screen for portable electronic devices (such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs)), but also as a display screen for various products (such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices). Additionally, the display device 1 according to one or more embodiments can be used in wearable devices such as smartwatches, smartwatch phones, glasses-type displays, and head-mounted displays (HMDs). Furthermore, the display device 1 according to one or more embodiments can be used as a dashboard of a car, a central information display (CID) placed on the center console or instrument panel of a car, an interior mirror display replacing the side mirrors of a car, or a display placed on the back of the front seats as a rear-seat entertainment display for a car.

[0046] Reference Figure 1A and Figure 1B The display device 1 may have an edge in a first direction and an edge in a second direction. In this respect, the first and second directions may intersect each other. For example, the first and second directions may form an acute angle relative to each other. As another example, the first and second directions may form an obtuse angle relative to each other, or they may be orthogonal to each other. The case where the first and second directions are orthogonal will be described in detail below. For example, the first direction may be direction x or direction -x, and the second direction may be direction y or direction -y. A third direction perpendicular to the first and second directions may be direction z or direction -z.

[0047] Display device 1 may include a display area DA and a peripheral area PA outside the display area DA. Display device 1 can provide a specific image by using light emitted from a plurality of pixels PX arranged in the display area DA. The peripheral area PA, which is the area outside the display area DA, may be a non-display area in which no pixels are arranged. The display area DA may (e.g., in a plan view) be completely surrounded by the peripheral area PA.

[0048] The display area DA may include a central portion DA1, corner portions DA2, and connecting portions DA3. The corner portions DA2 of the display area DA may be edge portions (e.g., a portion of an edge) of the display area DA. The display area DA may include four corner portions DA2. The connecting portions DA3 of the display area DA may be the area between the corner portions DA2. The corner portions DA2 may be arranged on either side of the connecting portions DA3. The central portion DA1 of the display area DA may be arranged inside the corner portions DA2 and the connecting portions DA3. In other words, the corner portions DA2 and the connecting portions DA3 of the display area DA may (e.g., in a plan view) surround the central portion DA1 of the display area DA.

[0049] Although the organic light-emitting display device described below is an example of a display device according to one or more embodiments, the display device described herein is not limited thereto. In one or more other embodiments, the display device described herein may be, for example, an inorganic light-emitting display (or an inorganic electroluminescent (EL) display) or a quantum dot light-emitting display. For example, the emitting layer of the display element included in the display device may include an organic or inorganic material. Optionally, the display device may include an emitting layer and quantum dots in the path of light emitted from the emitting layer.

[0050] Figure 2 and Figure 3 It is an equivalent circuit diagram of a pixel P that may be included in a display device 1 according to one or more embodiments.

[0051] Reference Figure 2 Each pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL, and an organic light-emitting diode (OLED) connected to the pixel circuit PC.

[0052] The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 may be connected to the scan line SL and the data line DL, and may be configured to transmit the data signal Dm input through the data line DL to the driving thin-film transistor T1 according to the scan signal Sn input through the scan line SL.

[0053] The storage capacitor Cst can be connected to the switching thin-film transistor T2 and the drive voltage line PL, and can store the voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0054] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can be configured to control the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) in response to the voltage value stored in the storage capacitor Cst. The OLED can be connected between the driving thin-film transistor T1 and the voltage line to which a second driving voltage ELVSS is applied, and can emit light with a specific brightness according to the driving current.

[0055] although Figure 2 The illustration shows a scenario where the pixel circuit PC includes two thin-film transistors and one storage capacitor, but one or more embodiments are not limited thereto. For example, the pixel circuit PC may include three or more thin-film transistors and / or two or more storage capacitors. In one or more embodiments, the pixel circuit PC may include seven thin-film transistors and one storage capacitor. Optionally, the pixel circuit PC may include seven thin-film transistors and two storage capacitors.

[0056] Reference Figure 3 A pixel P may include a pixel circuit PC and an organic light-emitting diode (OLED) electrically connected to the pixel circuit PC.

[0057] In one or more embodiments, such as Figure 3 As shown, the pixel circuit PC may include a plurality of thin-film transistors T1 to T7 and a storage capacitor Cst. The thin-film transistors T1 to T7 and the storage capacitor Cst may be connected to signal lines SL1, SL2, SLp, SLn, EL, and DL, the initialization voltage line VIL, and the drive voltage line PL. In one or more embodiments, at least one of the signal lines SL1, SL2, SLp, SLn, EL, DL, the initialization voltage line VIL, and the drive voltage line PL (e.g., the initialization voltage line VIL and / or the drive voltage line PL) may be shared by adjacent pixels P.

[0058] Thin-film transistors T1 to T7 may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0059] One or more of the multiple thin-film transistors T1 to T7 can be configured as n-channel MOSFETs (NMOS), and one or more other thin-film transistors can be configured as p-channel MOSFETs (PMOS).

[0060] For example, such as Figure 3As shown, among the multiple thin-film transistors T1 to T7, the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 can be configured as n-channel MOSFETs (NMOS), and the other thin-film transistors can be configured as p-channel MOSFETs (PMOS).

[0061] In one or more embodiments, the compensation thin-film transistor T3, the first initialization thin-film transistor T4, and the second initialization thin-film transistor T7 among the plurality of thin-film transistors T1 to T7 can be configured as n-channel MOSFETs (NMOS), and the other thin-film transistors can be configured as p-channel MOSFETs (PMOS). Optionally, only one of the plurality of thin-film transistors T1 to T7 can be configured as an NMOS, and the other thin-film transistors can be configured as PMOS. Optionally, all of the plurality of thin-film transistors T1 to T7 can be NMOS.

[0062] The signal lines may include a first scan line SL1 configured to transmit a first scan signal Sn, a second scan line SL2 configured to transmit a second scan signal Sn', a previous scan line SLp configured to transmit a previous scan signal Sn-1 to a first initialization thin-film transistor T4, an emit control line EL configured to transmit an emit control signal En to an operation control thin-film transistor T5 and an emit control thin-film transistor T6, a next scan line SLn configured to transmit a next scan signal Sn+1 to a second initialization thin-film transistor T7, and a data line DL that intersects the first scan line SL1 and is configured to transmit a data signal Dm.

[0063] The drive voltage line PL can be configured to transmit the drive voltage ELVDD to the drive thin-film transistor T1, and the initialization voltage line VIL can be configured to transmit the initialization voltage Vint used to initialize the drive thin-film transistor T1 and the pixel electrode.

[0064] The driving gate electrode of the driving thin-film transistor T1 is connected to the storage capacitor Cst. The driving source region of the driving thin-film transistor T1 is connected to the driving voltage line PL via the operation control thin-film transistor T5, and the driving drain region of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The driving thin-film transistor T1 can be configured to receive the data signal Dm according to the switching operation of the switching thin-film transistor T2, and can supply a driving current I to the OLED. OLED .

[0065] The switching gate electrode of the switching thin-film transistor T2 is connected to the first scan line SL1, the switching source region of the switching thin-film transistor T2 is connected to the data line DL, and the switching drain region of the switching thin-film transistor T2 is connected to the driving source region of the driving thin-film transistor T1 and is also connected to the driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 can be turned on according to the first scan signal Sn received through the first scan line SL1 and can be configured to perform a switching operation for transmitting the data signal Dm transmitted through the data line DL to the driving source region of the driving thin-film transistor T1.

[0066] The compensation gate electrode of the compensation thin-film transistor T3 is connected to the second scan line SL2. The compensation drain region of the compensation thin-film transistor T3 is connected to the driving drain region of the driving thin-film transistor T1, and is also connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The compensation source region of the compensation thin-film transistor T3 is connected to the bottom electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin-film transistor T1. In addition, the compensation source region is connected to the first initialization drain region of the first initialization thin-film transistor T4.

[0067] The compensation thin-film transistor T3 is turned on according to the second scan signal Sn' received through the second scan line SL2, and is configured to diode-connect the driving thin-film transistor T1 by electrically connecting the driving gate electrode and the driving drain region of the driving thin-film transistor T1 to each other.

[0068] The first initialization gate electrode of the first initialization thin-film transistor T4 is connected to the previous scan line SLp. The first initialization source region of the first initialization thin-film transistor T4 is connected to the second initialization source region of the second initialization thin-film transistor T7 and the initialization voltage line VIL. The first initialization drain region of the first initialization thin-film transistor T4 is connected to the bottom electrode CE1 of the storage capacitor Cst, the compensation source region of the compensation thin-film transistor T3, and the driving gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SLp, and can be configured to perform an initialization operation for initializing the voltage of the driving gate electrode of the driving thin-film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode of the driving thin-film transistor T1.

[0069] The operation control gate electrode of the operation control thin film transistor T5 is connected to the emitter control line EL, the operation control source region of the operation control thin film transistor T5 is connected to the drive voltage line PL, and the operation control drain region of the operation control thin film transistor T5 is connected to the drive source region of the drive thin film transistor T1 and the switch drain region of the switch thin film transistor T2.

[0070] The emission control gate electrode of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source region of the emission control thin film transistor T6 is connected to the driving drain region of the driving thin film transistor T1 and the compensation drain region of the compensation thin film transistor T3, and the emission control drain region of the emission control thin film transistor T6 is electrically connected to the second initialization drain region of the second initialization thin film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0071] When the operation control thin-film transistor T5 and the emission control thin-film transistor T6 are turned on in parallel or substantially simultaneously according to the emission control signal En received through the emission control line EL, the driving voltage ELVDD is transmitted to the organic light-emitting diode OLED, and therefore, the driving current I... OLED It flows through an organic light-emitting diode (OLED).

[0072] The second initialization gate electrode of the second initialization thin-film transistor T7 is connected to the next scan line SLn. The second initialization drain region of the second initialization thin-film transistor T7 is connected to the emission control drain region of the emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode (OLED). The second initialization source region of the second initialization thin-film transistor T7 is connected to the first initialization source region of the first initialization thin-film transistor T4 and the initialization voltage line VIL. The second initialization thin-film transistor T7 is turned on according to the next scan signal Sn+1 received through the next scan line SLn and is configured to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0073] like Figure 3 As shown, the second initialization thin-film transistor T7 can be connected to the next scan line SLn. In one or more embodiments, the second initialization thin-film transistor T7 can be connected to the emitter control line EL and can be driven according to the emitter control signal En. The positions of the source and drain regions can be reversed depending on the type of transistor (p-type or n-type).

[0074] The storage capacitor Cst may include a bottom electrode CE1 and a top electrode CE2. The bottom electrode CE1 of the storage capacitor Cst is connected to the driving gate electrode of the driving thin-film transistor T1, and the top electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst can store the charge corresponding to the difference between the driving gate electrode voltage of the driving thin-film transistor T1 and the driving voltage ELVDD.

[0075] The detailed operation of each pixel P according to one or more embodiments is as follows.

[0076] During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line SLp, the first initialization thin-film transistor T4 turns on in response to the previous scan signal Sn-1, and drives the thin-film transistor T1 to be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL.

[0077] During the data programming period, when the first scan signal Sn and the second scan signal Sn' are supplied through the first scan line SL1 and the second scan line SL2, the switching thin-film transistor T2 and the compensation thin-film transistor T3 are turned on in response to the first scan signal Sn and the second scan signal Sn'. In this respect, the driving thin-film transistor T1 is connected to and forward biased by the turned-on compensation thin-film transistor T3 diode.

[0078] Then, a compensation voltage (Dm+Vth) (where Vth is the (-) value) that reduces the threshold voltage (Vth) of the driving thin-film transistor T1 from the data signal Dm supplied by the data line DL is applied to the driving gate electrode of the driving thin-film transistor T1.

[0079] The driving voltage ELVDD and the compensation voltage (Dm+Vth) are applied to the two ends of the storage capacitor Cst, and the charge corresponding to the voltage difference between the two ends is stored in the storage capacitor Cst.

[0080] During the emission period, the operation control thin-film transistor T5 and the emission control thin-film transistor T6 are turned on by the emission control signal En supplied from the emission control line EL. A drive current I is generated based on the voltage difference between the voltage at the drive gate electrode of the driving thin-film transistor T1 and the drive voltage ELVDD. OLED And drive current I OLED The emission control thin-film transistor T6 supplies power to the organic light-emitting diode (OLED).

[0081] In one or more embodiments, at least one of the plurality of thin-film transistors T1 to T7 may include a semiconductor layer comprising an oxide semiconductor, and the other transistors may include a semiconductor layer comprising a silicon semiconductor.

[0082] For example, the driving thin-film transistor T1, which directly affects the brightness of the display device, may include a semiconductor layer formed of highly reliable polycrystalline silicon, through which a high-resolution display device can be realized.

[0083] Meanwhile, oxide semiconductors possess relatively high carrier mobility and relatively low leakage current, thus the voltage drop is not significant even with long driving times. In other words, even during low-frequency driving, the change in image color due to voltage drop is not significant, making low-frequency driving possible.

[0084] As described above, since oxide semiconductors have low leakage current, at least one of the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 connected to the drive gate electrode of the drive thin-film transistor T1 can include oxide semiconductors. Therefore, leakage current that may flow to the drive gate electrode can be reduced or prevented, and power consumption can also be reduced.

[0085] In one or more embodiments, the driving thin-film transistor T1, the switching thin-film transistor T2, the operation control thin-film transistor T5, the emission control thin-film transistor T6, and the second initialization thin-film transistor T7 may include a semiconductor layer comprising silicon semiconductor, and the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 may include a semiconductor layer comprising oxide semiconductor. However, one or more embodiments are not limited thereto.

[0086] Figure 4 This is a schematic cross-sectional view of the display panel 10 in the display device 1. For example, Figure 4 It is along Figure 1A The line I-I' intercepted Figure 1A A schematic cross-sectional view of the display panel 10 in the display device 1.

[0087] Reference Figure 4 The display panel 10 may include a substrate 100, an inorganic insulating layer 118, an organic insulating layer 119, a pixel circuit PC, a connecting electrode CM, an organic light-emitting diode (OLED), a third organic insulating layer 118, a spacer 119, and an encapsulation layer 300. That is, the substrate 100, the inorganic insulating layer 118, the organic insulating layer 118, the pixel circuit PC, the connecting electrode CM, the organic light-emitting diode (OLED), the third organic insulating layer 118, the spacer 119, and the encapsulation layer 300 may be arranged in the display area DA of the display panel 10. The organic light-emitting diode (OLED) is one type of display element and is described as an example.

[0088] The substrate 100 may include a first substrate layer 100a, a first barrier layer 100b, a second substrate layer 100c, and a second barrier layer 100d. In one or more embodiments, the first substrate layer 100a, the first barrier layer 100b, the second substrate layer 100c, and the second barrier layer 100d may be stacked sequentially in the thickness direction of the substrate 100.

[0089] At least one of the first matrix layer 100a and the second matrix layer 100c may include a polymer resin, such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0090] The first barrier layer 100b and the second barrier layer 100d are barrier layers that reduce or prevent the intrusion of external foreign objects, and both may contain inorganic materials (such as silicon nitride (SiN)). X A single-layer or multi-layer structure of silicon dioxide (SiO2) and / or silicon oxynitride (SiON).

[0091] The buffer layer 111 may be disposed on the substrate 100 (as used herein, "disposed on" can mean "above"). The buffer layer 111 may include, for example, silicon nitride (SiN). X Inorganic insulating materials consisting of silicon oxynitride (SiON) and silicon oxide (SiO2), and may have a single-layer or multi-layer structure including the above-mentioned inorganic insulating materials.

[0092] The inorganic insulating layer IIL can be disposed on the buffer layer 111. The inorganic insulating layer IIL may include a first inorganic insulating layer 112 and a second inorganic insulating layer 114. However, one or more embodiments are not limited thereto.

[0093] The pixel circuitry PC can be arranged in the display area DA. The pixel circuitry PC may include a thin-film transistor (TFT). The thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0094] The semiconductor layer Act can be disposed on the buffer layer 111. The semiconductor layer Act may include polycrystalline silicon. Optionally, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, or organic semiconductor. The semiconductor layer Act may include a channel region and drain and source regions disposed on both sides of the channel region, respectively.

[0095] The gate electrode GE can be disposed on the semiconductor layer Act. The gate electrode GE can be stacked with the channel region. The gate electrode GE can include a low-resistance metallic material. The gate electrode GE can include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a multilayer or single-layer structure including the above materials.

[0096] The first inorganic insulating layer 112 can be disposed between the semiconductor layer Act and the gate electrode GE. The first inorganic insulating layer 112 may include inorganic insulating materials, such as silicon oxide (SiO2) and silicon nitride (SiN). X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0097] The second inorganic insulating layer 114 can be disposed on the gate electrode GE. The second inorganic insulating layer 114 can cover the gate electrode GE. The second inorganic insulating layer 114 may include inorganic insulating materials, such as silicon oxide (SiO2) or silicon nitride (SiN). X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0098] Each of the drain electrode DE and the source electrode SE can be located on the second inorganic insulating layer 114. Each of the drain electrode DE and the source electrode SE can be connected to the semiconductor layer Act through contact holes defined in the first inorganic insulating layer 112 and the second inorganic insulating layer 114. The drain electrode DE and the source electrode SE can comprise highly conductive materials. The drain electrode DE and the source electrode SE can comprise conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a multilayer or single-layer structure comprising the aforementioned materials. For example, the drain electrode DE and the source electrode SE can have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0099] An organic insulating layer (OIL) can be disposed on an inorganic insulating layer (IIL). The organic insulating layer (OIL) may include a first organic insulating layer 115 and a second organic insulating layer 116. Although Figure 4 An organic insulating layer (OIL) comprising two layers is shown, but one or more embodiments are not limited thereto. The organic insulating layer (OIL) may comprise three or four layers.

[0100] The first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include organic insulating materials, such as commonly used commercial polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof.

[0101] The connecting electrode CM can be disposed on the first organic insulating layer 115. In this respect, the connecting electrode CM can be connected to the drain electrode DE or the source electrode SE through contact holes in the first organic insulating layer 115. The connecting electrode CM can include a highly conductive material. The connecting electrode CM can include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a multilayer or single-layer structure comprising the above materials. For example, the connecting electrode CM can have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0102] The second organic insulating layer 116 may be disposed on the connecting electrode CM. The second organic insulating layer 116 may cover the connecting electrode CM. The second organic insulating layer 116 may include the same material as the first organic insulating layer 115 or a different material.

[0103] A light-emitting diode (LED) can be disposed on the second organic insulating layer 116. For example, an organic light-emitting diode (OLED) can be disposed on the second organic insulating layer 116. Alternatively, in one or more embodiments, an inorganic light-emitting diode or the like can be disposed on the second organic insulating layer 116.

[0104] Organic light-emitting diodes (OLEDs) can emit red, green, or blue light, or they can emit red, green, blue, or white light. An OLED may include a first electrode 211, an emitting layer 212b, a functional layer 212f, a second electrode 213, and a capping layer 215. The first electrode 211 can be a pixel electrode (e.g., an anode) of the OLED, and the second electrode 213 can be a counter electrode (e.g., a cathode) of the OLED.

[0105] The first electrode 211 may be disposed on the second organic insulating layer 116. The first electrode 211 may be electrically connected to the connecting electrode CM through contact holes defined in the second organic insulating layer 116. The first electrode 211 may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In one or more embodiments, the first electrode 211 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In one or more embodiments, the first electrode 211 may also include a layer formed of ITO, IZO, ZnO, or In2O3 on / below the aforementioned reflective layer. For example, the first electrode 211 may have a multilayer structure of ITO / Ag / ITO.

[0106] A third organic insulating layer 118, having an opening that exposes at least a portion of the first electrode 211, may be disposed on the first electrode 211. The emission region of light emitted from the organic light-emitting diode (OLED) may be defined by the opening defined in the third organic insulating layer 118. For example, the width of the opening may correspond to the width of the emission region.

[0107] The third organic insulating layer 118 may include an organic insulating material. Optionally, the third organic insulating layer 118 may include an inorganic insulating material, such as silicon nitride, silicon oxynitride, or silicon oxide. Optionally, the third organic insulating layer 118 may include both organic and inorganic insulating materials. In one or more embodiments, the third organic insulating layer 118 may include a light-blocking material. The light-blocking material may include carbon black, carbon nanotubes, resins or pastes including black dyes, metal particles (e.g., nickel, aluminum, molybdenum, and alloys thereof), metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). When the third organic insulating layer 118 includes a light-blocking material, the reflection of external light caused by the metal structure disposed beneath the third organic insulating layer 118 can be reduced.

[0108] Spacer 119 may be disposed on the third organic insulating layer 118. Spacer 119 may include an organic insulating material, such as polyimide. Optionally, spacer 119 may include silicon nitride (SiN). X Inorganic insulating materials, such as silicon dioxide (SiO2), or may include both organic and inorganic insulating materials.

[0109] In one or more embodiments, spacer 119 may comprise the same material as the third organic insulating layer 118. In this case, the third organic insulating layer 118 and spacer 119 may be formed together during a masking process using a halftone mask or the like. Alternatively, spacer 119 and the third organic insulating layer 118 may each comprise different materials.

[0110] The emitting layer 212b may be disposed within an opening in the third organic insulating layer 118. The emitting layer 212b may comprise a high-molecular-weight or low-molecular-weight organic material for emitting light of a specific color.

[0111] Functional layer 212f may include a first functional layer 212a and a second functional layer 212c. The first functional layer 212a may be disposed between the first electrode 211 and the emitter layer 212b, and the second functional layer 212c may be disposed between the emitter layer 212b and the second electrode 213. However, at least one of the first functional layer 212a and the second functional layer 212c may be omitted. The following description will primarily focus on the case where each of the first functional layer 212a and the second functional layer 212c is disposed.

[0112] The first functional layer 212a may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer 212c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 212a and / or the second functional layer 212c may be a common layer that completely covers the substrate 100, just like the second electrode 213 described below.

[0113] The second electrode 213 may be disposed on the functional layer 212f. The second electrode 213 may include a conductive material with low work function. For example, the second electrode 213 may include a (semi)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Optionally, the second electrode 213 may also include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer comprising the above-mentioned materials.

[0114] In one or more embodiments, the capping layer 215 may be disposed on the second electrode 213. The capping layer 215 may include lithium fluoride (LiF), inorganic materials and / or organic materials.

[0115] The encapsulation layer 300 can be disposed on the organic light-emitting diode (OLED). The encapsulation layer 300 can cover the organic light-emitting diode (OLED). The encapsulation layer 300 can be disposed on the second electrode 213 and / or the capping layer 215. In one or more embodiments, the encapsulation layer 300 may include at least one inorganic encapsulation layer 30 and at least one organic encapsulation layer. Figure 4 An encapsulation layer 300 is shown, comprising a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 stacked sequentially on top of each other.

[0116] The inorganic encapsulation layer 30 may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have a single-layer or multi-layer structure including the aforementioned materials. The organic encapsulation layer 320 may include polymeric materials. Examples of polymeric materials may include acryloyl resins, epoxy resins, polyimide resins, and polyethylene resins. In one or more embodiments, the organic encapsulation layer 320 may include acrylates.

[0117] The input sensing layer 400 may be disposed on the encapsulation layer 300. The input sensing layer 400 may include a first touch insulating layer 410, a second touch insulating layer 420, a first conductive layer 430, a third touch insulating layer 440, a second conductive layer 450, and a planarization layer 460. The touch insulating layer 40 may include the first touch insulating layer 410, the second touch insulating layer 420, and / or the third touch insulating layer 440.

[0118] In one or more embodiments, the first touch insulating layer 410 may be disposed on the second inorganic encapsulation layer 330, and the second touch insulating layer 420 may be disposed on the first touch insulating layer 410. In one or more embodiments, the first touch insulating layer 410 and the second touch insulating layer 420 may comprise organic insulating materials.

[0119] In one or more embodiments, at least one of the first touch insulating layer 410 and the second touch insulating layer 420 may be omitted. For example, in one or more embodiments, the first touch insulating layer 410 may be omitted, and the second touch insulating layer 420 may be disposed on the second inorganic encapsulation layer 330 and the first conductive layer 430 may be disposed on the second touch insulating layer 420.

[0120] The first conductive layer 430 may be disposed on the second touch insulating layer 420, and the third touch insulating layer 440 may be disposed on the first conductive layer 430. In one or more embodiments, the third touch insulating layer 440 may comprise an organic insulating material.

[0121] The second conductive layer 450 may be disposed on the third touch insulating layer 440. The touch electrode TE of the input sensing layer 400 may have a structure in which the first conductive layer 430 and the second conductive layer 450 are connected to each other. Optionally, the touch electrode TE may be formed in one of the first conductive layer 430 and the second conductive layer 450, and may include metal wires contained in the respective conductive layer. Each of the first conductive layer 430 and the second conductive layer 450 may include at least one of aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), and indium tin oxide (ITO), and may have a single-layer or multi-layer structure comprising the above materials. For example, each of the first conductive layer 430 and the second conductive layer 450 may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0122] In one or more embodiments, the planarization layer 460 may cover the second conductive layer 450. The planarization layer 460 may include an organic insulating material.

[0123] Figure 5 An enlarged plan view of a portion of the display area DA of the display device 1 is shown schematically. Figure 6 A portion of the display area DA of the display device 1 is shown schematically.

[0124] Reference Figure 5 and Figure 6A first display element DPE1 can be arranged in a corner portion DA2 of the display area DA. A first pixel circuit unit PC1 electrically connected to the first display element DPE1 can be arranged in the corner portion DA2 of the display area DA to correspond to the first display element DPE1. A second display element DPE2 can be arranged in a connecting portion DA3 of the display area DA. A second pixel circuit unit PC2 electrically connected to the second display element DPE2 can be arranged in the connecting portion DA3 of the display area DA to correspond to the second display element DPE2. In the figures, for convenience, the display elements DPE (e.g., DPE1 and DPE2) and their corresponding pixel circuit units PC1 and PC2 are represented by a quadrilateral shape.

[0125] Gate drivers 130a or 130b may be arranged in the connection portion DA3 of the display area DA. Gate drivers 130a or 130b may be stacked with at least a portion of the second display element DPE2 arranged in the connection portion DA3 of the display area DA and the second pixel circuit unit PC2 arranged corresponding to the second display element DPE2. Gate drivers 130a or 130b may be electrically connected to the first pixel circuit unit PC1 arranged in the corner portion DA2 of the display area DA. Additionally, gate drivers 130a or 130b may be electrically connected to the second pixel circuit unit PC2 arranged in the connection portion DA3 of the display area DA.

[0126] Multiple gate drivers 130a or 130b may be configured. The multiple gate drivers 130 may be arranged in a line along a second direction (e.g., direction y or direction -y). Multiple first display elements DPE1 may be configured. The multiple first display elements DPE1 may include a first-1 display element DPE1-1 disposed at the uppermost part of the corner portion DA2 of the display area DA. Multiple first pixel circuit units PC1 may be configured. The multiple first pixel circuit units PC1 may include a first-1 pixel circuit unit PC1-1 disposed at the uppermost part of the corner portion DA2 of the display area DA. The first-1 pixel circuit unit PC1-1 may be electrically connected to the first-1 display element DPE1-1. The multiple gate drivers 130 may include a first gate driver 130a electrically connected to the first-1 pixel circuit unit PC1-1. The first gate driver 130a may be disposed at the uppermost part of the connection portion DA3 of the display area DA and may be closest to the first-1 pixel circuit unit PC1-1. Multiple gate drivers 130 may be arranged in a line relative to the first gate driver 130a along a second direction (e.g., direction y or direction -y).

[0127] A first pixel circuit unit PC1, corresponding to and electrically connected to the first display element DPE1 arranged in the corner portion DA2 of the display area DA, may be electrically connected to a gate driver 130a or 130b that is separate from it in a first direction (e.g., direction x). For example, the first pixel circuit unit PC1 may be electrically connected to the nearest gate driver 130a or 130b among a plurality of gate drivers 130 that are separate from it in the first direction (e.g., direction x). For example, the first pixel circuit unit PC1-1 corresponding to the first-1 display element DPE1-1 may be electrically connected to the nearest first gate driver 130a among a plurality of gate drivers 130 that are separate from it in the first direction (e.g., direction x).

[0128] Clock line 140 can be arranged in the connection portion DA3 of display area DA to be superimposed on a plurality of gate drivers 130. Clock line 140 can extend in a second direction (e.g., direction y or direction -y) to be superimposed on a plurality of gate drivers 130. In other words, clock line 140 can extend in a direction in which the plurality of gate drivers 130 are arranged as a line. In addition, clock line 140 can be configured to electrically connect the plurality of gate drivers 130 to each other.

[0129] When multiple gate drivers 130, which are electrically connected to multiple first pixel circuit units PC1 corresponding to multiple first display elements DPE1 arranged in corner portion DA2 of display area DA, are arranged in corner portion DA2 of display area DA, the circuits of the gate drivers 130 are stacked on each other depending on the curvature of corner portion DA2 of display area DA, or there may be no space for clock lines 140 that are configured to connect the gate drivers 130 to each other.

[0130] In one or more embodiments, a plurality of gate drivers 130 electrically connected to a plurality of first pixel circuit units PC1 corresponding to a plurality of first display elements DPE1 arranged in a corner portion DA2 of the display area DA can be arranged in a line in the connection portion DA3 of the display area DA. Therefore, the plurality of gate drivers 130 configured to provide signals to the plurality of first pixel circuit units PC1 corresponding to the first display elements DPE1 arranged in the corner portion DA2 of the display area DA can be arranged in a panel-embedded manner in the display area DA. Therefore, the area of ​​the image to be displayed on the display device can be expanded to improve the quality and reliability of the display device.

[0131] Figure 7 It is along Figure 5 The line II-II' intercepted Figure 5 A schematic cross-sectional view of the display area DA of the display device 1.

[0132] In one or more embodiments, the first PLR1 may be a layer including the first gate driver 130a. The second PLR2 may include display elements DPE1 and DPE2 and corresponding pixel circuit units PC1 and PC2. The second PLR2 may be disposed on the first PLR1. In other words, the first pixel circuit unit PC1 and the second pixel circuit unit PC2 may be disposed on the first gate driver 130a. The second PLR2 may be disposed on the first PLR1 such that, in addition to the first gate driver 130a, a plurality of gate drivers 130 (see reference 130a) are disposed on the first PLR1. Figure 5 It can also be placed in the display area DA instead of the peripheral area PA (see reference). Figure 1A Therefore, the area of ​​the image to be displayed on the display device can be expanded. The first planarization layer PNL1 can be included in the first layer PLR1, and the second planarization layer PNL2 can be included in the second layer PLR2.

[0133] The second display element DPE2 and its corresponding second pixel circuit unit PC2 can be arranged on top of the first gate driver 130a arranged in the connection portion DA3 of the display area DA, so as to be superimposed on the first gate driver 130a. However, one or more embodiments are not limited thereto.

[0134] Figure 8 An enlarged plan view of a portion of the display area DA of the display device 1 is shown schematically.

[0135] Reference Figure 8 A first display element DPE1 can be arranged in a corner portion DA2 of the display area DA. A first pixel circuit unit PC1 electrically connected to the first display element DPE1 can be arranged in the corner portion DA2 of the display area DA to correspond to the first display element DPE1. A second display element DPE2 can be arranged in a connecting portion DA3 of the display area DA. A second pixel circuit unit PC2 electrically connected to the second display element DPE2 can be arranged in the connecting portion DA3 of the display area DA to correspond to the second display element DPE2.

[0136] Gate drivers 130a or 130b may be arranged in the connection portion DA3 or the corner portion DA2 of the display area DA. Gate drivers 130a or 130b may be stacked with a second display element DPE2 arranged in the connection portion DA3 of the display area DA, and may be stacked with at least a portion of a second pixel circuit unit PC2 arranged corresponding to the second display element DPE2. Gate drivers 130a or 130b may be electrically connected to a first pixel circuit unit PC1 arranged in the corner portion DA2 of the display area DA. Additionally, gate drivers 130a or 130b may be electrically connected to the second pixel circuit unit PC2 arranged in the connection portion DA3 of the display area DA.

[0137] Multiple gate drivers 130a or 130b may be configured. The multiple gate drivers 130 may be arranged in a second direction (e.g., direction y or direction -y), and may be arranged in a stepped manner in the direction from the connection portion DA3 of the display area DA toward the corner portion DA2, or may be offset respectively. Multiple first display elements DPE1 may be configured. The multiple first display elements DPE1 may include a first-1 display element DPE1-1 disposed at the uppermost part of the corner portion DA2 of the display area DA. Multiple first pixel circuit units PC1 may be configured. The multiple first pixel circuit units PC1 may include a first-1 pixel circuit unit PC1-1 disposed at the uppermost part of the corner portion DA2 of the display area DA. The first-1 pixel circuit unit PC1-1 may be electrically connected to the first-1 display element DPE1-1. The multiple gate drivers 130 may include a first gate driver 130a electrically connected to the first-1 pixel circuit unit PC1-1. The first gate driver 130a may be arranged at the uppermost part of the connection portion DA3 of the display area DA, and may be closest to the first-1 pixel circuit unit PC1-1. The plurality of gate drivers 130 may be arranged in a stepped manner (e.g., offset from each other in a plan view) relative to the first gate driver 130a in the direction toward the corner portion DA2 of the display area DA.

[0138] The first pixel circuit unit PC1, corresponding to and electrically connected to the first display element DPE1 arranged in the corner portion DA2 of the display area DA, can be electrically connected to a gate driver 130a or 130b that is separate from it in the first direction (e.g., direction x). For example, the first pixel circuit unit PC1 can be electrically connected to the nearest gate driver 130a or 130b among a plurality of gate drivers 130 that are separate from it in the first direction (e.g., direction x). For example, the first pixel circuit unit PC1-1 corresponding to the first-1 display element DPE1-1 can be electrically connected to the nearest first gate driver 130a among a plurality of gate drivers 130 that are separate from it in the first direction (e.g., direction x).

[0139] When multiple gate drivers 130, which are electrically connected to multiple first pixel circuit units PC1 corresponding to multiple first display elements DPE1 arranged in the corner portion DA2 of the display area DA, are arranged in a stepped manner in the connection portion DA3 and the corner portion DA2 of the display area DA, the multiple gate drivers 130 configured to provide signals to the multiple first pixel circuit units PC1 can be arranged in a panel-embedded manner in the display area DA. Therefore, the area of ​​the image to be displayed on the display device can be expanded to improve the quality and reliability of the display device.

[0140] Furthermore, the distance d1 between the first gate driver 130a located at the uppermost part of the connection portion DA3 and the corner portion DA2 of the display area DA and the first pixel circuit unit PC1-1 adjacent to and electrically connected to it and corresponding to the first display element DPE1-1, and the distance d2 between the gate driver 130b located below the first gate driver 130a and the first pixel circuit unit PC1 adjacent to it and corresponding to the first display element DPE1, can be constant, and the output of the pixel circuit unit PCC located in the corner portion DA2 can be stable.

[0141] According to one or more of the above embodiments, a display device with improved quality and reliability can be realized. However, one or more embodiments are not limited in this respect.

[0142] It should be understood that the embodiments described herein should be considered descriptive in nature only and not for limiting purposes. The description of aspects within each embodiment should generally be considered applicable to other similar aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims and their functional equivalents to be included therein.

Claims

1. A display device, the display device comprising: A base includes a display area and a peripheral area, the display area including a corner portion, a connecting portion and a central portion, and the peripheral area surrounding at least a portion of the display area in a plan view; A first display element is located in the corner portion; A second display element is located in the connecting portion; A first pixel circuit unit is located in the corner portion and is electrically connected to the first display element; The second pixel circuit unit is located in the connection portion and is electrically connected to the second display element; as well as A plurality of gate drivers are arranged in a line along a first direction, wherein a gate driver of the plurality of gate drivers is superimposed on at least a portion of the second pixel circuit unit and electrically connected to the gate driver of the first pixel circuit unit in the connection portion.

2. The display device as claimed in claim 1, wherein, The first pixel circuit unit and the gate driver are spaced apart in a second direction that intersects the first direction.

3. The display device as claimed in claim 2, wherein, The gate driver among the plurality of gate drivers is closest to the first pixel circuit unit.

4. The display device as claimed in claim 1, wherein, The first pixel circuit unit and the second pixel circuit unit are located on the layer above the gate driver.

5. The display device as claimed in claim 1, wherein, The first display element is configured as a plurality of first display elements, the plurality of first display elements including a first-1 display element at the uppermost part of the corner portion.

6. The display device as claimed in claim 5, wherein, The first pixel circuit unit is configured as a plurality of first pixel circuit units, the plurality of first pixel circuit units including the first-1 pixel circuit unit at the uppermost part of the corner portion and electrically connected to the first-1 display element.

7. The display device as claimed in claim 6, wherein, The plurality of gate drivers includes a first gate driver located at the uppermost part of the connection portion and electrically connected to the first-1 pixel circuit unit.

8. The display device as claimed in claim 7, wherein, The plurality of gate drivers are aligned in the first direction.

9. The display device of claim 1, further comprising a clock line stacked with the plurality of gate drivers and extending in the first direction.

10. The display device as claimed in claim 9, wherein, The clock line is configured to electrically connect the plurality of gate drivers to each other.

11. The display device as claimed in claim 1, wherein, The gate driver is electrically connected to the second pixel circuit unit.

12. The display device as claimed in claim 1, wherein, The connecting portion is between one corner portion and another corner portion of the display area, and The central portion of the display area is located inside the corner portion and the connecting portion.

13. A display device, the display device comprising: A base includes a display area and a peripheral area, the display area including a corner portion, a connecting portion and a central portion, and the peripheral area surrounding at least a portion of the display area in a plan view; A first display element is located in the corner portion; A second display element is located in the connecting portion; A first pixel circuit unit is located in the corner portion and is electrically connected to the first display element; The second pixel circuit unit is located in the connection portion and is electrically connected to the second display element; as well as A plurality of gate drivers are arranged in a first direction, offset from each other in a direction from the connection portion toward the corner portion, and include a gate driver in the connection portion that is superimposed with at least a portion of the second pixel circuit unit and electrically connected to the first pixel circuit unit.

14. The display device as claimed in claim 13, wherein, The gate driver among the plurality of gate drivers is closest to the first pixel circuit unit in a second direction that intersects the first direction.

15. The display device as claimed in claim 13, wherein, The first display element is configured as a plurality of first display elements, the plurality of first display elements including a first-1 display element at the uppermost part of the corner portion.

16. The display device as claimed in claim 15, wherein, The first pixel circuit unit is configured as a plurality of first pixel circuit units, the plurality of first pixel circuit units including the first-1 pixel circuit unit at the uppermost part of the corner portion and electrically connected to the first-1 display element.

17. The display device as claimed in claim 16, wherein, The plurality of gate drivers includes a first gate driver located at the uppermost part of the connection portion and electrically connected to the first-1 pixel circuit unit.

18. The display device as claimed in claim 17, wherein, The plurality of gate drivers are offset relative to the first gate driver in a direction toward the corner portion.

19. The display device of claim 14, further comprising a clock line stacked with the plurality of gate drivers, having a stepped shape in a plan view, and configured to electrically connect the plurality of gate drivers to each other.

20. An electronic device including a display device, the display device comprising: A base includes a display area and a peripheral area, the display area including a corner portion, a connecting portion and a central portion, and the peripheral area surrounding at least a portion of the display area in a plan view; A first display element is located in the corner portion; A second display element is located in the connecting portion; A first pixel circuit unit is located in the corner portion and is electrically connected to the first display element; The second pixel circuit unit is located in the connection portion and is electrically connected to the second display element; as well as A plurality of gate drivers are arranged in a line along a first direction, wherein a gate driver of the plurality of gate drivers is superimposed on at least a portion of the second pixel circuit unit and electrically connected to the gate driver of the first pixel circuit unit in the connection portion.

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