Display panel and display device

Abstract

The invention discloses a display panel (PNL) and a display device, and belongs to the technical field of display. The display panel (PNL) includes a plurality of display units (DU) arranged in an array; the second display unit (DUR) comprises a second sub-pixel (PXR) and a pixel driving circuit (PDC), and the first display unit (DUB) comprises a first sub-pixel (PXB) and a pixel driving circuit (PDC); in a second display unit (DUR) in the second display unit column (VDUR), a second sub-pixel (PXR) is electrically connected with an output end of a pixel driving circuit (PDC); in a first display unit (DUB) in the first display unit column (VDUB), a first sub-pixel (PXB) is electrically connected with an output end of a pixel driving circuit (PDC); the first sub-pixels (PXB) in at least part of the second display unit columns (VDUR) are electrically connected with the output ends of the pixel driving circuits (PDC) of the second display units (DUR) in the first display unit columns (VDUB); the second sub-pixels (PXR) in at least part of the first display unit columns (VDUB) are electrically connected with the output ends of the pixel driving circuits (PDC) of the first display units (DUB) in the second display unit columns (VDUR). A display panel (PNL) may reduce driving power consumption.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In some display panels, part of data lines are used to drive sub-pixels of different colors, which results in high driving power consumption of the display panel.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] The present disclosure aims to overcome the shortcomings of the prior art, and provide a display panel and a display device to reduce the power consumption of the display panel.

[0006] According to a first aspect of the present disclosure, a display panel is provided, comprising a plurality of display units arranged in an array; the plurality of display units are arranged into a plurality of display unit columns and a plurality of display unit rows;

[0007] The plurality of display unit columns comprises second display unit columns and first display unit columns arranged alternately along the row direction; the second display unit columns and the first display unit columns each comprise second display units and first display units arranged alternately along the column direction; the second display units of the second display unit columns and the second display units of the first display unit columns are located in different display unit rows; the second display unit comprises a second sub-pixel and a pixel driving circuit, and the first display unit comprises a second sub-pixel and a pixel driving circuit;

[0008] The display panel further comprises a plurality of data lines corresponding to each display unit column; each pixel driving circuit of the second display unit column is electrically connected to a corresponding data line; each pixel driving circuit of the first display unit column is electrically connected to a corresponding data line;

[0009] In the second display unit in the second display unit column, the second sub-pixel is electrically connected to the output end of the pixel driving circuit; in the first display unit in the first display unit column, the first sub-pixel is electrically connected to the output end of the pixel driving circuit;

[0010] At least a portion of the first sub-pixels in the second display unit column are electrically connected to the output terminal of the pixel driving circuit of the second display unit in the first display unit column; at least a portion of the second sub-pixels in the first display unit column are electrically connected to the output terminal of the pixel driving circuit of the first display unit in the second display unit column.

[0011] According to one embodiment of this disclosure, at least some of the first sub-pixels in the second display unit column are located in different rows of the display unit with the pixel driving circuit that is electrically connected to them; at least some of the second sub-pixels in the first display unit column are located in different rows of the display unit with the pixel driving circuit that is electrically connected to them.

[0012] According to one embodiment of this disclosure, the plurality of display unit rows include non-heterogeneous display unit rows and heterogeneous display unit rows arranged alternately along the column direction; the second display unit in the second display unit column and the first display unit in the first display unit column are located in the non-heterogeneous display unit rows, and the first display unit in the second display unit column and the second display unit in the first display unit column are located in the heterogeneous display unit rows;

[0013] At least some of the first sub-pixels in the second display unit column and the pixel driving circuits electrically connected to them are located in two adjacent heterogeneous display unit rows, respectively;

[0014] At least some of the second sub-pixels in the first display unit column and the pixel driving circuits electrically connected to them are located in two adjacent heterogeneous display unit rows, respectively.

[0015] According to one embodiment of the present disclosure, the first sub-pixel in the second display unit column is located in the xth heterogeneous display unit row, and the pixel driving circuit electrically connected to the first sub-pixel in the second display unit column is located in the (x+1)th heterogeneous display unit row;

[0016] The second sub-pixel in the first display unit column is located in the xth heterogeneous display unit row, and the pixel driving circuit electrically connected to the second sub-pixel in the first display unit column is located in the (x+1)th heterogeneous display unit row;

[0017] Where x is a positive integer and x < M, and M is the number of rows of the heterogeneous display units.

[0018] According to one embodiment of the present disclosure, the display panel further includes an auxiliary pixel driving circuit row, the auxiliary pixel driving circuit row including a plurality of second auxiliary pixel driving circuits corresponding one-to-one with each of the second display unit columns and a plurality of first auxiliary pixel driving circuits corresponding one-to-one with each of the first display unit columns.

[0019] The second auxiliary pixel driving circuit is connected to the same data line as each pixel driving circuit in the corresponding second display unit column;

[0020] The first auxiliary pixel driving circuit is connected to the same data trace as each pixel driving circuit in the corresponding first display unit column;

[0021] The second sub-pixel in the Mth heterogeneous display unit row is electrically connected to the second auxiliary pixel driving circuit in the auxiliary pixel driving circuit row;

[0022] The first sub-pixel in the Mth heterogeneous display unit row is electrically connected to the first auxiliary pixel driving circuit in the auxiliary pixel driving circuit row.

[0023] According to one embodiment of the present disclosure, the first sub-pixel in the second display unit column is located in the y-th second display unit column, and the pixel driving circuit electrically connected to the first sub-pixel in the second display unit column is located in the first display unit column between the y-th second display unit column and the y+1-th second display unit column;

[0024] The second sub-pixel in the first display unit column is located in the z-th first display unit column, and the pixel driving circuit electrically connected to the second sub-pixel in the first display unit column is located in the second display unit column between the z-th first display unit column and the z+1-th first display unit column;

[0025] Where y is a positive integer and y < N, N is the number of columns in the second display unit; z is a positive integer and z < Q, Q is the number of columns in the first display unit.

[0026] According to one embodiment of this disclosure, the display panel further includes an auxiliary pixel driving circuit column and an auxiliary data trace, wherein the auxiliary pixel driving circuit column and the auxiliary data trace are located on the side away from the (N-1)th second display unit column and the Qth first display unit column and the Nth second display unit column; the auxiliary pixel driving circuit column includes pixel driving circuits corresponding one-to-one with each of the display unit rows and each pixel driving circuit is electrically connected to the auxiliary data trace;

[0027] The Nth second display unit column is located between the Qth first display unit column and the auxiliary pixel driving circuit column, and the pixel driving circuit electrically connected to the first sub-pixel on the Nth second display unit column is located in the auxiliary pixel driving circuit column; and / or, the Qth first display unit column is located between the Nth second display unit column and the auxiliary pixel driving circuit column, and the pixel driving circuit electrically connected to the second sub-pixel on the Qth first display unit column is located in the auxiliary pixel driving circuit column.

[0028] According to one embodiment of this disclosure, the plurality of display unit columns further includes a plurality of third display unit columns, wherein the third display unit columns are disposed between the second display unit columns and the adjacent first display unit columns;

[0029] The third display unit column includes a plurality of third display units arranged sequentially along the column direction. The third display unit includes a pixel driving circuit and a third sub-pixel electrically connected to the output terminal of the pixel driving circuit.

[0030] The display panel also includes multiple data traces that correspond one-to-one with each of the third display unit columns, and the pixel driving circuits of each of the third display unit columns are electrically connected to the corresponding data traces.

[0031] According to one embodiment of the present disclosure, the display panel is provided with a first transition trace corresponding to a first sub-pixel in the second display unit column, and a second transition trace corresponding to a second sub-pixel in the first display unit column.

[0032] The first sub-pixel in the second display unit column is electrically connected to the output terminal of the pixel driving circuit through the corresponding first adapter line; the second sub-pixel in the first display unit column is electrically connected to the output terminal of the pixel driving circuit through the corresponding second adapter line.

[0033] According to one embodiment of the present disclosure, the display panel includes a substrate, a driving layer, and a pixel layer stacked sequentially; the pixel driving circuit, the first transition trace, and the second transition trace are disposed on the driving layer, and the first sub-pixel and the second sub-pixel are disposed on the pixel layer.

[0034] According to one embodiment of this disclosure, the display panel includes a substrate, a driving layer, and a pixel layer stacked sequentially; the pixel driving circuit is disposed on the driving layer, and the first sub-pixel and the second sub-pixel are disposed on the pixel layer;

[0035] The pixel electrode of the first sub-pixel has a connection area, and the connection area of ​​the pixel electrode of the first sub-pixel is electrically connected to the pixel driving circuit that drives the first sub-pixel through a via; the orthographic projection of the connection area of ​​the pixel electrode of the first sub-pixel of the first display unit on the substrate is located within the orthographic projection of the pixel driving circuit of the first display unit on the substrate.

[0036] The pixel electrode of the second sub-pixel has a connection area, and the connection area of ​​the pixel electrode of the second sub-pixel is electrically connected to the pixel driving circuit that drives the second sub-pixel through a via; the orthographic projection of the connection area of ​​the pixel electrode of the second sub-pixel of the second display unit on the substrate is located within the orthographic projection of the pixel driving circuit of the second display unit on the substrate.

[0037] According to a second aspect of this disclosure, a display device is provided, including the display panel described above.

[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0040] Figure 1 is a schematic diagram of the structure of the display panel in one embodiment of this disclosure.

[0041] Figure 2 is a schematic diagram of the structure of the display panel in one embodiment of this disclosure.

[0042] Figure 3 is a partial cross-sectional view of the display panel in one embodiment of this disclosure.

[0043] Figure 4 is a schematic diagram of the structure of a sub-pixel in one embodiment of this disclosure.

[0044] Figure 5 is a schematic diagram of the structure of a sub-pixel in one embodiment of this disclosure.

[0045] Figure 6 is a schematic diagram of the display unit distribution structure on a display panel in a related technology.

[0046] Figure 7 is a schematic diagram of the display unit distribution structure on the display panel in one embodiment of this disclosure.

[0047] Figure 8 is a schematic diagram of the display unit distribution structure on the display panel in one embodiment of this disclosure.

[0048] Figure 9 is a schematic diagram of the display unit distribution structure on the display panel in one embodiment of this disclosure.

[0049] Figure 10 is a schematic diagram of the display unit distribution structure on the display panel in one embodiment of this disclosure. Detailed Implementation

[0050] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0051] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0052] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and that other elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0053] In this disclosure, when describing the overlapping arrangement of structure A and structure B, it means that structure A and structure B are disposed on different film layers, and the orthographic projection of structure A on the substrate overlaps with the orthographic projection of structure B on the substrate.

[0054] In this disclosure, structural layer C is located on the side of structural layer D away from the substrate. This can be understood as structural layer C being formed on the side of structural layer D away from the substrate. When structural layer C is a patterned structure, a portion of the structure of structural layer C may also be located at the same physical height as or below the physical height of structural layer D, wherein the substrate serves as the height reference.

[0055] This disclosure provides a display panel PNL and a display device employing the display panel PNL. Referring to FIG1, the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA; for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with sub-pixels PX for display; in the peripheral area BB, the display panel PNL may not be provided with sub-pixels PX for display, or the provided sub-pixels PX may not be used for displaying images.

[0056] In one embodiment of this disclosure, the sub-pixels PX in the display panel PNL are thin-film self-emissive light-emitting elements, such as OLED (Organic Light Emitting Diode), PLED (Polymer Light Emitting Diode), or QLED (Quantum Dot Light Emitting Diode). Furthermore, the sub-pixels PX located in the display area AA include sub-pixels PX of various colors. For example, in the example of FIG1, the sub-pixels PX include a second sub-pixel (PXR) for emitting a first color of light, a first sub-pixel PXB for emitting a second color of light, and a third sub-pixel PXG for emitting a third color of light. In one example, the wavelengths of the light emitted by the first sub-pixel PXB, the third sub-pixel PXG, and the second sub-pixel (PXR) increase sequentially; for example, the first sub-pixel PXB emits blue light, the third sub-pixel PXG emits green light, and the second sub-pixel (PXR) emits red light. It is understood that in other embodiments of this disclosure, the sub-pixels PX in the display area AA may also have sub-pixels PX of other colors (e.g., yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, magenta sub-pixels for emitting magenta light, or white sub-pixels for emitting white light, etc.). Of course, in other embodiments of this disclosure, the sub-pixels PX in the display panel PNL may not be thin-film light-emitting elements, for example, they may also be light-emitting elements such as LEDs (inorganic light-emitting diodes), Micro LEDs (micro light-emitting diodes), or Mini LEDs (mini light-emitting diodes).

[0057] In one embodiment of this disclosure, referring to FIG2, the display panel PNL may include a substrate SBT, a driving layer DRL and a pixel layer PXL stacked sequentially. The pixel layer PXL is provided with sub-pixels PX and the driving layer DRL is provided with a pixel driving circuit PDC for driving each sub-pixel PX. Each sub-pixel PX emits light under the drive of the electrically connected pixel driving circuit PDC, for example, each emits light independently, thereby realizing the display of the image.

[0058] Optionally, the substrate SBT can be an inorganic material substrate or an organic material substrate; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrates. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT may include polyimide.

[0059] Optionally, in the driving layer DRL, any pixel driving circuit may include a thin-film transistor and a storage capacitor. Further, the thin-film transistor may be selected from top-gate thin-film transistors, bottom-gate thin-film transistors, or dual-gate thin-film transistors; the material of the active layer of the thin-film transistor may be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type thin-film transistor or a P-type thin-film transistor.

[0060] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. Exemplarily, in some embodiments, some thin-film transistors in a pixel driving circuit can be N-type transistors and some thin-film transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some thin-film transistors can be low-temperature polycrystalline silicon semiconductor material, and the active layer material of some thin-film transistors can be metal-oxide-semiconductor material. In some embodiments of this disclosure, the thin-film transistor is a low-temperature polycrystalline silicon transistor. In other embodiments of this disclosure, some thin-film transistors are low-temperature polycrystalline silicon transistors, and some thin-film transistors are metal-oxide-semiconductor transistors.

[0061] In one embodiment of this disclosure, referring to FIG3, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, a planarization layer PLN, and other film layers stacked between the substrate SBT and the pixel layer PXL. Each thin-film transistor and storage capacitor can be formed from the semiconductor layer SCL, gate insulating layer GI, gate layer GT, interlayer dielectric layer ILD, source / drain metal layer SD, and other film layers; of course, other film layers can also be used. The positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor (as part of the active layer), and can also be used to form partial wiring or conductive structures if necessary. The gate layer can be used to form one or more gate layer wirings such as scan wiring, reset control wiring, and light emission control wiring, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrodes of the storage capacitor. The source / drain metal layer can be used to form data traces, drive power supply voltage traces, and other source / drain metal layer traces, and can also be used to form part of the electrode plate of the storage capacitor. Of course, in other embodiments of this disclosure, the driving layer DRL may also include other film layers as needed, such as a light-shielding layer located between the semiconductor layer SCL and the substrate SBT. As needed, any one of the above-mentioned semiconductor layer SCL, gate layer GT, source / drain metal layer SD, etc., can also be multiple layers. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate layers GT; correspondingly, the number or type of insulating film layers (such as gate insulating layer GI, interlayer dielectric layer ILD, planarization layer PLN, etc.) in the driving layer DRL can be adaptively increased or decreased, or new insulating film layers can be added as needed.

[0062] Optionally, the driving layer DRL may also include a passivation layer, which may be disposed on the surface of the source / drain metal layer SD away from the substrate SBT, in order to protect the source / drain metal layer SD.

[0063] As an example, referring to Figure 3, the driving layer DRL may include the following layers sequentially stacked on one side of the substrate SBT: a first inorganic buffer layer BUFA, a first semiconductor layer SCL1, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BUFB, a second gate layer GT2, a second gate insulating layer GI2, a second semiconductor layer SCL2, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a third source / drain metal layer SD3, and a third planarization layer PLN3. In this example, the driving layer DRL has two semiconductor layers SCL, namely the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The materials of the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can be different; for example, the material of the first semiconductor layer SCL1 can be low-temperature polycrystalline silicon, and the material of the second semiconductor layer SCL2 can be a metal-oxide-semiconductor material. In this example, the driving layer DRL has three gate layers GT, namely a first gate layer GT1, a second gate layer GT2, and a third gate layer GT3; correspondingly, the driving layer DRL has three gate insulating layers GI, namely a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3. In this example, the driving layer DRL has three source / drain metal layers SD, namely a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3; correspondingly, the driving layer DRL has three planarization layers PLN, namely a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3. It is understood that the example in Figure 3 is merely a specific example of the driving layer DRL according to an embodiment of this disclosure. Depending on the needs, the driving layer DRL of the display panel PNL can also adopt other structures, such as the driving layer DRL including only two source / drain metal layers SD, or the driving layer DRL including four source / drain metal layers SD, etc.

[0064] In one embodiment of this disclosure, referring to FIG3, the pixel layer PXL may include a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes PE in the display area of ​​the display panel. The pixel definition layer PDL has multiple through-holes corresponding to the multiple pixel electrodes PE, with each pixel hole exposing at least a portion of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EFL), thereby defining the light-emitting area and light-emitting area of ​​the sub-pixel PX. In this embodiment, the area of ​​the pixel electrode PE exposed by the pixel definition layer PDL can be referred to as the light-emitting area of ​​that pixel electrode PE. The common electrode layer COML covers the light-emitting functional layer EFL as a common electrode. The pixel electrodes PE and the common electrode layer COML provide electrons, holes, and other charge carriers to the light-emitting functional layer EFL, causing the light-emitting functional layer EFL to emit light. The light-emitting functional layer (EFL) is located between the pixel electrode (PE) and the common electrode layer (COML), and can serve as the light-emitting functional unit of the sub-pixel (PX). The pixel electrode (PE), the common electrode layer (COML), and the light-emitting functional unit form the light-emitting element of the sub-pixel (PX). One of the pixel electrode (PE) and the common electrode layer (COML) serves as the anode of the sub-pixel (PX), and the other serves as the cathode of the sub-pixel (PX).

[0065] In one embodiment of this disclosure, the planarization layer PLN (e.g., the third planarization layer PLN3 in FIG. 3) closest to the pixel layer PXL has a connection via exposing the source / drain metal layer SD (e.g., the third source / drain metal layer SD3 in FIG. 3) closest to the pixel layer PXL. The pixel electrode PE is electrically connected to the source / drain metal layer SD closest to the pixel layer PXL through the connection via. In this embodiment of the disclosure, the region of the pixel electrode PE located in the connection via is referred to as the connection region CNT of the pixel electrode PE; the connection region CNT of the pixel electrode PE is electrically connected to the source / drain metal layer SD in the driving layer DRL through the via; this allows the connection region CNT of the pixel electrode PE of the sub-pixel PX to be electrically connected to the output terminal of the pixel driving circuit PDC driving the sub-pixel PX through the via.

[0066] It is understandable that the materials and layers of the EFL (Emitting Functional Layer) differ depending on the type of sub-pixel (PX). For example, referring to Figure 4, when the sub-pixel (PX) is an OLED, the EFL may include an organic light-emitting layer (EML), and may include one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the organic light-emitting layer (EML) may include a host material and a guest material, where the guest material can be a fluorescent dopant or a phosphorescent dopant, particularly a thermally activated delayed fluorescence material. When the OLED uses a stacked structure, a charge generation layer may also be provided in the EFL. As another example, referring to Figure 5, when the sub-pixel (PX) is a QLED, the EFL may include a quantum dot layer (QDL), and may include one or more of the following: a hole injection layer (HIL), an electron transport layer (ETL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the quantum dot layer (QDL) can contain quantum dot particles, which can be interconnected through surface-modified groups. When the QLED adopts a stacked structure, a charge generation layer can also be provided in the light-emitting functional layer (EFL).

[0067] In one embodiment of this disclosure, referring to FIG3, the display panel PNL may further be provided with an encapsulation layer, such as a thin-film encapsulation layer TFE. The thin-film encapsulation layer TFE may be disposed on the surface of the pixel layer PXL away from the substrate SBT, and may include alternately stacked inorganic encapsulation layers and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing material aging in the pixel layer PXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer PXL away from the substrate SBT. Of course, in other embodiments of this disclosure, the display panel may also be provided with other types of encapsulation layers, such as a thin-film encapsulation layer using all inorganic materials.

[0068] In this embodiment, the display panel PNL is provided with sub-pixels PX and pixel driving circuits PDC. The sub-pixels PX emit light under the drive of the pixel driving circuits PDC. Based on the spatial relationship between the sub-pixels PX and the pixel driving circuits PDC, spatially corresponding sub-pixels PX and pixel driving circuits PDC can be combined to form a display unit DU. In one example, the pixel electrode of the sub-pixel PX has a connection region, and the connection region of the sub-pixel PX is electrically connected to the pixel driving circuit PDC used to drive the sub-pixel PX through a via. In the sub-pixels PX and pixel driving circuits PDC of the same display unit DU, the orthographic projection of the connection region of the pixel electrode of the sub-pixel PX onto the substrate SBT lies within the orthographic projection of the arrangement area of ​​the pixel driving circuit PDC onto the substrate SBT. In other words, in this example, when the orthographic projection of the connection region of the pixel electrode of a sub-pixel PX onto the substrate SBT lies within the orthographic projection of the arrangement area of ​​a pixel driving circuit PDC onto the substrate SBT, the sub-pixel PX and the pixel driving circuit PDC constitute a display unit DU. It is understandable that each sub-pixel PX used to form the display unit DU corresponds one-to-one with each pixel driving circuit PDC. Each sub-pixel PX forms the display unit DU with only one pixel driving circuit PDC, and each pixel driving circuit PDC forms the display unit DU with only one sub-pixel PX.

[0069] Referring to Figure 1, the display panel PNL includes arrayed display units DU, that is, the display units DU are arranged in an array along the row direction DH and the column direction DV. The display panel PNL can arrange multiple display unit columns VDU and multiple display unit rows HDU. Each display unit column VDU includes multiple display units DU arranged sequentially along the column direction DV, and these multiple display unit columns VDU are arranged sequentially along the row direction DH. Each display unit row HDU includes multiple display units DU arranged sequentially along the row direction DH, and these multiple display unit rows HDU are arranged sequentially along the column direction DV. Referring to Figure 1, the display panel PNL also has data traces DL corresponding one-to-one with each display unit column VDU. Each pixel driving circuit PDC of a display unit column VDU is electrically connected to its corresponding data trace DL. Thus, the data trace DL can apply data voltage to the pixel driving circuit PDC, and the pixel driving circuit PDC drives the electrically connected sub-pixels PX according to the data voltage. Referring to Figure 1, the display panel PNL also has multiple GLs corresponding one-to-one with each display unit row HDU, and each pixel driving circuit PDC of a display unit row HDU is electrically connected to its corresponding GL. In this embodiment of the disclosure, the direction in which the data trace DL extends as a whole can be called the column direction DV, and the direction in which the GL extends as a whole can be called the row direction DH; the row direction DH and the column direction DV intersect, for example, the row direction DH is perpendicular to the column direction DV.

[0070] Figure 6 is a schematic diagram of a display panel PNL in a related technology. Referring to Figure 6, in this related technology, the display panel PNL includes arrayed display units DU, but sub-pixels PX in the same display unit DU are electrically connected to a pixel driving circuit PDC. In other words, the pixel driving circuit PDC in the display unit DU drives the sub-pixels PX in that display unit DU. However, some display unit columns VDU do not only include sub-pixels PX of one color, but also include sub-pixels PX of multiple colors. For example, in the example in Figure 6, one display unit column VDU includes a second sub-pixel (PXR) and a first sub-pixel PXB alternately arranged along the column direction DV. The data trace DL driving this display unit column VDU needs to switch data voltages back and forth, resulting in high driving power consumption.

[0071] Figure 7 is a partial structural diagram of the display panel PNL in one embodiment of this disclosure. Referring to Figure 7, in this embodiment of the disclosure, at least some of the sub-pixels PX and pixel driving circuits PDC of the display unit DU are not electrically connected. The display unit DU where the sub-pixel PX is a second sub-pixel (PXR) is referred to as the second display unit DUR in this embodiment of the disclosure; the display unit DU where the sub-pixel PX is a first sub-pixel PXB is referred to as the first display unit DUB in this embodiment of the disclosure. For example, in the example of Figure 10, the first sub-pixel PXB located in the first row and second column is labeled as PXB12, and the pixel driving circuit PDC located in the first row and second column is labeled as PDC12. The sub-pixel PXB12 and the pixel driving circuit PDC12 together form a first display unit DUB. The second sub-pixel (PXR) located in the 1st row and 4th column is labeled (PXR)14, and the pixel driving circuit PDC located in the 1st row and 4th column is labeled PDC14. This sub-pixel (PXR)14 and the pixel driving circuit PDC14 together form a second display unit DUR. The first sub-pixel PXB located in the 1st row and 6th column is labeled PXB16, and the pixel driving circuit PDC located in the 1st row and 6th column is labeled PDC16. This sub-pixel PXB16 and the pixel driving circuit PDC16 together form a first display unit DUB. The second sub-pixel (PXR) located in the 2nd row and 2nd column is labeled (PXR)22, and the pixel driving circuit PDC located in the 2nd row and 2nd column is labeled PDC22. This sub-pixel (PXR)22 and the pixel driving circuit PDC22 together form a second display unit DUR. In the example of Figure 10, the illustrated display panel PNL has only four rows of sub-pixels PX, that is, the display panel PNL has four rows of display units HDU. It is understood that Figure 10 is only an example of a display panel PNL with four rows of display units HDU. In other embodiments of this disclosure, the number of display unit rows HDU can be more, for example, 500 to 8000.

[0072] The plurality of display unit columns VDUs include second display unit columns VDURs and first display unit columns VDUBs arranged alternately along the row direction DH; both the second display unit columns VDURs and the first display unit columns VDUBs include second display units DURs and first display units DUBs arranged alternately along the column direction DV; the second display units DURs of the second display unit columns VDURs and the second display units DURs of the first display unit columns VDUBs are located in different display unit rows HDUs; the second display unit DUR includes a second sub-pixel (PXR) and a pixel driving circuit PDC, and the first display unit DUB includes a first sub-pixel PXB and a pixel driving circuit PDC; In the second display unit DUR of the second display unit column VDUR, the second sub-pixel (PXR) is electrically connected to the output terminal of the pixel driving circuit PDC; in the first display unit DUB of the first display unit column VDUB, the first sub-pixel PXB is electrically connected to the output terminal of the pixel driving circuit PDC; at least a portion of the first sub-pixels PXB in the second display unit column VDUR are electrically connected to the output terminal of the pixel driving circuit PDC of the second display unit DUR in the first display unit column VDUB; at least a portion of the second sub-pixels (PXR) in the first display unit column VDUB are electrically connected to the output terminal of the pixel driving circuit PDC of the first display unit DUB in the second display unit column VDUR.

[0073] In this embodiment, when the second display unit DUR is located in the second display unit column VDUR, the pixel driving circuit PDC of the second display unit DUR is electrically connected to the second sub-pixel (PXR) of the second display unit DUR; when the second display unit DUR is located in the first display unit column VDUB, the pixel driving circuit PDC of the second display unit DUR is not electrically connected to the second sub-pixel (PXR) of the second display unit DUR. When the first display unit DUB is located in the first display unit column VDUB, the pixel driving circuit PDC of the first display unit DUB is electrically connected to the first sub-pixel PXB of the first display unit DUB; when the first display unit DUB is located in the second display unit column VDUR, the pixel driving circuit PDC of the first display unit DUB is not electrically connected to the first sub-pixel PXB of the first display unit DUB.

[0074] In this embodiment, each pixel driving circuit (PDC) in the second display unit column (VDUR) is electrically connected to the corresponding data trace (DL) of the second display unit column (VDUR). The output terminal of the pixel driving circuit (PDC) of the first display unit (DUB) in the second display unit column (VDUR) is not electrically connected to the first sub-pixel (PXB) of the first display unit (DUB). When the pixel driving circuit (PDC) of the first display unit (DUB) in the second display unit column (VDUR) is used to drive the sub-pixel (PX), the pixel driving circuit (PDC) is electrically connected to the second sub-pixel (PXR) located in the first display unit column (VDUB). Therefore, the pixel driving circuit (PDC) in the second display unit column (VDUR) is not used to drive the first sub-pixel (PXB), but is partially or entirely used to drive the second sub-pixel (PXR). The data trace (DL) electrically connected to the second display unit column (VDUR) only needs to be loaded with the driving voltage required by the second sub-pixel (PXR), without having to switch back and forth between the driving voltage required by the second sub-pixel (PXR) and the driving voltage required by the first sub-pixel (PXB), thereby reducing the driving power consumption of the second display unit column (VDUR).

[0075] Correspondingly, each pixel driving circuit (PDC) in the first display unit column VDUB is electrically connected to the corresponding data trace (DL) of the first display unit column VDUB. The output of the pixel driving circuit (PDC) of the second display unit (DUR) in the first display unit column VDUB is not electrically connected to the second sub-pixel (PXR) of the second display unit (DUR); when the pixel driving circuit (PDC) of the second display unit (DUR) in the first display unit column VDUB is used to drive the sub-pixel PX, the pixel driving circuit (PDC) is electrically connected to the first sub-pixel PXB located in the second display unit column VDUB. Therefore, the pixel driving circuit (PDC) in the first display unit column VDUB is not used to drive the second sub-pixel (PXR), but is partially or entirely used to drive the first sub-pixel PXB; the data trace (DL) electrically connected to the first display unit column VDUB only needs to load the driving voltage required by the first sub-pixel PXB, without having to switch back and forth between the driving voltage required by the first sub-pixel PXB and the driving voltage required by the second sub-pixel (PXR), thereby reducing the driving power consumption of the first display unit column VDUB.

[0076] In one example, the pixel electrode of the first sub-pixel PXB has a connection region, and the connection region of the pixel electrode of the first sub-pixel PXB is electrically connected to the pixel driving circuit PDC that drives the first sub-pixel PXB through a via; the orthographic projection of the connection region of the pixel electrode of the first sub-pixel PXB of the first display unit DUB on the substrate SBT is located within the orthographic projection of the pixel driving circuit PDC of the first display unit DUB on the substrate SBT.

[0077] In one example, the pixel electrode of the second sub-pixel (PXR) has a connection region, and the connection region of the pixel electrode of the second sub-pixel (PXR) is electrically connected to the pixel driving circuit PDC that drives the second sub-pixel (PXR) through a via; the orthographic projection of the connection region of the pixel electrode of the second sub-pixel (PXR) of the second display unit DUR on the substrate SBT is located within the orthographic projection of the pixel driving circuit PDC of the second display unit DUR on the substrate SBT.

[0078] In one embodiment of this disclosure, the sub-pixel PX further includes a third sub-pixel PXG, and correspondingly, the display unit DU further includes a third display unit DUG; the third display unit DUG includes the third sub-pixel PXG and a pixel driving circuit PDC. The pixel electrode of the third sub-pixel PXG has a connection region, and the connection region of the pixel electrode of the third sub-pixel PXG is electrically connected to the pixel driving circuit PDC that drives the third sub-pixel PXG through a via; the orthographic projection of the connection region of the pixel electrode of the third sub-pixel PXG of the third display unit DUG onto the substrate SBT is located within the orthographic projection of the pixel driving circuit PDC of the third display unit DUG onto the substrate SBT. In one example, the third sub-pixel PXG of the third display unit DUG is electrically connected to the pixel driving circuit PDC of the third display unit DUG, that is, the third display unit DUG includes the pixel driving circuit PDC and the third sub-pixel PXG electrically connected to the output terminal of the pixel driving circuit PDC.

[0079] In one embodiment of this disclosure, the display unit column VDU includes a third display unit column VDUG, which comprises a plurality of third display units DUGs arranged sequentially along the column direction DV. For example, each display unit DU in the third display unit column VDUG is a third display unit DUG. The display panel PNL also includes a plurality of data traces DL corresponding one-to-one with each of the third display unit columns VDUG. The pixel driving circuit PDC of each of the third display unit columns VDUG is electrically connected to the corresponding data trace DL. Therefore, the data trace DL corresponding to the third display unit column VDUG only needs to apply the driving voltage required by the third sub-pixel PXG to each pixel driving circuit PDC, without needing to switch back and forth between the driving voltages required by sub-pixels PX of different colors.

[0080] In one embodiment of this disclosure, the third display unit column VDUG is disposed between the second display unit column VDUR and the adjacent first display unit column VDUB.

[0081] In this embodiment, based on whether the sub-pixels PX and the pixel driving circuit PDC of a display unit DU are electrically connected, the display unit DU can be divided into a driving type display unit DU and a discrete type display unit DU. Specifically, when a sub-pixel PX in a display unit DU is electrically connected to the pixel driving circuit PDC of that display unit DU, that is, when the pixel driving circuit PDC of the display unit DU drives the sub-pixel PX in the display unit DU, the display unit DU is a driving type display unit DU. When a sub-pixel PX in a display unit DU is not electrically connected to the pixel driving circuit PDC of that display unit DU, that is, when the pixel driving circuit PDC of the display unit DU is not used to drive the sub-pixel PX in the display unit DU, the display unit DU is a discrete type display unit DU.

[0082] Based on whether the sub-pixels PX and pixel driving circuits PDC of the display units DU in the display unit column (VDU) are electrically connected, display unit columns (VDU) can be divided into two categories: heterogeneous display unit columns (VDUM) and non-heterogeneous display unit columns (VDUN). In a non-heterogeneous display unit column (VDUN), each display unit DU is a driven display unit DU; for example, the third display unit column (VDUG) is a non-heterogeneous display unit column (VDUN). In a heterogeneous display unit column (VDUM), at least one display unit DU is a discrete display unit DU; for example, the second display unit column (VDUR) and the first display unit column (VDUB) are both heterogeneous display unit columns (VDUM). In one example, along the row direction (DH), heterogeneous display unit columns (VDUM) and non-heterogeneous display unit columns (VDUN) are alternately arranged; within each heterogeneous display unit column (VDUM), the third display unit column (VDUG) and the second display unit column (VDUR) are alternately arranged.

[0083] Based on whether the sub-pixels PX and pixel driving circuits PDC of the display units DU in the display unit row HDU are electrically connected, display unit rows HDU can be divided into two categories: heterogeneous display unit rows HDUM and non-heterogeneous display unit rows HDUN. In the non-heterogeneous display unit row HDUN, each display unit DU is a driven display unit DU; for example, the second display unit DUR in the second display unit column VDUR and the first display unit DUB in the first display unit column VDUB can be located in the non-heterogeneous display unit row HDUN. In the heterogeneous display unit row HDUM, at least one display unit DU is a discrete display unit DU; for example, the first display unit DUB in the second display unit column VDUR and the second display unit DUR in the first display unit column VDUB can be located in the heterogeneous display unit row HDUM. In one example, along the column direction DV, heterogeneous display unit rows HDUM and non-heterogeneous display unit rows HDUN are alternately arranged.

[0084] In one embodiment of this disclosure, at least a portion of the first sub-pixels (PXB) in the second display unit column VDUR are located in different display unit rows (HDUs) with electrically connected pixel driving circuits (PDCs); at least a portion of the second sub-pixels (PXR) in the first display unit column VDUB are located in different display unit rows (HDUs) with electrically connected pixel driving circuits (PDCs). In this embodiment, the first sub-pixel (PXB) of the first display unit DUB in one heterogeneous display unit row (HDUM) is electrically connected to the output of the pixel driving circuit (PDC) of the second display unit DUR in another heterogeneous display unit row (HDUM); the second sub-pixel (PXR) of the second display unit DUR in one heterogeneous display unit row (HDUM) is electrically connected to the output of the pixel driving circuit (PDC) of the first display unit DUB in another heterogeneous display unit row (HDUM). For example, in the non-edge area of ​​the display area, the first sub-pixel PXB in the second display unit column VDUR and its electrically connected pixel driving circuit PDC are respectively located in two adjacent heterogeneous display unit rows HDUM; in the non-edge area of ​​the display area, the second sub-pixel (PXR) in the first display unit column VDUB and its electrically connected pixel driving circuit PDC are respectively located in two adjacent heterogeneous display unit rows HDUM. In this embodiment, the sub-pixel PX and pixel driving circuit PDC of the discrete display unit DU are located in two adjacent heterogeneous display unit rows HDUM, which can reduce the routing difficulty of the display panel PNL.

[0085] As an example, the first sub-pixel PXB in the second display unit column VDUR is located in the x-th heterogeneous display unit row HDUM, and the pixel driving circuit PDC electrically connected to the first sub-pixel PXB in the second display unit column VDUR is located in the (x+1)-th heterogeneous display unit row HDUM; the second sub-pixel (PXR) in the first display unit column VDUB is located in the x-th heterogeneous display unit row HDUM, and the pixel driving circuit PDC electrically connected to the second sub-pixel (PXR) in the first display unit column VDUB is located in the (x+1)-th heterogeneous display unit row HDUM; where x is a positive integer and x < M, and M is the number of heterogeneous display unit rows HDUM.

[0086] For example, let HDUM(i) represent the i-th heterogeneous display unit row HDUM, and let VDUM(j) represent the j-th heterogeneous display unit column VDUM. Here, i is a positive integer and i < M, j is a positive integer and j < Q + N, N is the number of second display unit columns VDUR, and Q is the number of first display unit columns VDUB. Display unit DU(i,j) represents a display unit DU located in the heterogeneous display unit row HDUM(i) and the heterogeneous display unit column VDUM(j). This display unit DU is a discrete display unit DU; the sub-pixel PX of display unit DU(i,j) is represented as sub-pixel PX(i,j), and the pixel driving circuit PDC of display unit DU(i,j) is represented as pixel driving circuit PDC(i,j). Sub-pixel PX(i,j) is electrically connected to pixel driving circuit PDC(i+1,j+1), that is, pixel driving circuit PDC(i+1,j+1) drives sub-pixel PX(i,j).

[0087] In one example, referring to Figure 8, the display panel PNL further includes an auxiliary pixel driving circuit row D-HPDC, which includes a plurality of second auxiliary pixel driving circuits PDCR corresponding to each of the second display unit columns VDUR and a plurality of first auxiliary pixel driving circuits PDCB corresponding to each of the first display unit columns VDUB; the second auxiliary pixel driving circuits PDCR and the corresponding pixel driving circuits PDC in the second display unit column VDUR are connected to the same data trace DL; the first auxiliary pixel driving circuits PDCB and the corresponding pixel driving circuits PDC in the first display unit column VDUB are connected to the same data trace DL; the second sub-pixel (PXR) in the Mth heterogeneous display unit row HDUM is electrically connected to the second auxiliary pixel driving circuit PDCR in the auxiliary pixel driving circuit row D-HPDC, and the first sub-pixel PXB in the Mth heterogeneous display unit row HDUM is electrically connected to the first auxiliary pixel driving circuit PDCB in the auxiliary pixel driving circuit row D-HPDC. Thus, the auxiliary pixel driving circuit line D-HPDC can drive the sub-pixels PX of the split display units DU in the last heterogeneous display unit line HDUM, such as driving the second sub-pixel (PXR) and the first sub-pixel PXB in the last heterogeneous display unit line HDUM.

[0088] In some examples, the auxiliary pixel driving circuit row D-HPDC also includes a third auxiliary pixel driving circuit PDCG corresponding to each of the third display unit columns VDUG. The third auxiliary pixel driving circuit PDCG and the corresponding pixel driving circuit PDC in the third display unit column VDUG are connected to the same data trace DL and arranged in a straight line. Furthermore, the display panel PNL is also provided with sub-pixels PX corresponding to each pixel driving circuit PDC in the auxiliary pixel driving circuit row D-HPDC. The sub-pixels PX and the corresponding pixel driving circuit PDC form display units DU. This allows the auxiliary pixel driving circuit row D-HPDC and the corresponding sub-pixels PX to form an auxiliary display unit row HDU. The sub-pixels PX in the auxiliary display unit row HDU may not be used for display, but the uniformity of the sub-pixels PX in adjacent display unit rows HDU can be improved.

[0089] For example, let HDUM(M) represent the Mth heterogeneous display unit row HDUM, and let VDUM(j) represent the jth heterogeneous display unit column VDUM. j is a positive integer and j < Q + N, where N is the number of second display unit columns VDUR and Q is the number of first display unit columns VDUB. Display unit DU(M,j) represents a display unit DU located in the heterogeneous display unit row HDUM(M) and the heterogeneous display unit column VDUM(j), and this display unit DU is a discrete display unit DU; the sub-pixel PX of display unit DU(M,j) is represented as sub-pixel PX(M,j), and the pixel driving circuit PDC of display unit DU(M,j) is represented as pixel driving circuit PDC(M,j). The pixel driving circuit PDC located in the auxiliary pixel driving circuit row D-HPDC and corresponding to the heterogeneous display unit column VDUM(j) is called the pixel driving circuit PDC(M+1,j); the sub-pixel PX(M,j) is electrically connected to the pixel driving circuit PDC(M+1,j+1), that is, the pixel driving circuit PDC(M+1,j+1) drives the sub-pixel PX(M,j).

[0090] In one embodiment of this disclosure, the sub-pixels PX and pixel driving circuits PDC of the discrete display unit DU are respectively located in two adjacent heterogeneous display unit columns VDUM. Specifically, at least a portion of the first sub-pixels PXB of the first display unit DUB in the second display unit column VDUR are electrically connected to the pixel driving circuits PDC in the second display unit DUR in the adjacent first display unit column VDUB; at least a portion of the second sub-pixels (PXR) of the second display unit DUR in the first display unit DUB are electrically connected to the pixel driving circuits PDC in the first display unit DUB in the adjacent second display unit column VDUR. This reduces the routing complexity of the display panel PNL.

[0091] In one example, the first sub-pixel PXB in the second display unit column VDUR is located in the y-th second display unit column VDUR, and the pixel driving circuit PDC electrically connected to the first sub-pixel PXB in the second display unit column VDUR is located in the first display unit column VDUB between the y-th and y+1-th second display unit columns VDUR; the second sub-pixel (PXR) in the first display unit column VDUB is located in the z-th first display unit column VDUB, and the pixel driving circuit PDC electrically connected to the second sub-pixel (PXR) in the first display unit column VDUB is located in the second display unit column VDUR between the z-th and z+1-th first display unit columns VDUB; where y is a positive integer and y < N, N is the number of second display unit columns VDUR; z is a positive integer and z < Q, Q is the number of first display unit columns VDUB.

[0092] In one example, the i-th heterogeneous display unit row HDUM(i) represents the heterogeneous display unit row HDUM, and the j-th heterogeneous display unit column VDUM(j) represents the heterogeneous display unit column VDUM. Here, i is a positive integer and i < M, j is a positive integer; and j < Q + N, where N is the number of second display unit columns VDUR, and Q is the number of first display unit columns VDUB. Display unit DU(i,j) represents a display unit DU located in the heterogeneous display unit row HDUM(i) and the heterogeneous display unit column VDUM(j), and this display unit DU is a discrete display unit DU; the sub-pixel PX of display unit DU(i,j) is represented as sub-pixel PX(i,j), and the pixel driving circuit PDC of display unit DU(i,j) is represented as pixel driving circuit PDC(i,j). Sub-pixel PX(i,j) is electrically connected to pixel driving circuit PDC(i+1,j+1), meaning that pixel driving circuit PDC(i+1,j+1) drives sub-pixel PX(i,j). When heterogeneous display unit column VDUM(j) is the second display unit column VDUR, heterogeneous display unit column VDUM(j+1) is the first display unit column VDUB, and heterogeneous display unit column VDUM(j+2) is the second display unit column VDUR. At this time, display unit DU(i,j) is the first display unit DUB, and display unit DU(i+1,j+1) is the second display unit DUR. At this time, sub-pixel PX(i,j) is the first sub-pixel PXB located in the second display unit column VDUR, and pixel driving circuit PDC(i+1,j+1) is the pixel driving circuit PDC located in the first display unit column VDUB. When the heterogeneous display unit column VDUM(j) is the first display unit column VDUB, the heterogeneous display unit column VDUM(j+1) is the second display unit column VDUR, and the heterogeneous display unit column VDUM(j+2) is the first display unit column VDUB. At this time, display unit DU(i,j) is the second display unit DUR, and display unit DU(i+1,j+1) is the first display unit DUB. At this time, sub-pixel PX(i,j) is the second sub-pixel (PXR) located in the first display unit column VDUB, and pixel driving circuit PDC(i+1,j+1) is the pixel driving circuit PDC located in the second display unit column VDUR.

[0093] In one example, referring to Figure 9, the display panel PNL further includes an auxiliary pixel driving circuit column D-VPDC and auxiliary data traces DL located on the side away from the (N-1)th second display unit column VDUR of the Qth first display unit column VDUB and the Nth second display unit column VDUR. The auxiliary pixel driving circuit column D-VPDC includes pixel driving circuits PDC corresponding one-to-one with each display unit column VDU, and each pixel driving circuit PDC is electrically connected to the auxiliary data traces DL. Therefore, the auxiliary pixel driving circuit column D-VPDC is located on the side away from the (Q+N)th heterogeneous display unit column VDUM of the Q+N-1th heterogeneous display unit column VDUM.

[0094] The Nth second display unit column VDUR is located between the Qth first display unit column VDUB and the H pixel driving circuit PDC, and the pixel driving circuit PDC electrically connected to the first sub-pixel PXB on the Nth second display unit column VDUR is located in the H pixel driving circuit PDC; and / or, the Qth first display unit column VDUB is located between the Nth second display unit column VDUR and the H pixel driving circuit PDC, and the pixel driving circuit PDC electrically connected to the second sub-pixel (PXR) on the Qth first display unit column VDUB is located in the H pixel driving circuit PDC.

[0095] In other words, after the last heterogeneous display unit column VDUM, an additional auxiliary pixel driving circuit column D-VPDC is provided. This auxiliary pixel driving circuit column D-VPDC can provide the pixel driving circuit PDC required to drive the first sub-pixel PXB or the second sub-pixel (PXR) in the last heterogeneous display unit column VDUM. When the last heterogeneous display unit column VDUM is the second display unit column VDUR, the auxiliary pixel driving circuit column D-VPDC can provide the pixel driving circuit PDC required to drive the first sub-pixel PXB in the last heterogeneous display unit column VDUM; when the last heterogeneous display unit column VDUM is the first display unit column VDUB, the auxiliary pixel driving circuit column D-VPDC can provide the pixel driving circuit PDC required to drive the second sub-pixel (PXR) in the last heterogeneous display unit column VDUM.

[0096] In some examples, the auxiliary pixel driving circuit column D-VPDC also includes a pixel driving circuit PDC corresponding one-to-one with each non-heterogeneous display unit row HDUN. This pixel driving circuit PDC is arranged in the same row as the corresponding pixel driving circuit PDC in the HDUN, for example, connected to the same scan trace. Furthermore, the display panel PNL also has sub-pixels PX corresponding one-to-one with each pixel driving circuit PDC in the auxiliary pixel driving circuit column D-VPDC. These sub-pixels PX and their corresponding pixel driving circuit PDCs form display units DU. This allows the V pixel driving circuit PDC and its corresponding sub-pixels PX to form an auxiliary display unit column VDU. The sub-pixels PX in the auxiliary display unit column VDU may not be used for display, but can improve the uniformity of sub-pixels PX in adjacent display unit columns VDU.

[0097] In one example, when the display panel PNL is provided with auxiliary pixel driving circuit row D-HPDC, the auxiliary pixel driving circuit row D-VPDC also includes a pixel driving circuit PDC corresponding to the auxiliary pixel driving circuit row D-HPDC, and the pixel driving circuit PDC is connected to each pixel driving circuit PDC of the auxiliary pixel driving circuit row D-HPDC on the same scan trace.

[0098] For example, let HDUM(i) represent the i-th heterogeneous display unit row HDUM, and let VDUM(Q+N) represent the Q+N-th heterogeneous display unit column VDUM, which is the last heterogeneous display unit column VDUM. Here, i is a positive integer and i≤M, and j is a positive integer. Display unit DU(i,Q+N) represents a display unit DU located in the heterogeneous display unit row HDUM(i) and the heterogeneous display unit column VDUM(Q+N). This display unit DU is a discrete display unit DU. The sub-pixel PX of display unit DU(i,Q+N) is represented as sub-pixel PX(i,Q+N), and the pixel driving circuit PDC of display unit DU(i,Q+N) is represented as pixel driving circuit PDC(i,Q+N). The display panel PNL is provided with an auxiliary pixel driving circuit column D-VPDC. The pixel driving circuit PDC corresponding to the heterogeneous display unit row HDUM(i) in this auxiliary pixel driving circuit column D-VPDC can be represented as pixel driving circuit PDC(i,Q+N+1); the pixel driving circuit PDC corresponding to the auxiliary pixel driving circuit row D-HPDC in this auxiliary pixel driving circuit column D-VPDC can be represented as pixel driving circuit PDC(M+1,Q+N+1). Sub-pixels PX(i,Q+N) are electrically connected to pixel driving circuits PDC(i+1,Q+N+1), meaning that pixel driving circuits PDC(i+1,Q+N+1) drive sub-pixels PX(i,Q+N).

[0099] When the heterogeneous display unit column VDUM(Q+N) is the second display unit column VDUR, then VDUM(Q+N) is the Nth second display unit column VDUR, and VDUM(Q+N-1) is the Qth first display unit column VDUB; VDUM(Q+N-2) is the (N-1)th second display unit column VDUR, and VDUM(Q+N-3) is the (Q-1)th first display unit column VDUB. At this time, the auxiliary pixel driving circuit column D-VPDC is located on the side of the heterogeneous display unit column VDUM(Q+N) away from the heterogeneous display unit column VDUM(Q+N-2).

[0100] When the heterogeneous display unit column VDUM(Q+N) is the first display unit column VDUB, then VDUM(Q+N) is the Qth first display unit column VDUB, and VDUM(Q+N-1) is the Nth second display unit column VDUR; VDUM(Q+N-2) is the Q-1th first display unit column VDUB, and VDUM(Q+N-3) is the N-1th second display unit column VDUR. At this time, the auxiliary pixel driving circuit column D-VPDC is located on the side of the heterogeneous display unit column VDUM(Q+N) away from the heterogeneous display unit column VDUM(Q+N-2).

[0101] In the example above, the sub-pixels PX of the discrete display unit DU and the electrically connected pixel driving circuit PDC are not located in the same heterogeneous display unit row HDUM. In other embodiments of this disclosure, the sub-pixels PX of the discrete display unit DU and the electrically connected pixel driving circuit PDC may also be located in the same heterogeneous display unit row HDUM.

[0102] For example, in one embodiment, the display panel PNL includes arrayed display unit groups (DUS). Each display unit group (DUS) includes a separate second display unit (DUR) and a separate first display unit (DUB) arranged in the same row. The separate second display unit (DUR) and the separate first display unit (DUB) are located in two adjacent heterogeneous display unit columns (VDUM). Within the same display unit group (DUS), the second sub-pixel (PXR) of the second display unit (DUR) is electrically connected to the pixel driving circuit (PDC) of the first display unit (DUB), and the pixel driving circuit (PDC) of the second display unit (DUR) is electrically connected to the first sub-pixel (PXB) of the first display unit (DUB).

[0103] Furthermore, the display panel PNL includes multiple display unit groups (VDUS) arranged sequentially along the row direction (DH). Each display unit group (VDUS) includes a second display unit group (VDUR) and a first display unit group (VDUB). Within the same display unit group (VDUS), the second display unit group (VDUR) and the first display unit group (VDUB) located in the same heterogeneous display unit row (HDUM) are situated in the same display unit group (DUS). Furthermore, each display unit group (VDUS) also includes two third display unit groups (VDUG); one of the third display unit groups (VDUG) is located between the second display unit group (VDUR) and the first display unit group (VDUB).

[0104] For example, a display unit group VDUS includes a second display unit group VDUR, a third display unit group VDUG, a first display unit group VDUB, and a third display unit group VDUG arranged sequentially along the row direction DH; or, a display unit group VDUS includes a first display unit group VDUB, a third display unit group VDUG, a second display unit group VDUR, and a third display unit group VDUG arranged sequentially along the row direction DH.

[0105] In one embodiment of this disclosure, the display panel PNL is provided with a transfer trace TRL corresponding to a separate display unit DU. The transfer trace TRL may include a first transfer trace TRLB corresponding to a first sub-pixel PXB in the second display unit column VDUR, and a second transfer trace TRLR corresponding to a second sub-pixel (PXR) in the first display unit column VDUB. Specifically, the first sub-pixel PXB in the second display unit column VDUR is electrically connected to the output terminal of the pixel driving circuit PDC of the second display unit DUR in the first display unit column VDUB via the corresponding first transfer trace TRLB; the second sub-pixel (PXR) in the first display unit column VDUB is electrically connected to the output terminal of the pixel driving circuit PDC of the first display unit DUB in the second display unit column VDUR via the corresponding second transfer trace TRLR.

[0106] In one example, the transition trace (TRL) is located on the side of the sub-pixel PX closest to the substrate SBT; the connection area of ​​the pixel electrode of the sub-pixel PX of the discrete display unit DU is electrically connected to the corresponding transition trace (TRL) through vias. Furthermore, the transition trace (TRL) is made of metal. This avoids the wiring difficulties and crosstalk issues that would result from placing the transition trace (TRL) on the pixel electrode layer; and by using a metal material for the transition trace (TRL), the resistance between the pixel electrode of the discrete display unit DU and the electrically connected pixel driving circuit (PDC) can be reduced.

[0107] Transition traces (TRLs) can be located on the same layer or between multiple metal layers. In one example, the drive layer (DRL) includes a first source / drain metal layer (SD1), a second source / drain metal layer (SD2), and a third source / drain metal layer (SD3) stacked sequentially on one side of the substrate SBT. Data traces (DL) and power supply traces (VDDL) are located on the second source / drain metal layer (SD2) and extend along the column direction (DV). Transition traces (TRLs) (e.g., a second transition trace (TRLR) and a first transition trace (TRLB)) can be located on the third source / drain metal layer (SD3) to avoid interfering with data traces (DL) and power supply traces (VDDL). In another example, the driving layer DRL includes a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3, which are sequentially stacked on one side of the substrate SBT; data traces DL and power supply voltage traces VDDL are disposed on the second source / drain metal layer SD2 and extend along the column direction DV; the transition traces TRL (e.g., the second transition trace TRLR and the first transition trace TRLB) may have trace segments located on the second source / drain metal layer SD2 and trace segments located on the third source / drain metal layer SD3, and adjacent trace segments of the same transition trace TRL are electrically connected through vias to cross or avoid other conductive structures.

[0108] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

A display panel includes a plurality of display units arranged in an array; the plurality of display units are arranged in a plurality of display unit columns and a plurality of display unit rows; The plurality of display unit columns include a second display unit column and a first display unit column arranged alternately along the row direction; both the second display unit column and the first display unit column include a second display unit and a first display unit arranged alternately along the column direction; the second display unit of the second display unit column and the second display unit of the first display unit column are located in different display unit rows; the second display unit includes a second sub-pixel and a pixel driving circuit, and the first display unit includes a second sub-pixel and a pixel driving circuit; The display panel also includes multiple data lines corresponding one-to-one with each display unit column; each pixel driving circuit of the second display unit column is electrically connected to the corresponding data line; each pixel driving circuit of the first display unit column is electrically connected to the corresponding data line. In the second display unit in the second display unit column, the second sub-pixel is electrically connected to the output terminal of the pixel driving circuit; in the first display unit in the first display unit column, the first sub-pixel is electrically connected to the output terminal of the pixel driving circuit. At least a portion of the first sub-pixels in the second display unit column are electrically connected to the output terminal of the pixel driving circuit of the second display unit in the first display unit column; at least a portion of the second sub-pixels in the first display unit column are electrically connected to the output terminal of the pixel driving circuit of the first display unit in the second display unit column. The display panel according to claim 1, wherein, At least some of the first sub-pixels in the second display unit column are located in different rows of the display unit with the electrically connected pixel driving circuit; at least some of the second sub-pixels in the first display unit column are located in different rows of the display unit with the electrically connected pixel driving circuit. The display panel according to claim 2, wherein, The plurality of display unit rows include non-heterogeneous display unit rows and heterogeneous display unit rows arranged alternately along the column direction; the second display unit in the second display unit column and the first display unit in the first display unit column The display unit is located in the non-heterogeneous display unit row, and the first display unit in the second display unit column and the second display unit in the first display unit column are located in the heterogeneous display unit row; At least some of the first sub-pixels in the second display unit column and the pixel driving circuits electrically connected to them are located in two adjacent heterogeneous display unit rows, respectively; At least some of the second sub-pixels in the first display unit column and the pixel driving circuits electrically connected to them are located in two adjacent heterogeneous display unit rows, respectively. The display panel according to claim 3, wherein, The first sub-pixel in the second display unit column is located in the xth heterogeneous display unit row, and the pixel driving circuit electrically connected to the first sub-pixel in the second display unit column is located in the (x+1)th heterogeneous display unit row; The second sub-pixel in the first display unit column is located in the xth heterogeneous display unit row, and the pixel driving circuit electrically connected to the second sub-pixel in the first display unit column is located in the (x+1)th heterogeneous display unit row; Where x is a positive integer and x < M, and M is the number of rows of the heterogeneous display units. The display panel according to claim 4, wherein, The display panel further includes an auxiliary pixel driving circuit row, which includes a plurality of second auxiliary pixel driving circuits corresponding to each of the second display unit columns and a plurality of first auxiliary pixel driving circuits corresponding to each of the first display unit columns. The second auxiliary pixel driving circuit is connected to the same data line as each pixel driving circuit in the corresponding second display unit column; The first auxiliary pixel driving circuit is connected to the same data trace as each pixel driving circuit in the corresponding first display unit column; The second sub-pixel in the Mth heterogeneous display unit row is electrically connected to the second auxiliary pixel driving circuit in the auxiliary pixel driving circuit row. The first sub-pixel in the Mth heterogeneous display unit row is electrically connected to the first auxiliary pixel driving circuit in the auxiliary pixel driving circuit row. The display panel according to claim 1, wherein, In the second display unit column The first sub-pixel is located in the y-th second display unit column, and the pixel driving circuit electrically connected to the first sub-pixel in the second display unit column is located in the first display unit column between the y-th second display unit column and the (y+1)-th second display unit column; The second sub-pixel in the first display unit column is located in the z-th first display unit column, and the pixel driving circuit electrically connected to the second sub-pixel in the first display unit column is located in the second display unit column between the z-th first display unit column and the z+1-th first display unit column; Where y is a positive integer and y < N, N is the number of columns in the second display unit; z is a positive integer and z < Q, Q is the number of columns in the first display unit. The display panel according to claim 6, wherein, The display panel further includes an auxiliary pixel driving circuit column and an auxiliary data trace, the auxiliary pixel driving circuit column and the auxiliary data trace being located on the side away from the (N-1)th second display unit column of the Qth first display unit column and the Nth second display unit column; the auxiliary pixel driving circuit column includes a pixel driving circuit that corresponds one-to-one with each of the display unit rows and each pixel driving circuit is electrically connected to the auxiliary data trace; The Nth second display unit column is located between the Qth first display unit column and the auxiliary pixel driving circuit column, and the pixel driving circuit electrically connected to the first sub-pixel on the Nth second display unit column is located in the auxiliary pixel driving circuit column; And / or, the Qth first display unit column is located between the Nth second display unit column and the auxiliary pixel driving circuit column, and the pixel driving circuit electrically connected to the second sub-pixel on the Qth first display unit column is located in the auxiliary pixel driving circuit column. The display panel according to claim 1, wherein, The plurality of display unit columns also include a plurality of third display unit columns, wherein the third display unit columns are disposed between the second display unit columns and the adjacent first display unit columns; The third display unit column includes a plurality of third display units arranged sequentially along the column direction. The third display unit includes a pixel driving circuit and a third sub-pixel electrically connected to the output terminal of the pixel driving circuit. The display panel also includes multiple data traces that correspond one-to-one with each of the third display unit columns, and the pixel driving circuits of each of the third display unit columns are electrically connected to the corresponding data traces. The display panel according to claim 1, wherein, The display panel is provided with a first transition line corresponding to the first sub-pixel in the second display unit column, and a second transition line corresponding to the second sub-pixel in the first display unit column. The first sub-pixel in the second display unit column is electrically connected to the output terminal of the pixel driving circuit through the corresponding first adapter line; the second sub-pixel in the first display unit column is electrically connected to the output terminal of the pixel driving circuit through the corresponding second adapter line. The display panel according to claim 9, wherein, The display panel includes a substrate, a driving layer, and a pixel layer stacked sequentially; the pixel driving circuit, the first adapter trace, and the second adapter trace are disposed on the driving layer, and the first sub-pixel and the second sub-pixel are disposed on the pixel layer. The display panel according to claim 1, wherein, The display panel includes a substrate, a driving layer, and a pixel layer stacked sequentially; the pixel driving circuit is disposed on the driving layer, and the first sub-pixel and the second sub-pixel are disposed on the pixel layer; The pixel electrode of the first sub-pixel has a connection area, and the connection area of ​​the pixel electrode of the first sub-pixel is electrically connected to the pixel driving circuit that drives the first sub-pixel through a via. The connection area of ​​the pixel electrode of the first sub-pixel of the first display unit is projected onto the substrate in orthographic projection, and the arrangement area of ​​the pixel driving circuit of the first display unit is located within the orthographic projection of the substrate in orthographic projection. The pixel electrode of the second sub-pixel has a connection area, and the connection area of ​​the pixel electrode of the second sub-pixel is electrically connected to the pixel driving circuit that drives the second sub-pixel through a via. The connection area of ​​the pixel electrode of the second sub-pixel of the second display unit is projected onto the substrate, and the pixel driving circuit of the second display unit is located on the substrate. Within the orthographic projection on the substrate. A display device comprising the display panel as described in any one of claims 1 to 11.

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