Semiconductor device

Abstract

The semiconductor device (1) is a chip-scale semiconductor device (1) that is square in plan view, and is provided with a semiconductor layer (40), a vertical MOS transistor (10) formed on the semiconductor layer (40), and a Schottky barrier diode (20) in which the semiconductor layer (40) functions as an anode or a cathode. A first pad (51), a second pad (52), a third pad (53), and a fourth pad (54) are provided on the upper surface of a semiconductor device (1), and the center of the first pad (51) and the center of the third pad (53) are located on one diagonal line of the semiconductor device (1) in a plan view of the semiconductor device (1). The center of the second pad (52) and the center of the fourth pad (54) are located on the other diagonal line of the semiconductor device (1), and the first pad (51), the second pad (52), the third pad (53), and the fourth pad (54) are circles having the same diameter.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Previously, there were commercially available semiconductor devices that sealed a MOS transistor and a Schottky barrier diode in a single package so that they could function as separate components.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2002-203966 Summary of the Invention

[0004] The problem that the invention aims to solve The aforementioned commercially available semiconductor devices all have dimensions of 2.0 mm × 2.0 mm or larger in a plan view.

[0005] On the other hand, the demand for high-density installation of electronic components in limited space is increasing.

[0006] Therefore, the object of this disclosure is to provide a semiconductor device that incorporates a MOS transistor and a Schottky barrier diode in a manner that allows them to function as separate components, and that enables the semiconductor device to have a smaller size in a plan view than previously possible.

[0007] Methods for solving problems One aspect of the semiconductor device disclosed herein is a chip-scale packaged semiconductor device, comprising: a semiconductor layer having a semiconductor substrate of a first conductivity type and a low-concentration impurity layer of the first conductivity type, the semiconductor substrate containing a first concentration of impurities, and the low-concentration impurity layer being formed in contact with the upper surface of the semiconductor substrate and containing a second concentration of impurities lower than the first concentration; a vertical MOS transistor formed on the semiconductor layer; and a Schottky barrier diode, wherein the low-concentration impurity layer functions as the cathode of the Schottky barrier diode when the first conductivity type is N-type, and functions as the anode of the Schottky barrier diode when the first conductivity type is P-type; the upper surface of the semiconductor device further comprises: a first pad functioning as the source pad of the vertical MOS transistor; a second pad functioning as the drain pad of the vertical MOS transistor, and functioning as the cathode pad of the Schottky barrier diode when the first conductivity type is N-type, and as the anode pad of the Schottky barrier diode when the first conductivity type is P-type. Functions: The third pad functions as the anode pad of the Schottky barrier diode when the first conductivity type is N-type, and as the cathode pad of the Schottky barrier diode when the first conductivity type is P-type; and the fourth pad functions as the gate pad of the vertical MOS transistor; In a plan view of the semiconductor device, the semiconductor device is a square having a first vertex, a second vertex, a third vertex, and a fourth vertex in a counterclockwise direction; the first pad, the second pad, the third pad, and the fourth pad are circles with the same diameter; the center of the first pad and the center of the third pad are located on a first diagonal connecting the first vertex and the third vertex; the center of the second pad and the center of the fourth pad are located on a second diagonal connecting the second vertex and the fourth vertex; the distances between the center of the semiconductor device and the center of the first pad, the distances between the center of the semiconductor device and the center of the second pad, the distances between the center of the semiconductor device and the center of the third pad, and the distances between the center of the semiconductor device and the center of the fourth pad are equal.

[0008] Invention Effects According to one aspect of the present disclosure, a semiconductor device is provided that incorporates a MOS transistor and a Schottky barrier diode in a manner that allows them to function as independent components, thereby enabling the semiconductor device to have a smaller size in a plan view than in the past. Attached Figure Description

[0009] Figure 1 This is a plan view illustrating an example of the structure of a semiconductor device according to an embodiment.

[0010] Figure 2 This is a cross-sectional schematic diagram illustrating an example of the structure of a semiconductor device according to an embodiment.

[0011] Figure 3A This is a circuit diagram of a semiconductor device in an embodiment where the first conductivity type is N-type.

[0012] Figure 3B This is a circuit diagram of a semiconductor device in an embodiment where the first conductivity type is P-type.

[0013] Figure 4 This is a comparison chart comparing the on-resistance of the vertical MOS transistor in the comparative example with the on-resistance of the vertical MOS transistor in the embodiment.

[0014] Figure 5 This is a schematic diagram illustrating the relationship between the type of metal material forming the Schottky junction and the characteristics of a Schottky barrier diode when the first conductivity type is N-type.

[0015] Figure 6 This is a plan view illustrating another example of the construction of a semiconductor device according to an embodiment.

[0016] Figure 7 This is a plan view illustrating an example of the structure of the semiconductor device in Modified Example 1.

[0017] Figure 8 This is a plan view illustrating an example of the structure of the semiconductor device in Modified Example 2. Detailed Implementation

[0018] (One way in which this disclosure was obtained) Conventional semiconductor devices that encapsulate MOS transistors and Schottky barrier diodes in a single package so that they can function as separate components have at least three terminals connected to the gate, source, and drain of the MOS transistor, and two terminals connected to the anode and cathode of the Schottky barrier diode, for a total of five terminals, on the mounting surface of the semiconductor device to be mounted on a mounting substrate or the like.

[0019] In this regard, the inventors have gained the following insight: When the above-mentioned semiconductor device is used to directly connect the drain of a MOS transistor to the anode or cathode of a Schottky barrier diode, by combining the terminal connected to the drain of the MOS transistor and the terminal connected to the anode or cathode of the Schottky barrier diode into one terminal, the number of terminals of the above-mentioned semiconductor device can be set to four.

[0020] Furthermore, based on this insight, the inventors conducted repeated and careful experiments and research, and came up with the semiconductor device disclosed below.

[0021] The semiconductor device disclosed herein is a chip-scale packaged semiconductor device, comprising: a semiconductor layer having a semiconductor substrate of a first conductivity type and a low-concentration impurity layer of the first conductivity type, the semiconductor substrate containing a first concentration of impurities, and the low-concentration impurity layer being formed in contact with the upper surface of the semiconductor substrate and containing a second concentration of impurities lower than the first concentration; a vertical MOS transistor formed on the semiconductor layer; and a Schottky barrier diode, wherein the low-concentration impurity layer functions as the cathode of the Schottky barrier diode when the first conductivity type is N-type, and functions as the anode of the Schottky barrier diode when the first conductivity type is P-type; the upper surface of the semiconductor device further comprises: a first pad functioning as the source pad of the vertical MOS transistor; a second pad functioning as the drain pad of the vertical MOS transistor, and functioning as the cathode pad of the Schottky barrier diode when the first conductivity type is N-type, and as the anode pad of the Schottky barrier diode when the first conductivity type is P-type. The third pad functions as the anode pad of the Schottky barrier diode when the first conductivity type is N-type, and as the cathode pad of the Schottky barrier diode when the first conductivity type is P-type; and the fourth pad functions as the gate pad of the vertical MOS transistor; in the plan view of the semiconductor device, the semiconductor device is a square with a first vertex, a second vertex, a third vertex, and a fourth vertex in a counterclockwise direction, the first pad, the second pad, the third pad, and the fourth pad are circles with the same diameter, the center of the first pad and the center of the third pad are located on the first diagonal connecting the first vertex and the third vertex, the center of the second pad and the center of the fourth pad are located on the second diagonal connecting the second vertex and the fourth vertex, and the distance between the center of the semiconductor device and the center of the first pad, the distance between the center of the semiconductor device and the center of the second pad, the distance between the center of the semiconductor device and the center of the third pad, and the distance between the center of the semiconductor device and the center of the fourth pad are equal.

[0022] The semiconductor device described above is an unsealed, chip-sized semiconductor device in which the vertical MOS transistor and Schottky barrier diode can function as independent components, and the upper surface of the mounting surface, which serves as the mounting surface for mounting the semiconductor device to a mounting substrate, has four pads, i.e., four terminals.

[0023] Therefore, the semiconductor device with the above structure can reduce its size in a plan view compared to conventional semiconductor devices that seal a MOS transistor and a Schottky barrier diode in a single package so that they can function as independent components.

[0024] Thus, a semiconductor device with the above structure is provided that, in a semiconductor device in which a MOS transistor and a Schottky barrier diode are provided so that they can function as independent components, can reduce the size in a plan view compared to the conventional semiconductor device.

[0025] Furthermore, in this specification, the term "center" in a plan view, for example, for a structure with a square or rectangular shape in a plan view such as a semiconductor device, refers to the intersection of the diagonals of the square or rectangle; for a structure with a circular shape in a plan view such as the first to fourth pads, it refers to the center of the circle; for a structure with an oblong shape in a plan view, it refers to the intersection of the line axis of symmetry extending along the long side and the line axis of symmetry extending along the short side of the oblong shape; and for a structure with an elliptical shape in a plan view, it refers to the intersection of the major axis and the minor axis of the ellipse.

[0026] Furthermore, in a plan view of the semiconductor device, if the area of ​​the semiconductor device is divided into four equal parts by four non-overlapping square regions: a first square region with a line connecting the first vertex and the center of the semiconductor device as its diagonal, a second square region with a line connecting the second vertex and the center of the semiconductor device as its diagonal, a third square region with a line connecting the third vertex and the center of the semiconductor device as its diagonal, and a fourth square region with a line connecting the fourth vertex and the center of the semiconductor device as its diagonal, then the first pad is contained within the first square region, the second pad is contained within either the second or fourth square region (i.e., a square region containing the second pad), the third pad is contained within the third square region, and the fourth pad is contained within either the second or fourth square region (i.e., a square region containing the fourth pad). The semiconductor layer also has a drain pull-out region of the first conductivity type containing a third concentration of impurities higher than the second concentration, which is entirely contained within the area of ​​the semiconductor layer in the plan view. The semiconductor device includes a square region containing a second pad, and the drain pull-up region extends from the upper surface of the semiconductor layer through the low-concentration impurity layer to the semiconductor substrate. Furthermore, in a plan view of the semiconductor device, the semiconductor device includes: a first electrode, at least a portion of which is contained in the first square region, functioning as the source electrode of the vertical MOS transistor; a second electrode, at least a portion of which is contained in the square region containing the second pad, functioning as the drain electrode of the vertical MOS transistor, and functioning as the cathode electrode of the Schottky barrier diode when the first conductivity type is N-type, and as the anode electrode of the Schottky barrier diode when the first conductivity type is P-type; a third electrode, at least a portion of which is contained in the third square region, functioning as the anode electrode of the Schottky barrier diode when the first conductivity type is N-type, and as the cathode electrode of the Schottky barrier diode when the first conductivity type is P-type; and a fourth electrode, at least a portion of which is contained in the square region containing the fourth pad, functioning as the gate electrode of the vertical MOS transistor.

[0027] In the semiconductor device with the above structure, the distance between the anode and cathode electrodes of the Schottky barrier diode is relatively close.

[0028] Therefore, the forward voltage of the Schottky barrier diode can be made relatively small by the semiconductor device with the above structure.

[0029] Furthermore, in the semiconductor device with the above structure, the source electrode and drain electrode of the vertical MOS transistor are relatively close together.

[0030] Therefore, the semiconductor device with the above structure can achieve a relatively small on-resistance for the vertical MOS transistor.

[0031] Alternatively, the Schottky barrier diode may be planar.

[0032] Typically, planar Schottky barrier diodes can be formed with fewer processing steps than other types of Schottky barrier diodes.

[0033] Therefore, a semiconductor device with the above structure is provided that can be manufactured relatively easily.

[0034] Alternatively, the second electrode may have multiple metal layers including an ohmic bonding metal layer that is ohmicly bonded to the drain pull-up region, and the third electrode may have multiple metal layers including a Schottky bonding metal layer that is ohmicly bonded to the low-concentration impurity layer, wherein the metal material of the ohmic bonding metal layer is the same as the metal material of the Schottky bonding metal layer.

[0035] Therefore, ohmic bonding metal layers and Schottky bonding metal layers can be formed through the same processing steps.

[0036] Therefore, a semiconductor device with the above structure is provided that can be manufactured relatively easily.

[0037] Alternatively, the second electrode may have multiple metal layers including an ohmic bonding metal layer that is ohmicly bonded to the drain pull-up region, and the third electrode may have multiple metal layers including a Schottky bonding metal layer that is ohmicly bonded to the low-concentration impurity layer, wherein the metal material of the ohmic bonding metal layer is different from the metal material of the Schottky bonding metal layer.

[0038] Therefore, it is possible to make the Schottky junction metal layer a metal layer containing a different type of metal material than the ohmic junction metal layer, which conforms to the desired characteristics of the Schottky barrier diode.

[0039] Therefore, based on the above-described semiconductor device structure, a semiconductor device having a Schottky barrier diode with desired characteristics is provided.

[0040] Alternatively, in a plan view of the semiconductor device, at least a portion of the first electrode may be included in the square region containing the second pad and / or the square region containing the fourth pad, wherein at least a portion of the second electrode, at least a portion of the third electrode, and at least a portion of the fourth electrode are not included in the first square region.

[0041] This allows for a larger source electrode area in the planar view of a semiconductor device for vertically oriented MOS transistors.

[0042] Therefore, the semiconductor device with the above structure can achieve a relatively small on-resistance for the vertical MOS transistor.

[0043] Alternatively, in a plan view of the semiconductor device, the second electrode may be a rectangle having a first opposing side and a second opposing side, the first opposing side having a portion that is parallel to a first portion of the outer periphery of the first electrode, and the second opposing side having a portion that is parallel to a second portion of the outer periphery of the first electrode.

[0044] Therefore, the opposing lengths of the source and drain electrodes of a vertical MOS transistor in a planar view of a semiconductor device can be relatively long.

[0045] Therefore, the semiconductor device with the above structure can achieve a relatively small on-resistance for the vertical MOS transistor.

[0046] Alternatively, in a plan view of the semiconductor device, at least a portion of the first electrode may not be included in the square region containing the second pad.

[0047] In the semiconductor device with the above structure, in a plan view of the semiconductor device, the source electrode of the vertical MOS transistor is not sandwiched between the anode and cathode electrodes of the Schottky barrier diode.

[0048] Therefore, the semiconductor device with the above structure can suppress the degradation of the characteristics of the Schottky barrier diode.

[0049] Alternatively, the third electrode and the low-concentration impurity layer may be Schottky-bonded in the Schottky junction region, the second electrode and the drain pull-out region may be Ohmically bonded in the Ohmically bonded region, and the first electrode and the semiconductor layer may be in contact in the source junction region. In a plan view of the semiconductor device, the Schottky junction region is contained within the third electrode and is any one of a circle, an ellipse, an oblong shape, and a rounded corner formed by rounding the corners of a rectangle. The shortest distance between the Schottky junction region and the Ohmically bonded region is shorter than the shortest distance between the Schottky junction region and the source junction region.

[0050] In a plan view of the semiconductor device described above, the Schottky junction region does not have a corner.

[0051] This suppresses excessive concentration of the electric field in the Schottky junction region.

[0052] Therefore, the semiconductor device with the above structure can improve the breakdown voltage characteristics in the Schottky junction region.

[0053] In addition, the semiconductor device with the above structure can make the distance between the Schottky junction region and the Ohm junction region relatively small.

[0054] Therefore, the forward voltage of the Schottky barrier diode can be made relatively small by the semiconductor device with the above structure.

[0055] Alternatively, in a plan view of the semiconductor device, the area of ​​the Schottky junction region may be larger than the area of ​​the third pad.

[0056] This allows for a larger area of ​​the Schottky junction region in the planar view of the semiconductor device.

[0057] Therefore, the forward voltage of the Schottky barrier diode can be made relatively small by the semiconductor device with the above structure.

[0058] Alternatively, in a plan view of the semiconductor device, the area of ​​the Schottky junction region may be smaller than the area of ​​the third pad.

[0059] This allows for a smaller area of ​​the Schottky junction region in the plan view of the semiconductor device.

[0060] Therefore, the semiconductor device with the above structure can achieve a relatively small reverse leakage current of the Schottky barrier diode.

[0061] Alternatively, the third electrode and the low-concentration impurity layer may be Schottky-bonded in the Schottky junction region, and the first electrode and the semiconductor layer may be bonded in the source junction region. In a plan view of the semiconductor device, the Schottky junction region is any one of a circle, an ellipse, an oblong shape, and a rounded shape obtained by rounding the corners of a rectangle. The source junction region is a rounded shape obtained by rounding the corners of a polygon. The minimum radius of curvature of the outer periphery of the Schottky junction region is greater than or equal to the minimum radius of curvature of the source junction region.

[0062] Therefore, the suppression of excessive concentration of electric field in the Schottky junction region can be improved to the suppression of excessive concentration of electric field in the source junction region.

[0063] Therefore, the breakdown voltage characteristics of the semiconductor device according to the above structure can be determined based on the excessive concentration of the electric field in the source junction region, rather than based on the excessive concentration of the electric field in the Schottky junction region.

[0064] Hereinafter, a specific example of a semiconductor device according to one aspect of the present disclosure will be described with reference to the accompanying drawings. The embodiments shown herein represent specific examples of the present disclosure. Therefore, the values, shapes, constituent elements, arrangements and connections of constituent elements, and steps (processes) and their order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, the figures are schematic diagrams and are not necessarily strictly illustrative. In the figures, substantially identical structures are labeled with the same reference numerals, and repeated descriptions are omitted or simplified.

[0065] (Implementation Method) The semiconductor device described below is an example of a chip-scale packaged semiconductor device comprising a vertical MOS transistor and a Schottky barrier diode.

[0066] <Structure of Semiconductor Devices> Figure 1 This is a plan view illustrating an example of the structure of the semiconductor device 1 according to the embodiment. Figure 1 In the diagram, the first electrode 61 (described later), the second electrode 62 (described later), the third electrode 63 (described later), the fourth electrode 64 (described later), the source junction region 91 (described later), the ohmic junction region 92 (described later), and the Schottky junction region 93 (described later) are represented by dashed lines as if they could be visually identified from the outside of the semiconductor device 1, but in reality they cannot be directly visually identified from the outside of the semiconductor device 1.

[0067] like Figure 1 As shown, in a plan view of semiconductor device 1, semiconductor device 1 is a square having a first vertex 71, a second vertex 72, a third vertex 73, and a fourth vertex 74 arranged counterclockwise.

[0068] In this specification, the semiconductor device 1 is a square shape, not limited to a rectangular shape in which the ratio of the length of the vertical side to the length of the horizontal side is exactly 1.0, but refers to a shape in which the ratio of the length of the vertical side to the length of the horizontal side is in the range of 0.9 to 1.1.

[0069] The semiconductor device 1 has a first pad 51, a second pad 52, a third pad 53 and a fourth pad 54 on its upper surface.

[0070] In a plan view of semiconductor device 1, the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54 are circles of the same diameter.

[0071] In this specification, the term "pad" as "circular" does not refer to a pad that is exactly a perfect circle, but rather to a flat, approximately circular shape within ±1% of a perfect circle.

[0072] In a plan view of semiconductor device 1, the center 151 of the first pad 51 and the center 153 of the third pad 53 are located on the first diagonal 81 connecting the first vertex 71 and the third vertex 73, and the center 152 of the second pad 52 and the center 154 of the fourth pad 54 are located on the second diagonal 82 connecting the second vertex 72 and the fourth vertex 74.

[0073] In a plan view of semiconductor device 1, the distances between the center 121 of semiconductor device 1 and the center 151 of the first pad 51, the distances between the center 121 of semiconductor device 1 and the center 152 of the second pad 52, the distances between the center 121 of semiconductor device 1 and the center 153 of the third pad 53, and the distances between the center 121 of semiconductor device 1 and the center 154 of the fourth pad 54 are equal.

[0074] The following, such as Figure 1 As shown, in a plan view of semiconductor device 1, it is assumed that the area of ​​semiconductor device 1 is divided into four equal square regions that are of equal shape and do not overlap. The four square regions are: a first square region 41 with the line connecting the first vertex 71 and the center 121 of semiconductor device 1 as its diagonal; a second square region 42 with the line connecting the second vertex 72 and the center 121 of semiconductor device 1 as its diagonal; a third square region 43 with the line connecting the third vertex 73 and the center 121 of semiconductor device 1 as its diagonal; and a fourth square region 44 with the line connecting the fourth vertex 74 and the center 121 of semiconductor device 1 as its diagonal.

[0075] In a plan view of semiconductor device 1, first pad 51 is contained within a first square region 41, second pad 52 is contained within one of the square regions 42 and 44, third pad 53 is contained within a third square region 43, and fourth pad 54 is contained within the other square region 42 and 44.

[0076] In this embodiment, as an example that is not necessarily limited, such as Figure 1 As shown, it is assumed that the second pad 52 is contained within the second square region 42 and the fourth pad 54 is contained within the fourth square region 44.

[0077] In the following description, the square region (here referring to the second square region 42) that is one of the second square region 42 and the fourth square region 44, that is, the square region containing the second pad 52 in the second square region 42 and the fourth square region 44 in the plan view of the semiconductor device 1 (here referring to the second square region 42), is also referred to as the square region containing the second pad 42.

[0078] Furthermore, in the following description, the square region that is the other of the second square region 42 and the fourth square region 44 (here, the fourth square region 44), that is, the square region containing the fourth pad 54 in the second square region 42 and the fourth square region 44 in the plan view of the semiconductor device 1 (here, the fourth square region 44), is also referred to as the square region containing the fourth pad 44.

[0079] Figure 2 This is a schematic cross-sectional view showing an example of the structure of semiconductor device 1, and is intended to illustrate the concept. Figure 1 A cross-sectional schematic diagram of the semiconductor device 1 at point II.

[0080] Below, except Figure 1 In addition to using Figure 2 The description of the structure of semiconductor device 1 will continue.

[0081] like Figure 2 As shown, the semiconductor device 1 includes a semiconductor layer 40, an interlayer insulating layer 34, a passivation layer 35, a first electrode 61, a second electrode 62, a third electrode 63, and a fourth electrode 64.

[0082] The semiconductor layer 40 is formed by stacking a semiconductor substrate 32 and a low-concentration impurity layer 33.

[0083] The semiconductor substrate 32 is disposed on the back side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities of a first concentration.

[0084] A low-concentration impurity layer 33 is disposed on the surface side of the semiconductor layer 40 and formed in contact with the semiconductor substrate 32. It is made of silicon of a first conductivity type containing impurities of a second concentration lower than the first concentration. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0085] Here, the second concentration is the concentration at which a Schottky barrier is formed at the contact surface between the low-concentration impurity layer 33 and the first metal layer 63A when the low-concentration impurity layer 33 comes into contact with the first metal layer 63A (described later). That is, the second concentration is the concentration at which the low-concentration impurity layer 33 and the first metal layer 63A are Schottky bonded at the contact surface between them.

[0086] Semiconductors typically exhibit two conductivity types: P-type and N-type. The first conductivity type can be either P-type or N-type. For ease of explanation, we will use N-type as the first conductivity type and P-type as the second conductivity type (described later). However, the first conductivity type can also be P-type, and the second conductivity type can also be N-type.

[0087] An interlayer insulating layer 34 is disposed on the upper surface of the semiconductor layer 40 and the upper surface of the gate conductor 15 inside the gate trench 17 (described later), and is formed in contact with the low-concentration impurity layer 33. Furthermore, the interlayer insulating layer 34 is mainly formed of an oxide film.

[0088] The passivation layer 35 is a protective film covering the upper surfaces of the interlayer insulating layer 34, the first electrode 61, the second electrode 62, the third electrode 63, and the fourth electrode 64. It has an opening that exposes the first pad 51 to the outside of the semiconductor device 1, an opening that exposes the second pad 52 to the outside of the semiconductor device 1, an opening that exposes the third pad 53 to the outside of the semiconductor device 1, and an opening that exposes the fourth pad 54 to the outside of the semiconductor device 1.

[0089] Here, the passivation layer 35 covering the upper surfaces of the interlayer insulating layer 34, the first electrode 61, the second electrode 62, the third electrode 63, and the fourth electrode 64 means that, in a plan view of the semiconductor device 1, the passivation layer 35 is formed on approximately the entire surface of the semiconductor device 1, excluding the opening. Here, "approximately the entire surface of the semiconductor device 1" refers to the entire surface of the semiconductor device 1 within the wafer region ensured as a cutting allowance when the semiconductor device 1 is removed from the wafer, excluding the slightly remaining outer peripheral regions on the four sides of the semiconductor device 1 after cutting. Therefore, in this outer peripheral region, the interlayer insulating layer 34 is exceptionally exposed on the upper surface of the semiconductor device 1.

[0090] Furthermore, the opening of the passivation layer 35 referred to in this disclosure refers to a shape in which the entire outer periphery of the opening is closed within the passivation layer 35 in a plan view of the semiconductor device 1. Therefore, a shape in a plan view of the semiconductor device 1 where a portion of the outer periphery overlaps with the outer periphery region of the interlayer insulating layer 34 exposed on the upper surface of the semiconductor device 1, as described above, does not correspond to the opening of the passivation layer 35 referred to in this disclosure.

[0091] The first electrode 61 is composed of a first metal layer 61A formed in contact with the upper surface of the semiconductor layer 40, a second metal layer 61B formed in contact with the upper surface of the first metal layer 61A, a third metal layer 61C formed in contact with the upper surface of the second metal layer 61B, a fourth metal layer 61D formed in contact with the upper surface of the third metal layer 61C, and a fifth metal layer 61E formed in contact with the upper surface of the fourth metal layer 61D.

[0092] As an example that is not limited, the first metal layer 61A is made of titanium with a thickness of tens of nm and functions as a metal component that forms the contact surface between the first electrode 61 and the semiconductor layer 40.

[0093] The first metal layer 61A can be formed, for example, by sputtering titanium onto the upper surface of the semiconductor layer 40.

[0094] As an example that is not limited, the second metal layer 61B is composed of titanium nitride with a thickness of tens of nm, which functions as a barrier metal to prevent the metal constituting the third metal layer 61C from diffusing into the semiconductor layer 40.

[0095] The second metal layer 61B can be formed, for example, by sputtering titanium nitride onto the upper surface of the first metal layer 61A.

[0096] As an example that is not limited, the third metal layer 61C is composed of aluminum or an alloy with aluminum as the main component with a thickness of several μm.

[0097] The third metal layer 61C can be formed, for example, by sputtering aluminum or an alloy with aluminum as the main component onto the upper surface of the second metal layer 61B.

[0098] As an example that is not limited, the fourth metal layer 61D is made of nickel with a thickness of several μm, and functions as a barrier metal to prevent the metal constituting the third metal layer 61C from diffusing into the fifth metal layer 61E described later.

[0099] The fourth metal layer 61D can be formed, for example, by plating nickel on the upper surface of the third metal layer 61C.

[0100] As an example that is not limited, the fifth metal layer 61E is made of gold with a thickness of several hundred nm and functions as a metal component to improve the wettability of the first electrode 61 when it is bonded to a bonding material such as solder.

[0101] The fifth metal layer 61E can be formed, for example, by plating gold on the upper surface of the fourth metal layer 61D.

[0102] The upper surface of the fifth metal layer 61E is exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35. Furthermore, the upper surface of the fifth metal layer 61E exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35 becomes the first pad 51.

[0103] That is, the first pad 51 is the portion of the upper surface of the first electrode 61 that is exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35.

[0104] like Figure 1 As shown, in a plan view of the semiconductor device 1, at least a portion of the first electrode 61 is contained within the first square region 41.

[0105] Here, as an example where it doesn't necessarily need to be limited, such as Figure 1As shown, in a plan view of semiconductor device 1, it is assumed that at least a portion of the first electrode 61 is contained in the second square region 42, the third square region 43, and the fourth square region 44.

[0106] However, in a plan view of the semiconductor device 1, the first electrode 61 does not need to be included at least in the second square region 42, the third square region 43, and the fourth square region 44.

[0107] The second electrode 62 is composed of a first metal layer 62A formed in contact with the upper surface of the semiconductor layer 40, a second metal layer 62B formed in contact with the upper surface of the first metal layer 62A, a third metal layer 62C formed in contact with the upper surface of the second metal layer 62B, a fourth metal layer 62D formed in contact with the upper surface of the third metal layer 62C, and a fifth metal layer 62E formed in contact with the upper surface of the fourth metal layer 62D.

[0108] As an example that is not limited, the first metal layer 62A is made of titanium with a thickness of tens of nm and functions as a metal component that forms the contact surface between the second electrode 62 and the semiconductor layer 40.

[0109] The first metal layer 62A can be formed, for example, by sputtering titanium onto the upper surface of the semiconductor layer 40.

[0110] As an example that is not limited, the second metal layer 62B is composed of titanium nitride with a thickness of tens of nm, which functions as a barrier metal to prevent the metal constituting the third metal layer 62C from diffusing into the semiconductor layer 40.

[0111] The second metal layer 62B can be formed, for example, by sputtering titanium nitride onto the upper surface of the first metal layer 62A.

[0112] As an example that is not limited, the third metal layer 62C is composed of aluminum or an alloy with aluminum as the main component with a thickness of several μm.

[0113] The third metal layer 62C can be formed, for example, by sputtering aluminum or an alloy with aluminum as the main component onto the upper surface of the second metal layer 62B.

[0114] As an example that is not limited, the fourth metal layer 62D is made of nickel with a thickness of several μm, and functions as a barrier metal to prevent the metal constituting the third metal layer 62C from diffusing into the fifth metal layer 62E described later.

[0115] The fourth metal layer 62D can be formed, for example, by plating nickel on the upper surface of the third metal layer 62C.

[0116] As an example that is not limited, the fifth metal layer 62E is made of gold with a thickness of several hundred nm and functions as a metal component to improve the wettability of the second electrode 62 when it is bonded to a bonding material such as solder.

[0117] The fifth metal layer 62E can be formed, for example, by plating gold on the upper surface of the fourth metal layer 62D.

[0118] The upper surface of the fifth metal layer 62E is exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35. Furthermore, the upper surface of the fifth metal layer 62E exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35 becomes the second pad 52.

[0119] That is, the second pad 52 is the portion of the upper surface of the second electrode 62 that is exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35.

[0120] like Figure 1 As shown, in a plan view of semiconductor device 1, at least a portion of the second electrode 62 is contained in the second square region 42, i.e., the square region 42 containing the second pad.

[0121] Here, as an example where it is not necessarily limited, such as Figure 1 As shown, in the plan view of semiconductor device 1, it is assumed that the second electrode 62 is entirely contained within the second square region 42, that is, the square region 42 containing the second pad.

[0122] The third electrode 63 is composed of a first metal layer 63A formed in contact with the upper surface of the semiconductor layer 40, a second metal layer 63B formed in contact with the upper surface of the first metal layer 63A, a third metal layer 63C formed in contact with the upper surface of the second metal layer 63B, a fourth metal layer 63D formed in contact with the upper surface of the third metal layer 63C, and a fifth metal layer 63E formed in contact with the upper surface of the fourth metal layer 63D.

[0123] As an example that is not limited, the first metal layer 63A is made of titanium, vanadium, molybdenum, tungsten or platinum with a thickness of tens of nm, and functions as a metal component that forms the contact surface between the third electrode 63 and the semiconductor layer 40.

[0124] The first metal layer 63A can be formed, for example, by sputtering titanium, vanadium, molybdenum, tungsten or platinum onto the upper surface of the semiconductor layer 40.

[0125] As an example that is not limited, the second metal layer 63B is composed of titanium nitride with a thickness of tens of nm, which functions as a barrier metal to prevent the metal constituting the third metal layer 63C from diffusing into the semiconductor layer 40.

[0126] The second metal layer 63B can be formed, for example, by sputtering titanium nitride onto the upper surface of the first metal layer 63A.

[0127] As an example that is not specified, the third metal layer 63C is composed of aluminum or an alloy with aluminum as the main component with a thickness of several μm.

[0128] The third metal layer 63C can be formed, for example, by sputtering aluminum or an alloy with aluminum as the main component onto the upper surface of the second metal layer 63B.

[0129] As an example that is not limited, the fourth metal layer 63D is composed of nickel with a thickness of several μm, and functions as a barrier metal to prevent the metal constituting the third metal layer 63C from diffusing into the fifth metal layer 63E described later.

[0130] The fourth metal layer 63D can be formed, for example, by plating nickel on the upper surface of the third metal layer 63C.

[0131] As an example that is not limited, the fifth metal layer 63E is made of gold with a thickness of several hundred [nm] and functions as a metal component to improve the wettability of the third electrode 63 when it is bonded to a bonding material such as solder.

[0132] The fifth metal layer 63E can be formed, for example, by plating gold on the upper surface of the fourth metal layer 63D.

[0133] The upper surface of the fifth metal layer 63E is exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35. Furthermore, the upper surface of the fifth metal layer 63E exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35 becomes the third pad 53.

[0134] That is, the third pad 53 is the portion of the upper surface of the third electrode 63 that is exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35.

[0135] like Figure 1 As shown, in a plan view of semiconductor device 1, at least a portion of the third electrode 63 is contained in the third square region 43.

[0136] Here, as an example where it is not necessarily limited, such as Figure 1 As shown, it is assumed that the third electrode 63 is entirely contained within the third square region 43 in a plan view of the semiconductor device 1.

[0137] The fourth electrode 64 is composed of a first metal layer 64A formed in contact with the upper surface of the interlayer insulating layer 34, a second metal layer 64B formed in contact with the upper surface of the first metal layer 64A, a third metal layer 64C formed in contact with the upper surface of the second metal layer 64B, a fourth metal layer 64D formed in contact with the upper surface of the third metal layer 64C, and a fifth metal layer 64E formed in contact with the upper surface of the fourth metal layer 64D.

[0138] As an undefined example, the first metal layer 64A is composed of titanium with a thickness of tens of nm.

[0139] The first metal layer 64A can be formed, for example, by sputtering titanium onto the upper surface of the interlayer insulating layer 34.

[0140] As an example that is not specified, the second metal layer 64B is composed of titanium nitride with a thickness of tens of nm.

[0141] The second metal layer 64B can be formed, for example, by sputtering titanium nitride onto the upper surface of the first metal layer 64A.

[0142] As an example that is not specified, the third metal layer 64C is composed of aluminum or an alloy with aluminum as the main component with a thickness of several μm.

[0143] The third metal layer 64C can be formed, for example, by sputtering aluminum or an alloy with aluminum as the main component onto the upper surface of the second metal layer 64B.

[0144] As an example that is not limited, the fourth metal layer 64D is made of nickel with a thickness of several μm, and functions as a barrier metal to prevent the metal constituting the third metal layer 64C from diffusing into the fifth metal layer 64E described later.

[0145] The fourth metal layer 64D can be formed, for example, by plating nickel on the upper surface of the third metal layer 64C.

[0146] As an example that is not limited, the fifth metal layer 64E is made of gold with a thickness of several hundred nm and functions as a metal component to improve the wettability of the fourth electrode 64 when it is bonded to a bonding material such as solder.

[0147] The fifth metal layer 64E can be formed, for example, by plating gold on the upper surface of the fourth metal layer 64D.

[0148] The upper surface of the fifth metal layer 64E is exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35. Furthermore, the upper surface of the fifth metal layer 64E exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35 becomes the fourth pad 54.

[0149] That is, the fourth pad 54 is the portion of the upper surface of the fourth electrode 64 that is exposed on the upper surface of the semiconductor device 1 through the opening of the passivation layer 35.

[0150] like Figure 1 As shown, in a plan view of semiconductor device 1, at least a portion of the fourth electrode 64 is contained in the fourth square region 44, i.e., the square region 44 containing the fourth pad.

[0151] Here, as an example that is not limited to, in the plan view of semiconductor device 1, as shown... Figure 1 As shown, it is assumed that the fourth electrode 64 is entirely contained within the fourth square region 44, that is, the square region 44 containing the fourth pad.

[0152] In a plan view of the semiconductor device 1, in the region of the low-concentration impurity layer 33 contained in the first electrode 61, a body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the range from the upper surface of the semiconductor layer 40 to a first predetermined depth.

[0153] In the body region 18, a source region 14 containing impurities is formed in the range from the upper surface of the semiconductor layer 40 to a second predetermined depth that does not penetrate the body region 18.

[0154] Furthermore, in a plan view of the semiconductor device 1, in the region of the low-concentration impurity layer 33 contained in the body region 18, a plurality of gate trenches 17 are formed at a third predetermined depth from the upper surface of the semiconductor layer 40 to a portion of the low-concentration impurity layer 33 that extends through the source region 14 and the body region 18.

[0155] Furthermore, within each of the plurality of gate trenches 17, a gate conductor 15 is formed, which is surrounded by a gate insulating film 16.

[0156] The gate conductor 15 is electrically connected to the fourth electrode 64.

[0157] As an example that is not limited, the gate conductor 15 is made of polysilicon containing impurities.

[0158] In the plan view of semiconductor device 1, in the region included in the first electrode 61, the upper surface of semiconductor layer 40 is in contact with the first metal layer 61A.

[0159] In the following description, the region where the upper surface of the semiconductor layer 40 contacts the first metal layer 61A is referred to as the source junction region 91.

[0160] In a plan view of the semiconductor device 1, in the region of the low-concentration impurity layer 33 included in the second electrode 62, a first conductivity type drain pull-out region 36 is formed that extends from the upper surface of the semiconductor layer 40 through the low-concentration impurity layer 33 to the semiconductor substrate 32 and contains a third concentration of impurities that is higher than the second concentration.

[0161] Here, the third concentration is the concentration at which a Schottky barrier does not form at the contact surface between the drain pull-up region 36 and the first metal layer 62A when the drain pull-up region 36 is in contact with the first metal layer 62A. That is, the third concentration is the concentration at which the drain pull-up region 36 and the first metal layer 62A are ohmically bonded at the contact surface between them.

[0162] The upper surface of the drain pull-up region 36 is in contact with the first metal layer 62A. Thus, in a plan view of the semiconductor device 1, the upper surface of the drain pull-up region 36 is ohmically bonded to the first metal layer 62A in the region included in the second electrode 62.

[0163] In the following description, the region where the upper surface of the drain pull-up region 36 is ohmically joined to the first metal layer 62A, i.e., the contact region, is referred to as the ohm junction region 92.

[0164] Additionally, in the following description, the first metal layer 62A that forms the metal layer of the second electrode 62 and is in contact with the upper surface of the drain pull-up region 36 in the ohmic junction region 92 is also referred to as the ohmic junction metal layer 62A.

[0165] In a plan view of semiconductor device 1, ohmic junction region 92 is included on the upper surface of drain pull-up region 36. Therefore, semiconductor layer 40 and first metal layer 62A, i.e. ohmic junction metal layer 62A, are in contact only at ohmic junction region 92.

[0166] In the plan view of semiconductor device 1, within the region of the third electrode 63, the upper surface of the low-concentration impurity layer 33 is in contact with the first metal layer 63A. Thus, the upper surface of the low-concentration impurity layer 33 and the first metal layer 63A are Schottky bonded in the region of the third electrode 63 in the plan view of semiconductor device 1.

[0167] In the following description, the region where the upper surface of the low-concentration impurity layer 33 is Schottky bonded to the first metal layer 63A, i.e., the contact region, is referred to as the Schottky bond region 93.

[0168] Furthermore, in the following description, the first metal layer 63A in the metal layer constituting the third electrode 63, which is in contact with the upper surface of the low-concentration impurity layer 33 in the Schottky junction region 93, is also referred to as the Schottky junction metal layer 63A.

[0169] In the region surrounding the Schottky junction region 93 in a plan view of the semiconductor device 1, a protective ring 37 containing impurities of a second conductivity type different from the first conductivity type is formed in the low-concentration impurity layer 33, extending from the upper surface of the semiconductor layer 40 to a fourth predetermined depth.

[0170] According to the above structure, the semiconductor device 1 includes a vertical MOS transistor 10 formed on the semiconductor layer 40, and a Schottky barrier diode 20 with a low concentration impurity layer 33 that functions as a cathode when the first conductivity type is N-type and as an anode when the first conductivity type is P-type.

[0171] Figure 3A This is a circuit diagram of semiconductor device 1 when the first conductivity type is N-type, i.e., when the second conductivity type is P-type. Figure 3B This is a circuit diagram of semiconductor device 1 when the first conductivity type is P-type, that is, when the second conductivity type is N-type.

[0172] like Figure 3A As shown, when the first conductivity type is N-type, the vertical MOS transistor 10 is a vertical N-channel MOS transistor 10. The first pad 51 functions as the source pad of the vertical N-channel MOS transistor 10, the second pad 52 functions as the drain pad of the vertical N-channel MOS transistor 10 and the cathode pad of the Schottky barrier diode 20, the third pad 53 functions as the anode pad of the Schottky barrier diode 20, and the fourth pad 54 functions as the gate pad of the vertical N-channel MOS transistor 10.

[0173] That is, when the first conductivity type is N-type, the first electrode 61 functions as the source electrode of the vertical N-channel MOS transistor 10, the second electrode 62 functions as the drain electrode of the vertical N-channel MOS transistor 10 and the cathode electrode of the Schottky barrier diode 20, the third electrode 63 functions as the anode electrode of the Schottky barrier diode 20, and the fourth electrode 64 functions as the gate electrode of the vertical N-channel MOS transistor 10.

[0174] like Figure 3BAs shown, when the first conductivity type is P-type, the vertical MOS transistor 10 is a vertical P-channel MOS transistor 10. The first pad 51 functions as the source pad of the vertical P-channel MOS transistor 10, the second pad 52 functions as the drain pad of the vertical P-channel MOS transistor 10 and the anode pad of the Schottky barrier diode 20, the third pad 53 functions as the cathode pad of the Schottky barrier diode 20, and the fourth pad 54 functions as the gate pad of the vertical P-channel MOS transistor 10.

[0175] That is, when the first conductivity type is P-type, the first electrode 61 functions as the source electrode of the vertical P-channel MOS transistor 10, the second electrode 62 functions as the drain electrode of the vertical P-channel MOS transistor 10 and the anode electrode of the Schottky barrier diode 20, the third electrode 63 functions as the cathode anode electrode of the Schottky barrier diode 20, and the fourth electrode 64 functions as the gate electrode of the vertical P-channel MOS transistor 10.

[0176] <Inspection> The semiconductor device 1 described above is a chip-sized, unsealed semiconductor device in which the vertical MOS transistor 10 and the Schottky barrier diode 20 can function as separate independent components, and the upper surface of the mounting surface on which the semiconductor device 1 is mounted to the mounting substrate or the like has four pads, i.e., four terminals.

[0177] Therefore, the semiconductor device 1 with the above structure can reduce its size in a plan view compared to conventional semiconductor devices that seal a MOS transistor and a Schottky barrier diode in a package in such a way that they can function as independent components.

[0178] Thus, the semiconductor device 1 according to the above structure provides a semiconductor device that can reduce the size in a plan view compared to the conventional one, in which a MOS transistor and a Schottky barrier diode are provided in such a way that they can function as independent elements.

[0179] Previously, commercially available semiconductor devices that encapsulate MOS transistors and Schottky barrier diodes in a single package, allowing them to function as independent components, and that have at least five terminals on the mounting surface, typically have dimensions of 2.0 mm × 2.0 mm or larger in a plan view. In contrast, semiconductor device 1 typically has dimensions of 0.6 mm × 0.6 mm in a plan view.

[0180] In the semiconductor device 1 with the above structure, in a plan view of the semiconductor device 1, at least a portion of the first electrode 61 is contained in the first square region 41, the second electrode 62 is contained in one of the square regions of the second square region 42 and the fourth square region 44, the third electrode 63 is contained in the third square region 43, and the fourth electrode 64 is contained in the other square region of the second square region 42 and the fourth square region 44.

[0181] Therefore, the distance between the anode and cathode of the Schottky barrier diode 20 can be made shorter, and the distance between the source and drain of the vertical MOS transistor 10 can also be made shorter.

[0182] Therefore, the semiconductor device 1 with the above structure can reduce the forward voltage of the Schottky barrier diode 20 and reduce the on-resistance of the vertical MOS transistor 10.

[0183] Figure 4 This is a comparison diagram of a comparative example semiconductor device 1000, which is configured by swapping the positions of the second electrode 62 and the third electrode 63 in a plan view of semiconductor device 1 relative to semiconductor device 1, comparing the on-resistance of the vertical MOS transistor of the comparative example with the on-resistance of the vertical MOS transistor 10 in semiconductor device 1.

[0184] That is, such as Figure 4 As shown, the comparative example semiconductor device 1000 is configured such that, in a plan view of the comparative example semiconductor device 1000, at least a portion of the comparative example first electrode 1061 and the comparative example first pad 1051 are included in a first square region 41, the comparative example third electrode 1063 and the comparative example third pad 1053 are included in a second square region 42, the comparative example second electrode 1062 and the comparative example second pad 1052 are included in a third square region 43, and the comparative example fourth electrode 1064 and the comparative example fourth pad 1054 are included in a fourth square region 44.

[0185] exist Figure 4 In this context, VGS is the applied voltage between the gate and source of the comparative example vertical MOS transistor and the vertical MOS transistor 10.

[0186] In addition, Figure 4 In the comparative example, the on-resistance values ​​of the vertical MOS transistor 10 and the vertical MOS transistor 10 are examples of simulated values ​​under the same conditions.

[0187] like Figure 4As shown, the on-resistance of the vertical MOS transistor 10 is lower than that of the vertical MOS transistor in the comparative example.

[0188] Thus, for semiconductor device 1, in a plan view of semiconductor device 1, the first electrode 61 is disposed in a position contained in the first square region 41, the second electrode 62 is disposed in a position contained in one of the square regions 42 and the fourth square region 44, the third electrode 63 is disposed in a position contained in the third square region 43, and the fourth electrode 64 is disposed in a position contained in the other square region contained in the second square region 42 and the fourth square region 44, thereby enabling the on-resistance of the vertical MOS transistor 10 to be relatively small.

[0189] In the implementation method, such as Figure 2 As shown, the Schottky barrier diode 20 is a planar type. Here, a planar Schottky barrier diode refers to a Schottky barrier diode with a structure in which a single impurity semiconductor and a metal are Schottky bonded in the planar portion of a single impurity semiconductor.

[0190] However, the Schottky barrier diode 20 is a planar type, but it is not necessarily limited to a planar type.

[0191] Furthermore, planar Schottky barrier diodes can typically be formed with fewer processing steps. Therefore, if the Schottky barrier diode 20 is planar, the semiconductor device 1 can be manufactured more easily.

[0192] Alternatively, the metal components of the first metal layer 61A, the first metal layer 62A, the first metal layer 63A, and the first metal layer 64A may be equal; the metal components of the second metal layer 61B, the second metal layer 62B, the second metal layer 63B, and the second metal layer 64B may be equal; the metal components of the third metal layer 61C, the third metal layer 62C, the third metal layer 63C, and the third metal layer 64C may be equal; the metal components of the fourth metal layer 61D, the fourth metal layer 62D, the fourth metal layer 63D, and the fourth metal layer 64D may be equal; and the metal components of the fifth metal layer 61E, the fifth metal layer 62E, the fifth metal layer 63E, and the fifth metal layer 64E may be equal.

[0193] Thus, the first metal layer 61A to the first metal layer 64A can be formed through the same processing steps, the second metal layer 61B to the second metal layer 64B can be formed through the same processing steps, the third metal layer 61C to the third metal layer 64C can be formed through the same processing steps, the fourth metal layer 61D to the fourth metal layer 64D can be formed through the same processing steps, and the fifth metal layer 61E to the fifth metal layer 64E can be formed through the same processing steps.

[0194] Therefore, it is relatively easy to manufacture semiconductor devices 1.

[0195] On the other hand, the metal material of the first metal layer 62A, i.e. the ohmic bonding metal layer 62A, and the metal material of the first metal layer 63A, i.e. the Schottky bonding metal layer 63A, can also be different from each other.

[0196] Thus, the characteristics of the Schottky barrier diode 20 can be made to be the desired characteristics that cannot be achieved when the metal material of the ohmic junction metal layer 62A is equal to that of the Schottky junction metal layer 63A.

[0197] Typically, the characteristics of a Schottky barrier diode vary depending on the type of metal material used to form the Schottky junction.

[0198] Figure 5 This is a schematic diagram illustrating the relationship between the type of metal material forming the Schottky junction and the characteristics of the Schottky barrier diode when the first conductivity type is N-type.

[0199] exist Figure 5 In the diagram, Φ represents the size of the Schottky barrier diode, VF represents the forward voltage of the Schottky barrier diode, and IR represents the reverse leakage current of the Schottky barrier diode. Additionally, in... Figure 5 In this system, Ti represents titanium, V represents vanadium, Mo represents molybdenum, W represents tungsten, and Pt represents platinum.

[0200] like Figure 5 As shown, the forward voltage VF and reverse leakage current IR in a Schottky barrier diode are typically in a trade-off relationship.

[0201] Therefore, if the desired characteristics of the Schottky barrier diode 20 cannot be achieved if the metal materials of the ohmic junction metal layer 62A and the Schottky junction metal layer 63A are the same, the desired characteristics of the Schottky barrier diode 20 that cannot be achieved when the metal materials of the Schottky junction metal layer 63A are the same can be achieved by setting the metal material of the Schottky junction metal layer 63A to a suitable metal material that is different from the metal material of the ohmic junction metal layer 62A.

[0202] For example, if the metal component of the ohmic junction metal layer 62A is titanium, and if the desired characteristics of the Schottky barrier diode 20 cannot be achieved if the metal component of the Schottky junction metal layer 63A is titanium, but the desired characteristics of the Schottky barrier diode 20 can be achieved if the metal component of the Schottky junction metal layer 63A is platinum, then the metal component of the Schottky junction metal layer 63A can be set to platinum, which is different from the titanium that is the metal component of the ohmic junction metal layer 62A.

[0203] In addition, such as Figure 1 As shown, in the plan view of semiconductor device 1, the Schottky junction region 93 can be any one of a circle, an ellipse, an oblong shape, and a rounded corner formed by rounding the corners of a rectangle (in... Figure 1 In the example, it is an oblong shape.

[0204] The Schottky junction region 93 of the above structure does not have corners. As a result, the excessive concentration of the electric field in the Schottky junction region 93 is mitigated.

[0205] Therefore, the semiconductor device 1 with the above structure can improve the withstand voltage characteristics in the Schottky junction region 93.

[0206] In addition, such as Figure 1 As shown, in a plan view of semiconductor device 1, the shortest distance dd between Schottky junction region 93 and Ohmic junction region 92 can be shorter than the shortest distance ds between Schottky junction region 93 and source junction region 91.

[0207] The semiconductor device 1 with the above structure can make the distance between the Schottky junction region 93 and the Ohm junction region 92 relatively small.

[0208] Therefore, the forward voltage of the Schottky barrier diode 20 can be made relatively small according to the semiconductor device 1 with the above structure.

[0209] Furthermore, the relationship between the area of ​​the Schottky junction region 93 and the area of ​​the third pad 53 in the plan view of semiconductor device 1 can be seen as follows: Figure 1 As illustrated, the area of ​​the Schottky junction region 93 can be made smaller than the area of ​​the third pad 53, or conversely, the area of ​​the Schottky junction region 93 can be made larger than the area of ​​the third pad 53.

[0210] In a plan view of semiconductor device 1, when the area of ​​Schottky junction region 93 is greater than the area of ​​third pad 53, the area of ​​Schottky junction region 93 can be made larger.

[0211] Therefore, the forward on-resistance of the Schottky barrier diode 20 is relatively small.

[0212] Therefore, the forward voltage of the Schottky barrier diode 20 can be made relatively small according to the semiconductor device 1 with the above structure.

[0213] Furthermore, in the plan view of semiconductor device 1, when the area of ​​Schottky junction region 93 is smaller than the area of ​​third pad 53, the area of ​​Schottky junction region 93 can be made relatively small.

[0214] Therefore, the semiconductor device 1 with the above structure can make the reverse leakage current of the Schottky barrier diode 20 relatively small.

[0215] In addition, such as Figure 1 As shown, in the plan view of semiconductor device 1, the Schottky junction region 93 is any one of a circle, an ellipse, an oblong shape, and a rounded shape obtained by rounding the corners of a rectangle. The source junction region 91 is a rounded shape obtained by rounding the corners of a polygon (in the embodiment, it is exemplified as a rounded shape obtained by rounding the corners of a rectangle; in the modified examples 1 and 2 described later, it is exemplified as a rounded shape obtained by rounding the corners of a polygon with more sides than a rectangle). The minimum radius of curvature of the outer periphery of the Schottky junction region 93 can be greater than or equal to the minimum radius of curvature of the source junction region 91.

[0216] Therefore, the suppression of excessive concentration of electric field in the Schottky junction region 93 can be equal to or greater than the suppression of excessive concentration of electric field in the source junction region 91.

[0217] Therefore, the semiconductor device 1 according to the above structure can have its breakdown voltage characteristics determined by the excessive concentration of the electric field in the source junction region 91, rather than by the excessive concentration of the electric field in the Schottky junction region 93.

[0218] Furthermore, as described above, in the embodiments, the first electrode 61 is not necessarily limited to any particular type, such as... Figure 1 As shown, in a plan view of semiconductor device 1, at least a portion of the first electrode 61 is also included in the second square region 42, the third square region 43, and the fourth square region 44.

[0219] In this case, such as Figure 1 As shown, in a plan view of semiconductor device 1, the first square region 41 may not include at least a portion of the second electrode 62, at least a portion of the third electrode 63, and at least a portion of the fourth electrode 64.

[0220] Therefore, semiconductor device 1 can make the active region of the vertical MOS transistor 10, which includes the entire portion of the channel formed when a voltage above a threshold is applied to the gate conductor 15, relatively large. Thus, semiconductor device 1 can make the on-resistance of the vertical MOS transistor 10 relatively small.

[0221] On the other hand, as described above, in a plan view of the semiconductor device 1, at least a portion of the first electrode 61 need not necessarily be included in the second square region 42, the third square region 43, and the fourth square region 44.

[0222] Figure 6 This is a planar schematic diagram illustrating another example of the construction of semiconductor device 1.

[0223] like Figure 6 As shown, for example, in a plan view of semiconductor device 1, the first electrode 61 may also be entirely contained within the first square region 41.

[0224] (Variation Example 1) Hereinafter, a modified semiconductor device of embodiment 1 will be described, in which the first electrode 61, the second electrode 62, the third electrode 63, and the fourth electrode 64 are respectively replaced with the first electrode of modified embodiment 1, the second electrode of modified embodiment 1, the third electrode of modified embodiment 1, and the fourth electrode of modified embodiment 1, and the source junction region 91, the ohmic junction region 92, and the Schottky junction region 93 are respectively replaced with the source junction region of modified embodiment 1, the ohmic junction region of modified embodiment 1, and the Schottky junction region of modified embodiment 1.

[0225] Here, regarding the semiconductor device of Modification 1, the same reference numerals are assigned to the same components as those of semiconductor device 1, and detailed descriptions are omitted. The description will focus on the differences from semiconductor device 1.

[0226] Figure 7 This is a plan view illustrating an example of the structure of semiconductor device 1A in Modified Example 1.

[0227] like Figure 7 As shown, semiconductor device 1A is constructed by changing the first electrode 61, the second electrode 62, the third electrode 63, and the fourth electrode 64 of semiconductor device 1 in the embodiment to the first electrode 161, the second electrode 162, the third electrode 163, and the fourth electrode 164, respectively, and changing the source junction region 91, the ohmic junction region 92, and the Schottky junction region 93 to the source junction region 191, the ohmic junction region 192, and the Schottky junction region 193, respectively.

[0228] exist Figure 7 In, with Figure 1Similarly, the first electrode 161, the second electrode 162, the third electrode 163, the fourth electrode 164, the source junction region 191, the ohmic junction region 192, and the Schottky junction region 193 are represented by dashed lines as if they could be visually identified from the outside of the semiconductor device 1A, but in reality they cannot be directly visually identified from the outside of the semiconductor device 1A.

[0229] like Figure 7 As shown, in a plan view of semiconductor device 1A, the first electrode 161 is partially contained in the first square region 41, and another portion of it is contained in the second square region 42 in a manner that protrudes between the second electrode 162 and the third electrode 163. Furthermore, another portion of it is contained in the fourth square region 44 in a manner that protrudes between the third electrode 163 and the fourth electrode 164.

[0230] Furthermore, in a plan view of semiconductor device 1A, the source junction region 191 is included in the second square region 42 in a manner that protrudes between the second electrode 162 and the third electrode 163, and in the fourth square region 44 in a manner that protrudes between the third electrode 163 and the fourth electrode 164.

[0231] In addition, such as Figure 7 As shown, in a plan view of semiconductor device 1A, the first square region 41 does not include at least a portion of the second electrode 162, at least a portion of the third electrode 163, and at least a portion of the fourth electrode 164.

[0232] According to the above structure, the semiconductor device 1A can make the active region of the vertical MOS transistor 10, which includes the entire portion of the channel formed when a voltage above a threshold is applied to the gate conductor 15, relatively large. Therefore, the semiconductor device 1A can make the on-resistance of the vertical MOS transistor 10 relatively small.

[0233] In addition, such as Figure 7 As shown in the plan view of semiconductor device 1A, the second electrode 162 is a rectangle having a first opposing side 621 and a second opposing side 622. The first opposing side 621 has a portion that is parallel to a first portion 611 in the outer periphery of the first electrode 161, and the second opposing side 622 has a portion that is parallel to a second portion 612 in the outer periphery of the first electrode 161.

[0234] According to the above structure, the semiconductor device 1A allows for a relatively long opposition length between the first electrode 161, which functions as the source electrode of the vertical MOS transistor 10, and the second electrode 162, which functions as the drain electrode of the vertical MOS transistor 10. Therefore, the semiconductor device 1A can reduce the on-resistance of the vertical MOS transistor 10.

[0235] (Variation Example 2) The semiconductor device of Modification 2 will now be described. This semiconductor device is configured such that, relative to the semiconductor device 1A of Modification 1, in a plan view of the semiconductor device 1A, a portion of the first electrode 161 protrudes between the third electrode 163 and the fourth electrode 164, while another portion of the first electrode 161 does not protrude between the second electrode 162 and the third electrode 163. Furthermore, a portion of the source junction region 191 protrudes between the third electrode 163 and the fourth electrode 164, and the other portion of the source junction region 191... The portion does not protrude between the second electrode 162 and the third electrode 163. In this way, the first electrode 161, the second electrode 162, the third electrode 163 and the fourth electrode 164 are respectively changed to the first electrode of Modified Example 2, the second electrode of Modified Example 2, the third electrode of Modified Example 2 and the fourth electrode of Modified Example 2. The source junction region 191, the ohmic junction region 192 and the Schottky junction region 193 are respectively changed to the source junction region of Modified Example 2, the ohmic junction region of Modified Example 2 and the Schottky junction region of Modified Example 2.

[0236] Here, regarding the semiconductor device of Modification 2, the same reference numerals are assigned to the same components as those of semiconductor device 1A, and their detailed descriptions are omitted. The description will focus on the differences from semiconductor device 1A.

[0237] Figure 8 This is a plan view illustrating an example of the structure of semiconductor device 1B in Modified Example 2.

[0238] like Figure 8 As shown, the semiconductor device 1B is configured such that, from the semiconductor device 1A of Modification 1, the first electrode 161, the second electrode 162, the third electrode 163, and the fourth electrode 164 are replaced with the first electrode 261, the second electrode 262, the third electrode 263, and the fourth electrode 264, respectively, and the source junction region 191, the ohmic junction region 192, and the Schottky junction region 193 are replaced with the source junction region 291, the ohmic junction region 292, and the Schottky junction region 293, respectively.

[0239] exist Figure 8 In, with Figure 1 and Figure 7Similarly, the first electrode 261, the second electrode 262, the third electrode 263, the fourth electrode 264, the source junction region 291, the ohmic junction region 292, and the Schottky junction region 293 are represented by dashed lines as if they could be visually identified from the outside of the semiconductor device 1B, but in reality they cannot be directly visually identified from the outside of the semiconductor device 1B.

[0240] like Figure 8 As shown, in a plan view of semiconductor device 1B, the first electrode 261 is partially contained in the first square region 41, and another portion of it is contained in the fourth square region 44 in a manner that protrudes between the third electrode 263 and the fourth electrode 264. On the other hand, it does not contain a portion that protrudes between the second electrode 262 and the third electrode 263.

[0241] Furthermore, in a plan view of semiconductor device 1B, the source junction region 291 is included in the fourth square region 44 in a manner that protrudes between the third electrode 263 and the fourth electrode 264, in addition to a portion of it being included in the first square region 41. On the other hand, it does not include a portion protruding between the second electrode 262 and the third electrode 263.

[0242] The semiconductor device 1B with the above structure, like the semiconductor device 1A of Modified Example 1, does not have a first electrode 261, which functions as the source electrode of the vertical MOS transistor 10, sandwiched between the second electrode 262, which functions as the cathode electrode of the Schottky barrier diode 20, and the third electrode 263, which functions as the anode electrode of the Schottky barrier diode 20.

[0243] Therefore, the semiconductor device 1B with the above structure can suppress the degradation of the characteristics of the Schottky barrier diode 20.

[0244] (Replenish) The above description illustrates a semiconductor device according to one aspect of this disclosure based on embodiments, variations 1 and 2. However, this disclosure is not limited to these embodiments, variations 1 and 2. Various modifications conceived by those skilled in the art to embodiments, variations 1 or 2 may be included within the scope of one or more aspects of this disclosure, provided they do not depart from the spirit of this disclosure.

[0245] Industrial applicability This disclosure can be widely used in semiconductor devices.

[0246] Explanation of reference numerals in the attached figures 1. 1A, 1B, 1000 semiconductor devices 10. Vertical MOS transistor, vertical N-channel MOS transistor, vertical P-channel MOS transistor 14 source regions 15 Gate Conductors 16 gate insulating film 17 gate trench 18 body regions 20 Schottky barrier diode 32 Semiconductor Substrate 33 Low-concentration impurity layer 34 interlayer insulation layers 35 passivation layer 36 Drain Pull-up Region 37 Protective Ring 40 semiconductor layers 41 First square region 42. Second square region, containing the second pad square region 43 Third square region 44. The fourth square region, containing the fourth pad square region. 51, 1051 first pad 52, 1052 second pad 53, 1053 third pad 54, 1054 fourth pad 61, 161, 261, 1061 First Electrode 61A, 64A First Metal Layer 62A First Metal Layer, Ohmic Bonding Metal Layer 63A first metal layer, Schottky bonding metal layer 61B, 62B, 63B, 64B Second Metal Layer 61C, 62C, 63C, 64C third metal layer 61D, 62D, 63D, 64D fourth metal layer 61E, 62E, 63E, 64E Fifth Metal Layer 62, 162, 262, 1062 second electrodes 63, 163, 263, 1063 third electrodes 64, 164, 264, 1064 fourth electrodes 71 First Vertex 72 Second Vertex 73 Third Vertex 74 Fourth Vertex 81 First diagonal 82 Second diagonal Source junction regions 91, 191, and 291 92, 192, 292 ohm joint area 93, 193, 293 Schottky junction regions Centers 121, 151, 152, 153, and 154 611 Part 1 612 Part Two 621 First Opposite Edge 622 Second Opposite Edge

Claims

1. A chip-scale packaged semiconductor device, characterized in that, have: A semiconductor layer having a semiconductor substrate of a first conductivity type and a low-concentration impurity layer of the first conductivity type, the semiconductor substrate containing a first concentration of impurities, and the low-concentration impurity layer being formed in contact with the upper surface of the semiconductor substrate and containing a second concentration of impurities lower than the first concentration; A vertical MOS transistor is formed on the semiconductor layer; as well as In a Schottky barrier diode, when the first conductivity type is N-type, the low-concentration impurity layer functions as the cathode; when the first conductivity type is P-type, the low-concentration impurity layer functions as the anode. The upper surface of the semiconductor device further includes: The first pad functions as the source pad of the vertical MOS transistor. The second pad functions as the drain pad of the vertical MOS transistor, and when the first conductivity type is N-type, it functions as the cathode pad of the Schottky barrier diode, and when the first conductivity type is P-type, it functions as the anode pad of the Schottky barrier diode. The third pad functions as the anode pad of the Schottky barrier diode when the first conductivity type is N-type, and as the cathode pad of the Schottky barrier diode when the first conductivity type is P-type; and The fourth pad functions as the gate pad of the vertical MOS transistor. In the plan view of the semiconductor device, The semiconductor device is a square with a first vertex, a second vertex, a third vertex, and a fourth vertex in a counterclockwise direction. The first pad, the second pad, the third pad, and the fourth pad are all circular with the same diameter. The center of the first pad and the center of the third pad are located on the first diagonal line connecting the first vertex and the third vertex. The center of the second pad and the center of the fourth pad are located on the second diagonal line connecting the second vertex and the fourth vertex. The distances between the center of the semiconductor device and the center of the first pad, the distances between the center of the semiconductor device and the center of the second pad, the distances between the center of the semiconductor device and the center of the third pad, and the distances between the center of the semiconductor device and the center of the fourth pad are equal.

2. The semiconductor device according to claim 1, characterized in that, In the plan view of the semiconductor device, If the area of ​​the semiconductor device is divided into four equal parts by four non-overlapping square regions: a first square region with a diagonal line connecting the first vertex and the center of the semiconductor device; a second square region with a diagonal line connecting the second vertex and the center of the semiconductor device; a third square region with a diagonal line connecting the third vertex and the center of the semiconductor device; and a fourth square region with a diagonal line connecting the fourth vertex and the center of the semiconductor device, then... The first pad is contained within the first square area. The second pad is contained within either the second square region or the fourth square region, i.e., the square region containing the second pad. The third pad is contained within the third square region. The fourth pad is contained in either the second square region or the fourth square region, i.e., the square region containing the fourth pad. The semiconductor layer further comprises a drain pull-out region of the first conductivity type containing a third concentration of impurities higher than the second concentration. This drain pull-out region is entirely contained within the square region containing the second pad in a plan view of the semiconductor layer. Furthermore, the drain pull-out region extends from the upper surface of the semiconductor layer through the low-concentration impurity layer to the semiconductor substrate. Furthermore, in a plan view of the semiconductor device, the semiconductor device includes: The first electrode, at least a portion of which is contained in the first square region, functions as the source electrode of the vertical MOS transistor. The second electrode, at least a portion of which is contained in the square region containing the second pad, functions as the drain electrode of the vertical MOS transistor, and functions as the cathode electrode of the Schottky barrier diode when the first conductivity type is N-type, and as the anode electrode of the Schottky barrier diode when the first conductivity type is P-type. The third electrode, at least a portion of which is contained in the third square region, functions as the anode electrode of the Schottky barrier diode when the first conductivity type is N-type, and as the cathode electrode of the Schottky barrier diode when the first conductivity type is P-type. as well as The fourth electrode, at least a portion of which is contained within the square region containing the fourth pad, functions as the gate electrode of the vertical MOS transistor.

3. The semiconductor device according to claim 2, characterized in that, The Schottky barrier diode is planar.

4. The semiconductor device according to claim 2, characterized in that, The second electrode has multiple metal layers including an ohmic-bonded metal layer that is ohmicly bonded to the drain pull-up region. The third electrode has multiple metal layers including a Schottky-bonded metal layer that is Schottky-bonded with the low-concentration impurity layer. The metal material of the ohmic bonding metal layer is the same as the metal material of the Schottky bonding metal layer.

5. The semiconductor device according to claim 2, characterized in that, The second electrode has multiple metal layers including an ohmic-bonded metal layer that is ohmicly bonded to the drain pull-up region. The third electrode has multiple metal layers including a Schottky-bonded metal layer that is Schottky-bonded with the low-concentration impurity layer. The metal material of the ohmic bonding metal layer is different from the metal material of the Schottky bonding metal layer.

6. The semiconductor device according to claim 2, characterized in that, In the plan view of the semiconductor device, At least a portion of the first electrode is further included in the square region containing the second pad and / or the square region containing the fourth pad. The first square region does not include at least a portion of the second electrode, at least a portion of the third electrode, and at least a portion of the fourth electrode.

7. The semiconductor device according to claim 6, characterized in that, In a plan view of the semiconductor device, the second electrode is a rectangle having a first opposing side and a second opposing side, the first opposing side having a portion that is parallel to a first portion of the outer periphery of the first electrode, and the second opposing side having a portion that is parallel to a second portion of the outer periphery of the first electrode.

8. The semiconductor device according to claim 6, characterized in that, In a plan view of the semiconductor device, at least a portion of the first electrode is not included in the square region containing the second pad.

9. The semiconductor device according to claim 2, characterized in that, The third electrode and the low-concentration impurity layer are Schottky bonded in the Schottky junction region. The second electrode and the drain pull-up region are ohmically bonded in the ohmically bonded region. The first electrode and the semiconductor layer are in contact in the source junction region. In the plan view of the semiconductor device, The Schottky junction region, contained within the third electrode, is any one of a circle, an ellipse, an oblong shape, and a rounded shape formed by rounding the corners of a rectangle. The shortest distance between the Schottky junction region and the Ohm junction region is shorter than the shortest distance between the Schottky junction region and the source junction region.

10. The semiconductor device according to claim 9, characterized in that, In a plan view of the semiconductor device, the area of ​​the Schottky junction region is larger than the area of ​​the third pad.

11. The semiconductor device according to claim 9, characterized in that, In a plan view of the semiconductor device, the area of ​​the Schottky junction region is smaller than the area of ​​the third pad.

12. The semiconductor device according to claim 2, characterized in that, The third electrode and the low-concentration impurity layer are Schottky bonded in the Schottky junction region. The first electrode is bonded to the semiconductor layer in the source junction region. In the plan view of the semiconductor device, The Schottky junction region is any one of the following: a circle, an ellipse, an oblong shape, and a rounded shape obtained by rounding the corners of a rectangle. The source junction region is a rounded shape obtained by rounding the corners of a polygon. The minimum radius of curvature of the outer periphery of the Schottky junction region is greater than or equal to the minimum radius of curvature of the source junction region.

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