Ferroelectric metal-controlled memristors and chips based on monolayer gallium oxide and monolayer blue phosphorus

Abstract

This invention relates to the field of memory technology, specifically to a ferroelectric metal-controlled memristor and chip based on a single layer of gallium oxide and a single layer of blue phosphorus. The ferroelectric metal-controlled memristor includes a top electrode layer, a control layer, and a bottom electrode layer, which are sequentially contacted from top to bottom. It combines the unique ferroelectric properties of gallium oxide with the excellent electrical properties of blue phosphorus, a two-dimensional material. The control layer formed by these two materials interacts through van der Waals forces, and the polarization direction of the gallium oxide layer is switched by applying voltages in different directions to the heterojunction, enabling memristor writing and reading. This avoids the interface defects and lattice mismatch problems introduced by strong chemical bonds in traditional memristors, thus reducing the operating power consumption of the memristor while improving its read / write speed and stability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to the field of memory technology, and preferably to a ferroelectric metal-controlled memristor and chip based on a single layer of gallium oxide and a single layer of blue phosphorus. Background Technology

[0002] With the rapid development of new technologies such as artificial intelligence and big data, the market demands increasingly higher performance from storage hardware. However, the huge demand for high-throughput data processing from current data-driven new technologies and scenarios highlights the shortcomings of silicon-based storage. Memristors are considered the fourth type of basic circuit component. They store information by adjusting the resistance state, exhibiting non-linear resistive characteristics that allow them to retain information even when power is off. Therefore, memristors can meet the needs of next-generation high-density information storage and high-performance computing. They can also achieve non-volatile state-based logic operations and neuromorphic computing functions, integrating information storage and computation into a single device. Among them, ferroelectric memristors (FeRAM-based memristors or Ferroelectric memristors) have attracted much attention due to their next-generation non-volatility and continuously adjustable resistance characteristics. Their ideal goal is to achieve ultra-high response speed, ultra-low operating voltage / power consumption, excellent multi-state storage capability (high distinguishability of low-conductivity states), and good scalability and reliability to meet the urgent needs of applications such as artificial intelligence and big data processing for high-performance, low-power integrated storage and computing.

[0003] However, current ferroelectric memristor technology based on ferroelectric materials is still in its immature stage. The main reason is that as the material size of memristors based on ferroelectric materials continues to shrink to the nanoscale, the ferroelectric polarization performance of the ferroelectric material decreases significantly at the critical thickness, disappears, or changes from out-of-plane polarization to in-plane polarization. Therefore, to maintain the stable ferroelectricity of ferroelectric memristors, the traditional ferroelectric layer is generally set to a thickness greater than 100 nm. This design severely restricts the miniaturization of memory cells, making it difficult to meet the requirements of high-density integration. For example, the ferroelectricity of PZT thin films degrades significantly when the thickness is less than about 70 nanometers, making it difficult to meet the high storage density requirements of modern electronic devices. Furthermore, although ferroelectric memories themselves have the advantage of low power consumption, some non-volatile memory devices based on ferroelectric materials represent information states through conductivity or DC current. As device size shrinks, the energy loss due to the Joule heating effect of the circuitry and devices increases significantly. When ferroelectric polarized charges come into contact with semiconductor or metal electrodes, free charges accumulate at the interface to counteract the internal polarization-bound charges, creating a "shielding effect" that reduces polarizability in order to meet electrostatic equilibrium conditions. Furthermore, traditional ferroelectrics are either insulators or semiconductors, requiring external driving charges to reverse their polarization. This necessitates integrating transistors (1T1C / 1T structure) into each memory cell, increasing the cell area (>6F). 2 This limits the improvement of storage density. Summary of the Invention

[0004] To address the technical problems of high reverse energy consumption and slow read / write speeds in existing ferroelectric memories due to their reliance on charge compensation transfer mechanisms, this invention provides a ferroelectric metal-controlled memristor and chip based on a single layer of gallium oxide and a single layer of blue phosphorus.

[0005] This invention employs the following technical solution: a ferroelectric metal-controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus, comprising a top electrode layer, a control layer, and a bottom electrode layer sequentially contacted from top to bottom, with the top and bottom electrode layers sandwiching the control layer in between; the control layer comprises a two-dimensional gallium oxide layer and a two-dimensional blue phosphorus layer, with the blue phosphorus layer stacked on the upper surface of the gallium oxide layer. After stacking, the blue phosphorus layer and the gallium oxide layer form a van der Waals heterojunction due to interlayer van der Waals forces. By applying voltages in different directions to the van der Waals heterojunction, the polarization direction of the gallium oxide layer is switched, thereby realizing the writing and reading of the memristor.

[0006] As a further improvement of the present invention, the van der Waals heterojunction exhibits metallic characteristics when the polarization direction of gallium oxide is toward the top electrode layer, and exhibits semiconductor characteristics when the polarization direction of gallium oxide is toward the bottom electrode layer.

[0007] As a further improvement of the present invention, when the polarization direction of gallium oxide is towards the top electrode layer, the potential at one end of the gallium oxide layer is higher than the potential at one end of the blue phosphorus layer, and the interlayer spacing between the gallium oxide layer and the blue phosphorus layer is a. When the polarization direction of gallium oxide is towards the bottom electrode layer, the potential at one end of the gallium oxide layer is lower than the potential at one end of the blue phosphorus layer, and the interlayer spacing between the gallium oxide layer and the blue phosphorus layer is b, where b < a.

[0008] As a further improvement of the present invention, when the polarization direction of gallium oxide is toward the top electrode layer, the potential difference between the gallium oxide layer and the blue phosphorus layer is greater than when the polarization direction of gallium oxide is toward the bottom electrode layer.

[0009] As a further improvement of the present invention, both the top electrode layer and the bottom electrode layer are made of the same material, and the material of the top electrode layer includes any one of Pt, Au or Ti.

[0010] As a further improvement of the present invention, a dielectric layer is deposited between the bottom electrode layer and the control layer. The dielectric layer is made of Al2O3 grown by atomic deposition technology.

[0011] As a further improvement of the present invention, a second dielectric layer is deposited between the top electrode layer and the control layer. The second dielectric layer is formed by growing silicon dioxide on the surface of a heavily doped silicon wafer through a thermal oxidation process.

[0012] As a further improvement of the present invention, the memristor also includes a source and a drain disposed on the left and right sides of the van der Waals heterojunction, respectively. The drain and the source are connected to the blue phosphor layer, the top electrode layer and the bottom electrode layer as gates, and then assembled into a gate-controlled memristor.

[0013] As a further improvement of the present invention, the top electrode layer and the bottom electrode layer are symmetrically grown on the upper and lower surfaces of the control layer, and the growth methods of the top electrode layer and the bottom electrode layer include any one of magnetron sputtering, electron beam evaporation, and atomic layer deposition.

[0014] The present invention also includes a non-volatile memory chip, which is packaged from a ferroelectric metal controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus as described above.

[0015] The technical solution provided by this invention has the following beneficial effects:

[0016] (1) The memristor based on ferroelectric metal modulation of monolayer gallium oxide and monolayer blue phosphorus provided in this solution combines the unique ferroelectric properties of gallium oxide (Ga2O3) with the excellent electrical properties of blue phosphorus (P) two-dimensional material. The modulation layers formed by the two have the interface advantage of a van der Waals heterojunction with typical van der Waals forces, avoiding the interface defects and lattice mismatch problems introduced by strong chemical bonds in traditional memristors, enhancing the reliability and stability of the device, and effectively reducing leakage current. By applying voltages in different directions to the heterojunction to switch the polarization direction of the gallium oxide layer, the polarization direction of gallium oxide can be switched, thereby realizing the writing and reading of the memristor. By adjusting the voltage, the energy consumption of the memristor during use can be greatly reduced, and the read and write speed of the memristor can be improved. This overcomes the problem that traditional memory relies on ion displacement to achieve polarization reversal, which requires charge replenishment, resulting in high energy consumption and limited read and write speed.

[0017] (2) The memristor based on gallium oxide and blue phosphorus provided in this solution achieves the reversible conversion of metal-semiconductor characteristics by combining van der Waals heterojunction into the memristor. This allows the memristor to retain the inherent advantages of the van der Waals heterojunction, such as weak interlayer interaction and atomic flat interface, while also having non-volatile resistance control characteristics, thereby reducing the operating power consumption of the memristor and improving the read / write speed and stability of the memristor. Attached Figure Description

[0018] Figure 1 This invention provides a schematic diagram of a ferroelectric metal-controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus.

[0019] Figure 2 This invention provides a schematic diagram of the structure of a ferroelectric metal-controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus, showing the polarization direction of gallium oxide as upward or downward.

[0020] Figure 3 This is a schematic diagram of the structure of a ferroelectric metal-controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus as a gate-controlled memristor, provided by the present invention.

[0021] Figure 4 This is a schematic diagram of the structure of the gallium oxide van der Waals heterojunction in the memristor provided by the present invention under different polarization directions.

[0022] Figure 5 This is a schematic diagram showing the distribution of electrostatic potential between the gallium oxide layer and the blue phosphorus layer in different polarization directions in the memristor provided by the present invention.

[0023] Figure 6 The image shows the projected energy band diagram of gallium oxide in the memristor provided by this invention under different polarization directions.

[0024] The layers in the diagram are labeled as follows: 1. Bottom electrode layer; 2. Control layer; 3. Top electrode layer; 4. Dielectric layer 2; 5. Dielectric layer 1. Detailed Implementation

[0025] The present invention will now be further described in conjunction with specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0026] In the description of this invention, it should be noted that directional terms such as "center," "lateral," "longitudinal," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limiting the specific scope of protection of this invention. The terms "first," "second," etc., in the specification and claims of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. The terms "comprising" and "having," and any variations thereof, in the specification and claims of this invention, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0027] This embodiment provides a ferroelectric metal-controlled memristor based on a single layer of gallium oxide (Ga2O3) and a single layer of blue phosphorus (P). Please refer to [reference needed]. Figure 1 and Figure 2As shown, it includes a top electrode layer 3, a control layer 2, and a bottom electrode layer 1 arranged sequentially from top to bottom. The top electrode layer 3 is disposed on the upper surface of the control layer 2 and contacts the upper surface of the control layer 2. The bottom electrode layer 1 is disposed on the lower surface of the control layer 2 and contacts the lower surface of the control layer 2. The top electrode layer 3 and the bottom electrode layer 1 sandwich the control layer 2 in the middle, thus forming a memristor with a sandwich-like structure. The control layer 2 includes a gallium oxide layer and a blue phosphorus layer with a two-dimensional material structure. The blue phosphorus layer is stacked on the upper surface of the gallium oxide layer. After stacking, the blue phosphorus layer and the gallium oxide layer form a van der Waals heterojunction due to the interlayer van der Waals forces. This scheme cleverly combines the unique ferroelectric properties of gallium oxide (Ga2O3) and the excellent electrical properties of blue phosphorus (P) two-dimensional material. The control layer 2 formed by the two has the interface advantage of a van der Waals heterojunction with typical van der Waals forces, avoiding the interface defects and lattice mismatch problems introduced by strong chemical bonds in traditional memristors, enhancing the reliability and stability of the device, and effectively reducing leakage current. By applying voltages in different directions to the heterojunction to switch the polarization direction of the gallium oxide layer, the writing and reading of the memristor can be achieved. Adjusting the voltage can significantly reduce the power consumption of the memristor and improve its read / write speed. In practical applications, the voltage applied to the heterojunction needs to meet the following requirements: the voltage must act on the gallium oxide barrier layer to generate an electric field capable of overcoming the coercive field of gallium oxide, a ferroelectric material; and the voltage application time must be longer than the relaxation time of the ferroelectric domains. In practical applications, applying a positive voltage can cause the polarization direction of the gallium oxide layer to face the top electrode layer 3 (i.e., polarization direction upwards), at which point the heterojunction can exhibit metallic characteristics, such as... Figure 2 As shown in the left-middle figure, by applying a directional voltage, the polarization direction of gallium oxide can be oriented towards the bottom electrode layer 1 (i.e., the polarization direction is downward). At this time, the heterojunction can exhibit semiconductor characteristics, such as... Figure 2As shown in the right-middle figure, this scheme integrates a van der Waals heterojunction into the memristor, achieving a reversible conversion between metal and semiconductor characteristics. This allows the memristor to retain the inherent advantages of the van der Waals heterojunction, such as weak interlayer interactions and atomically flat interfaces, while also possessing non-volatile resistance control characteristics. This reduces the operating power consumption of the memristor and improves its read / write speed and stability. It can be understood that when the heterojunction exhibits metallic characteristics, the corresponding logic value of the memristor is "1," and when it exhibits semiconductor characteristics, the corresponding logic value is "0." This allows the memristor to directly perform Boolean operations such as AND, OR, and NOT by applying voltages of different polarities / amplitudes, eliminating the need for data to travel back and forth between the storage and computing units. This reduces computational latency and power consumption by 1-2 orders of magnitude, making it an ideal carrier for neural network synaptic simulation. Because the van der Waals heterojunction in this scheme has an adjustable polarization direction, when the polarization direction of gallium oxide (GaO) is towards the top electrode layer 3, the potential at one end of the GaO layer is higher than that at the other end of the blue phosphorus layer. When the polarization direction of GaO is towards the top electrode layer 3, a polarization electric field pointing from GaO to blue phosphorus is generated at the van der Waals heterojunction interface. This electric field causes the energy bands near the interface to bend, forming a barrier configuration that facilitates the tunneling of charge carriers (electrons or holes). At the same time, since the work function / potential of GaO is higher than that of blue phosphorus, the two together will form an internal electric field pointing from GaO to blue phosphorus. At this time, the polarization electric field and the internal electric field are aligned, which can achieve a superposition enhancement effect of electric field, so that the potential at one end of the GaO layer is lower than that at the other end of the blue phosphorus layer. Moreover, this superimposed electric field will reduce the interface barrier height and widen the barrier tunneling width, making it easier for charge carriers to be injected from the high-potential GaO into the blue phosphorus. When the polarization direction of the gallium oxide layer faces the bottom electrode layer 1, the potential at one end of the gallium oxide layer is less than the potential at the other end of the blue phosphorus layer. Specifically, when the polarization direction is downward, the polarization electric field direction of the van der Waals heterojunction is from blue phosphorus to gallium oxide, and the potential of the gallium oxide layer is less than that of the blue phosphorus layer. Under the superposition of the two electric fields, a strong built-in barrier electric field is generated at the van der Waals heterojunction interface. The generated strong built-in barrier electric field significantly increases the barrier height at the van der Waals heterojunction interface, greatly suppressing the tunneling and drift of charge carriers. This allows the memristor to be in a high-resistance state of deep shutdown. Furthermore, since gallium oxide itself is a wide bandgap semiconductor, its low potential characteristics further weaken its charge carrier generation capability. Combined with the built-in barrier electric field, this achieves both improved storage reliability and reduced power consumption of the memristor. This scheme achieves the resistance switching function of the memristor through the configuration of gallium oxide polarization direction downward and gallium oxide potential being less than blue phosphorus potential.

[0028] Specifically, when the polarization direction of gallium oxide is towards the top electrode layer 3, the potential difference between the gallium oxide layer and the blue phosphorus layer is greater than when the polarization direction of gallium oxide is towards the bottom electrode layer 1.

[0029] When the polarization direction of gallium oxide (GaO) faces the top electrode layer 3, the interlayer spacing between the GaO and blue phosphorus layers is 'a'. When the polarization direction of GaO faces the bottom electrode layer 1, the interlayer spacing between the GaO and blue phosphorus layers is 'b', where b < a. The essence of the above structural characteristics of the memristor in this scheme is mainly the van der Waals force modulation effect caused by the difference in interlayer charge distribution induced by ferropolarization: when GaO is polarized upwards, the interlayer spacing between GaO and blue phosphorus is larger. A larger interlayer spacing reduces the interlayer coupling strength of the van der Waals heterojunction, thereby reducing the width of the tunneling barrier at the van der Waals heterojunction interface, making it easier for charge carriers (electrons / holes) to jump between layers. At the same time, the large spacing weakens the trapping effect of defects at the van der Waals heterojunction interface. When GaO is polarized downwards, the interlayer anisotropic electrostatic attraction between GaO and blue phosphorus is dominant, making the interlayer spacing between the GaO and blue phosphorus layers smaller. The smaller interlayer spacing enhances the interlayer coupling between the gallium oxide layer and the blue phosphorus layer, and the height and width of the van der Waals heterojunction interface barrier increase simultaneously. In addition, this scheme can achieve precise control of polarization intensity by adjusting the amplitude of the external voltage, thus enabling the memristor of this scheme to form multiple stable intermediate resistance states, thereby improving the storage density of the memristor.

[0030] The advantages of using the same material for both the top electrode layer 3 and the bottom electrode layer 1 are as follows: (1) This allows the memristor to be designed as a symmetrical electrode structure, thereby eliminating the "asymmetry" of the interface between the electrode layer and the control layer 2, and improving the uniformity and consistency of the van der Waals heterojunction in the resistive state. (2) When the top electrode layer 3 and the bottom electrode layer 1 are made of the same material, the upper and lower electrodes can be prepared in one coating process (such as using magnetron sputtering to deposit the top electrode layer 3 and the bottom electrode layer 1 at the same time), or the top electrode layer 3 and the bottom electrode layer 1 can be deposited separately using the same set of masks, thereby greatly shortening the process flow of the memristor and reducing the equipment debugging cost during mass production. (3) The top electrode layer 3 and the bottom electrode layer 1 are made of the same material, so that the electrochemical stability of the two electrode layers is consistent, and the corrosion resistance of their upper and lower interfaces is the same. There will be no situation where the active electrode side is prone to oxidation / degradation due to the different electrochemical activities of the heteroelectrodes, thereby destroying the interface contact. (4) Symmetrical electrode design of the same material In the three-dimensional integrated architecture of vertically bonding of multilayer memristors, adjacent memristors can share the same material electrode in the middle, without the need to introduce a heterogeneous transition layer, thereby reducing the signal transmission loss of multilayer memristors.

[0031] The material of the top electrode layer 3 includes any one of Pt, Au, or Ti.

[0032] The top electrode layer 3 and the bottom electrode layer 1 are symmetrically grown on the upper and lower surfaces of the control layer 2. The growth methods of the top electrode layer 3 and the bottom electrode layer 1 include any one of magnetron sputtering, electron beam evaporation, and atomic layer deposition.

[0033] A dielectric layer 5 is deposited between the bottom electrode layer 1 and the control layer 2. The dielectric layer 5 is made of Al2O3 grown using atomic deposition technology. A dielectric layer 4 is deposited between the top electrode layer 3 and the control layer 2. The dielectric layer 4 is made by growing silicon dioxide on the surface of a heavily doped silicon wafer using a thermal oxidation process.

[0034] Please refer to Figure 3 As shown, the memristor also includes source and drain electrodes located on the left and right sides of the van der Waals heterojunction, respectively. The drain and source electrodes are connected to the blue phosphor layer, and the top electrode layer 3 and bottom electrode layer 1 serve as the gate, thus assembling a gate-controlled memristor. This gate-controlled memristor structure is essentially a fusion of the functions of a two-dimensional semiconductor field-effect transistor and a ferroelectric memristor. Its core innovation lies in achieving synergistic control of "polarization state and carrier concentration" through dual gates, which not only improves the stability and multi-valued capability of non-volatile memory but also endows the device with logic operation functions. It is a key architectural solution to solve the von Neumann bottleneck and realize high-density in-memory computing chips, especially suitable for applications such as artificial intelligence neural networks, flexible electronics, and IoT edge computing.

[0035] The ferroelectric metal controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus provided in this embodiment can also be marketed in the form of a packaged integrated circuit chip. Therefore, this embodiment can also provide a non-volatile memory chip, which is packaged from the aforementioned ferroelectric metal controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus.

[0036] Performance testing

[0037] To verify the performance of the ferroelectric metal-controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus provided in this embodiment, first-principles calculations (i.e., DFT calculations) were performed, and van der Waals force corrections and Grimme's D3 method were used to obtain the interlayer spacing, potential difference, and band structure of the gallium oxide and blue phosphorus layers under different polarization directions. The specific results are as follows:

[0038] Figure 4 This is a schematic diagram of the structure of gallium oxide van der Waals heterojunctions in different polarization directions. Figure 4 Figure (a) shows a schematic diagram of the van der Waals heterojunction structure when the polarization direction of gallium oxide is upward. Figure 4 Figure (b) shows a schematic diagram of the van der Waals heterojunction structure when the polarization direction of gallium oxide is downward.

[0039] First-principles calculations (DFT calculations) and using van der Waals force correction and Grimme's D3 method yielded that when the polarization direction of gallium oxide is upward, the interlayer spacing between the gallium oxide layer and the blue phosphorus layer is approximately [value missing]. When the polarization direction of gallium oxide is downward, the interlayer spacing between the gallium oxide layer and the blue phosphorus layer is approximately... This result also proves that there is a typical van der Waals interaction (VDW) between the gallium oxide layer and the blue phosphorus layer.

[0040] Figure 5 This is a schematic diagram showing the distribution of electrostatic potential between the gallium oxide layer and the blue phosphorus layer under different polarization directions. Figure 5 The horizontal axis Z represents the height of the van der Waals heterojunction in the Z direction. Figure 5 Figure (a) shows the distribution of electrostatic potential between the gallium oxide layer and the blue phosphorus layer when the gallium oxide polarization direction is upward. Figure 5 Figure (b) shows a schematic diagram of the electrostatic potential distribution between the gallium oxide layer and the blue phosphorus layer when the polarization direction of gallium oxide is downward. Through analysis of... Figure 5 Analysis shows that when the polarization direction of gallium oxide is upward, the potential at one end of the gallium oxide layer is higher than that at the end of the blue phosphorus layer, resulting in a small potential difference of approximately 1.2 eV between the two layers. When the polarization direction of gallium oxide is downward, the potential at one end of the gallium oxide layer is lower than that at the end of the blue phosphorus layer, resulting in a larger potential difference of approximately 2.77 eV between the two layers.

[0041] Figure 6 This is a projected band structure of gallium oxide in different polarization directions. Figure 6 The horizontal axis represents the high-symmetry points of the Brillouin zone. Figure 6 Figure (a) shows the projected band structure of the van der Waals heterojunction with the gallium oxide polarization direction upward. Figure 6 As can be seen in Figure (a), when the polarization direction of gallium oxide is upward, the conduction band bottom (CBM) contributed by gallium oxide crosses the Fermi level, while the valence band top (VBM) contributed by blue phosphorus crosses the Fermi level. Therefore, the van der Waals heterojunction under this polarization direction produces metallic properties. Figure 6 Figure (b) shows the projected band structure of the van der Waals heterojunction with the gallium oxide polarization direction pointing downwards. Figure 6 As can be seen in Figure (b), when the polarization direction of gallium oxide is downward, neither the conduction band bottom (CBM) contributed by gallium oxide nor the valence band top (VBM) contributed by blue phosphorus can cross the Fermi level. Therefore, the van der Waals heterojunction under this polarization direction produces semiconductor characteristics.

[0042] The basic principles, main features, and advantages of this invention have been described above. Those skilled in the art should understand that this invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made without departing from the spirit and scope of the invention, and all such changes and modifications fall within the scope of the invention as claimed. The scope of protection claimed by this invention is defined by the appended claims and their equivalents.

Claims

1. A ferroelectric metal-gated memristor based on a single layer of gallium oxide and a single layer of blue phosphorus, characterized in that, It includes a top electrode layer (3), a control layer (2) and a bottom electrode layer (1) arranged sequentially from top to bottom; the control layer (2) includes a blue phosphorus layer of two-dimensional material and a gallium oxide layer of two-dimensional material stacked on the upper surface of the blue phosphorus layer. After stacking, the blue phosphorus layer and the gallium oxide layer form a van der Waals heterojunction due to the interlayer van der Waals forces. By applying voltages in different directions to the van der Waals heterojunction, the polarization direction of the gallium oxide layer can be switched, thereby enabling the writing and reading of the memristor. When the polarization direction of the gallium oxide is toward the top electrode layer (3), the potential at one end of the gallium oxide layer is higher than the potential at one end of the blue phosphorus layer and the interlayer spacing between the gallium oxide layer and the blue phosphorus layer is a; When the polarization direction of the gallium oxide layer is toward the bottom electrode layer (1), the potential at one end of the gallium oxide layer is less than the potential at one end of the blue phosphorus layer and the interlayer spacing between the gallium oxide layer and the blue phosphorus layer is b, b < a; When the polarization direction of gallium oxide is toward the top electrode layer (3), the potential difference between the gallium oxide layer and the blue phosphorus layer is greater than when the polarization direction of gallium oxide is toward the bottom electrode layer (1).

2. The ferroelectric metal-controlled memristor based on monolayer gallium oxide and monolayer blue phosphorus as described in claim 1, characterized in that, The van der Waals heterojunction exhibits metallic properties when the gallium oxide polarization direction is toward the top electrode layer (3), and semiconductor properties when the gallium oxide polarization direction is toward the bottom electrode layer (1).

3. The ferroelectric metal-controlled memristor based on monolayer gallium oxide and monolayer blue phosphorus as described in claim 1, characterized in that, The top electrode layer (3) and the bottom electrode layer (1) are both made of the same material, and the material of the top electrode layer (3) includes any one of Pt, Au or Ti.

4. The ferroelectric metal-controlled memristor based on monolayer gallium oxide and monolayer blue phosphorus as described in claim 1, characterized in that, A dielectric layer (5) is also deposited between the bottom electrode layer (1) and the control layer (2), and the dielectric layer (5) is made of Al2O3 grown by atomic deposition technology.

5. The ferroelectric metal-controlled memristor based on monolayer gallium oxide and monolayer blue phosphorus as described in claim 1, characterized in that, A dielectric layer 2 (4) is also deposited between the top electrode layer (3) and the control layer (2). The dielectric layer 2 (4) is made by growing silicon dioxide on the surface of a heavily doped silicon wafer through a thermal oxidation process.

6. The ferroelectric metal-controlled memristor based on monolayer gallium oxide and monolayer blue phosphorus as described in claim 1, characterized in that, The ferroelectric metal controlled memristor also includes a source and a drain located on the left and right sides of the van der Waals heterojunction, respectively. The drain and the source are connected to the blue phosphorus layer, and the top electrode layer (3) and the bottom electrode layer (1) serve as the gate, thus assembling a gate-controlled memristor.

7. The ferroelectric metal-controlled memristor based on monolayer gallium oxide and monolayer blue phosphorus as described in claim 1, characterized in that, The top electrode layer (3) and the bottom electrode layer (1) are symmetrically grown on the upper and lower surfaces of the control layer (2). The growth methods of the top electrode layer (3) and the bottom electrode layer (1) include any one of magnetron sputtering, electron beam evaporation, and atomic layer deposition.

8. A non-volatile memory chip, characterized in that, It is packaged from a ferroelectric metal controlled memristor based on a single layer of gallium oxide and a single layer of blue phosphorus as described in any one of claims 1-7.

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