Detection substrate and manufacturing method thereof, detector and imaging system

Abstract

The invention discloses a detection substrate, a manufacturing method thereof, a detector and an imaging system. The detection base plate comprises a substrate base plate and a substrate base plate, wherein the substrate base plate comprises a substrate base plate (BS) which comprises a pixel setting area (R0); and a plurality of pixel units (PXU) located in the pixel setting area (R0), the plurality of pixel units (PXU) including a mark pixel (MPX) in which at least one alignment mark (MK) is provided. The alignment marks are arranged, so that the alignment precision is improved in the manufacturing process of the detection substrate, and the uniformity of the image quality of a final product is improved.

Description

Detection substrate and manufacturing method thereof, detector, and imaging system Technical Field

[0001] Embodiments of the present disclosure relate to a detection substrate and a manufacturing method thereof, a detector, and an imaging system. Background Art

[0002] Cone beam CT (CBCT) is a cone beam projection computed tomography (CT) device. Its principle is that an X-ray generator uses a low dose (typically around 10 mA) of radiation to create a circular digital projection (DR) around the object being examined. The data from these multiple (180 to 360, depending on the device) digital projections around the object are then reconstructed in a computer to produce a three-dimensional image. The projection principle used by CBCT data acquisition is completely different from that of traditional sector scan CT, but the algorithms used for subsequent computer reconstruction are similar.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide a detection substrate and a manufacturing method thereof, a detector, and an imaging system.

[0005] An embodiment of the present disclosure provides a detection substrate, comprising: a base substrate including a pixel setting area; and a plurality of pixel units located in the pixel setting area, wherein the plurality of pixel units include a marking pixel, and at least one alignment mark is provided in the marking pixel.

[0006] In the detection substrate provided by the embodiment of the present disclosure, the alignment mark includes a first graphic and a second graphic, and the orthographic projection of the second graphic on the base substrate overlaps with the orthographic projection of the first graphic on the base substrate.

[0007] In the detection substrate provided in the embodiment of the present disclosure, the alignment mark includes an overlay mark, the first graphic of the overlay mark is a first material layer, the second graphic of the overlay mark is a second material layer, and the first material layer and the second material layer are made of different materials.

[0008] In the detection substrate provided by the embodiment of the present disclosure, multiple superimposed marks are provided in the same mark pixel, the first graphics of the multiple superimposed marks are made of the same material, and the second graphics of at least two of the multiple superimposed marks are made of different materials.

[0009] In the detection substrate provided by the embodiment of the present disclosure, the multiple superimposed marks are spaced apart from each other and arranged sequentially along one direction, or arranged in an array along two directions.

[0010] In the detection substrate provided in the embodiment of the present disclosure, the detection substrate includes a gate layer, an active layer, and a source-drain layer, the active layer is located on the side of the gate layer away from the base substrate, the source-drain layer is located on the side of the active layer away from the base substrate, the multiple superimposed marks include a first superimposed mark and a second superimposed mark, the first graphic of the first superimposed mark is located in the gate layer, the second graphic of the first superimposed mark is in the same layer as the active layer, the first graphic of the second superimposed mark is located in the gate layer, and the second graphic of the second superimposed mark is located in the source-drain layer.

[0011] In the detection substrate provided in the embodiment of the present disclosure, the detection substrate also includes a first passivation layer, which is located on the side of the source and drain layer away from the base substrate. The multiple superimposed marks also include a third superimposed mark, and the first graphic of the third superimposed mark is located in the gate layer. The second graphic of the third superimposed mark is a via in the first passivation layer.

[0012] In the detection substrate provided in the embodiment of the present disclosure, the detection substrate also includes a first passivation layer, a first electrode layer, a photoelectric sensing layer, a planarization layer, a second passivation layer, a bias line layer, and a third passivation layer arranged in sequence, wherein the multiple superimposed marks are located in the same mark pixel, and the multiple superimposed marks also include at least one of a third superimposed mark, a fourth superimposed mark, a fifth superimposed mark, a sixth superimposed mark, a seventh superimposed mark, an eighth superimposed mark, and a ninth superimposed mark.

[0013] In the detection substrate provided in the embodiment of the present disclosure, the multiple superimposed marks include a third superimposed mark, a fourth superimposed mark, a fifth superimposed mark, a sixth superimposed mark, a seventh superimposed mark, an eighth superimposed mark, and a ninth superimposed mark; the first graphics in the third superimposed mark, the fourth superimposed mark, the fifth superimposed mark, the sixth superimposed mark, the seventh superimposed mark, the eighth superimposed mark, and the ninth superimposed mark are all located in the gate layer, the second graphics of the third superimposed mark is a via in the first passivation layer, the second graphics of the fourth superimposed mark is located in the first electrode layer, the second graphics of the fifth superimposed mark is located in the photoelectric sensing layer, the second graphics of the sixth superimposed mark is a via in the planarization layer, the second graphics of the seventh superimposed mark is a via in the second passivation layer, the second graphics of the eighth superimposed mark is located in the second electrode layer, and the second graphics in the ninth superimposed mark is located in the bias line layer.

[0014] In the detection substrate provided in the embodiment of the present disclosure, the detection substrate also includes a gate line and a data line, at least one of the multiple pixel units includes a transistor, the gate line is connected to the gate of the transistor, and the data line is connected to the source of the transistor, and the alignment mark includes at least one of a first alignment mark and a second alignment mark. In the first alignment mark, the first graphic is in the same layer as the gate line, and the data line is the second graphic. In the second alignment mark, the second graphic is in the same layer as the data line, and the gate line is the first graphic.

[0015] In the detection substrate provided in the embodiment of the present disclosure, the alignment mark further includes a third alignment mark, and the orthographic projection of the second graphic of the third alignment mark on the base substrate is within the orthographic projection of the first graphic of the third alignment mark on the base substrate.

[0016] In the detection substrate provided by the embodiment of the present disclosure, the alignment mark further includes a splicing mark, the first graphic of the splicing mark is an alignment material layer, and the second graphic of the splicing mark is a hollow area.

[0017] In the detection substrate provided in the embodiment of the present disclosure, the stitching mark includes a first stitching mark, a second stitching mark and a third stitching mark, the first stitching mark is located in the gate layer, the second stitching mark is in the same layer as the active layer, and the third stitching mark is located in the source and drain layer.

[0018] In the detection substrate provided by the embodiment of the present disclosure, the marking pixel includes a first marking pixel, the splicing mark is located in the first marking pixel, the marking pixel includes a second marking pixel, the superimposed mark is located in the second marking pixel, and the first marking pixel and the second marking pixel are adjacent to each other.

[0019] In the detection substrate provided in an embodiment of the present disclosure, the marking pixel includes a first marking pixel, the stitching mark is located in the first marking pixel, the marking pixel includes a second marking pixel, the superimposed mark is located in the second marking pixel, the first marking pixel and the second marking pixel are spaced apart from each other, the multiple pixel units include multiple non-marking pixels, and at least one of the multiple non-marking pixels is provided between the first marking pixel and the second marking pixel.

[0020] In the detection substrate provided in the embodiment of the present disclosure, the first figure and the second figure have a first boundary distance and a second boundary distance in the first direction, the first direction is parallel to the base substrate, the ratio of the first boundary distance to the size of the larger one of the first figure and the second figure in the first direction is less than or equal to 1 / 3, and the ratio of the second boundary distance to the size of the larger one of the first figure and the second figure in the first direction is less than or equal to 1 / 3, the ratio of the first boundary distance to the size of the larger one of the first figure and the second figure in the first direction is greater than or equal to 1 / 4, and the ratio of the second boundary distance to the size of the larger one of the first figure and the second figure in the first direction is greater than or equal to 1 / 4.

[0021] In the detection substrate provided by the embodiment of the present disclosure, the orthographic projection of the second graphic on the base substrate is within the orthographic projection of the first graphic on the base substrate.

[0022] In the detection substrate provided in the embodiment of the present disclosure, the first figure and the second figure have a third boundary distance and a fourth boundary distance in the second direction, the second direction is parallel to the base substrate, the second direction intersects with the first direction, the ratio of the third boundary distance to the size of the first figure in the second direction is less than or equal to 1 / 3, and the ratio of the fourth boundary distance to the size of the first figure in the second direction is less than or equal to 1 / 3, the first figure and the second figure have a third boundary distance and a fourth boundary distance in the second direction, the ratio of the third boundary distance to the size of the first figure in the second direction is greater than or equal to 1 / 4, and the ratio of the fourth boundary distance to the size of the first figure in the second direction is greater than or equal to 1 / 4.

[0023] In the detection substrate provided by the embodiment of the present disclosure, at least two alignment marks are provided in the same marking pixel, and the two alignment marks are spaced apart from each other.

[0024] In the detection substrate provided in the embodiment of the present disclosure, the multiple pixel units include multiple photosensitive pixels and multiple positioning pixels, at least one marking pixel among the multiple marking pixels is adjacent to at least one photosensitive pixel among the multiple photosensitive pixels, and the marking pixel includes at least one positioning pixel among the multiple positioning pixels and / or at least one photosensitive pixel among the multiple photosensitive pixels.

[0025] In the detection substrate provided by the embodiment of the present disclosure, the positioning pixels include non-photosensitive pixels.

[0026] In the detection substrate provided by the embodiment of the present disclosure, the positioning pixel is configured to have a fixed grayscale, and the fixed grayscale does not change with real-time changes in incident light.

[0027] In the detection substrate provided in the embodiment of the present disclosure, the photosensitive pixel includes a first transistor, a first photoelectric sensing device, and a first bias line, the first electrode of the first photoelectric sensing device is electrically connected to the first transistor, and the second electrode of the first photoelectric sensing device is electrically connected to the first bias line.

[0028] In the detection substrate provided in the embodiment of the present disclosure, the positioning pixel includes a second transistor, or the positioning pixel includes a second transistor, a second photoelectric sensing device, and a second bias line, the first electrode of the second photoelectric sensing device is connected to the second transistor, and the second electrode of the second photoelectric sensing device is not electrically connected to the second bias line.

[0029] In the detection substrate provided by the embodiment of the present disclosure, the positioning pixel includes a third transistor, a connecting electrode, and a second bias line, and the second bias line is electrically connected to the third transistor through the connecting electrode.

[0030] An embodiment of the present disclosure also provides a detector comprising any of the above-mentioned detection substrates.

[0031] An embodiment of the present disclosure also provides an imaging system, comprising any of the above-mentioned detectors.

[0032] An embodiment of the present disclosure further provides a method for manufacturing a detection substrate, comprising: forming a plurality of pixel units in a pixel setting area of ​​a base substrate, wherein the plurality of pixel units include a marking pixel, and at least one alignment mark is provided in the marking pixel.

[0033] In the method for manufacturing a detection substrate provided in an embodiment of the present disclosure, forming an alignment mark includes: forming a first pattern and forming a second pattern, wherein the orthographic projection of the second pattern on the base substrate overlaps with the orthographic projection of the first pattern on the base substrate.

[0034] In the manufacturing method of the detection substrate provided in the embodiment of the present disclosure, the first figure is closer to the base substrate than the second figure, and the manufacturing method includes: performing a threshold comparison, and the threshold comparison includes: detecting whether the first boundary distance and the second boundary distance of the first figure and the second figure in the first direction are within a first threshold range, and / or detecting whether the third boundary distance and the fourth boundary distance of the first figure and the second figure in the second direction are within a second threshold range, if so, continuing the subsequent process, if not, removing the second figure and forming a new second figure; and continuing to repeat the threshold comparison step for the first figure and the new second figure.

[0035] In the method for manufacturing a detection substrate provided by an embodiment of the present disclosure, the second pattern is a photoresist layer.

[0036] In the manufacturing method of the detection substrate provided in the embodiment of the present disclosure, the manufacturing method also includes forming data lines and forming gate lines, wherein forming the multiple pixel units includes forming transistors, the gate lines are connected to the gates of the transistors, and the data lines are connected to the sources of the transistors, and the alignment marks include at least one of a first alignment mark and a second alignment mark, in which the first alignment mark is in the same layer as the gate line, and the data line is the second graphic, and in the second alignment mark, the second graphic is in the same layer as the data line, and the gate line is the first graphic.

[0037] In the manufacturing method of the detection substrate provided in the embodiment of the present disclosure, the first figure and the second figure have the first boundary distance and the second boundary distance in the first direction, the ratio of the first boundary distance to the size of the larger one of the first figure and the second figure in the first direction is less than or equal to 1 / 3, and the ratio of the second boundary distance to the size of the larger one of the first figure and the second figure in the first direction is less than or equal to 1 / 3, the ratio of the first boundary distance to the size of the larger one of the first figure and the second figure in the first direction is greater than or equal to 1 / 4, and the ratio of the second boundary distance to the size of the larger one of the first figure and the second figure in the first direction is greater than or equal to 1 / 4.

[0038] In the manufacturing method of the detection substrate provided in the embodiment of the present disclosure, the first figure and the second figure have the third boundary distance and the fourth boundary distance in the second direction, the ratio of the third boundary distance to the size of the first figure in the second direction is less than or equal to 1 / 3, and the ratio of the fourth boundary distance to the size of the first figure in the second direction is less than or equal to 1 / 3, the first figure and the second figure have the third boundary distance and the fourth boundary distance in the second direction, the ratio of the third boundary distance to the size of the first figure in the second direction is greater than or equal to 1 / 4, and the ratio of the fourth boundary distance to the size of the first figure in the second direction is greater than or equal to 1 / 4.

[0039] In the manufacturing method of the detection substrate provided in the embodiment of the present disclosure, forming the multiple pixel units includes forming multiple photosensitive pixels and forming multiple positioning pixels, wherein at least one marking pixel among the multiple marking pixels is adjacent to at least one photosensitive pixel among the multiple photosensitive pixels, and the marking pixel includes at least one positioning pixel among the multiple positioning pixels and / or at least one photosensitive pixel among the multiple photosensitive pixels.

[0040] In the method for manufacturing the detection substrate provided by the embodiment of the present disclosure, the first pattern is formed in the same layer as a component in the marking pixel, and the second pattern is formed in the same layer as another component in the marking pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0042] FIG1 is a schematic plan view of a detection substrate provided by an embodiment of the present disclosure.

[0043] FIG2 is a schematic plan view of a detection substrate provided by another embodiment of the present disclosure.

[0044] FIG3 is a schematic plan view of a detection substrate provided by another embodiment of the present disclosure.

[0045] FIG4 is a schematic plan view of a detection substrate provided by another embodiment of the present disclosure.

[0046] FIG5 is a layout diagram of photosensitive pixels in a detection substrate provided by an embodiment of the present disclosure.

[0047] FIG6 is a cross-sectional view taken along line C1 - C2 of FIG5 .

[0048] FIG7 is a cross-sectional view taken along line C3 - C4 of FIG5 .

[0049] FIG8 is a layout diagram of normally black pixels in a detection substrate provided by an embodiment of the present disclosure.

[0050] FIG9 is a layout diagram of normally black pixels with superimposed marks in a detection substrate provided by an embodiment of the present disclosure.

[0051] FIG10 is a cross-sectional view taken along line A1-A2 of FIG9.

[0052] FIG11 is a cross-sectional view taken along line A3 - A4 of FIG9 .

[0053] FIG12 is a cross-sectional view taken along line A5-A6 of FIG9.

[0054] FIG13 is a cross-sectional view taken along line A7-A8 of FIG9.

[0055] FIG14 is a plan view of the gate layer LY1 in FIG9 .

[0056] FIG. 15A is a schematic diagram of forming a target thin film and forming a photoresist pattern on the target thin film.

[0057] FIG15B is a plan view of the gate layer LY1 and the semiconductor layer SC in FIG9 .

[0058] FIG16 is a layout diagram of always-on pixels in a detection substrate provided by an embodiment of the present disclosure.

[0059] FIG17 is a layout diagram of always-on pixels with superimposed marks in a detection substrate provided by an embodiment of the present disclosure.

[0060] FIG18 is a layout diagram of normally black pixels provided with a stitching mark in a detection substrate provided by an embodiment of the present disclosure.

[0061] FIG19A is a plan view of the photoresist pattern of the photoresist layer in the detection substrate shown in FIG18 after the first exposure.

[0062] FIG19B is a plan view of the photoresist pattern of the photoresist layer in the detection substrate shown in FIG18 after the second exposure.

[0063] FIG19C is a plan view of a structure obtained by etching a material film using the photoresist pattern shown in FIG18 as a mask.

[0064] FIG20 is a layout diagram of always-on pixels with splicing marks in a detection substrate provided by an embodiment of the present disclosure.

[0065] FIG21 is a layout diagram of photosensitive pixels with superimposed marks in a detection substrate provided by an embodiment of the present disclosure.

[0066] FIG22 is a layout diagram of photosensitive pixels with splicing marks in a detection substrate provided by an embodiment of the present disclosure.

[0067] FIG23 is a layout diagram of photosensitive pixels with superimposed marks in a detection substrate provided by an embodiment of the present disclosure.

[0068] FIG24 is a layout diagram of photosensitive pixels with superimposed marks in a detection substrate provided by an embodiment of the present disclosure.

[0069] FIG25 is a layout diagram of photosensitive pixels with superimposed marks in a detection substrate provided by an embodiment of the present disclosure.

[0070] FIG. 26 is a plan view of another superimposed mark in a detection substrate provided by an embodiment of the present disclosure.

[0071] FIG. 27 is a plan view of another type of splicing mark detected in a substrate according to an embodiment of the present disclosure.

[0072] FIG28 is a schematic diagram of an imaging system provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0074] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0075] X-ray detectors are X-ray imaging detectors with photodiode arrays at their core. Under X-ray irradiation, the detector's scintillator or phosphor layer converts X-ray photons into visible light. The array, acting as photodiodes, then converts these into electrical image signals. These signals are then transmitted through peripheral circuits and subjected to analog-to-digital conversion, resulting in a digitized image. Because the imaging process involves X-rays, visible light, charge image, and finally digital image, these detectors are often referred to as indirect conversion flat-panel detectors. For example, photodiodes include, but are not limited to, amorphous silicon.

[0076] Because dynamic, real-time scanning is required, precise positioning of the scanned area becomes extremely important. This can be achieved by setting a combination of permanently black and permanently bright pixels for algorithm capture, thereby achieving precise image positioning.

[0077] When using a small-scale exposure machine to produce X-ray detector backplanes, if the backplane is larger than the mask, multiple splicing exposures are often required to complete the circuit structure. Precision control during these splicing exposures is crucial. However, in typical detectors, the pixel setting area is entirely filled with active pixels, leaving no space for alignment marks. This makes it impossible to monitor the splicing and alignment accuracy of the pixel setting area, resulting in uneven grayscale quality in the final product.

[0078] FIG1 is a schematic plan view of a detection substrate according to an embodiment of the present disclosure. FIG2 is a schematic plan view of a detection substrate according to another embodiment of the present disclosure. FIG3 is a schematic plan view of a detection substrate according to another embodiment of the present disclosure. FIG4 is a schematic plan view of a detection substrate according to another embodiment of the present disclosure.

[0079] As shown in Figures 1 to 4, an embodiment of the present disclosure provides a detection substrate, which includes: a base substrate BS and a plurality of pixel units PXU. The base substrate BS includes a pixel setting area R0, and the plurality of pixel units PXU are located in the pixel setting area R0.

[0080] As shown in Figures 1 to 4, the plurality of pixel units PXU include at least one marking pixel MPX. At least one alignment mark MK is provided in the marking pixel MPX.

[0081] An embodiment of the present disclosure provides a detection substrate having at least one alignment mark MK provided in a mark pixel MPX, which is beneficial for improving alignment accuracy during the production process of the detection substrate and improving the uniformity of image quality of the final product.

[0082] As shown in Figures 1 to 4, the multiple pixel units PXU include multiple photosensitive pixels PXL and multiple positioning pixels PX0, the multiple photosensitive pixels PXL are located in the pixel setting area R0, the multiple positioning pixels PX0 are located in the pixel setting area R0, and at least one positioning pixel PX0 among the multiple positioning pixels PX0 is adjacent to at least one photosensitive pixel PXL among the multiple photosensitive pixels PXL.

[0083] For example, as shown in FIG. 1 to FIG. 3 , the marking pixel MPX includes at least one positioning pixel among the plurality of positioning pixels PX0 and / or at least one photosensitive pixel among the plurality of photosensitive pixels PXL.

[0084] As shown in FIG. 1 to FIG. 4 , an alignment mark MK is provided in at least one of the plurality of positioning pixels PX0 and the plurality of photosensitive pixels PXL.

[0085] The detection substrate provided by the embodiment of the present disclosure is provided with an alignment mark MK in at least one of the multiple marking pixels MPX (for example, an alignment mark MK is provided in at least one of the multiple positioning pixels PX0 and the multiple photosensitive pixels PXL), so as to facilitate monitoring the stitching accuracy and / or alignment accuracy during the production process of the detection substrate, improve the alignment accuracy in the process, improve the problems of being unable to achieve overlay compensation in the stitching exposure pixel setting area and / or the stitching accuracy being unable to be controlled, avoid the image quality problem of uneven grayscale in the final product image, and improve the uniformity of the image quality of the final product.

[0086] In the embodiments of the present disclosure, a marking pixel MPX is a pixel unit for setting an alignment mark MK. For example, in some embodiments, one or more photosensitive pixels PXL are selected as marking pixels MPX. For example, in other embodiments, the detection substrate has a positioning pixel PX0, and one or more positioning pixels PX0 are selected as marking pixels MPX. For example, in other embodiments, the detection substrate has a positioning pixel PX0, one or more photosensitive pixels PXL are selected as marking pixels MPX, and one or more positioning pixels PX0 are selected as marking pixels MPX.

[0087] As shown in FIG. 1 to FIG. 4 , the photosensitive pixel PXL may be referred to as a pixel unit PXU, the positioning pixel PX0 may be referred to as a pixel unit PXU, and the detection substrate includes a plurality of pixel units PXU, which are arranged in an array.

[0088] Figure 3 omits the alignment mark MK in the marker pixel MPX. Figure 3 shows four exposure zones ST1 to ST4. Figure 4 shows six exposure zones ST1 to ST6. Each exposure zone is provided with multiple photosensitive pixels and multiple marker pixels. Figure 4 shows the alignment mark MK, but does not show the photosensitive pixels PXL and the marker pixel MPX. Figures 1 and 2 only show one exposure zone. Figure 3 also shows a chip-on-film (COF).

[0089] For example, the splicing exposure process includes the following steps: forming a target thin film, forming a photoresist layer on the target thin film, exposing the photoresist layer in batches (multiple exposures) to form a photoresist pattern, and etching the target thin film using the photoresist pattern as a mask to form a target pattern. For example, the detection substrate shown in Figure 3 can sequentially perform exposure in exposure area ST1, exposure area ST2, exposure area ST3, and exposure area ST4, that is, perform exposure in four batches. For example, the detection substrate shown in Figure 4 can sequentially perform exposure in exposure area ST1, exposure area ST2, exposure area ST3, exposure area ST4, exposure area ST5, and exposure area ST6, that is, perform exposure in six batches.

[0090] Figure 3 shows the secondary exposure region R2. The secondary exposure region R2 is the region that is exposed twice during the exposure process of two adjacent exposure regions, that is, the overlapping region of the two exposure regions.

[0091] For example, each of the plurality of photosensitive pixels PXL includes a photoelectric sensing device configured to convert incident light into an electrical signal so that the photosensitive pixel where it is located has a grayscale that changes with the real-time change of the incident light, thereby generating a charge image.

[0092] The object to be imaged is illuminated by light, and the light passing through the object to be imaged is incident on the flat-panel detector. The photosensitive element (photoelectric sensing device) of the flat-panel detector then converts the optical signal of the incident light into an image electrical signal, thereby generating a charge image. In this process, when the position where the incident light is incident on the flat-panel detector moves, the flat-panel detector receives and responds to the incident light and generates different charge images at different positions. The positions of these charge images are located in different areas. Subsequently, it is necessary to use multiple real-time charge images obtained as the incident light moves in real time to synthesize the final image. In this process, it is necessary to use the position information of multiple real-time charge images to synthesize the final image. It is required that the multiple real-time charge images are all located in a preset area to facilitate the synthesis of the ideal final image.

[0093] For example, in the detection substrate, the marking pixels MPX include non-light-sensitive pixels.

[0094] For example, as shown in FIG. 1 to FIG. 3 , in the detection substrate, the positioning pixel PX0 (non-light-sensitive pixel) includes at least one of a normally bright pixel PX1 or a normally black pixel PX2 .

[0095] For example, in the detection substrate, the positioning pixel PX0 is configured to have a fixed grayscale, which does not change with the real-time change of the incident light.

[0096] The detection substrate provided by the embodiment of the present disclosure is provided with a positioning pixel PX0 with a fixed grayscale, so that multiple positioning pixels can be identified and the position information of the multiple positioning pixels can be obtained. The position information is, for example, coordinates. The coordinates of the multiple positioning pixels are used as a reference to determine the position of the charge image generated by the detection substrate (detector).

[0097] The detection substrate provided by the embodiment of the present disclosure, the positioning pixel PX0 can be used for positioning. The setting of the positioning pixel PX0 is conducive to the precise positioning of the image, improves the accuracy of imaging, reduces the interference of artifacts, and lays the foundation for subsequent image processing.

[0098] For example, the grayscale of the normally-on pixel PX1 is different from the grayscale of the normally-black pixel PX2. For example, the grayscale of the normally-on pixel PX1 is greater than the grayscale of the normally-black pixel PX2.

[0099] For example, the normally black pixel PX2 is always in the black state. For example, the normally bright pixel PX1 is always in the bright state, for example, its brightness is always at its highest achievable brightness. Thus, when the flat panel detector is in the black state as a whole, the normally bright pixel PX1, which is always in the bright state, can be accurately identified; and when the flat panel detector is in the bright state as a whole, the normally black pixel PX2, which is always in the dark state, can be accurately identified. In other words, accurate positioning can be achieved when the flat panel detector is in both the black and bright states.

[0100] As shown in Figures 1 to 4, the alignment mark MK may include at least one of a stitch mark SM and an overlay mark LM. The stitch mark SM is provided to facilitate monitoring stitching accuracy during the substrate production process, and the overlay mark LM is provided to facilitate monitoring alignment accuracy during the substrate production process.

[0101] FIG4 shows a block B1 and a block B2 . In each of the blocks B1 and B2 , a splicing mark SM and an overlapping mark LM are provided. The splicing mark SM is provided at the seam SS, and two overlapping marks LM are provided on both sides of the seam SS.

[0102] 3 and 4 illustrate the example of the seam SS being a straight line, however, the embodiments of the present disclosure are not limited thereto. For example, the seam SS may be bent at the splicing mark.

[0103] Figure 5 is a layout diagram of photosensitive pixels in a detection substrate provided by an embodiment of the present disclosure. Figure 6 is a cross-sectional view along line C1-C2 of Figure 5. Figure 7 is a cross-sectional view along line C3-C4 of Figure 5.

[0104] As shown in FIG. 5 to FIG. 7 , the photosensitive pixel PXL includes a transistor T0 and a photoelectric sensing device S0 .

[0105] FIG8 is a layout diagram of normally black pixels in a detection substrate provided in an embodiment of the present disclosure. FIG9 is a layout diagram of normally black pixels with superimposed marks in a detection substrate provided in an embodiment of the present disclosure. FIG10 is a cross-sectional view along line A1-A2 of FIG9. FIG11 is a cross-sectional view along line A3-A4 of FIG9. FIG12 is a cross-sectional view along line A5-A6 of FIG9. FIG13 is a cross-sectional view along line A7-A8 of FIG9. FIG14 is a plan view of the gate layer LY1 in FIG9. FIG15A is a schematic diagram of forming a target thin film and forming a photoresist pattern on the target thin film. FIG15B is a plan view of the gate layer LY1 and the semiconductor layer SC in FIG9.

[0106] As shown in Figures 8 to 15B , the normally black pixel PX2 includes a transistor T1. Figure 9 shows nine alignment marks MK located in the normally black pixel PX2. These nine alignment marks MK are all superimposed marks LM. The normally black pixel PX2 may not include a photoelectric sensing device S0, or the photoelectric sensing device S0 may not be connected to the transistor T1. The alignment mark MK includes a first pattern P1 and a second pattern P2.

[0107] The superimposed marker LM is used to monitor the alignment accuracy between different film layers within the same exposure area. By monitoring the distance between the upper, lower, left, and right boundaries of the first and second patterns, the alignment deviation between the two layers can be determined. By using parameter compensation, the alignment deviation between the two layers can be adjusted to meet design requirements.

[0108] Figure 14 shows a plan view of the gate layer LY1 in Figure 9. As shown in Figure 14, the gate layer LY1 includes a gate line GL, a gate electrode GT2, and a first pattern P1 of nine alignment marks MK (superimposed marks LM). As shown in Figure 14, the gate line GL and the gate electrode GT2 are an integrated structure.

[0109] As shown in FIG. 15A and FIG. 15B , the exposure process of the probe substrate includes the following steps.

[0110] Step 1) forming a target thin film TF0 on the gate layer LY1 and forming a photoresist film on the target thin film TF0.

[0111] Step 2) exposing the photoresist film to form an exposed photoresist film, wherein the exposed photoresist film includes pattern P201 and pattern P202.

[0112] Step 3) Check whether the pattern P201 and the first pattern P1 meet the requirements. If not, remove the photoresist film and remake them. If they meet the requirements, proceed to the next step.

[0113] Step 4) Develop the exposed photoresist film to form a photoresist pattern, in which the patterns P201 and P202 are retained. The target film TF0 is etched using the photoresist pattern as a mask to form a target pattern, which includes the second pattern P2 and the active layer AL2.

[0114] FIG15B shows a plan view of the gate layer LY1 and the semiconductor layer SC in FIG9. As shown in FIG15B, the semiconductor layer SC includes the active layer AL2 and the second pattern P2 superimposing the mark LM1. That is, the second pattern P2 superimposing the mark LM1 is formed in the same process as the active layer AL2.

[0115] The second patterns P2 of the superimposed marks LM other than superimposed mark LM1 shown in FIG9 are also formed in a manner similar to the second pattern P2 of superimposed mark LM1, and are formed simultaneously during the process of forming the components of the photosensitive pixels and the marking pixels. For each superimposed mark LM, reference is made to the layout diagram shown in FIG9 and the cross-sectional views shown in FIG10 to FIG13.

[0116] Figure 16 is a layout diagram of always-on pixels in a detection substrate provided by an embodiment of the present disclosure. Figure 17 is a layout diagram of always-on pixels with superimposed marks in a detection substrate provided by an embodiment of the present disclosure.

[0117] The superimposed marks LM in FIG17 may refer to the superimposed marks LM shown in FIG9 . In FIG9 , nine superimposed marks LM are set in the normally black pixel PX2 , while in FIG17 , nine superimposed marks LM are set in the normally bright pixel PX1 .

[0118] FIG18 is a layout diagram of normally black pixels with splicing marks in a detection substrate according to an embodiment of the present disclosure. FIG19A is a plan view of the photoresist pattern of the detection substrate shown in FIG18 after the first exposure. FIG19B is a plan view of the photoresist pattern of the detection substrate shown in FIG18 after the second exposure. FIG19C is a plan view of a structure obtained by etching a material film using the photoresist pattern shown in FIG18 as a mask.

[0119] As shown in Figure 18 , a splicing mark SM is set in the normally black pixel PX2. Figure 18 takes setting three splicing marks SM in one normally black pixel PX2 as an example for explanation.

[0120] As shown in Figure 18, the normally black pixel PX2 does not have a photoelectric sensing device. The splicing mark SM requires the superposition of two exposed patterns.

[0121] The stitching mark SM is used to monitor the stitching accuracy between different exposure areas. The stitching mark SM is used to monitor the stitching accuracy between two adjacent exposure areas.

[0122] By measuring the upper, lower, left, and right boundary distances between the first and second figures in the stitching mark SM, the stitching alignment accuracy of the two exposures can be monitored. By performing parameter compensation based on the measurement, the stitching accuracy of the stitched exposures can be improved, further enhancing the uniformity of product image quality.

[0123] FIG19A shows secondary exposure area R2, and its boundaries R21 and R22. The right boundary of the exposure area on the left is boundary R22, and the left boundary of the exposure area on the right is boundary R21. The area between boundaries R21 and R22 is secondary exposure area R2. For example, the exposure area on the left undergoes the first exposure, while the exposure area on the right undergoes the second exposure.

[0124] As shown in FIG. 19A to FIG. 19C , the secondary stitching exposure process includes the following steps.

[0125] Step 1): As shown in FIG. 19A , a target thin film TF is formed on a base substrate.

[0126] Step 2): forming a photoresist film on the target film TF.

[0127] Step 3): performing a first exposure process on the photoresist film to form the exposed photoresist film shown in FIG19A . The exposed photoresist film includes pattern P11 , pattern P21 , and pattern P31 .

[0128] Step 4): The photoresist film is subjected to a second exposure process to form the exposed photoresist film shown in FIG. 19B . The exposed photoresist film includes pattern P12 , pattern P22 , and pattern P32 .

[0129] Step 5): Check whether the first pattern PA and the second pattern PB in the pattern P12 meet the requirements. If not, remove the photoresist film and re-make them. If they meet the requirements, proceed to the next step.

[0130] Step 6): Develop the exposed photoresist film to obtain a photoresist pattern, wherein pattern P12, pattern P22, and pattern P32 are retained, and the rest are removed.

[0131] Step 7): The target thin film TF is etched using the photoresist pattern shown in FIG. 19B as a mask to form the splicing mark SM1 , the gate line GL and the gate GT2 shown in FIG. 19C .

[0132] 19A to 19C illustrate the formation of the splicing mark SM1 as an example. The formation process of other splicing marks also has similar steps, which will not be described in detail here.

[0133] Figures 18 and 19A to 19C take the example that the alignment mark MK (splicing mark SM) also includes the third graphic P3. For example, the third graphic P3 includes characters or text. For example, the third graphic P3 includes English letters. For example, in an embodiment of the present disclosure, the third graphic includes the letter A, the letter S, the letter B, and the letter G. For example, for the splicing mark SM, the third graphic is the letter A, indicating that the alignment mark MK (splicing mark SM) refers to the splicing mark of the semiconductor layer SC. For example, the third graphic is the letter S, indicating that the alignment mark MK (splicing mark SM) refers to the splicing mark of the source and drain layer LY2. For example, the third graphic is the letter B, indicating that the alignment mark MK (splicing mark SM) refers to the splicing mark of the bias line layer LYc. For example, the third graphic is the letter G, indicating that the alignment mark MK (splicing mark SM) refers to the splicing mark of the gate layer LY1. Setting the third graphic P3 can better identify the alignment mark MK. In other embodiments, the alignment mark MK (splicing mark SM) may not include the third graphic P3. For example, as shown in FIG. 18 and FIG. 19A to FIG. 19C , the third graphic P3 is located on one side of the first graphic P1 and / or the second graphic P2 .

[0134] FIG20 is a layout diagram of a normally-on pixel with a splicing mark provided in a detection substrate according to an embodiment of the present disclosure. As shown in FIG20 , a splicing mark SM is provided in the normally-on pixel PX1. The splicing mark SM shown in FIG20 can refer to the splicing mark SM shown in FIG18 .

[0135] Figure 21 is a layout diagram of a photosensitive pixel with a superimposed mark in a detection substrate provided by an embodiment of the present disclosure. As shown in Figure 21, the superimposed mark LM is provided in the photosensitive pixel PXL.

[0136] As shown in Figure 21, an overlay mark LM is added to a conventional photosensitive pixel PXL to form a marker pixel MPX. As shown in Figure 21, the first pattern P1 of the overlay mark LM1 is located on the gate layer LY1, the second pattern P2 of the overlay mark LM1 is located on the semiconductor layer SC, and the third pattern P3 of the overlay mark LM1 is located on the semiconductor layer SC. As shown in Figure 21, the first pattern P1 of the overlay mark LM2 is located on the gate layer LY1, the second pattern P2 of the overlay mark LM2 is located on the source / drain layer LY2, and the third pattern P3 of the overlay mark LM2 is located on the source / drain layer LY2. This allows for alignment control between the gate layer LY1 and the semiconductor layer SC, and between the gate layer LY1 and the source / drain layer LY2, within the pixel arrangement area. These three layers significantly influence the characteristics of the transistor, directly impacting the grayscale uniformity of the image quality and various artifacts caused by alignment deviation.

[0137] Figure 22 is a layout diagram of a photosensitive pixel with a splicing mark provided in a detection substrate according to an embodiment of the present disclosure. As shown in Figure 22, the splicing mark SM is provided in the photosensitive pixel PXL.

[0138] As shown in Figure 22, on the basis of the conventional photosensitive pixel PXL, a splicing mark SM is added to monitor the splicing accuracy of the gate layer LY1, semiconductor layer SC, and source / drain layer LY2 of the pixel setting area. Since these three layers are the constituent film layers of the transistor, they have a significant impact on the image quality. In actual products, improving the splicing accuracy of these three layers can improve the uniformity of the image quality. Setting the splicing mark SM in the photosensitive pixel PXL is conducive to splicing alignment. Because the splicing mark SM is located below the photoelectric sensing device S0, that is, the splicing mark SM is located between the photoelectric sensing device S0 and the substrate, it has little effect on the photosensitivity of the photosensitive pixel PXL where the splicing mark SM is set. This design can be applied to products that do not require marking pixels. That is, only photosensitive pixels PXL are set in the detection substrate, and non-photosensitive pixels (always bright pixels and always dark pixels) are not set. Non-photosensitive pixels can also be called bad pixels. However, by setting the splicing mark SM in a non-photosensitive pixel (a mark pixel, a normally bright pixel or a normally dark pixel), it is possible to fundamentally avoid the splicing mark SM from affecting the photosensitivity of the detection substrate.

[0139] Figure 23 is a layout diagram of photosensitive pixels with superimposed markings in a detection substrate provided in an embodiment of the present disclosure. Figure 24 is a layout diagram of photosensitive pixels with superimposed markings in a detection substrate provided in an embodiment of the present disclosure. Figure 25 is a layout diagram of photosensitive pixels with superimposed markings in a detection substrate provided in an embodiment of the present disclosure.

[0140] As shown in FIG. 23 to FIG. 25 , the superimposed mark LM is provided in the photosensitive pixel PXL.

[0141] 23 to 25 illustrate one of the gate line GL or the data line DL as the first pattern P1 or the second pattern P2 in the superimposed mark LM.

[0142] Figure 26 is a plan view of another superimposed mark in a detection substrate provided by an embodiment of the present disclosure. As shown in Figure 26, the alignment mark MK is a superimposed mark LM, the first figure P1 is an octagon, and the second figure P2 is an octagon.

[0143] Figure 27 is a plan view of another splicing mark detection method in a substrate according to an embodiment of the present disclosure. As shown in Figure 27 , the alignment mark MK is a splicing mark SM, the first pattern P1 is an octagon, and the second pattern P2 is an octagon.

[0144] In the embodiment of the present disclosure, the first graphic P1 of the alignment mark MK can be in a rectangular, octagonal, or circular shape, and the second graphic P2 of the alignment mark MK can be in a rectangular, octagonal, or circular shape. The shapes of the first graphic P1 and the second graphic P2 can be determined as needed.

[0145] 5 , 8 , and 16 respectively show the layout diagrams of the photosensitive pixels PXL, the normally black pixels PX2 , and the normally bright pixels PX1 in the detection substrate.

[0146] As shown in Figures 5, 8 and 16, the detection substrate includes a gate layer LY1, a gate insulation layer GI, a semiconductor layer SC, a source and drain layer LY2, a first passivation layer PVX1, a first electrode layer LYa, a photoelectric sensing layer LY0, a second electrode layer LYb, a planarization layer PLN, a second passivation layer PVX2, a bias line layer LYc, and a third passivation layer PVX3.

[0147] As shown in Figures 6, 7, 10 to 13, in the detection substrate, a gate layer LY1 is provided on the base substrate, a gate insulating layer GI is provided on the gate layer LY1, a semiconductor layer SC is provided on the gate insulating layer GI, a source and drain layer LY2 is provided on the semiconductor layer SC, a first passivation layer PVX1 is provided on the source and drain layer LY2, a first electrode layer LYa is provided on the first passivation layer PVX1, a photoelectric sensing layer LY0 is provided on the first electrode layer LYa, a second electrode layer LYb is provided on the photoelectric sensing layer LY0, a planarization layer PLN and a second passivation layer PVX2 are provided on the second electrode layer LYb, a bias line layer LYc is provided on the second passivation layer PVX2, and a third passivation layer PVX3 is provided on the bias line layer LYc.

[0148] Each film layer is formed layer by layer through the steps of film formation, exposure, development, etching, etc. The subsequent conductive film layer will not cover the previous film layer, that is, it will not affect the recognition of the pattern of the registration mark.

[0149] For example, the base substrate BS may be a rigid substrate, the material of which includes glass, quartz, and metal. Alternatively, the base substrate BS may be a flexible substrate, the material of which includes a polymer such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate diformic acid glycol ester (PEN), or polycarbonate (PC).

[0150] For example, the gate insulating layer GI, the first passivation layer PVX1, the second passivation layer PVX2, and the third passivation layer PVX3 are all insulating layers and can be made of inorganic insulating materials, such as at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0151] For example, the planarization layer PLN is an insulating layer and can be made of an organic insulating material, such as, but not limited to, resin.

[0152] As shown in FIG. 5 to FIG. 13 , the active layer SC is located on a side of the gate layer LY1 away from the substrate BS, and the source / drain layer LY2 is located on a side of the active layer SC away from the substrate BS.

[0153] In the embodiments of the present disclosure, film layer B being located on the side of film layer A facing away from base substrate BS means that film layer B is formed after film layer A, that is, film layer A is formed before film layer B. For example, film layer B being located on the side of film layer A facing away from base substrate BS may also mean that film layer A is closer to base substrate BS than film layer B.

[0154] As shown in Figures 5, 8 and 16, the gate layer LY1 includes gate lines GL and gate electrodes GT, which are an integrated structure. For example, the gate layer LY1 is made of metal, but is not limited thereto.

[0155] As shown in Figures 5, 8, and 16, the source / drain layer LY2 includes a data line DL, a source electrode SE, and a drain electrode DE. For example, the source / drain layer LY2 is made of, but not limited to, a metal. For example, the source / drain layer LY2 is made of at least one of titanium (Ti) and aluminum (Al).

[0156] As shown in FIG. 5 , the semiconductor layer SC includes an active layer AL.

[0157] As shown in FIG5 , the first electrode layer LYa includes a first electrode E1. For example, the material of the first electrode layer LYa includes metal. For example, the metal includes at least one of molybdenum, aluminum, and copper, but is not limited thereto.

[0158] As shown in FIG5 , the photoelectric sensing layer LY0 includes a photoelectric sensing structure PIN. For example, the photoelectric sensing structure PIN includes an N-type semiconductor layer, an intrinsic semiconductor layer, and a P-type semiconductor layer. For example, the photoelectric sensing structure PIN is a PIN junction. For example, the first electrode E1 is connected to the N-type semiconductor layer, but this is not limited thereto.

[0159] As shown in FIG5 , the second electrode layer LYb includes a second electrode E2. For example, the material of the second electrode layer LYb includes a transparent conductive material. For example, the transparent conductive material includes a transparent conductive metal oxide. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto.

[0160] As shown in Figure 5 , the bias line layer LYc includes a bias line BL. The bias line BL is configured to provide a bias voltage to the photosensitive pixel PXL. As shown in Figures 5 and 6 , the bias line BL is connected to the second electrode E2 via a via V2. For example, the bias line layer LYc is made of a conductive material, such as, but not limited to, a metal. For example, the bias line layer LYc is made of at least one of molybdenum, aluminum, copper, and titanium.

[0161] As shown in FIG5 , the photosensitive pixel PXL includes a transistor T0 , which includes an active layer AL, a gate electrode GT, a source electrode SE, and a drain electrode SE.

[0162] As shown in FIG5 , the photosensitive pixel PXL includes a photoelectric sensing device S0 . The photoelectric sensing device S0 includes a first electrode E1 , a photoelectric sensing structure PIN , and a second electrode E2 . As shown in FIG5 and FIG7 , the first electrode E1 is connected to the drain electrode SE through a via V1 .

[0163] As shown in FIG8 , the semiconductor layer SC includes an active layer AL2 , a source-drain layer LY2 including a source electrode SE2 and a drain electrode DE2 , a gate layer LY1 including a gate electrode GT2 , and a transistor T2 including an active layer AL2 , a gate electrode GT2 , a source electrode SE2 , and a drain electrode SE2 .

[0164] As shown in Figure 8, the bias line layer LYc includes a bias line BL2. The bias line BL2 is not connected to the transistor T2.

[0165] The detection substrate shown in Figure 8 does not have a photoelectric sensing device. Figure 8 shows a normally black pixel PX2.

[0166] As shown in FIG16 , the semiconductor layer SC includes an active layer AL1 , a source-drain layer LY2 including a source electrode SE1 and a drain electrode DE1 , a gate layer LY1 including a gate electrode GT1 , and a transistor T1 including an active layer AL1 , a gate electrode GT1 , a source electrode SE1 , and a drain electrode SE1 .

[0167] 16 , the bias line layer LYc includes a bias line BL1 , which is also configured to provide a bias voltage to the normally-on pixel PX1 .

[0168] As shown in Figure 16, bias line BL1 is connected to drain electrode DE1 via connecting electrode Ea. Connecting electrode Ea can be on the same layer as first electrode E1 or second electrode E2. As shown in Figure 16, one end of connecting electrode Ea is connected to drain electrode DE1 via via V3, and the other end of connecting electrode Ea is connected to bias line BL1 via via V4.

[0169] The detection substrate shown in Figure 16 does not have a photoelectric sensing device. Figure 16 shows a normally-on pixel PX1.

[0170] As shown in Figure 16, the bias voltage is transmitted to the drain electrode DE1 through the link electrode Ea. After the transistor T1 is turned on, the bias voltage is read to obtain a permanently lit pixel. The permanently lit pixel PX1 shown in Figure 16 does not have a photoelectric sensor S0.

[0171] As shown in FIG16 , by monitoring the upper, lower, left, and right boundary distances between the first and second graphics, the alignment deviation between the two film layers can be obtained. By parameter compensation, the alignment deviation between the two film layers can be made to meet the design requirements.

[0172] For example, the bias voltage is a common voltage, such as a ground voltage or other types of common voltages. The bias line BL is connected to the photosensitive pixel PXL. The bias line BL is also connected to the always-on pixel PX1.

[0173] In the embodiments of the present disclosure, if a column of pixel units includes at least two of the photosensitive pixel PXL, the normally black pixel PX2, and the normally bright pixel PX1, the two pixel units share the same bias line. That is, the bias line BL, the bias line BL1, and the bias line BL2 can be the same bias line and can be an integrated structure.

[0174] The detection substrate provided by the embodiment of the present disclosure may be provided with at least one alignment mark MK in at least one of the photosensitive pixel PXL, the normally black pixel PX2, and the normally bright pixel PX1.

[0175] For example, as shown in Figures 9 to 13, 15B, 17, 18, and 20 to 27, in the detection substrate, the alignment mark MK includes a first graphic P1 and a second graphic P2, and the orthographic projection of the second graphic P2 on the base substrate BS overlaps with the orthographic projection of the first graphic P1 on the base substrate BS.

[0176] In the detection substrate provided by the embodiment of the present disclosure, the second pattern P2 and the first pattern P1 overlap, which is beneficial for monitoring the alignment accuracy.

[0177] For example, as shown in Figures 18, 20, 22, 25, and 27, in this detection substrate, the alignment mark MK includes a splicing mark SM. The first pattern P1 of the splicing mark SM represents the alignment material layer, and the second pattern P2 of the splicing mark SM represents a hollowed-out area. In other words, the splicing mark SM is a component within a single film layer.

[0178] For example, as shown in Figures 9 to 13, 15B, 17, 21, 23, and 25, in this detection substrate, the alignment mark MK includes an overlay mark LM. The first pattern P1 of the overlay mark LM is a first material layer, and the second pattern P2 of the overlay mark LM is a second material layer. The first material layer and the second material layer are made of different materials. In other words, the overlay mark LM includes two overlapping components located on two different film layers.

[0179] For example, as shown in Figures 9 to 13, 15B, 17, 21, 23, and 25, in the detection substrate, multiple superimposed marks LM are provided in the same mark pixel MPX. The first graphics P1 of the multiple superimposed marks LM are made of the same material, and the second graphics P2 of at least two of the multiple superimposed marks LM are made of different materials. The superimposed marks LM include a bottom graphic and a top graphic. In the embodiment of the present disclosure, the first graphic P1 is the bottom graphic, and the second graphic P2 is the top graphic. The bottom graphics of the multiple superimposed marks LM can be set in the same layer, such as the gate layer LY1, and the top graphic can be set in a layer different from the bottom graphic as needed. This facilitates alignment monitoring during the production process of the detection substrate.

[0180] For example, as shown in Figures 9 to 13, 15B, 17, 21, 23, and 25, in this detection substrate, multiple superimposed marks LM are spaced apart and arranged sequentially in one direction or in an array along two directions. Of course, the multiple superimposed marks LM can also be arranged in other ways. As shown in Figures 9 and 17, the multiple superimposed marks LM are arranged in an array. Figures 9 and 17 show three rows and three columns of nine superimposed marks LM. The number of superimposed marks LM is not limited to that shown in the figures. In Figures 9 and 17, the superimposed marks LM are set in the marking pixels. However, the embodiments of the present disclosure are not limited to this. Superimposed marks LM can also be set in the photosensitive pixels. Figure 21 shows two superimposed marks LM: superimposed mark LM1 and superimposed mark LM2. Figure 23 shows superimposed marks LM set in the photosensitive pixel PXL. Figure 23 shows superimposed marks LM1 and superimposed mark LM2. Figure 24 shows three superimposed marks LM: superimposed mark LM1, superimposed mark LM2, and superimposed mark LM3. FIG. 25 shows three superimposed marks LM: superimposed mark LM1 , superimposed mark LM2 , and superimposed mark LM3 , and three splicing marks: splicing mark SM1 , splicing mark SM2 , and splicing mark SM3 .

[0181] For example, as shown in Figures 9 to 13 and Figure 17, in the detection substrate, the detection substrate includes a gate layer LY1, a semiconductor layer SC, and a source / drain layer LY2, and the multiple superimposed marks LM include a superimposed mark LM1 and a superimposed mark LM2. The first graphic P1 of the superimposed mark LM1 is located in the gate layer LY1 and is in the same layer as the gate electrode GT and the gate line GL. The second graphic P2 of the superimposed mark LM1 is located in the semiconductor layer SC and is in the same layer as the active layer AL. The first graphic P1 of the superimposed mark LM2 is located in the gate layer LY1 and is in the same layer as the gate electrode GT and the gate line GL. The second graphic P2 of the superimposed mark LM2 is located in the source / drain layer LY2 and is in the same layer as the source electrode SE, the drain electrode DE, and the data line DL.

[0182] For example, as shown in Figures 21, 23, and 25, in this detection substrate, multiple superimposed marks LM are located in the same photosensitive pixel PXL. To ensure that the function of the photosensitive pixel PXL is not affected, the number of superimposed marks LM provided in the photosensitive pixel PXL can be less than or equal to three. Figures 21 and 25 illustrate the arrangement of three superimposed marks LM in the same photosensitive pixel PXL. Figure 23 illustrates the arrangement of two superimposed marks LM in the same photosensitive pixel PXL. As shown in Figures 21 and 25, the first pattern P1 of the superimposed mark LM1 can be located in the gate layer LY1, and the second pattern P2 of the superimposed mark LM1 can be located in the semiconductor layer SC. As shown in Figures 21 and 25, the first pattern P1 of the superimposed mark LM2 can be located in the gate layer LY1, and the second pattern P2 of the superimposed mark LM1 can be located in the source / drain layer LY2. As shown in Figures 23 and 25, the data line DL serves as the second pattern P2 (second pattern 1P2) of the superimposed mark LM1, and the first pattern P1 (first pattern 1P1) of the superimposed mark LM1 is located in the gate layer LY1.

[0183] As shown in Figure 23, two superimposed marks LM: superimposed mark LM1 and superimposed mark LM2 are located in the same photosensitive pixel PXL. As shown in Figure 23, the gate line GL serves as the first graphic P1 (first graphic 2P1) of the superimposed mark LM2, and the second graphic P2 (second graphic 2P2) of the superimposed mark LM2 is located in the source-drain layer LY2. As shown in Figure 23, the data line DL serves as the second graphic P2 (second graphic 1P2) of the superimposed mark LM1, and the first graphic P1 (first graphic 1P1) of the superimposed mark LM1 is located in the gate layer LY1. Figure 23 shows that the superimposed mark LM1 and the superimposed mark LM2 are set in the same photosensitive pixel PXL. In other embodiments, the superimposed mark LM1 or the superimposed mark LM2 can be set in the same photosensitive pixel PXL.

[0184] For example, as shown in Figures 5 and 23, in the detection substrate, the detection substrate further includes a gate line GL and a data line DL, the photosensitive pixel PXL includes a transistor T0, the gate line GL is connected to the gate GT of the transistor T0, and the data line DL is connected to the source SE of the transistor T0.

[0185] For example, as shown in Figure 23, in the detection substrate, the direction X is parallel to the extension direction of the gate line GL. For the superimposed mark LM1, the first graphic P1 (first graphic 1P1) is in the same layer as the gate line GL, and the data line DL serves as the second graphic P2 (second graphic 1P2).

[0186] As shown in FIG. 23 , the direction Y is parallel to the extending direction of the data line GL, the second pattern P2 (second pattern 2P2 ) is in the same layer as the data line DL, and the gate line GL serves as the first pattern P1 (first pattern 2P1 ).

[0187] In an embodiment of the present disclosure, direction X is parallel to the substrate, direction Y is parallel to the substrate, and direction X intersects direction Y. For example, direction X is perpendicular to direction Y.

[0188] For example, the direction X and the direction Y are parallel to the surface of the substrate base plate on which the respective components are fabricated.

[0189] For example, as shown in Figures 9 to 11, in this detection substrate, the detection substrate further includes a first passivation layer PVX1, which is located on the side of the source / drain layer LY2 facing away from the base substrate BS. The multiple superimposed marks LM also include a superimposed mark LM3. A first pattern P1 of the superimposed mark LM3 is located on the gate layer LY1 and is on the same layer as the gate electrode GE and the gate line GL. A second pattern P2 of the superimposed mark LM3 is a via HPVX1 in the first passivation layer PVX1.

[0190] For example, as shown in Figures 9 to 13, in the detection substrate, the detection substrate further includes a first passivation layer PVX1, a first electrode layer LYa, a photoelectric sensing layer LY0, a planarization layer PLN, a second passivation layer PVX2, a bias line layer LYc, and a third passivation layer PVX3, which are sequentially arranged. Multiple superimposed marks LM are located in the same mark pixel MPX. The multiple superimposed marks LM also include superimposed marks LM3, superimposed marks LM4, superimposed marks LM5, superimposed marks LM6, superimposed marks LM7, superimposed marks LM8, and superimposed marks LM9. The first graphics P1 of the superimposed marks LM3, superimposed marks LM4, superimposed marks LM5, superimposed marks LM6, superimposed marks LM7, superimposed marks LM8, and superimposed marks LM9 are all located in the same layer, namely, in the gate layer LY1, that is, in the same layer as the gate GE and the gate line GL. The second graphics P2 of the superimposed mark LM3 is a via HPVX1 in the first passivation layer PVX1. The second graphics P2 of the superimposed mark LM are located in the first electrode layer LYa, that is, in the same layer as the first electrode E1. The second graphic P2 of the superimposed mark LM5 is located in the photoelectric sensing layer LY0, that is, in the same layer as the photoelectric sensing structure PIN. The second graphic P2 of the superimposed mark LM6 is the via HPLN in the planarization layer PLN. The second graphic P2 of the superimposed mark LM7 is the via H PVX2 in the second passivation layer PVX2. The second graphic P2 of the superimposed mark LM8 is located in the second electrode layer LYb, that is, in the same layer as the second electrode E2. The second graphic P2 of the superimposed mark LM9 is located in the bias line layer LYc, that is, in the same layer as the bias line BL.

[0191] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM1 has a first figure P1 (first figure 1P1 ) and a second figure P2 (second figure 1P2 ).

[0192] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM2 has a first figure P1 (first figure 2P1 ) and a second figure P2 (second figure 2P2 ).

[0193] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM3 has a first pattern P1 (first pattern 3P1 ) and a second pattern P2 (second pattern 3P2 ).

[0194] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM4 has a first pattern P1 (first pattern 4P1 ) and a second pattern P2 (second pattern 4P2 ).

[0195] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM5 has a first figure P1 (first figure 5P1 ) and a second figure P2 (second figure 5P2 ).

[0196] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM6 has a first figure P1 (first figure 6P1 ) and a second figure P2 (second figure 6P2 ).

[0197] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM7 has a first pattern P1 (first pattern 7P1 ) and a second pattern P2 (second pattern 7P2 ).

[0198] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM8 has a first figure P1 (first figure 8P1 ) and a second figure P2 (second figure 8P2 ).

[0199] As shown in FIG. 9 to FIG. 13 , the superimposed mark LM9 has a first figure P1 (first figure 9P1 ) and a second figure P2 (second figure 9P2 ).

[0200] For example, as shown in Figures 18 and 20, in the detection substrate, the stitching mark SM includes a first stitching mark SM1, a second stitching mark SM2, and a third stitching mark SM3. The first stitching mark SM1 is located in the gate layer LY1, that is, in the same layer as the gate GE and the gate line GL. The second stitching mark SM2 is located in the source and drain layer LY2, that is, in the same layer as the source SE, the drain DE, and the data line DL. The third stitching mark SM3 is located in the bias line layer LYc, that is, in the same layer as the bias line BL. In the always-on pixel PX1, the gate layer LY1, the source and drain layer LY2, and the bias line layer LYc are relatively important film layer structures. Therefore, stitching marks are set in these three layers to facilitate stitching alignment.

[0201] For example, as shown in Figure 22, in the detection substrate, the stitching mark SM includes a first stitching mark SM1, a second stitching mark SM2 and a third stitching mark SM3. The first stitching mark SM1 is located in the gate layer LY1, that is, in the same layer as the gate electrode GE and the gate line GL. The second stitching mark SM2 is located in the source and drain layer LY2, that is, in the same layer as the source electrode SE, the drain electrode DE and the data line DL. The third stitching mark SM3 is located in the semiconductor layer SC, that is, in the same layer as the active layer AL. Because the gate layer LY1, the semiconductor layer SC and the source and drain layer LY2 are crucial to the formation of the transistor T0, the stitching mark SM can include the above three stitching marks SM to form a transistor T0 with high reliability. The three stitching marks SM shown in Figure 18 are located in the same normally black pixel PX2. In other embodiments, the same normally black pixel PX2 can be provided with one, two or more than three stitching marks SM.

[0202] For example, as shown in Figures 2 and 3 , in the detection substrate, the marking pixel MPX includes a first marking pixel MPX1, in which the splicing mark SM is located. The marking pixel MPX includes a second marking pixel MPX2, in which the superimposed mark LM is located. In the detection substrate shown in Figure 2 , either the superimposed mark LM or the splicing mark SM can be provided in the second marking pixel MPX2. That is, at least one of the superimposed mark LM and the splicing mark SM can be provided in a second marking pixel MPX2.

[0203] For example, as shown in Figure 2, in the detection substrate, the first marking pixel MPX1 and the second marking pixel MPX2 are adjacent to each other, or, as shown in Figure 3, the first marking pixel MPX1 and the second marking pixel MPX2 are spaced apart from each other, and at least one of the multiple non-marking pixels (photosensitive pixels PXL) is provided between the first marking pixel MPX1 and the second marking pixel MPX2.

[0204] For example, the remaining pixel units except the mark pixel MPX are called non-mark pixels. That is, the plurality of pixel units PXU include the mark pixel MPX and the non-mark pixels. For example, the non-mark pixels include the photosensitive pixel PXL.

[0205] As shown in Figures 1 to 4, the marking pixels MPX or photosensitive pixels PXL provided with the alignment mark MK are located at the edge of the exposure area. In an exposure area, the area enclosed by the pixel units containing the alignment mark MK is as large as possible.

[0206] For example, as shown in Figures 9, 17, 18, 20, 21, 22, 24, and 25, in the detection substrate, the first figure P1 and the second figure P2 have a first boundary distance D1 and a second boundary distance D2 in the direction X, the ratio of the first boundary distance D1 to the larger dimension of the first figure P1 and the second figure P2 in the direction X is less than or equal to 1 / 3, and the ratio of the second boundary distance D2 to the larger dimension of the first figure P1 and the second figure P2 in the direction X is less than or equal to 1 / 3. Figures 17 and 20 show the dimension Dx of the first figure P1 in the direction X.

[0207] The detection substrate provided by the embodiment of the present disclosure makes the lateral alignment more accurate by limiting the upper limit of the range of the distance between the two boundaries of the first figure P1 and the second figure P2 in the lateral direction.

[0208] For example, in the detection substrate, the ratio of the first boundary distance D1 to the size of the larger one of the first figure P1 and the second figure P2 in the direction X is greater than or equal to 1 / 4, and the ratio of the second boundary distance D2 to the size of the larger one of the first figure P1 and the second figure P2 in the direction X is greater than or equal to 1 / 4.

[0209] The detection substrate provided by the embodiment of the present disclosure makes the lateral alignment more accurate by limiting the lower limit of the range of the distance between the two boundaries of the first figure P1 and the second figure P2 in the lateral direction.

[0210] In some embodiments, the ratio of the first boundary distance D1 to the size of the larger dimension of the first figure P1 and the second figure P2 in the direction X is greater than or equal to 1 / 4 and less than or equal to 1 / 3, and the ratio of the second boundary distance D2 to the size of the larger dimension of the first figure P1 and the second figure P2 in the direction X is greater than or equal to 1 / 4 and less than or equal to 1 / 3.

[0211] The detection substrate provided by the embodiment of the present disclosure makes the lateral alignment more accurate by limiting the upper and lower limits of the range of the distance between the two boundaries of the first figure P1 and the second figure P2 in the lateral direction.

[0212] For example, as shown in Figures 23 and 25, in the detection substrate, the alignment mark MK includes an alignment mark MK1 (superimposed mark LM1) and an alignment mark MK2 (superimposed mark LM2). The data line DL extends along a direction Y, and the direction X is perpendicular to the extension direction of the data line DL. The gate line GL extends along the direction X. The gate line GL is the first graphic P1 of the alignment mark MK2 (superimposed mark LM2). The second graphic P2 of the alignment mark MK2 is on the same layer as the data line DL. The first graphic P1 of the alignment mark MK1 (superimposed mark LM1) is on the same layer as the gate line GL, that is, located in the gate layer LY1. The data line DL is the second graphic P2 of the alignment mark MK1 (superimposed mark LM1).

[0213] For example, as shown in Figures 24 and 25, in the detection substrate, the alignment mark MK includes the alignment mark MK1 (superimposed mark LM1), the first graphic P1 of the alignment mark MK1 (superimposed mark LM1) is in the same layer as the gate line GL, that is, located in the gate layer LY1, and the data line DL is the second graphic P2 of the alignment mark MK1 (superimposed mark LM1).

[0214] For example, as shown in Figures 24 and 25 , in this detection substrate, the alignment mark MK further includes an alignment mark MK2 (superimposed mark LM2), and the orthographic projection of the second pattern P2 of the alignment mark MK2 on the base substrate BS is within the orthographic projection of the first pattern P1 of the alignment mark MK2 on the base substrate BS. For example, as shown in Figures 24 and 25 , the first pattern P1 of the alignment mark MK2 (superimposed mark LM2) is located on the gate layer LY1, and the second pattern P2 of the alignment mark MK2 (superimposed mark LM2) is located on the semiconductor layer SC.

[0215] For example, as shown in Figures 24 and 25, in the detection substrate, the alignment mark MK also includes an alignment mark MK3 (superimposed mark LM3), and the orthographic projection of the second graphic P2 of the alignment mark MK3 on the base substrate BS is within the orthographic projection of the first graphic P1 of the alignment mark MK3 on the base substrate BS. For example, as shown in Figures 24 and 25, the first graphic P1 of the alignment mark MK3 (superimposed mark LM3) is located in the gate layer LY1, and the second graphic P2 of the alignment mark MK3 (superimposed mark LM3) is located in the source and drain layer LY2. For example, as shown in Figures 9, 17, and 21, in the detection substrate, the orthographic projection of the second graphic P2 on the base substrate BS is within the orthographic projection of the first graphic P1 on the base substrate BS.

[0216] For the alignment mark MK2 (superimposed mark LM2) and the alignment mark MK3 (superimposed mark LM3) in Figures 24 and 25, the orthographic projection of the second graphic P2 on the base substrate BS is within the orthographic projection of the first graphic P1 on the base substrate BS.

[0217] For example, as shown in Figures 9, 17, 18, 20, 21, 22, 24, and 25, in this detection substrate, the first pattern P1 and the second pattern P2 have a third boundary distance D3 and a fourth boundary distance D4 in the direction Y. The ratio of the third boundary distance D3 to the dimension of the first pattern P1 in the direction Y is less than or equal to 1 / 3, and the ratio of the fourth boundary distance D4 to the dimension of the first pattern P1 in the direction Y is less than or equal to 1 / 3. Figure 17 shows the dimension Dy of the first pattern P1 in the direction Y.

[0218] The detection substrate provided by the embodiment of the present disclosure makes the vertical alignment more accurate by limiting the upper limit of the range of the distance between the two boundaries of the first figure P1 and the second figure P2 in the vertical direction.

[0219] For example, in the detection substrate, the first figure P1 and the second figure P2 have a third boundary distance D3 and a fourth boundary distance D4 in direction Y, the ratio of the third boundary distance D3 to the size of the first figure P1 in direction Y is greater than or equal to 1 / 4, and the ratio of the fourth boundary distance D4 to the size of the first figure P1 in direction Y is greater than or equal to 1 / 4.

[0220] The detection substrate provided by the embodiment of the present disclosure makes the vertical alignment more accurate by limiting the lower limit of the range of the distance between the two vertical boundaries of the first figure P1 and the second figure P2.

[0221] For example, in some embodiments, the ratio of the third boundary distance D3 to the size of the first figure P1 in direction Y is greater than or equal to 1 / 4 and less than or equal to 1 / 3, and the ratio of the fourth boundary distance D4 to the size of the first figure P1 in direction Y is greater than or equal to 1 / 4 and less than or equal to 1 / 3.

[0222] The detection substrate provided by the embodiment of the present disclosure makes vertical alignment more accurate by defining upper and lower limits on the range of the distance between the two vertical boundaries of the first figure P1 and the second figure P2.

[0223] For example, as shown in Figures 9, 17, 18, 20, 21, 22, 24, and 25, in the detection substrate, at least two alignment marks MK are provided in the same marking pixel MPX, and the two alignment marks MK are spaced apart from each other. The spacing of the alignment marks MK facilitates determination of the boundary distance between each alignment mark MK.

[0224] For example, in the detection substrate, the photosensitive pixel PXL includes a first pixel structure PXS1, and the marking pixel MPX includes a second pixel structure PXS2, and the first pixel structure PXS1 is different from the second pixel structure PXS2.

[0225] FIG25 shows four photosensitive pixels PXL, of which the photosensitive pixel in the upper right corner is not a marker pixel MPX, while the remaining three photosensitive pixels PXL are marker pixels MPX. The marker pixel MPX in the upper left corner of FIG25 has superimposed marks: superimposed mark LM1, superimposed mark LM2, and superimposed mark LM3. The marker pixel MPX in the lower left corner of FIG25 has superimposed marks: superimposed mark LM1, superimposed mark LM2, and superimposed mark LM3. The marker pixel MPX in the lower right corner of FIG25 has splicing marks: splicing mark SM1, splicing mark SM2, and splicing mark SM3.

[0226] FIG25 illustrates an example in which the registration mark MK (superimposed mark LM) also includes a third graphic P3. For example, the third graphic P3 includes characters or text. For example, the third graphic P3 includes English letters. For example, in an embodiment of the present disclosure, the third graphic includes the letters A, S, B, and G.

[0227] For example, as shown in FIG25 , in the superimposed mark LM, the third graphic is the letter A, indicating that the second graphic P2 of the alignment mark MK (superimposed mark LM) is located in the semiconductor layer SC. For example, the third graphic is the letter S, indicating that the second graphic P2 of the alignment mark MK (superimposed mark LM) is located in the source / drain layer LY2. For example, the third graphic is the letter B, indicating that the second graphic P2 of the alignment mark MK (superimposed mark LM) is located in the bias line layer LY. For example, the third graphic is the letter G, indicating that the second graphic P2 of the alignment mark MK (superimposed mark LM) is located in the gate layer LY1. Providing the third graphic P3 can better identify the alignment mark MK. In other embodiments, the alignment mark MK (superimposed mark LM) may not include the third graphic P3. For example, as shown in FIG25 , the third graphic P3 is located on one side of the first graphic P1 and / or the second graphic P2.

[0228] For example, as shown in Figures 5 to 7 and Figures 9 to 13, in the detection substrate, the first pixel structure PXS1 includes a transistor T0, a photoelectric sensing device S0, and a bias line BL, the first electrode E1 of the photoelectric sensing device S0 is electrically connected to the transistor T0, and the second electrode E2 of the photoelectric sensing device S0 is electrically connected to the bias line BL.

[0229] For example, as shown in Figures 8 and 9, the second pixel structure PXS2 includes a transistor T2, or as shown in Figures 16 and 17, the second pixel structure PXS2 includes a transistor T1, a connecting electrode Ea, and a bias line BL1, and the bias line BL1 is electrically connected to the transistor T1 through the connecting electrode Ea. In this case, the second pixel structure PXS2 is a pixel structure of a normally bright pixel PX1, or the second pixel structure PXS2 includes a transistor T1, a photoelectric sensing device, and a bias line BL, the first electrode E1 of the photoelectric sensing device is connected to the transistor T1, and the second electrode of the photoelectric sensing device is not electrically connected to the bias line BL. In this case, the second pixel structure PXS2 is a pixel structure of a normally black pixel PX2.

[0230] For example, as shown in Figure 1, there is an example of a combination of marked pixels, which is an example of the smallest pixel array splicing unit (the actual unit size needs to be treated according to the specific situation of each product). Each square represents a pixel unit. The normally bright pixel PX1 can adopt the pixel design shown in Figure 17 or Figure 20, and the normally dark pixel PX2 can use the pixel design shown in Figure 9 or Figure 18; the pixel unit with a splicing mark (marked pixel MPX) can use the pixel design containing the splicing mark shown in Figure 18 or Figure 20, which can realize the image positioning function of the marked pixel and the alignment control in the process, killing two birds with one stone. It is a pixel design scheme that is conducive to stable product production.

[0231] For example, as shown in Figure 2, there is another example of the arrangement and combination of marking pixels, which is an example of the smallest pixel array stitching unit (the actual unit size needs to be treated according to the specific situation of each product). Each square represents a pixel unit PXU, and the marking pixel MPX uses the design in Figure 21 or Figure 22. The marking pixel MPX2 is a pixel unit for monitoring overlay, and the marking pixel MPX1 is a pixel for monitoring stitching accuracy. In products that do not require normally dark pixels or normally bright pixels, this solution can be used to control graphic alignment and stitching accuracy.

[0232] It should be noted that the number and size of alignment mark graphics can be set based on the pixel size and alignment accuracy requirements; the number of mark pixels can be adjusted as needed. In addition to squares, alignment mark shapes with straight lines and central symmetry, such as rectangles and octagons, can also be designed. The vertical and horizontal wrapping distances of the inner and outer graphics can be the same, as shown in Figures 26 and 27.

[0233] For example, in an embodiment of the present disclosure, the alignment mark MK is located between the third passivation layer PVX3 and the base substrate BS. For example, as shown in Figures 9 to 13, 17, 21, 24, and 25, the alignment mark MK (superimposed mark LM) is located between the third passivation layer PVX3 and the base substrate BS. For example, as shown in Figures 9 to 13, 18, 20, and 22, the alignment mark MK (splicing mark SM) is located between the third passivation layer PVX3 and the base substrate BS. According to the previously described splicing mark SM being located at the gate layer LY1, the source and drain layer LY2, the semiconductor layer SC, or the bias line layer LYc, it can be seen that the alignment mark MK (splicing mark SM) is located between the third passivation layer PVX3 and the base substrate BS.

[0234] For example, when the stitching mark SM or the overlay mark LM is located in the gate layer LY1, the source and drain layer LY2, and the semiconductor layer SC, the alignment mark MK (including at least one of the stitching mark SM and the overlay mark LM) is located between the first passivation layer PVX1 and the base substrate BS.

[0235] It should be noted that the specific layer where the alignment mark is designed can be determined based on needs and is not limited to the ones depicted in the accompanying figures. For example, in the embodiments shown in Figures 9 and 17 , only one or more of the superimposed marks LM1 through LM9 can be provided. The same applies to the pixel cells where the stitching mark SM is provided, where one or more of the superimposed marks can be selected.

[0236] An embodiment of the present disclosure further provides a detector comprising any of the above-mentioned detection substrates. The detector may be a flat-panel detector.

[0237] An embodiment of the present disclosure further provides an imaging system, comprising any of the above-mentioned detectors.

[0238] When the detector includes an image acquisition area, multiple photosensitive pixels generate a charge image based on electrical signals. The detector may also include: a coordinate acquisition unit and a data output unit. The coordinate acquisition unit is configured to acquire the coordinates of each positioning pixel and the real-time coordinates of at least some of the photosensitive pixels used to form the charge image; the data output unit is configured to output the electrical signal of each photosensitive pixel for image formation, and is configured to output the coordinates of each positioning pixel and the real-time coordinates of at least some of the photosensitive pixels for positioning the charge image so as to control the charge image to remain within the image acquisition area. For example, for ease of operation, a positioning point is selected on the charge image, and the position of the detector is adjusted based on the positional relationship between the positioning point and the positioning pixel or alignment mark. The detector can be moved to ensure that the charge image remains within the image acquisition area.

[0239] FIG28 is a schematic diagram of an imaging system provided by an embodiment of the present disclosure. As shown in FIG28 , the imaging system 100 includes any detector 10 provided by an embodiment of the present disclosure, as well as a position control unit 11, a position adjustment device 12, and an imaging processing module 13. The position control unit 11 is configured to receive, in real time, the coordinates of the positioning pixels and the real-time coordinates of at least a portion of the photosensitive pixels from the detector 10. Using the received coordinates, the position adjustment device 12 calculates the distance of at least a portion of the photosensitive pixels relative to the positioning pixels and issues instructions based on the calculation results. The at least portion of the photosensitive pixels, for example, a selected portion of the photosensitive pixels, are used to generate a charge image by sensing light. The position adjustment device 12 is configured to receive, in real time, instructions from the position control unit 11 and, under the control of these instructions, adjust the position of the detector 10 in real time so that the charge image remains within the aforementioned image acquisition area D. The imaging processing module 13 includes a display 131 and an imaging processor 132. The display 131 includes a preset display area. The imaging processor 132 is configured to receive the electrical signal output by the detector 10 and the position information of the charge image after the position of the detector 10 is adjusted. The position adjustment device 12 uses these electrical signals and the position information of the charge image to generate an image of the object to be imaged within the preset display area.

[0240] For example, to facilitate operation, a positioning point is selected on the charge image, and the coordinates of the positioning point and the positional relationship between the positioning point and the positioning pixel or alignment mark are obtained by the position control unit 11. For example, the position control unit 11 includes a processor, which calculates the distance between the positioning point and the positioning pixel or alignment mark, and adjusts the position of the detector 10 based on the distance, moving the detector 10 so that the charge image is always located in the image acquisition area.

[0241] For example, the imaging system 100 further includes a light emitter configured to emit light toward the object to be imaged. The light passes through the object to be imaged and then illuminates the detector 10 . The light after passing through the object to be imaged is the incident light.

[0242] For example, a light emitter is configured to rotate around an object to be imaged and emit light at multiple angles toward the object to be imaged, thereby generating corresponding charge images at each of the angles in real time. The imaging processing module processes the multiple charge images generated by emitting light at the multiple angles toward the object to be imaged to generate a three-dimensional image within a predetermined display area.

[0243] For example, the imaging system 100 can be used in the field of medical testing, where the light emitter emits X-rays. The imaging system 100 uses X-rays to form an image of a part of the human body, such as an organ. In this case, the imaging system 100 provided by the embodiments of the present disclosure can form an image of the object to be detected with an ideal effect, such as forming an ideal three-dimensional image, reflecting the morphology of the object to be detected more realistically and accurately, obtaining more realistic and accurate image information, improving the accuracy of the detection results, and increasing the imaging speed. It is also convenient to always make the formed image located in the preset area of ​​the display, which is simple to operate and has good film output. Of course, in some other embodiments, the light emitted by the light emitter can also be visible light, so as to form a black and white image or a color image. The black and white image or the color image is, for example, a planar image or a three-dimensional image. The application scenarios and imaging types of the flat-panel detector provided by the embodiments of the present disclosure are not limited to the above-mentioned situations.

[0244] The embodiment of the present disclosure further provides a method for manufacturing a detection substrate, including: forming a plurality of pixel units PXU in a pixel setting region R0 of a base substrate BS, the plurality of pixel units PXU including a marking pixel MPX, and at least one alignment mark MK is provided in the marking pixel MPX.

[0245] The manufacturing method of the detection substrate provided by the embodiment of the present disclosure sets an alignment mark MK in at least one of the multiple marking pixels MPX to facilitate monitoring the stitching accuracy and / or alignment accuracy during the manufacturing process of the detection substrate, thereby avoiding the image quality problem of uneven grayscale in the final product image.

[0246] For example, in the manufacturing method of the detection substrate, forming multiple pixel units PXU includes forming multiple photosensitive pixels PXL and forming multiple positioning pixels PX0, wherein at least one marking pixel MPX among the multiple marking pixels MPX is adjacent to at least one photosensitive pixel PXL among the multiple photosensitive pixels PXL; the marking pixel MPX includes at least one positioning pixel among the multiple positioning pixels PX0 and / or at least one photosensitive pixel among the multiple photosensitive pixels PXL.

[0247] For example, in the method for manufacturing the detection substrate, forming the alignment mark MK includes forming a first graphic P1 and a second graphic P2, wherein the orthographic projection of the second graphic P2 on the base substrate BS overlaps with the orthographic projection of the first graphic P1 on the base substrate BS.

[0248] In the method for manufacturing a detection substrate provided by an embodiment of the present disclosure, the second pattern P2 overlaps with the first pattern P1, which is beneficial for monitoring alignment accuracy.

[0249] For example, in the manufacturing method of the detection substrate, the first figure P1 is closer to the base substrate BS than the second figure P2. The manufacturing method includes: performing a threshold comparison, the threshold comparison includes: detecting whether the first boundary distance D1 and the second boundary distance D2 of the first figure P1 and the second figure P2 in the direction X are within the first threshold range, and / or detecting whether the third boundary distance D3 and the fourth boundary distance of the first figure P1 and the second figure P2 in the direction Y are within the second threshold range. If so, continue the subsequent process; if not, remove the second figure P2 and form a new second figure P2; and continue to repeat the threshold comparison step for the first figure P1 and the new second figure P2.

[0250] Step 3) of detecting whether the graphic P201 and the first graphic P1 meet the requirements, as previously described in conjunction with Figures 15A to 15B , and step 5) of detecting whether the first graphic PA and the second graphic PB in the graphic P12 meet the requirements, as previously described in conjunction with Figures 19A to 19C , are both the threshold comparison steps mentioned here.

[0251] For example, in the method for manufacturing the detection substrate, as shown in FIG. 15A to FIG. 15B and FIG. 19A to FIG. 19C , the second pattern P2 is a photoresist pattern.

[0252] In the embodiment of the present disclosure, in the description of the product, the second pattern P2 is a structure in the product. In the manufacturing method, the second pattern P2 is a photoresist pattern. The second pattern P2 in the manufacturing method can refer to the pattern P201 shown in FIG. 15A and the pattern P12 shown in FIG. 19B.

[0253] For example, in the manufacturing method of the detection substrate, the first graphic P1 is formed in the same layer as a component in the photosensitive pixel PXL and / or the marking pixel MPX, and the second graphic P2 is formed in the same layer as another component in the photosensitive pixel PXL and / or the marking pixel MPX.

[0254] For example, in the manufacturing method of the detection substrate, the manufacturing method also includes forming a data line DL and forming a gate line GL, wherein forming the photosensitive pixel PXL includes forming a transistor T0, the gate line GL is connected to the gate GT of the transistor T0, and the data line DL is connected to the source SE of the transistor T0.

[0255] For example, as shown in FIG23 , in this method for manufacturing a detection substrate, a direction X is perpendicular to the extension direction of the data lines DL. The alignment mark is an overlay mark (overlay mark LM1). A first pattern P1 of the overlay mark is on the same layer as the gate lines GL, and a second pattern P2 is provided for the data lines DL. Overlay mark LM1 can be used to monitor alignment accuracy in direction X.

[0256] For example, as shown in Figures 23 to 25 , in this method for manufacturing a detection substrate, a direction Y is perpendicular to the extension direction of the gate line GL, and the alignment mark is a superimposed mark (superimposed mark LM2). The second pattern P2 of the superimposed mark is on the same layer as the data line DL, and the gate line GL is the first pattern P1. The superimposed mark LM1 can be used to monitor alignment accuracy in the direction Y.

[0257] For example, as shown in Figures 23 to 25, in the manufacturing method of the detection substrate, the alignment mark MK includes a first alignment mark MK1 (superimposed mark LM1) and a second alignment mark MK2 (superimposed mark LM2), the direction X is perpendicular to the extension direction of the data line DL, the first graphic P1 of the first alignment mark MK1 (superimposed mark LM1) is in the same layer as the gate line GL, the data line DL is the second graphic P2 of the first alignment mark MK1 (superimposed mark LM1), the second graphic P2 of the second alignment mark MK2 (superimposed mark LM2) is in the same layer as the data line DL, and the gate line GL is the first graphic P1 of the second alignment mark MK2 (superimposed mark LM2).

[0258] The manufacturing method of the detection substrate provided by the embodiment of the present disclosure adopts the gate line GL or the data line DL as a pattern of the alignment mark, thereby avoiding affecting the photosensitivity effect of the photosensitive pixel PXL and improving the display effect.

[0259] For example, as shown in Figures 15A and 19B , in the method for manufacturing a detection substrate, first and second figures P1 and P2 have a first boundary distance D1 and a second boundary distance D2 in direction X, the ratio of the first boundary distance D1 to the larger dimension of the first and second figures P1 and P2 in direction X is less than or equal to 1 / 3, and the ratio of the second boundary distance D2 to the larger dimension of the first and second figures P1 and P2 in direction X is less than or equal to 1 / 3. The second figure P2 herein is the figure P201 shown in Figure 15A and / or the figure P12 shown in Figure 19B .

[0260] For example, as shown in Figures 15A and 19B , in the method for manufacturing a detection substrate, the ratio of the first boundary distance D1 to the larger dimension of the first and second figures P1 and P2 in the direction X is greater than or equal to 1 / 4, and the ratio of the second boundary distance D2 to the larger dimension of the first and second figures P1 and P2 in the direction X is greater than or equal to 1 / 4. The second figure P2 herein is the figure P201 shown in Figure 15A and / or the figure P12 shown in Figure 19B .

[0261] For example, as shown in Figures 15A and 19B , in this method for manufacturing a detection substrate, first pattern P1 and second pattern P2 have a third boundary distance D3 and a fourth boundary distance in direction Y, the ratio of the third boundary distance D3 to the dimension of the first pattern P1 in direction Y is less than or equal to 1 / 3, and the ratio of the fourth boundary distance to the dimension of the first pattern P1 in direction Y is less than or equal to 1 / 3. The second pattern P2 herein is pattern P201 shown in Figure 15A and / or pattern P12 shown in Figure 19B .

[0262] For example, as shown in Figures 15A and 19B , in this method for manufacturing a detection substrate, first pattern P1 and second pattern P2 have a third boundary distance D3 and a fourth boundary distance in direction Y, the ratio of the third boundary distance D3 to the dimension of the first pattern P1 in direction Y is greater than or equal to 1 / 4, and the ratio of the fourth boundary distance to the dimension of the first pattern P1 in direction Y is greater than or equal to 1 / 4. The second pattern P2 herein is pattern P201 shown in Figure 15A , or pattern P12 shown in Figure 19B , or both pattern P12 and pattern P22 shown in Figure 19B .

[0263] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A detection substrate, comprising: A substrate base, including a pixel setting area; as well as A plurality of pixel units are located in the pixel setting area, The plurality of pixel units include marking pixels, and at least one alignment mark is provided in the marking pixels.

2. The detection substrate according to claim 1, wherein: The alignment mark includes a first figure and a second figure, wherein an orthographic projection of the second figure on the base substrate overlaps with an orthographic projection of the first figure on the base substrate.

3. The detection substrate according to claim 2, wherein: The alignment mark includes an overlay mark, the first graphic of the overlay mark is a first material layer, the second graphic of the overlay mark is a second material layer, and the first material layer and the second material layer are made of different materials.

4. The detection substrate according to claim 3, wherein: In the same mark pixel, a plurality of superimposed marks are provided, the first graphics of the plurality of superimposed marks are made of the same material, and the second graphics of at least two of the plurality of superimposed marks are made of different materials.

5. The detection substrate according to claim 4, wherein: The multiple superimposed marks are spaced apart from each other, arranged in sequence along one direction, or arranged in arrays along two directions.

6. The detection substrate according to claim 4 or 5, comprising a gate layer, an active layer, and a source-drain layer, wherein: The active layer is located on a side of the gate layer away from the substrate, the source-drain layer is located on a side of the active layer away from the substrate, the multiple superimposed marks include a first superimposed mark and a second superimposed mark, the first graphic of the first superimposed mark is located in the gate layer, the second graphic of the first superimposed mark is in the same layer as the active layer, the first graphic of the second superimposed mark is located in the gate layer, and the second graphic of the second superimposed mark is located in the source-drain layer.

7. The detection substrate according to claim 6, further comprising a first passivation layer, wherein: The first passivation layer is located on a side of the source / drain layer away from the substrate, the multiple overlay marks further include a third overlay mark, the first graphic of the third overlay mark is located in the gate layer, and the second graphic of the third overlay mark is a via in the first passivation layer.

8. The detection substrate according to claim 6 further comprises a first passivation layer, a first electrode layer, a photoelectric sensing layer, a planarization layer, a second passivation layer, a bias line layer, and a third passivation layer which are sequentially arranged, wherein: The multiple superimposed marks are located in the same mark pixel, and the multiple superimposed marks further include at least one of a third superimposed mark, a fourth superimposed mark, a fifth superimposed mark, a sixth superimposed mark, a seventh superimposed mark, an eighth superimposed mark, and a ninth superimposed mark.

9. The detection substrate according to claim 8, wherein: The plurality of superimposed marks include a third superimposed mark, a fourth superimposed mark, a fifth superimposed mark, a sixth superimposed mark, a seventh superimposed mark, an eighth superimposed mark, and a ninth superimposed mark, The first graphics in the third superimposed mark, the fourth superimposed mark, the fifth superimposed mark, the sixth superimposed mark, the seventh superimposed mark, the eighth superimposed mark, and the ninth superimposed mark are all located in the gate layer, The second graphic of the third superimposed mark is a via in the first passivation layer, the second graphic of the fourth superimposed mark is located in the first electrode layer, the second graphic of the fifth superimposed mark is located in the photoelectric sensing layer, the second graphic of the sixth superimposed mark is a via in the planarization layer, the second graphic of the seventh superimposed mark is a via in the second passivation layer, the second graphic of the eighth superimposed mark is located in the second electrode layer, and the second graphic of the ninth superimposed mark is located in the bias line layer.

10. The detection substrate according to any one of claims 2 to 5, further comprising gate lines and data lines, wherein: At least one of the plurality of pixel units comprises a transistor, the gate line is connected to a gate of the transistor, the data line is connected to a source of the transistor, The alignment mark includes at least one of a first alignment mark and a second alignment mark, In the first alignment mark, the first pattern is in the same layer as the gate line, and the data line is the second pattern. In the second alignment mark, the second pattern is in the same layer as the data line, and the gate line is the first pattern.

11. The detection substrate according to claim 10, wherein: The alignment mark further includes a third alignment mark, and the orthographic projection of the second graphic of the third alignment mark on the base substrate is within the orthographic projection of the first graphic of the third alignment mark on the base substrate.

12. The detection substrate according to any one of claims 3 to 9, wherein: The alignment mark further includes a splicing mark, the first graphic of the splicing mark is an alignment material layer, and the second graphic of the splicing mark is a hollow area.

13. The detection substrate according to claim 12, wherein: The stitching mark includes a first stitching mark, a second stitching mark and a third stitching mark, the first stitching mark is located at the gate layer, the second stitching mark is in the same layer as the active layer, and the third stitching mark is located at the source and drain layer.

14. The detection substrate according to any one of claims 1 to 13, wherein: The marking pixels include a first marking pixel, the splicing mark is located in the first marking pixel, the marking pixels include a second marking pixel, the superimposed mark is located in the second marking pixel, and the first marking pixel and the second marking pixel are adjacent to each other.

15. The detection substrate according to any one of claims 1 to 13, wherein: The marking pixel includes a first marking pixel, the splicing mark is located in the first marking pixel, the marking pixel includes a second marking pixel, the superimposed mark is located in the second marking pixel, the first marking pixel and the second marking pixel are spaced apart from each other, the multiple pixel units include a plurality of non-marking pixels, and at least one of the plurality of non-marking pixels is arranged between the first marking pixel and the second marking pixel.

16. The detection substrate according to any one of claims 2 to 13, wherein: The first figure and the second figure have a first boundary distance and a second boundary distance in a first direction, the first direction is parallel to the base substrate, and a ratio of the first boundary distance to a larger size of the first figure and the second figure in the first direction is less than or equal to 1 / 3, and The ratio of the second boundary distance to the larger size of the first figure and the second figure in the first direction is less than or equal to 1 / 3, and the ratio of the first boundary distance to the larger size of the first figure and the second figure in the first direction is greater than or equal to 1 / 4, and A ratio of the second boundary distance to a larger size of the first figure and the second figure in the first direction is greater than or equal to 1 / 4.

17. The detection substrate according to any one of claims 2 to 9 and 12 to 14, wherein: The orthographic projection of the second graphic on the base substrate is within the orthographic projection of the first graphic on the base substrate.

18. The detection substrate according to claim 17, wherein: The first figure and the second figure have a third boundary distance and a fourth boundary distance in a second direction, the second direction is parallel to the substrate, the second direction intersects the first direction, and the ratio of the third boundary distance to the size of the first figure in the second direction is less than or equal to 1 / 3, and The ratio of the fourth boundary distance to the size of the first figure in the second direction is less than or equal to 1 / 3, the first figure and the second figure have a third boundary distance and a fourth boundary distance in the second direction, and the ratio of the third boundary distance to the size of the first figure in the second direction is greater than or equal to 1 / 4, and The ratio of the fourth boundary distance to the size of the first graphic in the second direction is greater than or Equal to 1 / 4.

19. The detection substrate according to any one of claims 2 to 13, wherein: At least two alignment marks are provided in the same marking pixel, and the two alignment marks are spaced apart from each other.

20. The detection substrate according to any one of claims 1 to 19, wherein: The plurality of pixel units include a plurality of photosensitive pixels and a plurality of positioning pixels. Among them, at least one of the multiple marking pixels is adjacent to at least one of the multiple photosensitive pixels, and the marking pixel includes at least one of the multiple positioning pixels and / or at least one of the multiple photosensitive pixels.

21. The detection substrate according to claim 20, wherein: The positioning pixels include non-light-sensitive pixels.

22. The detection substrate according to claim 21, wherein The positioning pixel is configured to have a fixed gray scale, and the fixed gray scale does not change with real-time changes in incident light.

23. The detection substrate according to claim 20 or 21, wherein: The photosensitive pixel includes a first transistor, a first photoelectric sensing device, and a first bias line. The first electrode of the first photoelectric sensing device is electrically connected to the first transistor, and the second electrode of the first photoelectric sensing device is electrically connected to the first bias line.

24. The detection substrate according to claim 23, wherein: The positioning pixel includes a second transistor, or The positioning pixel includes a second transistor, a second photoelectric sensing device, and a second bias line. The first electrode of the second photoelectric sensing device is connected to the second transistor, and the second electrode of the second photoelectric sensing device is not electrically connected to the second bias line.

25. The detection substrate according to claim 23, wherein The positioning pixel includes a third transistor, a connecting electrode, and a second bias line, wherein the second bias line is electrically connected to the third transistor through the connecting electrode.

26. A detector comprising the detection substrate according to any one of claims 1-25.

27. An imaging system comprising a detector according to claim 25.

28. A method for manufacturing a detection substrate, comprising: A plurality of pixel units are formed in a pixel setting area of ​​a substrate. The plurality of pixel units include a marking pixel, in which at least one alignment mark is provided.

29. The method for manufacturing a detection substrate according to claim 28, wherein: Forming the registration mark includes: A first figure is formed and a second figure is formed, wherein an orthographic projection of the second figure on the base substrate overlaps with an orthographic projection of the first figure on the base substrate.

30. The method for manufacturing a detection substrate according to claim 29, wherein: The first pattern is closer to the base substrate than the second pattern, The production method comprises: Performing a threshold comparison, wherein the threshold comparison includes: detecting whether a first boundary distance and a second boundary distance between the first graphic and the second graphic in the first direction are within a first threshold range, and / or detecting whether a third boundary distance and a fourth boundary distance between the first graphic and the second graphic in the second direction are within a second threshold range, if so, continuing with the subsequent process, if not, removing the second graphic and forming a new second graphic; The threshold comparison step is then repeated for the first graph and the new second graph.

31. The method for manufacturing a detection substrate according to claim 30, wherein: The second pattern is a photoresist layer.

32. The method for manufacturing a detection substrate according to claim 31, further comprising forming data lines and forming gate lines, wherein: Forming the plurality of pixel units includes forming a transistor, the gate line is connected to a gate of the transistor, the data line is connected to a source of the transistor, The alignment mark includes at least one of a first alignment mark and a second alignment mark, In the first alignment mark, the first pattern is in the same layer as the gate line, and the data line is the second pattern. In the second alignment mark, the second pattern is in the same layer as the data line, and the gate line is the first pattern.

33. The method for manufacturing a detection substrate according to any one of claims 29 to 32, wherein: The first figure and the second figure have the first boundary distance and the second boundary distance in the first direction, and the ratio of the first boundary distance to the larger size of the first figure and the second figure in the first direction is less than or equal to 1 / 3, and The ratio of the second boundary distance to the larger size of the first figure and the second figure in the first direction is less than or equal to 1 / 3, The ratio of the first boundary distance to the larger size of the first figure and the second figure in the first direction is greater than or equal to 1 / 4, and The second boundary distance is the distance between the first figure and the second figure in the first direction The ratio of the larger dimension is greater than or equal to 1 / 4.

34. The method for manufacturing a detection substrate according to any one of claims 29 to 33, wherein: The first figure and the second figure have the third boundary distance and the fourth boundary distance in the second direction, and the ratio of the third boundary distance to the size of the first figure in the second direction is less than or equal to 1 / 3, and The ratio of the fourth boundary distance to the size of the first graphic in the second direction is less than or equal to 1 / 3, The first figure and the second figure have a third boundary distance and a fourth boundary distance in the second direction, and the ratio of the third boundary distance to the size of the first figure in the second direction is greater than or equal to 1 / 4, and A ratio of the fourth boundary distance to a size of the first graphic in the second direction is greater than or equal to 1 / 4.

35. The method for manufacturing a detection substrate according to any one of claims 29 to 34, wherein: Forming the plurality of pixel units includes forming a plurality of photosensitive pixels and forming a plurality of positioning pixels. Among them, at least one of the multiple marking pixels is adjacent to at least one of the multiple photosensitive pixels, and the marking pixel includes at least one of the multiple positioning pixels and / or at least one of the multiple photosensitive pixels.

36. The method for manufacturing a detection substrate according to any one of claims 29 to 35, wherein: The first pattern is formed in the same layer as one component in the marking pixel, and the second pattern is formed in the same layer as another component in the marking pixel.

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