Matrix tail block data calculation processing method and device based on multi-core CPU

Abstract

The invention relates to the technical field of computers, in particular to a matrix tail block data calculation processing method and device based on a multi-core CPU. The method comprises the steps that a matrix enters a DDR memory, region division is carried out on a CPU calculation core end to obtain a plurality of calculation regions, and data region division is carried out on the matrix to obtain a plurality of matrix blocks; in the process that the DDR is mainly stored in the on-packing memory cache, whether a current matrix block and a next matrix block are combined into a matrix or not is judged, and then the matrix enters the on-packing memory cache; the method comprises the following steps: when a matrix is in an on-packing memory cache, cutting the matrix into blocks according to the characteristics of the Cache cache; in the process that the matrix is cached to the cache in the on-packing memory, whether a current matrix block and a next matrix block are combined into a matrix or not is judged, and then the matrix enters the cache; in the cache, the matrix is cut into blocks according to the storage unit of the register and is transmitted to the register. According to the method, the tail block calculation is better fused into the overall calculation process, the multi-core parallel processing capacity of the CPU is fully played, and the calculation power waste caused by insufficient data volume of the tail block is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a matrix tail block data calculation processing method and device based on multi-core CPU. BACKGROUND

[0002] At present, big data and artificial intelligence are developing rapidly, and the demand for high-performance computing is increasing. In the high-performance computing system, matrix operation plays a key role, which is a series of mathematical operations on matrices. Matrix block, as an important strategy for optimizing matrix operation, divides large matrices into multiple sub-matrix blocks, and each sub-block can be independently operated. In the multi-core processor environment, different sub-blocks can be processed in parallel, which can significantly shorten the operation time and improve the computing efficiency.

[0003] In modern CPU architecture, multi-core design has become a mainstream trend. Each core has independent computing power and interacts and cooperates through a shared cache hierarchy and high-bandwidth memory bus. This design enables the CPU to perform multi-core collaboration when processing parallel tasks, thereby significantly improving throughput and resource utilization. Especially in the matrix block calculation scenario, the CPU can simultaneously operate on multiple sub-blocks, effectively reducing the waiting time of single-core calculation, and fully utilizing the advantages of instruction-level parallelism and thread-level parallelism. However, there is a tail block processing problem in CPU-based matrix block. After block division according to fixed specifications, there will always be a tail block. Common processing methods include padding, direct calculation or separate design. However, these methods do not fully utilize the storage capacity of modern CPUs. Padding the tail block in the CPU requires post-processing to remove the padded part, which increases the time cost; separate design of the tail block results in a large amount of idle computing power due to small calculation amount. SUMMARY

[0004] To solve the technical problems existing in the prior art, the present application provides a matrix tail block data calculation processing method and device based on multi-core CPU, which integrates tail block calculation into the overall calculation process, fully utilizes the multi-core parallel processing capability of the CPU, and enables each core to participate in the calculation, effectively avoiding the waste of computing power caused by insufficient tail block data, and making full and reasonable use of hardware resources in matrix operation.

[0005] The first object of the present application is to provide a matrix tail block data calculation processing method based on multi-core CPU.

[0006] The second object of the present application is to provide a computer device.

[0007] The first object of the present application can be achieved by adopting the following technical solutions: A matrix tail block data calculation processing method based on multi-core CPU, the method comprising: S1, after the matrix enters the DDR memory, a plurality of calculation regions are divided at the CPU calculation core end, the dimensions M and N of the matrix are divided to obtain a plurality of matrix blocks, and the data of each matrix block is distributed to each calculation region; S2, in the process of storing the matrix in the DDR memory to the on-packing memory cache, it is judged whether the size of the next matrix block of the current matrix block meets a preset condition; when the preset condition is met, the current matrix block and the next matrix block are merged into a matrix block and then enter the on-packing memory cache; when the preset condition is not met, the current matrix block directly enters the on-packing memory cache; S3, in the on-packing memory cache, the matrix is divided into matrix subblocks with sizes suitable for the cache according to the characteristics of the cache, so that different calculation cores cyclically obtain matrix subblocks with different fixed sizes; S4, in the process of storing the matrix in the on-packing memory cache to the cache, the size of the matrix block is judged and processed; whether the size of the next matrix block of the current matrix block meets a second preset condition is judged, when the second preset condition is met, the current matrix block and the next matrix block are merged into a matrix block and then enter the cache; when the second preset condition is not met, the current matrix block directly enters the cache; S5, in the cache, the matrix is cut and transmitted to the register according to the storage unit of the register, and the matrix is calculated in the register.

[0008] Specifically, the step S1 comprises: According to the calculation task and the number of CPU calculation cores, a plurality of calculation cores are combined to form a calculation region, and a plurality of calculation regions are divided at the CPU calculation core end; according to the load balancing strategy, the dimensions M and N of the matrix are divided to obtain a plurality of matrix blocks with sizes suitable for the on-packing memory cache. The matrix blocks are arranged in row priority order to form a logical two-dimensional block structure, and a round-robin distribution mechanism is used to distribute the matrix blocks to each calculation region for processing.

[0009] Specifically, the step S2 comprises: The value of the position where the end of the matrix block of the current matrix block is located, the value of the position where the start of the current block is located, and the set threshold value are matched with the preset condition to judge whether the current matrix block and the next matrix block are merged into a matrix block and then enter the on-packing memory cache.

[0010] Specifically, the preset condition is defined as a function f (x), which is expressed as: ; Wherein, is the position of the end of the matrix block, is the position of the start of the current block, x and y are coefficient variables, represents a threshold value, C and k are normal numbers.

[0011] Specifically, the step S4 comprises: After the matrix block completes the flow from the previous storage level to the current storage level, the value of the position of the end of the current matrix block, the value of the position of the start of the current block and the second threshold value are matched according to the second preset condition, so as to determine whether the current matrix block is merged with the next matrix block to form a matrix block and then enter the Cache cache.

[0012] Specifically, the second preset condition is defined as a function , and the function is expressed as: ; Wherein is the position of the end of the matrix block, is the position of the start of the current block, x and y are coefficient variables, represents a second threshold value, C and k are normal numbers.

[0013] The second object of the application can be achieved by adopting the following technical scheme: A computer device comprises a processor and a memory for storing programs executable by the processor, and when the processor executes the programs stored in the memory, the above-mentioned matrix tail block data calculation processing method based on a multi-core CPU is realized.

[0014] Compared with the prior art, the application has the following advantages and beneficial effects: This invention proposes a matrix tail block data computation and processing method based on multi-core CPUs. During the task partitioning phase, the main block and tail block of the matrix are simultaneously incorporated into a unified block scheduling scheme according to the matrix dimension and the number of CPU cores. Secondly, during the fusion phase, the computation results of the tail block and the main block are converged at the cache or on-packing memory level, thereby maintaining data continuity and cache friendliness, and reducing bandwidth consumption during cross-core data migration. Thirdly, during the computation core allocation phase, each matrix block is mapped to a specific CPU core, ensuring that all cores have tasks to execute, preventing some cores from being idle during the tail block phase, and achieving full utilization of computing resources. During the computation execution phase, each core performs the corresponding matrix block multiplication and addition operations through register-level parallel computation. Through the above methods, tail block data can be collaboratively executed with main block computation within the same parallel framework, significantly reducing additional loop counts and branch judgments. This method integrates tail block computation into a unified scheduling process, keeping each core active throughout the entire computation phase. This not only improves load balancing among cores and prevents some cores from being idle during the tail block phase, but also enhances the collaborative efficiency between multi-cores. Meanwhile, due to the reduction in the number of computation loops and the shorter data migration path, the overall execution latency and energy consumption of the system are reduced, ultimately achieving more efficient hardware utilization and better parallel performance.

[0015] This invention integrates tail block computation into the overall computation process, fully leverages the multi-core parallel processing capabilities of the CPU, and enables each core to participate in the computation. This effectively avoids the waste of computing power caused by insufficient tail block data, allowing hardware resources to be used more fully and rationally in matrix operations. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a matrix tail block data calculation and processing method based on a multi-core CPU in an embodiment of the present invention; Figure 2 This is a logical flowchart of the matrix tail block data calculation and processing method based on a multi-core CPU in an embodiment of the present invention; Figure 3 This is a diagram showing the distribution of matrix blocks corresponding to the computational region processing in this embodiment of the invention. Figure 4This is a distribution diagram of matrix blocks with tails corresponding to the computational region processing in this embodiment of the invention; Figure 5 This is a memory pipeline diagram of the matrix block at various levels in the embodiments of the present invention; Figure 6 This is a pipeline diagram showing the existence of matrix blocks at various memory levels in embodiments of the present invention. Detailed Implementation

[0018] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the implementation of the present invention is not limited thereto. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1: like Figures 1-2 As shown, the matrix tail block data calculation and processing method based on a multi-core CPU according to the present invention includes the following steps: S1. After the matrix enters the DDR memory, it is divided into several computing regions at the CPU computing core. The dimensions M and N of the matrix are divided into several matrix blocks, and the data of each matrix block is allocated to each computing region.

[0020] S11. Based on the computing task and the number of CPU cores, a number of computing cores are grouped into a computing region, and several computing regions are divided at the CPU core end. Based on the load balancing strategy and combined with the characteristics of on-packing memory cache, the dimensions M and N of the matrix are divided to obtain several matrix blocks with sizes adapted to on-packing memory cache.

[0021] Because on-packing memory caches have capacity limitations, the entire matrix cannot be processed in matrix and vector operation units at once. Therefore, the matrix needs to be divided into multiple sub-blocks based on the number of CPU cores and cache size, utilizing cache space as much as possible. This ensures that each core processes a similar number of blocks, maximizing system resources and improving overall computational efficiency. Load balancing strategies refer to a method of rationally allocating computational tasks in a multi-core CPU, aiming to keep all cores busy as simultaneously as possible to improve overall efficiency. Based on load balancing strategies and the characteristics of on-packing memory caches, the matrix dimensions M and N are divided into several matrix blocks. Data from different matrix blocks is then allocated to corresponding computational regions, ensuring that the data processed by each region is not duplicated. However, even after these operations, the matrix size in each region still far exceeds memory capacity. Dividing the matrix into computational regions at the CPU core level is system-level task partitioning, focusing on task allocation strategies. Dividing the matrix into matrix blocks is data-level data partitioning.

[0022] Specifically, the CPU computing core is divided into several computing regions. This includes dividing the entire computing task into several regions row-wise, with each region assigned to a different CPU core for execution. This ensures a balanced workload across cores and reduces idle waiting time. The matrix dimensions M and N are also divided, including partitioning the matrix along the row direction M and column direction N to obtain multiple smaller sub-matrix blocks. For example, in matrix multiplication C = A × B, assuming matrices A, B, and C are all 1024 × 1024, to achieve multi-core parallel computing, matrix A can be divided into four 256 × 1024 row blocks, and matrix B can be divided into four 1024 × 256 column blocks. This results in matrix C having 4 × 4 = 16 256 × 256 sub-blocks. Each C sub-block can be assigned to a different CPU core for independent computation, thus achieving multi-core parallel processing and improving overall computing efficiency.

[0023] Generally, the dimensions of a matrix include three subdivisions: M, N, and K. Matrix multiplication is of the form: C = A × B; in this equation, M, N, and K define the dimensions of the three matrices: M represents the number of rows in the resulting matrix C, which is also equal to the number of rows in matrix A. N represents the number of columns in the resulting matrix C, which is also equal to the number of columns in matrix B. K represents the number of columns in matrix A, which is also equal to the number of rows in matrix B. Each row vector of matrix A needs to be multiplied by each column vector of matrix B, and the length of this multiplication product is K. Matrix A is M*K, matrix B is K*N, and matrix C is M*N.

[0024] Specifically, the characteristics of on-packing memory caching include cache capacity and read / write speed. These parameters may vary depending on the hardware, and the size of the blocks used to divide the matrix dimensions M and N will also differ. Here, we take a cache capacity of 4096 bytes per block as an example. This block-based approach enables efficient data storage and fast retrieval.

[0025] In this embodiment, the matrix is ​​loaded into DDR memory during system startup. Because matrix operations are highly dependent on memory access performance, the dimensions M and N of the matrix need to be finely divided. In a multi-core CPU architecture, multi-core parallelism is utilized to improve computational efficiency. Different computational regions are allocated different matrix blocks of fixed sizes. For example, matrix A has a size of m × k = 1024 × 2048, and matrix B has a size of k × n = 2048 × 83498. Taking matrix B as an example, multi-core CPU computation is performed, assuming 100 computational cores. These cores are further divided into 10 computational regions. Based on the data scale of matrix B in the n-dimensional direction, the dimension is partitioned according to the number of computational regions. Based on the load balancing principle, the theoretical value of the matrix block size in the n-dimensional direction corresponding to each computational region is 8349.8. Since n = 83498, and it is divided into 10 regions, each region has a size of 8349.8. Considering the integrity requirements of matrix data storage and computation, in practice, the matrix block size is rounded up to 8350.

[0026] S12. Arrange the matrix blocks in row-major order to form a logical two-dimensional block structure, and use a round-robin allocation mechanism to allocate the matrix blocks to each computing region for processing.

[0027] like Figure 3 The diagram shown is a distribution diagram of the matrix blocks corresponding to the computational region processing in an embodiment of the present invention. This diagram illustrates in detail the parallel computing strategy of matrix partitioning and multi-core allocation. Figure 3As shown in the upper part, the original matrix is ​​first divided into several consecutive matrix blocks (Block 0, Block 1, Block 2, ..., Block m+2). These matrix blocks are arranged in row-major order, forming a logical two-dimensional block structure, laying the data foundation for subsequent parallel processing. Figure 3 The lower part of the diagram shows the resource allocation scheme for the computing cores. The system organizes four computing cores (core 0 to core 3) into parallel computing units, with each core assigned an independent processing queue.

[0028] The matrix blocks are allocated using a round-robin mechanism: Block 0 is allocated to core 0, Block 1 to core 1, Block 2 to core 2, Block 3 to core 3, then Block 4 is allocated to core 0, and so on, forming a cyclical allocation pattern of "Block 4 → core 0, Block 5 → core 1, Block 6 → core 2, Block 7 → core 3". This allocation scheme ensures that the continuous data block stream (Block m, Block m+1, Block m+2, Block m+3...) can sequentially guarantee that all computations have a computational core to participate in the computation.

[0029] S2. During the process of transferring the matrix from DDR main memory to the on-packing memory cache, it is determined whether the size of the next matrix block meets a preset condition. If the preset condition is met, the current matrix block and the next matrix block are merged into one matrix before entering the on-packing memory cache. If the preset condition is not met, the current matrix block directly enters the on-packing memory cache. By introducing a tail-merging processing method, the matrix partitioning rules are optimized, the number of loops in the matrix processing process is reduced, and data can flow between upper and lower memory levels more quickly.

[0030] Specifically, based on preset conditions, the system matches the values ​​at the end and start points of the current matrix block with a set threshold Msize to determine whether the current matrix block should be merged with the next matrix block into a single matrix before entering the on-packing memory cache. The preset conditions are defined as a function f(x), which can be expressed as: (1) in, This represents the location of the endpoint of the matrix block. This represents the starting position of the current block. x and y are coefficient variables, Msize represents the threshold, and C and k are positive constants.

[0031] During the transfer of the matrix from DDR memory to on-packing memory, the system uses a dynamic memory access optimization algorithm to obtain the tail address of the current matrix block and the starting address and size parameters of the next block through an address mapping mechanism. The function f(x) is used to determine whether the size of the next matrix block of the current matrix block meets the conditions. If it does, adjacent blocks are merged into optimized data units through memory remapping to reduce the number of memory accesses. If it does not meet the conditions, the original block strategy is maintained to ensure the continuity of data transmission. This method integrates a cache prefetching algorithm and a memory access scheduler, and reduces memory access latency and improves data transfer efficiency through predictive data layout optimization.

[0032] In this embodiment, the front matrix block is set. The size is: ; If the current matrix block is The dimension is m*n, and the size of the tail block matrix is ​​m*k. The size of the matrix after merging the current matrix block and the next matrix block (m*k+n) is made to be carried into the next level of memory as a whole. That is, the current matrix plus the tail matrix of the next row can be represented as: ; If the current matrix block is The dimension is m*n, and the size of the tail block matrix is ​​k*n. The size of the matrix after merging the current matrix block and the next matrix block is (m+k)*n, so that the two are entered as a whole into the next level of memory. That is, the current matrix plus the tail matrix of the next row can be represented as: ; In this example, matrix B: K*N is used as an example to divide the matrix into blocks. Matrix B is transferred from DDR memory to on-packing memory. The block size in the N direction is 4096, so 8350 / 4096 = 3. The block size of each division is: 4096, 4096, 158. During the process of transferring from DDR to on-packing memory, the generated tail_k is the tail block, corresponding to the block size of 158 in the data above. It can be calculated according to the function f(x) (1), while assigning constants to the formula, x=1, y=11 / 10, Substituting 4096 into function (1) yields: ; In this embodiment, after the first 4096 matrix block enters... =8350, =0, then a judgment is made: 8350 > 11 / 10 * 4096 = 4505, so 8350 does not meet the condition. Therefore, the first block goes to the no branch of the judgment and enters the on-packingmemory with a matrix block size of 4096. When the second matrix block enters the judgment, =8350, =4096 We can see that: 8350-4096=4254, 4254>4096 At the same time, 4254<11 / 10 * 4096 = 4505, which meets the judgment condition. Therefore, the size of the second matrix is: the size of the second matrix block of 4096 plus the size of the last matrix block of 158, and enters the on-packing memory with a matrix block size of 4254.

[0033] Specifically, the N-dimensional size of the first matrix block is 4096, represented as: ; The second matrix block has an N-dimensional size of 4505, represented as:

[0034] like Figure 4 The figure shown is a distribution diagram of matrix blocks with tails corresponding to the computational region processing in an embodiment of the present invention. This figure illustrates the matrix block parallel computation strategy based on dynamic task merging. Figure 4 As shown in the upper part, during the matrix partitioning stage, the system divides the original matrix into sequence blocks from BLOCK0 to BLOCKm+2. Of particular note are the adjacency relationships between sequence blocks BLOCK2 and BLOCK3, BLOCK6 and BLOCK7, etc. Figure 4 As shown in the lower part, during the task allocation phase, the system detects that the data size of the next block, BLOCK3, in sequence block BLOCK2 does not reach the effective computational granularity. Therefore, it binds BLOCK3 with sequence block BLOCK2. This dynamic merging mechanism is reflected in the actual task queue of computing core 2. This computing core not only needs to process the originally allocated regular block BLOCK2, but also undertakes the computational tasks of BLOCK3 that should belong to computing core 3. Computing core 3 then performs the computational tasks of BLOCK3 and BLOCK4, and so on. By merging two adjacent data blocks for computation, the problem of low efficiency in small-scale matrix computation is avoided, while maintaining the continuity of the task queue. This intelligent task allocation scheme significantly improves the overall computational efficiency by dynamically adjusting the computational granularity while ensuring load balancing, and particularly optimizes the computational performance of boundary small block matrices.

[0035] S3. In the on-packing memory cache, the matrix is ​​divided into matrix sub-blocks of different sizes according to the characteristics of the cache, so that different computing cores can obtain matrix sub-blocks of different fixed sizes in a loop.

[0036] Specifically, in multi-core CPUs, because the cache capacity is significantly smaller than the on-chip packaged memory, it is impossible to load the complete matrix into the matrix operation unit and vector operation unit for processing at once. The system needs to partition the data using a block matrix algorithm based on cache characteristics, the principle of locality of reference, cache line size, and other features. Through load balancing strategies, combined with cache capacity limitations and cache line alignment rules, the matrix is ​​decomposed into matrix sub-blocks of a size adapted to the cache, ensuring that the number of blocks processed by each computing core and the computational complexity tend to be consistent, achieving cache-aware load balancing. The cache characteristics include cache capacity, cache line size, read / write speed, and other metrics.

[0037] The matrix resides in on-packing memory. It is divided into blocks, with different computational cores iteratively generating different fixed-size matrix blocks. Cache characteristics are analyzed to ensure that the partitioned matrix data effectively utilizes memory while avoiding performance bottlenecks caused by memory overflow. Since different hardware may result in different parameters, this example uses 1920 pixels per block.

[0038] like Figure 5The diagram shows the memory pipeline of the matrix blocks at various levels in this embodiment of the invention. This diagram illustrates the data transfer relationship in the multi-layered storage system (DDR main memory, On-Packing Memory cache, and Cache) during matrix multiplication, demonstrating the hierarchical loading and block-based computation mechanism from main memory to on-chip cache. The topmost DDR is the global storage layer, storing the complete matrix data. Data in DDR is divided into several ON-PACKING MEMORY_M, ON-PACKING MEMORY_N, and ON-PACKING MEMORY_K sub-blocks according to their dimensions. Each sub-block corresponds to a different data segmentation along the matrix dimensions (M, N, K). During the data transfer phase, these blocks in DDR are progressively loaded onto the cache of the intermediate ON-PACKING MEMORY layer. This layer temporarily stores the sub-block data required for computation through areas such as CACHE_M, CACHE_N, and CACHE_K, thereby achieving continuous access and cross-dimensional reuse of the blocks. The lowest-level cache corresponds to the on-chip cache area used by the actual computing core. Each CACHE_M, CACHE_K, and CACHE_N block is further subdivided into smaller data blocks that can be directly read and written back by the computing units. During computation, blocks of the matrix in different matrix dimensions are sequentially passed down from DDR → On-Packing Memory → Cache through hierarchical mapping. This achieves data localization, bandwidth reuse, and minimizes memory access overhead, thereby improving the overall throughput efficiency and cache hit rate of matrix multiplication in multi-core or heterogeneous architectures.

[0039] S4. During the process of caching the matrix from on-packing memory to the cache, the size of the matrix block is judged. It is determined whether the size of the next matrix block of the current matrix block meets the second preset condition. If the second preset condition is met, the current matrix block and the next matrix block are merged into one matrix and then entered into the cache. If the second preset condition is not met, the current matrix block is directly entered into the cache.

[0040] Specifically, during the flow of a matrix from on-packing memory to cache memory, after a matrix block completes its transfer from the previous storage level to the current storage level, a second preset condition is applied to match the values ​​at the end point of the current matrix block, the start point of the current block, and a set second threshold. This determines whether the current matrix block should be merged with the next matrix block to form a single matrix before entering the on-packing memory cache. The second preset condition is defined as a function... ,function It can be represented as: (2) in This represents the location of the endpoint of the matrix block. The current block starts at position x, y are coefficient variables. This represents the second threshold, where C and k are positive constants.

[0041] Through this function Perform a judgment: if the next block of the current matrix block satisfies the function... If the function is not satisfied, the next matrix block will be merged into the current matrix block and moved together to the next level of memory. Then the current matrix block and the next matrix block will be loaded into the next level of memory according to the original matrix block size.

[0042] Taking matrix B as an example, we divide matrix B into data blocks. Assuming this region extends from on-packing memory to cache memory, the block size in the n-direction is 4096 (this 4096 is passed from the memory matrix block in the previous layer), then 4096 / 1920 = 3. The block size for each division is: 1920, 1920, 256.

[0043] Associative functions At the same time, constants are assigned to the formula: x=1, y=3 / 2. Substituting 1920 into the formula yields... ; In this embodiment, the process of determining whether the size of the next matrix block of the current matrix segment meets the second preset condition includes: when the first 1920 matrix block enters, =4096, =0, then perform a judgment: 4096 > 3 / 2 * 1920 = 2880, so 4096 does not meet the condition. Therefore, the first block goes to the no branch of the judgment and enters the cache with a matrix block size of 1920. When the second matrix block enters the judgment, =4096, =1920 We can see that: 4096 -1920=2176, 2176>1920 At the same time, 2176<3 / 2 * 1920 =2880, which meets the judgment requirements. Therefore, the size of the second matrix is: the size of the second matrix block of 1920 plus the size of the last matrix block of 256, and enters the cache with a matrix block size of 2176.

[0044] The first matrix block has an N-dimensional size of 1920, represented as: ; The second matrix block has an N-dimensional size of 2176, represented as: ; In this embodiment, during the stage of transferring matrix data from the on-chip on-packing memory cache to the cache cache, the address mapping mechanism of the memory management unit is used to obtain in real time the tail address of the current matrix block, the start address of the next block, and the size parameters. This is based on a preset mathematical judgment model function. The threshold is dynamically calculated based on hardware parameters such as cache line size and cache capacity to determine whether the size of the next block meets ΔS. If the preset condition is met, the current block and the next tail block are merged into an optimized data unit adapted to the cache level; otherwise, the original block boundary is maintained.

[0045] S5. The matrix is ​​in the cache. The matrix is ​​divided into blocks according to the storage unit of the register and transferred to the register. The matrix is ​​then used for calculation in the register.

[0046] Specifically, matrix data resides in the cache storage level. The system, based on the register's bit width (e.g., 32-bit, 64-bit, or wider vector registers), pipelines the matrix data from the cache to the next level of memory, according to the amount of data the register can process at a time. Matrix calculations are then performed within these registers. In the CPU, registers are the lowest-level unit for performing matrix calculations and also the fastest storage area. During matrix multiplication, the processor first retrieves a portion of the matrix data from the cache (e.g., a row of A and a column of B) and loads it into registers. Then, it uses calculation instructions to directly perform multiplication and addition operations within the registers, gradually accumulating the results.

[0047] like Figure 6The diagram shows the pipeline of matrix blocks at various memory levels in this embodiment of the invention. It illustrates the block loading and cache mapping process of matrix multiplication in a multi-layered storage system, with particular emphasis on the data processing method of the tail block. In the top-level DDR (main memory), the complete matrix data is divided into multiple blocks, some corresponding to the data blocks of matrix $A$ and others to the blocks of matrix $B$. Whenever the dimension of the matrix is ​​not divisible by the block size, a special tail block appears in the DDR, representing the remaining boundary data. At this point, the size of the tail block is determined to determine whether it can be passed to the next-level cache (on-packing memory) along with the previous matrix block, allowing the data to enter the next-level cache normally and ignoring the computational loss caused by the tail block. In the on-packing memory cache, the matrix blocks obtained from the DDR are further divided. Similar to the previous discussion, when a tail block of a matrix appears, its data size is determined. The tail block region is typically smaller than a standard block, so this size check ensures that the combined length of the data from the previous block is sufficient to satisfy the size of the next-level cache and participate in subsequent calculations. Within the cache, the matrix is ​​further divided into fine-grained computational blocks, such as CACHE_M, CACHE_K, and CACHE_N regions, for high-speed single-core computation. Since the tail block data is usually smaller than a standard computational block, this method uses a strategy of merging it with the previous matrix block, allowing it to be mapped to the same CACHE_M, CACHE_K, or CACHE_N region for processing. This allows the tail block data to participate in computation in the same way as regular blocks, without requiring separate branches or additional loops, thus maintaining consistency between the data flow and computation flow and fully leveraging the computational efficiency at the cache and register levels.

[0048] In summary, the matrix tail block data processing method based on a multi-core CPU architecture provided in this embodiment incorporates both the main and tail blocks of the matrix into a unified block scheduling scheme during the task partitioning phase, according to the matrix dimension and the number of CPU cores. Secondly, during the fusion phase, the computation results of the tail block and the main block are converged at the cache or on-packing memory level, maintaining data continuity and cache friendliness, and reducing bandwidth consumption during cross-core data migration. Thirdly, during the computation core allocation phase, each matrix block (including the matrix block combined with the tail block) is mapped to a specific CPU core, ensuring all cores have tasks to execute and preventing some cores from being idle during the tail block phase, thus achieving full utilization of computational resources. Next, during the computation execution phase, each core performs the corresponding matrix block multiplication and addition operations through register-level parallel computation. Through these methods, tail block data can be executed collaboratively with main block computation within the same parallel framework, significantly reducing additional loop counts and branch judgments. This method integrates tail block computation into a unified scheduling process, keeping each core active throughout the entire computation phase. This not only improves load balancing among cores, preventing some cores from being idle during the tail block phase, but also enhances the collaborative efficiency between multiple cores. Simultaneously, due to the reduced number of computation loops and shorter data migration paths, the overall system execution latency and energy consumption are reduced, ultimately achieving more efficient hardware utilization and superior parallel performance.

[0049] This invention proposes a matrix tail block data calculation and processing method based on a multi-core CPU. From a computational efficiency perspective, traditional padding methods require the CPU to consume additional computing resources and time to process new data, as a subsequent culling operation is necessary, making the process cumbersome. This method directly avoids the complex process of traditional padding, significantly reducing unnecessary computation and greatly simplifying the matrix tail block calculation process. Regarding computing power utilization, compared to the traditional approach of designing the tail block separately, traditional methods, due to the small size of the tail block data, struggle to fully utilize the CPU's multi-core resources, resulting in resource waste. This invention, by better integrating tail block calculation into the overall computational flow, fully leverages the parallel processing capabilities of the CPU's multi-cores, enabling each core to participate in the calculation. This effectively avoids the waste of computing power caused by insufficient tail block data, allowing hardware resources to be used more fully and rationally in matrix operations.

[0050] Example 2 This embodiment provides a computer device, which may be a server, computer, etc., including a processor, memory, input device, display, and network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. When the processor executes the computer programs stored in the memory, it implements the matrix tail block data processing method based on a multi-core CPU architecture as described in Embodiment 1 above, as follows: S1. The matrix involved in the matrix operation is stored in DDR memory. At the CPU computing core, it is divided into several computing regions. The matrix is ​​divided into several matrix blocks, and the data of the matrix blocks is allocated to the corresponding computing regions. S2. During the process of moving the matrix from DDR main memory to on-packing memory cache, it is determined whether the size of the next matrix block of the current matrix block meets the preset conditions. If the preset conditions are met, the current matrix block and the next matrix block are merged into one matrix and then enter the on-packing memory cache. If the preset conditions are not met, the current matrix block directly enters the on-packing memory cache. S3. In the on-packing memory cache, the matrix is ​​divided into blocks according to the characteristics of the cache, so that different computing cores obtain matrix blocks of different fixed sizes in a loop. S4. During the process of caching the matrix from on-packing memory to the cache, the size of the matrix block is judged. It is determined whether the size of the next matrix block of the current matrix block meets the second preset condition. If the second preset condition is met, the current matrix block and the next matrix block are merged into one matrix and then entered into the cache. If the second preset condition is not met, the current matrix block is directly entered into the cache. S5. The matrix is ​​in the cache. The matrix is ​​divided into blocks according to the storage unit of the register and transferred to the register. The matrix is ​​then used for calculation in the register.

[0051] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for processing matrix tail block data based on a multi-core CPU, characterized in that, The method comprises the following steps: S1, after the matrix enters the DDR memory, the CPU calculation core end is divided into several calculation regions, the dimensions M and N of the matrix are divided to obtain several matrix blocks, and the data of each matrix block is distributed to each calculation region; S2, during the process of storing the matrix in the DDR memory to the on-packing memory cache, it is judged whether the size of the next matrix block of the current matrix block meets a preset condition; when the preset condition is met, the current matrix block and the next matrix block are merged into a matrix block and then enter the on-packing memory cache; When the preset condition is not met, the current matrix block directly enters the on-packing memory cache; S3, in the on-packing memory cache, the matrix is divided into matrix sub-blocks with sizes suitable for the cache according to the characteristics of the cache, so that different calculation cores cyclically obtain matrix sub-blocks with different fixed sizes; S4, during the process of storing the matrix in the on-packing memory cache to the cache, the size of the matrix block is judged and processed; it is judged whether the size of the next matrix block of the current matrix block meets a second preset condition; when the second preset condition is met, the current matrix block and the next matrix block are merged into a matrix block and then enter the cache; When the second preset condition is not met, the current matrix block directly enters the cache; S5, in the cache, the matrix is cut into pieces according to the storage unit of the register and is transmitted to the register, and the matrix is calculated in the register.

2. The method of claim 1, wherein the method is based on a multi-core CPU. The step S1 comprises: According to the calculation task and the number of CPU calculation cores, a plurality of calculation cores are combined to form a calculation region, and the CPU calculation core end is divided into a plurality of calculation regions; according to a load balancing strategy, the dimensions M and N of the matrix are divided to obtain a plurality of matrix blocks with sizes suitable for the on-packing memory cache according to the characteristics of the on-packing memory cache; The matrix blocks are arranged in row priority order to form a two-dimensional block structure, and a round-robin distribution mechanism is used to distribute the matrix blocks to each calculation region for processing.

3. The method of claim 2, wherein the method further comprises: The characteristics of the on-packing memory cache include cache capacity and read-write speed.

4. The method of claim 1, wherein the method is based on a multi-core CPU. The step S2 comprises: The value of the position where the matrix block of the current matrix block ends, the value of the position where the start of the current block is located, and the set threshold value are matched with the preset condition to judge whether the current matrix block and the next matrix block are merged into a matrix block and then enter the on-packing memory cache.

5. The method of claim 4, wherein the method further comprises: The preset condition is defined as a function f(x), and the function f(x) is represented as: wherein, is the location of the end of the matrix block, is the location of the start of the current block; x, y are coefficient variables, represents a threshold value, C, k are normal numbers.

6. The method of claim 5, wherein the method further comprises: The step S4 comprises: When the matrix block completes the flow from the previous storage to the current storage level, the second preset condition matching is performed on the value at the position of the matrix block end point of the current matrix block, the value at the position of the current block start point and the set second threshold value, to determine whether the current matrix block is merged with the next matrix block to form a matrix and then enter the Cache cache.

7. The method of claim 6, wherein the method further comprises: The second preset condition is defined as a function , the function represents: ； wherein, is a location of a matrix block end point, is a location of a current block start point, x, y are coefficient variables, represents a second threshold value, C, k is a normal number.

8. A computer device comprising a processor and a memory for storing a processor executable program, characterized in that, The processor implements the program stored in the memory, and a matrix tail block data calculation processing method based on a multi-core CPU is realized. The processor implements the program stored in the memory, and a matrix tail block data calculation processing method based on a multi-core CPU is realized.

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