BIOS flash updating method and related device

Abstract

The invention discloses a BIOS flash updating method and a related device, and relates to the field of computers.The BIOS flash updating device comprises a complex programmable logic device CPLD, a first selective switch, a second selective switch and an external device access end, the first selective switch is connected with the CPLD, the CPLD is connected with the second selective switch, the second selective switch is connected with the BIOS flash, when a CPU is abnormal due to BIOS abnormity, the external device access end is connected with the external device access end, and the external device access end is connected with the external device access end. The CPLD detects whether a power supply signal is accessed to the access end of the external equipment or not; if yes, the first selective switch is controlled to connect the external equipment with the first selective switch; and receiving BIOS flash update data of the external equipment, sending the BIOS flash update data to the BIOS flash, controlling the second option switch to be connected, and updating the BIOS flash through the BIOS flash update data. The problem that the BIOS flash is difficult to update when the CPU is abnormal is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a BIOS flash updating method and related device. BACKGROUND

[0002] BIOS (Basic Input Output System) can refer to: the program in the read-only memory chip on the motherboard. When the computer is started, BIOS can be started first, checks whether the CPU, memory, hard disk, etc. are normal, finds and guides the start of the computer operating system. BIOS Flash updating can refer to: updating the firmware program of the BIOS chip on the motherboard to realize functions such as old version bug fixing and performance optimization.

[0003] When the CPU is normally running, BIOS Flash updating can be realized through the SFC (System File Checker) interface of the CPU. Since BIOS abnormality can cause CPU abnormality, when BIOS abnormality occurs, BIOS Flash cannot be updated through the SFC interface of the CPU to solve the problem of BIOS abnormality. SUMMARY

[0004] In view of the above problems, the present application provides a BIOS flash updating method and related device to update BIOS Flash when BIOS abnormality occurs. The specific scheme is as follows:

[0005] The first aspect of the present application provides a BIOS flash updating method applied to a BIOS flash updating device, the updating device comprising a complex programmable logic device (CPLD), a first selection switch, a second selection switch and an external device access end, the first selection switch being connected to the CPLD, an output interface of the CPLD being connected to an input end of the second selection switch, an output end of the second selection switch being connected to the BIOS flash, and the BIOS flash updating method comprising the following steps:

[0006] When the CPU works abnormally or is not started due to BIOS abnormality, the CPLD detects whether the external device access end has a power signal access through a detection line;

[0007] If the CPLD detects that the external device access end has a power signal access through the detection line, it is determined that the external device access end has connected an external device, and the first selection switch is controlled to connect the external device with the CPLD;

[0008] The CPLD receives the BIOS flash update data sent by the external device, sends the BIOS flash update data to the BIOS flash through an output interface, and controls the second switch to automatically connect.

[0009] In a possible implementation, a serial flash controller (SFC) interface of the CPU is connected with an input end of the second switch, and the BIOS flash updating method further includes:

[0010] When the BIOS flash updating is completed, the CPLD controls the second switch to automatically connect the SFC interface of the CPU with the BIOS flash.

[0011] The CPU loads the updated BIOS flash through the SFC interface, and the CPU enters a normal operation state.

[0012] In a possible implementation, the CPU is connected with the first switch, and the BIOS flash updating method further includes:

[0013] When the CPU returns to the normal operation state, the CPLD controls the first switch to connect the external device access end with the CPU.

[0014] In a possible implementation, the external device is connected with an input interface of the CPLD through a universal serial bus (USB) interface, and an output port, to which the CPLD is connected with the input end of the second switch, is a serial peripheral interface (SPI) interface.

[0015] The CPLD receives the BIOS flash update data sent by the external device, sends the BIOS flash update data to the BIOS flash through an output interface, and controls the second switch to automatically connect.

[0016] The CPLD receives the BIOS flash update data in a USB data format sent by the external device through the USB interface.

[0017] The CPLD converts the BIOS flash update data in the USB data format into BIOS flash update data in an SPI data format.

[0018] The CPLD sends the BIOS flash update data in the SPI data format to the BIOS flash through the SPI interface.

[0019] The second aspect of the application provides an updating device for BIOS flash, the updating device comprising a complex programmable logic device (CPLD), a first switch, a second switch and an external device access end, the first switch being connected to the CPLD, an output interface of the CPLD being connected to an input end of the second switch, an output end of the second switch being connected to the BIOS flash,

[0020] The CPLD is used for detecting whether the external device access end has a power signal access through a detection line when the CPU works abnormally or is not started due to BIOS abnormality, determining that the external device access end has connected an external device if the external device access end is detected to have the power signal access from the detection line, and controlling the first switch to connect the external device with the CPLD.

[0021] The CPLD is also used for receiving BIOS flash updating data sent by the external device, sending the BIOS flash updating data to the BIOS flash through an output interface, and controlling the second switch to be automatically connected, so that the BIOS flash is updated through the BIOS flash updating data.

[0022] In a possible implementation, a serial flash controller (SFC) interface of the CPU is connected to an input end of the second switch.

[0023] The CPLD is also used for controlling the second switch to automatically connect the SFC interface of the CPU with the BIOS flash after the BIOS flash updating is completed, the CPU loading the updated BIOS flash through the SFC interface, and the CPU entering a normal operation state.

[0024] In a possible implementation, the CPU has a connection with the first switch.

[0025] The CPLD is also used for controlling the first switch to connect the external device access end with the CPU when the CPU recovers to the normal operation state.

[0026] In a possible implementation, the external device is connected with an input interface of the CPLD through a universal serial bus (USB) interface, and an output port of the CPLD connected with the input end of the second switch is a serial peripheral interface (SPI) interface.

[0027] The CPLD receives the BIOS flash updating data sent by the external device, and sends the BIOS flash updating data to the BIOS flash through an output interface, and the specific configuration is that:

[0028] The CPLD receives the BIOS flash update data in the USB data format sent by the external device through the USB interface, converts the BIOS flash update data in the USB data format into BIOS flash update data in the SPI data format, and sends the BIOS flash update data in the SPI data format to the BIOS flash through the SPI interface.

[0029] The third aspect of the present application provides an electronic device, comprising at least one processor and a memory connected to the processor, wherein:

[0030] The memory is configured to store a computer program;

[0031] The processor is configured to execute the computer program, so that the electronic device can implement the BIOS flash update method of the first aspect or any implementation manner of the first aspect.

[0032] The fourth aspect of the present application provides a computer program product comprising computer readable instructions, which, when executed on an electronic device, cause the electronic device to implement the BIOS flash update method of the first aspect or any implementation manner of the first aspect.

[0033] By means of the above technical solution, the present application provides a BIOS flash update method and related device, which are applied to a BIOS flash update device. The update device can comprise a complex programmable logic device (CPLD), a first selection switch, a second selection switch, and an external device access end. The first selection switch is connected to the CPLD, the output interface of the CPLD is connected to the input end of the second selection switch, and the output end of the second selection switch is connected to the BIOS flash. When the CPU works abnormally or is not started due to BIOS abnormality, the CPLD detects whether the external device access end has a power signal access through a detection line. If the CPLD detects that the external device access end has a power signal access through the detection line, it is determined that the external device access end has been connected to the external device, and the first selection switch is controlled to connect the external device to the CPLD. The CPLD receives the BIOS flash update data sent by the external device, sends the BIOS flash update data to the BIOS flash through the output interface, and controls the second selection switch to be automatically connected, so as to update the BIOS flash through the BIOS flash update data. This method can update the BIOS flash through the CPLD and the external device without the participation of the CPU, effectively preventing the problem that the BIOS flash is difficult to update and the BIOS abnormality cannot be solved when the CPU works abnormally or is not started due to BIOS abnormality. Attached Figure Description

[0034] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0035] Figure 1 A connection diagram of a BIOS flash update device provided in an embodiment of this application;

[0036] Figure 2 A flowchart illustrating a BIOS flash update method provided in this application embodiment;

[0037] Figure 3 This application provides a schematic diagram of a connection during a BIOS flash update.

[0038] Figure 4 This is another connection diagram for BIOS flash update provided in an embodiment of this application;

[0039] Figure 5 This application provides a hardware structure block diagram of an electronic device. Detailed Implementation

[0040] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is for explaining specific embodiments only and is not intended to limit the scope of this application.

[0041] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0042] The terms "first," "second," etc., used in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units, but may include other units not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0043] To address the aforementioned problems, this application provides a method for updating BIOS flash, which can be applied to... Figure 1 The illustrated device is a BIOS flash update device, such as... Figure 1 As shown, the update device may include a Complex Programmable Logic Device (CPLD), a first selector switch, a second selector switch, and an external device access terminal. One end of the first selector switch is connected to the CPLD, and the other end is connected to the external device access terminal. An additional detection line connects the CPLD and the external device access terminal. The output interface of the CPLD is connected to the input terminal of the second selector switch, and the output terminal of the second selector switch is connected to the BIOS flash. Specifically, one end of the first selector switch is connected to the external device access terminal by default. The other end of the first selector switch can be connected to the CPU's USB interface (default connection) or switched to the CPLD's USB interface, switching when the CPU malfunctions. The input terminal of the second selector switch is connected to the CPLD's SPI interface, the other input terminal is connected to the CPU's SFC interface, and the output terminal of the second selector switch is connected to the BIOS flash.

[0044] USB (Universal Serial Bus) can refer to a commonly used interface standard that enables data transmission, power supply, and peripheral expansion. SPI (Serial Peripheral Interface) can refer to a high-speed synchronous serial communication protocol used for short-range communication between low-level hardware such as microcontrollers and memory chips. SFC (System File Checker) can refer to a low-level file integrity verification and automatic repair tool that can repair low-level system files.

[0045] A CPLD (Complex Programmable Logic Device) can refer to a semiconductor chip whose logic functions can be customized by the user. Its core function is to implement arbitrary digital logic circuits through software programming.

[0046] The first switch can be a switch such as a MOS transistor or a triode that controls the connection object of the external device access end by selecting or switching a signal path. In this embodiment, the first switch can be a SW (Switch) switch that can be turned on or off by a physical operation or a simple hardware signal to connect or disconnect one or more signal paths.

[0047] In this embodiment, the first switch can be used to control the connection of the external device access end to the CPU module of the mainboard (default connection state) or the connection of the external device access end to the CPLD, and the second switch can be used to control the connection of the BIOS flash to the CPU module of the mainboard or the connection of the BIOS flash to the CPLD. When the CPU is abnormally running, the first switch connects the external device access end to the CPLD, and after the CPU is normally running, the first switch connects the external device access end to the CPU by default. Therefore, the first switch connects one path by default each time and does not need to frequently change the path, and a switch that can be controlled by a simple hardware signal can be selected. The second switch needs to automatically select one path from the outputs of the CPU and the CPLD to connect to the BIOS flash. Therefore, the second switch needs to have the function of automatically selecting a connection path, and a flexible programmable switch can be selected to flexibly switch the connection path. Of course, in another optional embodiment, the first switch can also be a switch that flexibly switches the connection path.

[0048] The external device access end can be a port for accessing an external device, which can be a built-in external port of the mainboard (the USB interface of the CPU of the mainboard can be reused) or an independent external port. The external device can be a device with an interface corresponding to the external device access end, such as another computer, a mobile phone, or a tablet. In specific applications, corresponding software needs to be developed and installed for the external device. When the internal CPU is abnormal or not started, the external device is used as a host to update the BIOS flash. When the CPU is normally running, the external device connected to the external device access end communicates with the CPU through the first switch to perform normal USB communication. When the CPU is abnormally running, the external device connected to the external device access end communicates with the CPLD through the first switch to update the BIOS flash.

[0049] The BIOS flash updating method of the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0050] Referring to Figure 2 , Figure 2 A flowchart of the BIOS flash updating method provided by the embodiment of the present application is shown in FIG. 1. The BIOS flash updating method provided by the embodiment of the present application can include steps S10 to S12, which will be described in detail below. Figure 2

[0051] S10, when the CPU works abnormally or is not started due to BIOS abnormality, the CPLD detects whether there is a power signal input into the external device access end through a detection line;

[0052] S11, if the CPLD detects that there is a power signal input into the external device access end through the detection line, it is determined that the external device access end has been connected to an external device, and the first switch is controlled to connect the external device and the CPLD;

[0053] S12, the CPLD receives the BIOS flash updating data sent by the external device, sends the BIOS flash updating data to the BIOS flash through an output interface, and controls the second switch to be automatically connected, so as to update the BIOS flash through the BIOS flash updating data.

[0054] As shown in FIG. 2, when the CPU normally runs, the BIOS flash can be updated in real time through the SFC interface, and after the BIOS flash is updated, the new BIOS flash is loaded through the SFC interface again. The CPU can also update the BIOS flash through the CPLD of the embodiment (another optional way, represented by a dashed line in FIG. 3), send the BIOS flash updating data to the CPLD, and send the BIOS flash updating data to the BIOS flash by the CPLD, so as to update the BIOS flash. Wherein, the first switch is in the default state (connecting the CPU and the external device access end), and the second switch selects the connection object (CPU or CPLD) of the BIOS flash according to the control signal. Figure 3 Figure 3 When the CPU runs abnormally due to BIOS, the CPU cannot solve the problem of BIOS abnormality by updating the BIOS flash. Therefore, as shown in FIG. 4, when the CPU runs abnormally due to BIOS, the first switch is controlled to connect the external device and the CPLD, and the second switch is controlled to connect the CPLD and the BIOS flash, so as to update the BIOS flash through the CPLD.

[0055] When the CPU runs abnormally due to BIOS, the CPU cannot solve the problem of BIOS abnormality by updating the BIOS flash. Therefore, as shown in FIG. 4, when the CPU runs abnormally due to BIOS, the first switch is controlled to connect the external device and the CPLD, and the second switch is controlled to connect the CPLD and the BIOS flash, so as to update the BIOS flash through the CPLD. Figure 4 ​​As shown in the connection diagram, the embodiment can update the BIOS flash through the external device and the CPLD to recover the abnormal BIOS so that the CPU can run normally. Among them, the first switch changes the state to connect the CPLD and the external device access end, and the second switch connects the CPLD and the BIOS flash.

[0056] The detection circuit is used for the CPLD to detect whether the external device access end is connected to the external device, such as Figure 4 As shown, it can be an additional connection line between the external device access end and the CPLD. If the CPLD detects that the external device access end has a power signal access from the detection line, it is confirmed that the external device has been connected. Among them, in this embodiment, the power signal is generally a 5V power signal.

[0057] When the external device has been connected, the CPLD needs to obtain the BIOS flash update data from the external device in order to update the BIOS flash. Since the first switch is connected to the external device access end and the CPU by default, as shown in Figure 4 The CPLD sends a simple hardware signal to the first switch to control the first switch to switch and connect the external device access end to itself. The first switch switches from the default connection (dashed line) to the CPLD connection (solid line). Specifically, the external device access end is generally a USB interface, so the external device can connect to the CPLD USB interface through the USB interface and send the BIOS flash update data in USB data format to the CPLD through the USB interface.

[0058] After the CPLD receives the BIOS flash update data in USB data format sent by the external device through the USB interface, since the USB protocol used by the USB interface is incompatible with the SPI communication protocol and hardware interface of the SPI flash chip that stores the BIOS, the CPLD in this embodiment can convert the BIOS flash update data in USB data format to BIOS flash update data in SPI data format that conforms to the BIOS.

[0059] After the CPLD converts the data format of the BIOS flash update data, it can send a control signal to the second switch, and the second switch selects to connect the CPLD and the BIOS flash according to the control signal, such as Figure 4As shown, the CPLD and the second switch are connected by a solid line, while the CPU and the second switch are connected by a dashed line. The output port of the CPLD connected to the input of the second switch is an SPI interface. The CPLD sends a control signal to the second switch through the SPI interface, controls the second switch to switch, connects the SPI interface of the CPLD to the BIOS flash, and then sends BIOS flash update data in SPI data format to the BIOS flash through the SPI interface. Of course, the control signal of the second switch can also be sent together with the BIOS flash update data in SPI data format from the SPI interface of the CPLD.

[0060] Of course, in another alternative embodiment, the CPLD can control the second switch to connect itself to the BIOS flash when controlling the first switch to connect itself to the external device access end.

[0061] After the BIOS flash obtains the BIOS flash update data in SPI data format, the BIOS flash can update by relying on the hardware function of the BIOS. Specifically, the BIOS flash can read the BIOS flash update data in SPI data format according to the independent auxiliary control circuit on the motherboard, and write it into the BIOS flash chip to update the BIOS flash.

[0062] When the BIOS flash update is completed, since the input of the second switch of the CPLD is also connected to the SFC interface of the CPU, the CPLD can control the second switch to restore the default state, control the second switch to automatically connect the SFC interface of the CPU to the BIOS flash, and the CPU can load the updated BIOS flash through the SFC interface. The CPU enters a normal operating state or a normal start state.

[0063] When the CPU returns to normal operation, the CPLD can also control the first switch to restore the default state and connect the external device access end to the CPU. When the external device access end is connected to an external device, the first switch can connect the external device to the CPU. Specifically, the external device can be connected to the external device access end through a USB interface, the external device access end is connected to one end of the first switch, and the other end of the first switch is connected to the USB interface of the CPU.

[0064] The embodiment of the application provides a BIOS flash updating method, which is applied to a BIOS flash updating device.

[0065] The BIOS flash updating device can comprise a complex programmable logic device (CPLD), a first switch, a second switch and an external device access end, the first switch is connected to the CPLD, an output interface of the CPLD is connected to an input end of the second switch, and an output end of the second switch is connected to the BIOS flash.

[0066] The CPLD is configured to detect, when the CPU works abnormally or is not started due to BIOS abnormality, whether the external device access end has a power signal access through a detection circuit, and if the CPLD detects that the external device access end has the power signal access through the detection circuit, it is determined that the external device access end has connected the external device, and the first switch is controlled to connect the external device and the CPLD.

[0067] The CPLD is further configured to receive BIOS flash updating data sent by the external device, send the BIOS flash updating data to the BIOS flash through the output interface, control the second switch to be automatically connected, and update the BIOS flash through the BIOS flash updating data.

[0068] In a possible implementation, a serial flash controller SFC interface of the CPU is connected with an input end of the second switch;

[0069] The CPLD is further configured to control the second switch to connect the SFC interface of the CPU with the BIOS flash automatically after the BIOS flash update is completed, and the CPU loads the updated BIOS flash through the SFC interface, and the CPU enters a normal operation state.

[0070] In a possible implementation, the CPU is connected with the first switch;

[0071] The CPLD is further configured to control the first switch to connect the external device connection end with the CPU when the CPU returns to the normal operation state.

[0072] In a possible implementation, the external device is connected with an input interface of the CPLD through a universal serial bus USB interface, and an output port of the CPLD connected with the input end of the second switch is a serial peripheral interface SPI interface.

[0073] The CPLD receives the BIOS flash update data sent by the external device, and sends the BIOS flash update data to the BIOS flash through an output interface, and the specific configuration is as follows:

[0074] The CPLD receives the BIOS flash update data in a USB data format sent by the external device through the USB interface, converts the BIOS flash update data in the USB data format into BIOS flash update data in an SPI data format, and sends the BIOS flash update data in the SPI data format to the BIOS flash through the SPI interface.

[0075] The embodiment of the present application further provides an electronic device. Figure 5 As shown in the figure, a structure diagram suitable for implementing the electronic device in the embodiment of the present application is shown. The electronic device in the embodiment of the present application can include but is not limited to fixed terminals such as mobile phones, notebook computers, PDAs (personal digital assistants), PADs (tablet computers), desktop computers and the like. Figure 5 The electronic device shown in the figure is only an example, and should not bring any limitation to the functions and use range of the embodiment of the present application.

[0076] As Figure 5As shown, the electronic device can include a processing device (e.g., a central processor, a graphics processor, etc.) 501 that can perform various appropriate actions and processes according to programs stored in a read only memory (ROM) 502 or loaded into a random access memory (RAM) 503 from a storage device 508. In a state where the electronic device is powered on, various programs and data required for operation of the electronic device are also stored in the RAM 503. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output interface (I / O interface) 505 is also connected to the bus 504.

[0077] Generally, the following devices can be connected to the I / O interface 505: input devices 506 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 508 including, for example, a memory card, a hard disk, etc.; and communication devices 509. The communication devices 509 can allow the electronic device to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 An electronic device having various devices is shown, but it should be understood that all of the shown devices are not required to be implemented or possessed. More or fewer devices can be alternatively implemented or possessed.

[0078] The embodiments of the present application also provide a computer program product comprising computer readable instructions, which, when executed on an electronic device, cause the electronic device to implement any of the BIOS flash updating methods provided by the embodiments of the present application.

[0079] The embodiments of the present application also provide a computer readable storage medium carrying one or more computer programs, which, when executed by an electronic device, can cause the electronic device to implement any of the BIOS flash updating methods provided by the embodiments of the present application.

[0080] In addition, it should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments. In addition, the connection relationship between the modules in the device embodiments provided by the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0082] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0083] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0084] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0085] It is understood that before using the technical solutions disclosed in the various embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0086] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for updating a BIOS flash, characterized in that, The application discloses an updating device for BIOS flash, and the updating device comprises a complex programmable logic device (CPLD), a first switch, a second switch and an external device access end, the first switch is connected with the CPLD, the output interface of the CPLD is connected with the input end of the second switch, the output end of the second switch is connected with the BIOS flash, and the updating method of the BIOS flash comprises the following steps: When the CPU works abnormally or is not started due to BIOS abnormality, the CPLD detects whether the external device access end has a power signal access through a detection line; If the CPLD detects that the external device access end has a power signal access through the detection line, it is determined that the external device access end has been connected with an external device, the first switch is controlled to connect the external device with the CPLD; The CPLD receives BIOS flash updating data sent by the external device, sends the BIOS flash updating data to the BIOS flash through an output interface, controls the second switch to be automatically connected, and updates the BIOS flash through the BIOS flash updating data.

2. The method of claim 1, wherein the BIOS flash is updated by: The SFC interface of the CPU is connected with the input end of the second switch, and the updating method of the BIOS flash further comprises the following steps: After the updating of the BIOS flash is completed, the CPLD controls the second switch to automatically connect the SFC interface of the CPU with the BIOS flash; The CPU loads the updated BIOS flash through the SFC interface, and the CPU enters a normal operation state.

3. The method of claim 1, wherein the BIOS flash is updated by: The CPU is connected with the first switch, and the updating method of the BIOS flash further comprises the following steps: When the CPU returns to the normal operation state, the CPLD controls the first switch to connect the external device access end with the CPU.

4. The method of claim 1, wherein the BIOS flash update is performed by a BIOS update program. The external device is connected with the input interface of the CPLD through a universal serial bus (USB) interface, the output port of the CPLD connected with the input end of the second switch is an SPI interface; The CPLD receives BIOS flash updating data in a USB data format sent by the external device through the USB interface, sends the BIOS flash updating data to the BIOS flash through an output interface, and comprises the following steps: The CPLD receives BIOS flash updating data in a USB data format sent by the external device through the USB interface; The CPLD converts the BIOS flash updating data in the USB data format into BIOS flash updating data in an SPI data format; The CPLD sends the BIOS flash updating data in the SPI data format to the BIOS flash through the SPI interface.

5. An apparatus for updating a BIOS flash, the apparatus comprising: a BIOS flash memory; a BIOS update module; and a BIOS update module interface. The updating device comprises a complex programmable logic device (CPLD), a first switch, a second switch and an external device access end, the first switch is connected to the CPLD, an output interface of the CPLD is connected to an input end of the second switch, an output end of the second switch is connected to a BIOS flash, The CPLD is used for detecting whether the external device access end has a power signal access through a detection line when the CPU works abnormally or is not started due to BIOS abnormality, determining that the external device access end has connected an external device if the external device access end is detected to have the power signal access from the detection line, and controlling the first switch to connect the external device with the CPLD. The CPLD is also used for receiving BIOS flash updating data sent by the external device, sending the BIOS flash updating data to the BIOS flash through an output interface, and controlling the second switch to be automatically connected, so that the BIOS flash is updated by the BIOS flash updating data.

6. The apparatus for updating BIOS flash according to claim 5, wherein, A serial flash controller (SFC) interface of the CPU is connected to an input end of the second switch; The CPLD is also used for controlling the second switch to automatically connect the SFC interface of the CPU with the BIOS flash after the BIOS flash updating is completed, the CPU loads the updated BIOS flash through the SFC interface, and the CPU enters a normal operation state.

7. The apparatus for updating BIOS flash according to claim 5, wherein, The CPU is connected to the first switch; The CPLD is also used for controlling the first switch to connect the external device access end with the CPU when the CPU recovers to the normal operation state.

8. The apparatus for updating BIOS flash according to claim 5, wherein, The external device is connected to an input interface of the CPLD through a universal serial bus (USB) interface, an output port of the CPLD connected to the input end of the second switch is a serial peripheral interface (SPI) interface; The CPLD receives BIOS flash updating data sent by the external device, and sends the BIOS flash updating data to the BIOS flash through an output interface, and the specific configuration is that: The CPLD receives USB data format BIOS flash updating data sent by the external device through the USB interface, converts the USB data format BIOS flash updating data into SPI data format BIOS flash updating data, and sends the SPI data format BIOS flash updating data to the BIOS flash through the SPI interface.

9. An electronic device, comprising: The electronic device comprises at least one processor and a memory connected to the processor, wherein: The memory is used for storing a computer program; The processor is used for executing the computer program, so that the electronic device can implement the BIOS flash updating method according to any one of claims 1 to 4.

10. A computer program product, characterised in that, The computer readable instructions, when run on an electronic device, cause the electronic device to implement the BIOS flash updating method as claimed in any one of claims 1 to 4.

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