Memory access management method and device and electronic equipment
By statistically analyzing and progressively increasing memory access frequency, the problem of system instability under high load conditions in on-chip storage units was solved, achieving smooth transition and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-28
- Publication Date
- 2026-03-10
AI Technical Summary
In high-performance computing and large-scale data processing systems, a sudden increase in memory access load on on-chip storage units can lead to system instability.
By counting the total number of memory blocks that need to be accessed in the current clock cycle and calculating the access increment based on the average value of historical clock cycles, a warm-up process is executed when the access increment exceeds a preset threshold, gradually increasing the access intensity so that the on-chip storage unit can smoothly transition to a high-load state.
This avoids bottlenecks or jitter caused by sudden surges in access, thus maintaining system stability.
Smart Images
Figure CN121636367A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of on-chip memory, and particularly to a memory access management method and device and electronic equipment. BACKGROUND
[0002] With the increasing progress of integrated circuit technology, on-chip memory units such as SRAM, DRAM, etc. are becoming more and more common in modern microprocessors and system chips (SoC). In high-performance computing and large-scale data processing systems, the memory access load demand of on-chip memory units often suddenly increases, causing system instability. SUMMARY
[0003] Therefore, the present application provides a memory access management method and device and electronic equipment to enable the on-chip memory unit to smoothly transition to a high load state and avoid bottlenecks or jitter caused by sudden large access, thereby maintaining stability.
[0004] Specifically, the present application is implemented by the following technical solutions:
[0005] The first aspect of the present application provides a memory access management method, which comprises:
[0006] According to the memory access requests or read-write requests received in the current clock cycle, the total number of memory blocks that need to be accessed in the current clock cycle is counted;
[0007] According to the total number and the average value of the number of memory blocks that need to be accessed in a preset number of historical clock cycles, the access increment corresponding to the current clock cycle is determined;
[0008] When the access increment is greater than a preset threshold, a warm-up process is performed; wherein the warm-up process comprises: taking the average value as the initial value of the number of memory blocks that need to be accessed, gradually increasing the number of memory blocks that need to be accessed according to a preset incremental rule, until the number of memory blocks after the increase is greater than or equal to the total number, to gradually increase the access intensity, so that the on-chip memory unit completes the warm-up process and enters a stable state.
[0009] The second aspect of the present application provides a memory access management device, which comprises a counting module, a register group, a comparison unit and a controller; wherein,
[0010] The counting module is configured to count the total number of memory blocks that need to be accessed in the current clock cycle according to the memory access requests received in the current clock cycle;
[0011] The register group is configured to store the number of memory blocks that need to be accessed in the historical clock cycles.
[0012] the comparison unit is configured to determine an access increment corresponding to the current clock cycle according to the total number and an average value of the number of memory blocks accessed in a preset number of historical clock cycles;
[0013] the controller is configured to control the state machine to enter a warm-up state when the access increment is greater than the preset threshold; the controller executes a warm-up process in the warm-up state; the warm-up process includes taking the average value as an initial value of the number of memory blocks to be accessed, gradually increasing the number of memory blocks to be accessed according to a preset increment rule, and increasing the number of memory blocks to be accessed until the increased number of memory blocks to be accessed is greater than or equal to the total number, so as to gradually increase the access intensity and make the on-chip storage unit complete a warm-up process and enter a stable state.
[0014] The third aspect of the present application provides an electronic device including any memory access management device provided by the second aspect of the present application.
[0015] The memory access management method, device and electronic device provided by the present application can determine an access increment corresponding to the current clock cycle according to the total number of memory blocks to be accessed in the current clock cycle and an average value of the number of memory blocks accessed in a preset number of historical clock cycles, so that the warm-up process is entered when the access increment is greater than a preset threshold, and the number of memory blocks to be accessed is gradually increased in the warm-up process instead of being suddenly and massively accessed, so that the on-chip storage unit can more smoothly transit to a high load state, and thus the bottleneck or jitter caused by sudden and massive access can be avoided and stability can be maintained. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 A flowchart of the memory access management method provided by the first embodiment of the present application;
[0017] Figure 2 A flowchart of the memory access management method provided by the second embodiment of the present application;
[0018] Figure 3 A flowchart of the memory access management method provided by the third embodiment of the present application;
[0019] Figure 4 A structural schematic diagram of the memory access management device provided by the first embodiment of the present application;
[0020] Figure 5 A state transition schematic diagram of the state machine shown in an exemplary embodiment of the present application;
[0021] Figure 6A schematic diagram of a memory access management device according to an example embodiment of the present application;
[0022] Figure 7 A schematic diagram of a memory access management device according to an example embodiment of the present application;
[0023] Figure 8 A schematic diagram of a merging unit according to an example embodiment of the present application;
[0024] Figure 9 A schematic diagram of an electronic device according to an example embodiment of the present application. DETAILED DESCRIPTION
[0025] The example embodiments will be described in detail herein with reference to the attached drawings. In the following description, unless otherwise indicated, like numbers refer to like elements throughout the description and drawings. The following description is not intended to represent all embodiments in accordance with the present application.
[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0027] It should be understood that although the terms first, second, third, etc. can be used herein to describe various information, these terms are not intended to denote a particular order or hierarchy. These terms are used only to distinguish one from another. For example, a first information can be termed a second information, and similarly, a second information can be termed a first information without departing from the scope of the present application. As used herein, the term "if' can be construed to mean "when" or "in response to determining" depending on the context.
[0028] The following specific embodiments are given to provide a detailed description of the technical solutions of the present application.
[0029] Figure 1 A flow chart of a memory access management method according to an example embodiment of the present application. Please refer to Figure 1 The method provided by the present embodiment can include:
[0030] S101, according to the memory access request or read-write request received in the current clock cycle, statistics the total number of memory blocks that need to be accessed in the current clock cycle.
[0031] The memory access management method provided in the application is applied to a memory access management device in an electronic device provided with an on-chip storage unit. The on-chip storage unit refers to a storage unit integrated on a chip. Further, the memory access management method provided in the application is used to manage the access behavior of other functional modules in the electronic device to the memory blocks in the on-chip storage unit.
[0032] It should be noted that the on-chip storage unit includes a plurality of memory blocks. In addition, the number and size of the memory blocks included in the on-chip storage unit are set according to actual needs, and in the embodiment, they are not limited.
[0033] Further, after the on-chip storage unit is divided into memory blocks of a fixed size, the electronic device records the mapping relationship between the address range and the memory block identifier. For example, in a possible implementation manner, the on-chip storage unit is divided into 64 memory blocks, each memory block has a size of 16 bits, the address range of the first memory block is 0-16 bits, the address range of the second memory block is 16-32 bits, and so on.
[0034] Specifically, the memory access request or the read-write request comes from other functional modules in the electronic device. It should be noted that the memory access request and the read-write request are two different types of requests. The memory access request is a request for indicating the access behavior to a specific memory block, and the memory access request carries a memory access bitmap, which is used to mark which memory blocks need to be accessed. The corresponding processing manner is to parse the memory access bitmap and determine whether to access the corresponding memory block according to the value of each bit. Further, the read-write request is a request for executing a specific read operation or write operation, which carries information such as operation type, start address and data length, and the corresponding processing manner is to determine the specific memory block range according to the start address and the data length, and then execute the read operation or the write operation.
[0035] It should be noted that the memory access bitmap includes a series of bits, each bit corresponds to a memory block in the on-chip storage unit, and the value of each bit indicates whether the corresponding memory block needs to be accessed (the value of each bit is 0 or 1, 0 indicates that the corresponding memory block does not need to be accessed, and 1 indicates that the corresponding memory block needs to be accessed). For example, in a possible implementation manner, the on-chip storage unit includes four memory blocks, and the memory access bitmap carried in a certain memory access request is 1010, which indicates that the first memory block and the third memory block need to be accessed.
[0036] Further, when the received request is a read-write request, for each read-write request, the read-write request needs to be converted into a memory access request first, and then according to the memory access request, the total number of memory blocks that need to be accessed in the current clock cycle is counted. When the received request is a memory access request, the total number of memory blocks that need to be accessed in the current clock cycle is counted directly based on the memory access request.
[0037] Optionally, in a possible implementation, the step of converting the read-write request into the memory access request can include:
[0038] (1) determining an address range to be accessed according to a start address and a data length in the read-write request.
[0039] It should be noted that the start address and the data length in the read-write request from each functional module are set by each functional module according to actual needs, and in this embodiment, they are not limited.
[0040] In a specific implementation, when the address range to be accessed is determined, the end address can be determined based on the start address and the data length first, and then a continuous region from the start address to the end address is determined as the address range to be accessed. The end address can be determined according to the following formula:
[0041] End address = start address + data length - 1
[0042] In combination with the foregoing examples, for example, in an embodiment, the start address of the read-write request is 0 bit, and the data length is 33 bits, so the address range accessed by the read-write request is 0-32 bits; in another embodiment, the start address of the read-write request is 2 bits, and the data length is 33 bits, so the address range accessed by the read-write request is 2-34 bits.
[0043] (2) determining a memory block to be accessed according to the address range and a mapping relationship between the address range and a memory block identifier recorded in advance.
[0044] In a specific implementation, the mapping relationship containing the address range can be found from the mapping relationship between the address range and the memory block identifier, and then the memory block indicated by the memory block identifier recorded in the found mapping relationship is determined as the memory block to be accessed.
[0045] Referring to the above example, the range of memory block 1 is 0-16 bits, the range of memory block 2 is 16-32 bits, the range of memory block 3 is 32-48 bits, and so on, and the range of memory block 10 is 144-160 bits. Further, in an embodiment, when the address range accessed by a read / write request is 0-32 bits, the memory blocks accessed by the read / write request are memory block 1 and memory block 2; in another embodiment, when the address range accessed by a read / write request is 2-34 bits, the memory blocks accessed by the read / write request are memory block 1, memory block 2, and memory block 3.
[0046] (3) Generating a memory access request according to the memory block to be accessed; wherein the memory access request carries a memory access bitmap, which is used to mark which memory blocks in the on-chip storage unit need to be accessed.
[0047] In specific implementation, the corresponding memory access bitmap can be generated according to the memory block to be accessed, and then the memory access bitmap can be encapsulated to generate the memory access request. In specific implementation, when generating the corresponding memory access bitmap, a corresponding binary bitmap can be created based on the number of memory blocks included in the on-chip storage unit, each bit of the binary bitmap identifying the state of a memory block. Further, for each memory block in the on-chip storage unit, if the memory block is the memory block to be accessed, the value of the corresponding position is set to 1, otherwise the value of the corresponding position is set to 0, so that the memory access bitmap can be obtained.
[0048] For example, in an embodiment, assuming that the on-chip storage unit is divided into 8 memory blocks (memory block 0 to memory block 7), the memory blocks to be accessed are memory block 1, memory block 3, and memory block 5, at this time, the generated memory access bitmap is 01010100, and the generated memory access request can be: Request ID: 1234 Timestamp: 2024-07-24 15:00:00 Memory access bitmap: 01010100.
[0049] It should be noted that when the total number of memory blocks to be accessed in the current clock cycle is counted based on the memory access request, the memory access bitmap can be extracted from each memory access request; then the extracted memory access bitmap is parsed, each bit is mapped to a specific memory block, and the memory blocks to be accessed by the memory access request are determined; finally, the union of the memory blocks to be accessed by all memory access requests is determined, and the number of memory blocks included in the union is determined as the total number of memory blocks to be accessed in the current clock cycle (when different memory access requests need to access the same memory block, it is counted once).
[0050] With the above description, for example, in a possible implementation, three memory access requests are received in a current clock cycle, after analyzing the memory access bitmaps carried by the memory access requests, it is determined that memory access request 1 requests to access memory block 2-10, memory access request 2 requests to access memory block 4-11, and memory access request 3 requests to access memory block 4-15. After taking the union set, it is determined that the memory blocks to be accessed are memory blocks 2-15. Further, it is determined that the total number of memory blocks to be accessed in the current clock cycle is 14.
[0051] S102, determining an access increment corresponding to the current clock cycle according to the total number and an average value of the number of memory blocks to be accessed in a preset number of historical clock cycles.
[0052] Specifically, the preset number is set according to actual needs, which is not limited in the embodiment. For example, in a possible implementation, the preset number is 5, that is, in this step, the access increment is determined based on the average value of the number of memory blocks to be accessed in 5 historical clock cycles.
[0053] It should be noted that the access increment corresponding to the current clock cycle is equal to the difference between the total number of memory blocks to be accessed in the current clock cycle and the average value of the number of memory blocks to be accessed in the preset number of historical clock cycles.
[0054] For example, in a possible implementation, the average value of the number of memory blocks to be accessed in the preset number of historical clock cycles is 4, and the total number of memory blocks to be accessed in the current clock cycle is 20. At this time, the access increment corresponding to the current clock cycle is 16.
[0055] S103, when the access increment is greater than a preset threshold, performing a warm-up process; wherein the warm-up process comprises: taking the average value as an initial value of the number of memory blocks to be accessed, gradually increasing the number of memory blocks to be accessed according to a preset increasing rule, until the number of memory blocks after the increase is greater than or equal to the total number, to gradually increase the access intensity, so that the on-chip storage unit completes the warm-up process and enters a stable state.
[0056] Specifically, the specific value of the preset threshold is set according to actual needs, which is not limited in the embodiment. For example, in a possible implementation, the preset threshold is 5.
[0057] Further, the preset increment rule is set according to actual needs, and is not limited in the embodiment. For example, in a possible implementation, the preset increment rule is to increase the same number of memory blocks at each level. For example, in an embodiment, 2 memory blocks are added at each level; for another example, in another possible implementation, the preset increment rule is that the number of memory blocks added at the first level is a preset value, and the number of memory blocks added at the next level is 1 more than the number of memory blocks added at the previous level. For example, in an embodiment, 2 memory blocks are added at the first level, 3 memory blocks are added at the second level, and so on, until the number of memory blocks after addition is greater than or equal to the total number.
[0058] In combination with the above example, the initial value of the number of memory blocks to be accessed is 4, the preset increment rule is to increase 2 memory blocks at each level, after the first level is added, the number of memory blocks after addition is 6, after the second level is added, the number of memory blocks after addition is 8, and the number of memory blocks after addition is increased level by level until the number of memory blocks after addition is greater than or equal to the total number, and the warm-up process is completed.
[0059] It should be noted that the specific implementation process of the warm-up process can include: taking the average value as the number of memory blocks to be accessed, generating a memory read request, and sending the memory read request to the arbitrator for execution; increasing the number of memory blocks to be accessed according to the preset increment rule to obtain the number of memory blocks after addition; taking the number of memory blocks after addition as the number of memory blocks to be accessed, and executing the step of generating a memory read request again until the number of memory blocks after addition is greater than or equal to the total number, and the warm-up process is completed.
[0060] It should be noted that the memory read request carries a memory access bitmap, and in addition, the memory read request only pays attention to the number of memory blocks to be accessed, and does not pay attention to which memory block is accessed.
[0061] The method provided in the embodiment determines the access increment corresponding to the current clock cycle according to the total number of memory blocks to be accessed in the current clock cycle and the average value of the number of memory blocks to be accessed in the preset number of historical clock cycles, so that the warm-up process is entered when the access increment is greater than the preset threshold, and in the warm-up process, the number of memory blocks to be accessed is increased level by level instead of sudden mass access, so that the on-chip storage unit can be more smoothly transitioned to a high load state, and thus the bottleneck or jitter caused by sudden mass access is avoided, and stability is maintained.
[0062] Optionally, in a possible implementation, after the number of memory blocks to be accessed is increased each time, the method further includes:
[0063] Controlling to stay for a preset clock cycle.
[0064] The preset clock period is set according to actual needs, and is not limited in the embodiment. It can be understood that the preset clock period to be stayed is the same after the number of memory blocks to be accessed is increased each time. For example, in a possible implementation manner, the preset clock period is 1, that is, 1 clock period is needed to be stayed after the number of memory blocks to be accessed is increased each time.
[0065] The method provided in the embodiment can ensure that the on-chip storage unit has enough time to adapt to the new load after the number of memory blocks is increased each time, so as to smoothly transit to the high load state, effectively prevent the sudden fluctuation of the load, and ensure the stability.
[0066] Figure 2 The flowchart of the second embodiment of the memory access management method provided in the application is shown in FIG. 2. Figure 2 The method provided in the embodiment can include the following steps.
[0067] S201, merge the memory access requests to obtain a merged signal.
[0068] Specifically, the memory access requests can be merged by or operation. As introduced above, each memory access request carries a memory access bitmap, and in the specific implementation, for a plurality of memory access requests, a plurality of memory access bitmaps of the plurality of memory access requests can be merged to obtain a merged memory access bitmap, and then a merged signal (carrying the merged memory access bitmap) is obtained based on the merged memory access bitmap.
[0069] It should be noted that, as described above, it can be understood that the plurality of memory access bitmaps contain the same number of bits, and the number of bits is equal to the number of memory blocks contained in the on-chip storage unit, and each bit corresponds to a memory block in the on-chip storage unit. Further, when the plurality of memory access bitmaps are merged into a merged memory access bitmap, or operation can be performed on each bit to obtain an update value corresponding to the bit, and finally, after obtaining the update values corresponding to all bits, the merged memory access bitmap is obtained. When or operation is performed on each bit, if the value of the bit in any memory access request is 1, the update value corresponding to the bit obtained after or operation is 1, and if the value of the bit in all memory access requests is 0, the update value corresponding to the bit obtained after or operation is 0.
[0070] Referring to the previous example, in an embodiment, for example, assuming that the on-chip storage unit comprises 8 memory blocks, there are three memory access requests in the current clock cycle, the memory access bitmap of the memory access request 1 is 01010100, the memory access bitmap of the memory access request 2 is 11001011, and the memory access bitmap of the memory access request 3 is 01000101. After merging the three memory access bitmaps of the three memory access requests, the obtained merged memory access bitmap is 11011111.
[0071] S202, determining the total quantity according to the merging signal.
[0072] Referring to the previous introduction, the merging signal carries the merged memory access bitmap, and the value of each bit in the memory access bitmap indicates whether the corresponding memory block needs to be accessed. When the value is 1, it indicates that the corresponding memory block needs to be accessed. In this step, the number of 1s in the merged memory access bitmap can be counted, and then the counted number is determined as the total quantity.
[0073] In combination with the above example, for example, the merged memory access bitmap is 11011111, and there are 7 bits with a value of 1, indicating that the number of memory blocks that need to be accessed is 7, i.e., the total number of memory blocks that need to be accessed in the current clock cycle is 7 blocks.
[0074] S203, determining an access increment corresponding to the current clock cycle according to the total quantity and an average value of the number of memory blocks that need to be accessed in a preset number of historical clock cycles.
[0075] S204, judging whether the access increment is greater than a preset threshold, if yes, performing step S205, and if no, performing step S206.
[0076] Specifically, the specific implementation principles and implementation processes of steps S203 and S204 can be referred to the description in the previous embodiments, which will not be repeated here.
[0077] S205, performing a warm-up process.
[0078] Specifically, the warm-up process comprises: taking the average value as an initial value of the number of memory blocks that need to be accessed, gradually increasing the number of memory blocks that need to be accessed according to a preset increasing rule, until the number of memory blocks after the increase is greater than or equal to the total quantity, so as to gradually increase the access intensity, so that the on-chip storage unit completes the warm-up process and enters a stable state.
[0079] Referring to the foregoing description, for example, in an embodiment, the average value of the number of memory blocks required to be accessed in a preset number of historical clock cycles is 4, and the access increment corresponding to the current clock cycle is 16. At this time, the number of memory blocks required to be accessed can be increased step by step in a manner of 64’b1111->64’b11111->64’b111111->.... In addition, in order to further realize smooth transition of memory access, after the number of memory blocks required to be accessed is increased each time, the control stays for a preset clock cycle. For example, after 64’b1111 is issued, the next level 64’b11111 is entered after staying for a preset clock cycle.
[0080] S206, performing a standard memory access operation.
[0081] Specifically, when performing the standard memory access operation, the memory access management apparatus directly sends the memory access request or the read-write request received in the current clock cycle to the arbitrator for execution.
[0082] S207, after the warm-up process is completed, performing a standard memory access operation.
[0083] Specifically, for details about the content of performing the standard memory access operation, please refer to the foregoing description, which will not be repeated here.
[0084] The method provided in this embodiment can make the on-chip storage unit transition to a high-load state more smoothly by increasing the number of memory blocks required to be accessed step by step instead of suddenly accessing a large number of memory blocks when the access increment is greater than a preset threshold, which helps to avoid bottlenecks or jitter caused by sudden large access and maintain stability. In this way, the on-chip storage unit can quickly and safely reach a stable working state before performing the standard memory access operation, and then the standard memory access operation is performed only after the on-chip storage unit reaches the stable working state, which can ensure the stability of the standard memory access operation.
[0085] Figure 3 The flowchart of the memory access management method embodiment three provided in this application is shown in FIG. 3. Figure 3 The method provided in this embodiment can further include the following steps on the basis of the foregoing embodiments.
[0086] S301, in the warm-up process, determining first state information for indicating whether the warm-up process is completed and second state information for indicating a current stage of the warm-up process.
[0087] Specifically, the first status information indicates whether the on-chip storage unit has completed the preheating process and is ready for the standard memory access operation. The state of the first status information includes 1 or 0. When the state value of the first status information is 1, it indicates that the on-chip storage unit has completed the preheating process and can perform the standard memory access operation. When the state value of the first status information is 0, it indicates that the on-chip storage unit is in the preheating process or has not completed the preheating process, and cannot perform the standard memory access operation.
[0088] Specifically, during the preheating process, the number of added memory blocks can be monitored in real time, and the first status information is determined based on this. In actual implementation, when the number of added memory blocks is less than a preset threshold, it is determined that the preheating process is not completed, and the state value of the first status information is determined to be 0. When the number of added memory blocks is greater than or equal to the preset threshold, it is determined that the preheating process is completed, and the state value of the first status information is determined to be 1.
[0089] Further, the second status information indicates the preheating stage in which the on-chip storage unit is currently located. For example, in a possible implementation, when the second status information is 1, it indicates that the on-chip storage unit is in the initial stage of the preheating process; when the second status information is 2, it indicates that the on-chip storage unit is in the middle stage of the preheating process; and when the second status information is 3, it indicates that the on-chip storage unit is in the completion stage of the preheating process, and the on-chip storage unit completes the preheating process and enters a stable state.
[0090] In actual implementation, during the preheating process, the number of added memory blocks can be monitored in real time, and based on the number of currently added memory blocks and the access increment, the increase percentage (which is equal to the percentage of the number of currently added memory blocks and the access increment) is calculated. Further, according to the increase percentage, and a preset increase percentage and preheating stage correspondence relationship, the current preheating stage is determined.
[0091] It should be noted that the number of preheating stages included in the preheating stage is set according to actual needs, which is not limited in this embodiment. In addition, the preset increase percentage and preheating stage correspondence relationship is also set according to actual needs. For example, in a possible implementation, in combination with the above example, the preset stage includes three stages, which are the start stage, the middle stage and the completion stage. The preset increase percentage and preheating stage correspondence relationship is shown in Table 1:
[0092] Table 1: Preset increase percentage and preheating stage correspondence relationship
[0093] Pre-heat phase Start phase Middle phase Finish phase Increase percentage 0％-10％ More than 10% and less than 100% 100％
[0094] S302, feedback the first state information and the second state information to a state management apparatus in the electronic device, so that the state management apparatus acquires the state of the memory access management apparatus.
[0095] Specifically, the state management apparatus can be a CPU or a GPU in the electronic device, which is not limited in the embodiment. Further, by sending the first state information and the second state information to the state management apparatus, the state management apparatus can comprehensively understand the state of the memory access management apparatus, help the state management apparatus to make more effective monitoring and management, and make corresponding state management.
[0096] The memory access management method provided in the embodiment can determine the first state information for indicating whether the preheating process is completed, and the second state information for indicating the current stage of the preheating process, and then feed back the first state information and the second state information to the state management apparatus in the electronic device, so that the state management apparatus can acquire the state of the memory access management apparatus, and realize real-time monitoring and accurate control of the preheating process.
[0097] Corresponding to the foregoing embodiment of the memory access management method, the present application also provides an embodiment of a memory access management apparatus.
[0098] Figure 4 The structure diagram of the memory access management apparatus embodiment one provided in the present application is shown in FIG. 4. Please refer to FIG. 4. Figure 4 The apparatus provided in the embodiment is applied to an electronic device provided with on-chip storage, and the apparatus includes a counting module 410, a register group 420, a comparison unit 430, and a controller 440.
[0099] The counting module 410 is configured to count the total number of memory blocks that need to be accessed in a current clock cycle according to the memory access requests received in the current clock cycle.
[0100] The register group 420 is configured to store the number of memory blocks that need to be accessed in historical clock cycles.
[0101] The comparison unit 430 is configured to determine an access increment corresponding to the current clock cycle according to the total number and an average value of the number of memory blocks that need to be accessed in a preset number of historical clock cycles.
[0102] The controller 440 is provided with a state machine; the controller 440 is configured to control the state machine to enter a preheating state when the access increment is greater than the preset threshold; wherein the controller executes a preheating process in the preheating state; the preheating process comprises: taking the average value as an initial value of the number of memory blocks to be accessed, gradually increasing the number of memory blocks to be accessed according to a preset increment rule, until the number of memory blocks after the increase is greater than or equal to the total number, to gradually increase the access intensity, so that the on-chip storage unit completes the preheating process and enters a stable state.
[0103] Specifically, the controller 440 is provided with a state machine, Figure 5 The state transition diagram of the state machine is shown in an exemplary embodiment of the present application. Please refer to Figure 5 Specifically, the state machine includes three states, which are idle state, preheating state and working state. Further, in the idle state, the controller waits for the next memory access request or read-write request, and in the idle state, the controller only performs some basic maintenance and inspection work, until a new memory access request or read-write request is detected, the idle state is left and the preheating state or the working state is entered; in the preheating state, the controller executes the preheating process; in the working state, the controller executes the standard memory access operation.
[0104] Further, in the idle state, when a new memory access request or read-write request is detected, if the access increment is not greater than the preset threshold, the working state is directly entered; if the access increment is greater than the preset threshold, the preheating state is entered, and in addition, after the preheating state is completed, the working state is entered.
[0105] The device of the embodiment can be used to execute the steps of the method embodiment shown in the figure, and the specific implementation principle and implementation process are similar, which will not be repeated here. Figure 1
[0106] Further, Figure 6 The schematic diagram of the memory access management device is shown in an exemplary embodiment of the present application. Please refer to Figure 6 The memory access management device includes a register group, the number of registers included in the register group is equal to a preset number, and each register is used to store the number of memory blocks to be accessed in a historical clock cycle. Further, the preset number is set according to actual needs, and in the embodiment, the specific value of the preset number is not limited. For example, in a possible implementation manner, the preset number can be equal to 2 n .
[0107] Further, please refer to Figure 6 When the preset number is 4, the number of memory blocks required to be accessed in 4 history clock cycles stored in 4 registers can be added and divided by 4, that is, the register values are added and then the result is right shifted by 2 bits to calculate the average of the number of memory blocks required to be accessed in 4 history clock cycles.
[0108] It should be noted that after the average of the number of memory blocks required to be accessed in the preset number of history clock cycles is calculated, in each clock cycle, the total number of memory blocks required to be accessed in the current clock cycle is stored in the latest register position, and the existing register value is right shifted.
[0109] In addition, please refer to Figure 6 It can be understood that the comparison unit can be a subtractor to determine the access increment corresponding to the current clock cycle through subtraction operation.
[0110] The memory access management device provided in the embodiment determines the access increment corresponding to the current clock cycle according to the total number of memory blocks required to be accessed in the current clock cycle and the average of the number of memory blocks required to be accessed in the preset number of history clock cycles, so that when the access increment is greater than a preset threshold, the preheating process is entered, and in the preheating process, the number of memory blocks required to be accessed is gradually increased instead of sudden large access, so that the on-chip storage unit can be more smoothly transitioned to a high load state, and the bottleneck or jitter caused by sudden large access can be avoided, and stability is maintained.
[0111] Figure 7 A schematic diagram of the memory access management device embodiment two provided in the present application is shown. Please refer to Figure 7 The counting module 410 includes a merging unit 411 and a statistical unit 412; wherein,
[0112] The merging unit 411 is configured to merge the memory access requests to obtain a merging signal.
[0113] The statistical unit 412 is configured to determine the total number according to the merging signal.
[0114] Specifically, Figure 8 A schematic diagram of the merging unit shown in an exemplary embodiment of the present application is shown. Please refer to Figure 8 The merging unit can be an OR gate. The OR gate is a basic logic gate used to implement the "OR" operation in logic operation. As described above, its function is to perform "OR" operation on the number of bits contained in the plurality of memory access bitmaps, and when the value of any memory access request at the bit is 1, the output is 1; when the value of all memory access requests at the bit is 0, the output is 0.
[0115] Optionally, in a possible implementation, the controller 440 is further configured to control the state machine to be in a working state after each time the number of memory blocks to be accessed is increased.
[0116] Optionally, the controller 440 is further configured to control the state machine to be in a working state when the access increment is not greater than the preset threshold, wherein the controller performs a standard memory access operation when the state machine is in the working state.
[0117] The application further provides an electronic device comprising any of the memory access management apparatuses provided in the second aspect of the application.
[0118] Figure 9 An example of an electronic device according to an example embodiment of the application is shown in the schematic diagram of FIG. 1. Please refer to Figure 9 The electronic device provided in the example embodiment comprises a plurality of functional modules, a memory access management apparatus, an arbiter and an on-chip memory unit; the on-chip memory unit is divided into a plurality of memory blocks; wherein,
[0119] The plurality of functional modules are configured to send memory access requests and read-write requests to the memory access management apparatus.
[0120] The memory access management apparatus is configured to perform access management.
[0121] The arbiter is configured to receive and execute memory read requests from the memory access management apparatus, or receive and execute memory access requests or read-write requests from the memory access management apparatus.
[0122] Each memory block is configured to store data.
[0123] As described above, the memory access management apparatus performs access management according to any of the memory access management methods provided in the first aspect of the application. When the memory access management apparatus performs a warm-up process, it sends memory read requests to the arbiter step by step, and the number of memory blocks to be accessed by each memory read request increases step by step to complete the warm-up process and make the on-chip memory unit enter a stable state. Further, when performing a standard memory access operation, the memory access management apparatus directly sends memory access requests or read-write requests from the functional modules to the arbiter for execution.
[0124] The electronic device provided in the example embodiment can make the on-chip memory unit smoothly transit to a high-load state, avoid bottlenecks or jitter caused by sudden large access, and maintain stability.
[0125] Further, please continue to refer to Figure 9The electronic device further includes a state management device that can send a preset clock cycle set by a user to the memory access management device, and further receive first state information and second state information from the memory access management device.
[0126] The implementation process of the functions and roles of the units in the above device is specifically described in the implementation process of the corresponding steps in the above method, and will not be repeated here.
[0127] For the device embodiment, since it basically corresponds to the method embodiment, the relevant part can be seen in the part of the method embodiment. The device embodiments described above are only schematic, and the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or they can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the scheme of the present application according to actual needs. Those skilled in the art can understand and implement it without creative labor.
[0128] The above only describes the preferred embodiments of the present application and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.
Claims
1. A memory access management method characterized by comprising: The method is applied to a memory access management device in an electronic device provided with an on-chip storage unit, and the method comprises: According to the memory access request or read-write request received in the current clock cycle, the total number of memory blocks needing to be accessed in the current clock cycle is counted; According to the total number and the average value of the number of memory blocks needing to be accessed in a preset number of historical clock cycles, an access increment corresponding to the current clock cycle is determined; When the access increment is greater than a preset threshold, a warm-up process is performed; wherein the warm-up process comprises: taking the average value as an initial value of the number of memory blocks needing to be accessed, gradually increasing the number of memory blocks needing to be accessed according to a preset increasing rule, until the number of memory blocks after the increase is greater than or equal to the total number, so as to gradually increase the access intensity, so that the on-chip storage unit completes the warm-up process and enters a stable state.
2. The method of claim 1, wherein, After each increase in the number of memory blocks needing to be accessed, the method further comprises: Controlling to stay for a preset clock cycle.
3. The method of claim 1, wherein, According to the read-write request received in the current clock cycle, the total number of memory blocks needing to be accessed in the current clock cycle is counted, comprising: For each read-write request, the read-write request is converted into a memory access request; According to the memory access request, the total number of memory blocks needing to be accessed in the current clock cycle is counted.
4. The method according to claim 1 or 3, characterized in that, According to the memory access request received in the current clock cycle, the total number of memory blocks needing to be accessed in the current clock cycle is counted, comprising: Merging the memory access requests to obtain a merged signal; According to the merged signal, the total number is determined.
5. The method of claim 1, wherein, The method further comprises: When the access increment is not greater than a preset threshold, a standard memory access operation is performed.
6. The method of claim 1, wherein, After completing the warm-up process, the method further comprises: Performing a standard memory access operation.
7. The method of claim 1, wherein, The method further comprises: In the warm-up process, first state information for indicating whether the warm-up process is completed and second state information for indicating a current stage of the warm-up process are determined; The first state information and the second state information are fed back to a state management device in the electronic device, so that the state management device obtains the state of the memory access management device.
8. A memory access management apparatus characterized by comprising: The memory access management device is applied to an electronic device provided with an on-chip storage, and the memory access management device comprises a counting module, a register group, a comparison unit and a controller; wherein, The counting module is configured to count the total number of memory blocks needing to be accessed in the current clock cycle according to the memory access request received in the current clock cycle; The register group is configured to store the number of memory blocks needing to be accessed in the historical clock cycles; The comparison unit is configured to determine an access increment corresponding to the current clock cycle according to the total number and the average value of the number of memory blocks needing to be accessed in a preset number of historical clock cycles; The controller is internally provided with a state machine; the controller is configured to control the state machine to enter a preheating state when the access increment is greater than the preset threshold; wherein the controller executes a preheating process in the preheating state; the preheating process comprises: taking the average value as an initial value of the number of memory blocks to be accessed, gradually increasing the number of memory blocks to be accessed according to a preset increment rule, until the number of memory blocks after the increase is greater than or equal to the total number, to gradually increase the access intensity, so that the on-chip storage unit completes the preheating process and enters a stable state.
9. The apparatus of claim 8, wherein, The counting module comprises a merging unit and a statistical unit; wherein, The merging unit is configured to merge the memory access requests to obtain a merging signal; The statistical unit is configured to determine the total number according to the merging signal.
10. The apparatus of claim 8, wherein, The controller is further configured to control a preset clock period after each increase in the number of memory blocks to be accessed.
11. An electronic device, comprising: The electronic device comprises the memory access management device according to any one of claims 8-10.