Frame delay time counting circuit and near field communication card comprising same

Abstract

A near field communication (NFC) card includes a frame delay time (FDT), in which the FDT counting circuit includes a first comparator configured to compare an envelope voltage signal with a first reference voltage and output a first comparison output signal, a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal, and a third comparator configured to compare the envelope voltage signal with the second reference voltage and output a third comparison output signal. The FDT compensation circuit is configured to output a compensation signal based on the first comparison output signal and the second comparison output signal, and the trigger generation circuit is configured to output a trigger signal based on the first comparison output signal and the compensation signal.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2024-0118805, filed on September 2, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to near field communication (NFC) systems, and more specifically, to a frame delay time (FDT) counting circuit for an NFC card. Background Technology

[0004] Contactless NFC card communication uses the communication protocol specified by the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC) standard 14443. The ISO / IEC 14443 standard specifies the signal transmission protocol between the NFC card reader and the NFC card. This protocol includes specifications for transmitted signals, such as the rise and fall times of the transmitted signals, and the modulation index (MI) for the pause section included in the transmitted signal. The protocol also specifies the frame delay time (FDT), which indicates the time delay between the NFC card initiating a transmission operation to the NFC reader after receiving the transmission signal from the NFC card reader. The FDT may fluctuate depending on the characteristics of the NFC card reader and / or the NFC card, as well as variations in the communication environment. In some cases, the FDT fluctuation may exceed the preset value specified in the standard, and near-field communication between the reader and the NFC card may be impossible or suffer from severe degradation in communication efficiency. Therefore, it is necessary to control the FDT fluctuation within the value specified in the standard. Summary of the Invention

[0005] A Near Field Communication (NFC) card includes a rectification and filtering circuit and a Frame Delay Time (FDT) counting circuit. The rectification and filtering circuit is configured to receive a radio signal and generate an envelope voltage signal based on the radio signal, wherein the envelope voltage signal includes multiple pause portions. The Frame Delay Time (FDT) counting circuit is configured to detect the rising portion of the last pause portion, measure the rising slope of the last pause portion, and generate a trigger signal that triggers the NFC card to transmit within the Frame Delay Time (FDT) from the rising portion of the last pause portion. The FDT counting circuit includes: a first comparator configured to compare the envelope voltage signal with a first reference voltage and output a first comparison output signal; a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal; an FDT compensation circuit configured to output a compensation signal based on the first comparison output signal and the second comparison output signal; and a trigger generation circuit configured to output a trigger signal based on the first comparison output signal and the compensation signal.

[0006] A Frame Delay Time (FDT) counting circuit in a Near Field Communication (NFC) card includes: a first comparator configured to compare an envelope voltage signal with a first reference voltage and output a first comparison output signal; a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal; an FDT compensation circuit configured to generate a compensation signal based on the first comparison output signal and the second comparison output signal; and a trigger generation circuit configured to output a trigger signal based on the first comparison output signal and the compensation signal, wherein the trigger signal initiates a transmission operation of the NFC card.

[0007] A Near Field Communication (NFC) system includes an NFC card, wherein the NFC card includes a rectification and filtering circuit and a frame delay time (FDT) counting circuit. The rectification and filtering circuit is configured to receive a radio signal and generate an envelope voltage signal based on the radio signal, and the envelope voltage signal includes multiple pause portions. The frame delay time (FDT) counting circuit is configured to detect the rising portion of the last pause portion, measure the rising slope of the last pause portion, and generate a trigger signal based on the measured value of the rising slope of the last pause portion. The trigger signal triggers a transmission operation of the NFC card within the frame delay time (FDT) from the rising portion of the last pause portion. The FDT counting circuit includes: a first comparator configured to compare the envelope voltage signal with a first reference voltage and output a first comparison output signal; a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal; an FDT compensation circuit configured to output a compensation signal based on the first comparison output signal and the second comparison output signal; and a trigger generation circuit configured to output a trigger signal based on the first comparison output signal and the compensation signal. Attached Figure Description

[0008] The features and advantages of this disclosure will become apparent and more readily understood from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating a near field communication (NFC) system according to an example embodiment;

[0010] Figure 2 This is a block diagram illustrating an NFC card according to an example embodiment;

[0011] Figure 3 , Figure 4 , Figure 5 and Figure 6 This is a diagram illustrating an example of the frame and pause portion of the Type A interface protocol of ISO / IEC 14443;

[0012] Figure 7 This is a diagram illustrating the encoding scheme based on the modified Miller encoding scheme;

[0013] Figure 8 This is a diagram illustrating an example of frame delay time (FDT) counting;

[0014] Figure 9 and Figure 10 This is a diagram illustrating the FDT counting operation according to an example embodiment;

[0015] Figure 11 This is a block diagram illustrating an FDT counting circuit according to an example embodiment;

[0016] Figure 12 This is a diagram illustrating a method for counting FDTs according to an example embodiment; and

[0017] Figure 13 This is a block diagram illustrating an FDT compensation circuit according to an example embodiment. Detailed Implementation

[0018] In the following, embodiments of the inventive concept are described in detail with reference to the accompanying drawings.

[0019] The terms “input voltage,” “input voltage level,” and “radio signal” are used interchangeably. Depending on the context of the embodiments, these terms may have the same or different meanings, and the meaning of each term can be understood in the context of the embodiments described below.

[0020] Figure 1 This is a block diagram illustrating a near field communication (NFC) system according to an example embodiment.

[0021] refer to Figure 1The NFC system 1 may include an NFC reader 10 and an NFC card 100. The NFC reader 10 may also be referred to as a proximity coupling device (PCD), and the NFC card 100 may also be referred to as a proximity integrated circuit card (PICC) or an contactless integrated circuit card (CICC). Alternatively, the NFC reader 10 may be referred to as an interrogator, and the NFC card 100 may be referred to as a tag, label, or transponder.

[0022] Unless otherwise stated, the NFC card 100 and NFC reader 10 described below may conform to the ISO / IEC 14443 Type A standard.

[0023] The NFC reader 10 includes an antenna coil 11 and receives and transmits signals through the antenna coil 11. The NFC card 100 includes an antenna coil 110 and receives and transmits signals through the antenna coil 110.

[0024] The ISO / IEC 14443 standard specifies proximity communication with a transmission range of approximately 10 cm. Depending on how the data is modulated and encoded, and how collision avoidance is achieved, the standard can be classified as Type A or Type B.

[0025] For example, ISO / IEC 14443 Type A specifies a bit rate of 106 kbps (kilobits per second) for receiving and transmitting signals, which is 1 / 128th of the carrier frequency (fc), where the carrier frequency is 13.56 MHz. Before being transmitted from NFC reader 10 to NFC card 100 or from NFC card 100 to NFC reader 10, the transmitted signal is modulated to have the carrier frequency (fc) using an amplitude shift keying (ASK) 100% modulation scheme. NFC reader 10 can also power NFC card 100 via the transmitted signal. NFC card 100 can draw power from the transmitted signal and can continue receiving and transmitting operations without an independent power supply. The transmitted signal can be modulated using a modified Miller coding scheme. Because the modulated signal is modulated with the carrier frequency, it is transmitted at 128 times the bit rate of the data signal. NFC reader 10 can transmit the modulated signal by radiating strong electromagnetic waves through antenna coil 11. NFC card 100 can receive the electromagnetic waves through magnetic induction with antenna coil 110 of NFC card 100. The NFC card 100 can extract data signals and power from the received signals by demodulating the received signals. For efficient data communication and power transmission, the antenna coils and other passive components of the NFC reader 10 and the NFC card 100 are designed to have the same resonant frequency. Although the NFC system 1 according to this embodiment is described in accordance with the ISO / IEC 14443 Type A standard, the inventive concept is not limited to a specific standard type.

[0026] According to an example embodiment, the NFC card 100 may use a subcarrier load modulation method, wherein an on / off key (OOK) modulation method is combined with Manchester encoding to transmit a data signal to the NFC reader 10. The amplitude of the data signal transmitted from the antenna coil 110 of the NFC card 100 to the NFC reader 10 can be changed by adjusting the load resistance value, thereby making the waveform of the data signal similar to an ASK modulated waveform.

[0027] According to an example embodiment, NFC reader 10 can send a request data frame to NFC card 100 for selecting NFC card 100. NFC reader 10 can anticipate a response data frame from the selected NFC card within a preset time after sending the request data frame. Each of the request data frame and the response data frame is a bit sequence defined in the ISO / IEC 14443 standard. The request data frame may include start bits, end bits, and data bits. The start bits and end bits may indicate the start and end of the request data frame, respectively. The response data frame may include length information, a parity bit, and the data bits requested by NFC reader 10. The length information identifies the total size of the response data frame, and the parity bit is used by NFC reader 10 to determine whether the response data frame contains errors. If no response data frame is received within the preset time after sending the request data frame from NFC card 100, NFC reader 10 can determine that NFC card 100 failed to receive the request data frame. Communication failure typically occurs when the NFC card 100 is not ready to send a response data frame requested from the NFC reader 10 within a preset time after recognizing the last bit of the request data frame sent from the NFC reader 10.

[0028] According to the example embodiment, the preset time can be referred to as the Frame Delay Time (FDT). The NFC card 100 needs to initiate a data transmission operation within the FDT specified in the standard. To achieve the preset time requirement at the circuit level, the NFC card 100 can detect and measure the rising slope of the pause portion of the last bit in the request data frame sent to the NFC card 100 by counting the rising portion of the pause portion of the last bit using an internal clock. The number of clock cycles counted from the rising portion of the pause portion is called the FDT count value. The FDT count value multiplied by the internal clock cycle corresponds to the FDT. The preset number of internal clock cycles required for the NFC card 100 to initiate a data transmission operation can be referred to as the trigger reference count value. When the FDT count value reaches the trigger reference count value, the NFC card 100 can begin sending a data signal to the NFC reader 10. Typically, due to FDT fluctuations, the trigger reference count value can have a range of maximum and minimum values. FDT fluctuations are unavoidable due to mismatches between the antenna coil 11 of the NFC reader 10 and the antenna coil 110 of the NFC card 100, as well as changes in the communication environment. The ISO / IEC 14443 Type A standard specifies the permissible range for the FDT based on a carrier frequency (fc) of 13.56 MHz in the Type A standard. When the FDT fluctuation exceeds the preset permissible range, in other words, when the FDT count value does not reach the trigger reference count value within the FDT, the FDT reader 10 can identify it as a timeout failure. Figure 11 , Figure 12 and Figure 13Describe the FDT counting operation in detail.

[0029] Figure 2 This is a block diagram illustrating an NFC card 100 according to an example embodiment.

[0030] refer to Figure 2 The NFC card 100 may include an antenna coil 110, a matching circuit 120, a demodulation circuit 130, a rectification and filtering circuit 140, a clock extraction circuit 150, a clock divider circuit 160, a processing circuit 170, a memory 180, and a modulation circuit 190.

[0031] Alternatively, the NFC card 100 can be implemented as a single transmit / receive circuit, which includes an antenna coil 110, a matching circuit 120, a demodulation circuit 130, a rectification and filtering circuit 140, a clock extraction circuit 150, a clock divider circuit 160, and / or a modulation circuit 190.

[0032] The antenna coil 110 of the NFC card 100 can generate electromagnetic waves through mutual coupling with the antenna coil 11 of the corresponding NFC reader 10 for receiving and transmitting data signals. Additionally, the NFC card 100 can be powered by magnetic induction between the antenna coil 110 and the antenna coil 11 of the NFC reader 10. Mutual coupling between the antenna coil 110 and the antenna coil 110 of the NFC card 100 can be achieved by matching the resonant frequency of the antenna coil 110 with the resonant frequency of the antenna coil 11 of the NFC reader 10. The resonant frequency of the NFC card 100 can be determined by adjusting the inductance value of the antenna coil 110 and the corresponding capacitance value of the capacitor included in the matching circuit 120. Similarly, the resonant frequency of the NFC reader 10 can be determined by adjusting the inductance value of the antenna coil 11 and the corresponding capacitance value of the capacitor included in the NFC reader 10.

[0033] Furthermore, by adjusting the impedance of the signal transmission path using the matching circuit 120, the signal transmission efficiency between the NFC reader 10 and the NFC card 100 can be improved. For example, the matching circuit 120 can switch between using a capacitor for receiving operations and a capacitor for transmitting operations.

[0034] Antenna coil 110 and matching circuit 120 can also be referred to as resonant circuits. The resonant circuit of NFC card 100 can receive the input voltage VIN induced by the mutual coupling operation with the resonant circuit of NFC reader 10. Matching circuit 120 can provide the input voltage VIN to demodulation circuit 130, rectification and filtering circuit 140, and clock extraction circuit 150. The input voltage VIN can correspond to a request data frame sent from NFC reader 10.

[0035] The demodulation circuit 130 generates received data RDATA by demodulating the input voltage VIN and provides the received data RDATA to the processing circuit 170. The received data RDATA can be demodulated data pre-modulated in the NFC reader 10 using the ASK 100% amplitude modulation scheme and a modified Miller coding scheme. The processing circuit 170 can store the received data RDATA in the memory 180.

[0036] The rectifier and filter circuit 140 can output an envelope voltage signal VENV relative to the input voltage VIN. The voltage level of the envelope voltage signal VENV can be the envelope of the input voltage VIN. According to an example embodiment, the envelope voltage signal VENV can include seven bits of data, and some bits of data include pause portions, such as... Figure 5 , Figure 6 and Figure 7 As shown. The rectifier and filter circuit 140 can output the envelope voltage signal VENV by rectifying and filtering the input voltage VIN.

[0037] The rectification and filtering circuit 140 may include a rectifier circuit and a low-pass filter. The rectifier circuit rectifies the input voltage VIN, and the rectified input voltage passes through the low-pass filter. By filtering out the high-frequency components of the rectified input voltage, the rectification and filtering circuit 140 can output an envelope voltage signal VENV with a bit rate of the data signal. The rectification and filtering circuit 140 can provide the envelope voltage signal VENV to the FDT counting circuit 200. Because the cutoff frequency of the low-pass filter is less than the carrier frequency (fc) of the radio signal received by the antenna coil 110, the carrier frequency component of the received radio signal is removed by the low-pass filter, so that the voltage level of the envelope voltage signal VENV can represent the envelope of the radio signal. For example, the carrier frequency (fc) may be 13.56 MHz, and the cutoff frequency of the low-pass filter may be set to less than 13.56 MHz to filter out the carrier frequency component of the radio signal.

[0038] Additionally, the rectifier and filter circuit 140 can generate an internal voltage VINT by rectifying the input voltage VIN to power the NFC card 100.

[0039] To generate the internal voltage VINT, the rectifier and filter circuit 140 may also include a regulating circuit that adjusts the output of the filter circuit. The internal voltage VINT can be supplied to the processing circuit 170 or any other component of the NFC card 100, such as the demodulation circuit 130, the clock extraction circuit 150, the modulation circuit 190, and the FDT counting circuit 200.

[0040] The clock extraction circuit 150 can generate a clock signal CLK with a carrier frequency (fc) of the radio signal based on the input voltage VIN. The clock extraction circuit 150 can extract the clock signal CLK from the received radio signal by passing the received radio signal through a high-pass filter in the clock extraction circuit 150.

[0041] The clock divider circuit 160 can generate an internal clock signal CLK_INT by dividing the clock signal CLK. The internal clock signal CLK_INT can have various frequencies. The clock divider circuit 160 can provide the internal clock signal CLK_INT to any other components in the processing circuit 170 and the NFC card 100, such as the demodulation circuit 130, the clock extraction circuit 150, the modulation circuit 190, and the FDT counting circuit 200.

[0042] The processing circuit 170 can control the overall operation of the NFC card 100. For example, during a receiving operation, the processing circuit 170 can receive received data RDATA from the demodulation circuit 130 and store the received data RDATA in the memory 180. During a transmitting operation, the processing circuit 170 can read the transmitted data TDATA from the memory 180 and provide the transmitted data TDATA to the modulation circuit 190.

[0043] The modulation circuit 190 can modulate the transmitted data TDATA to generate an output voltage VOUT, and can send the output voltage VOUT to the NFC reader 10. The modulation circuit 190 can load the modulated transmitted data TDATA onto the resonant circuit of the modulation circuit 190, and provide the output voltage VOUT to the NFC reader 10 through the antenna coil 110.

[0044] According to an embodiment, the modulation circuit 190 can provide an output voltage VOUT to the NFC reader 10 in response to the trigger signal TRIG_RES from the FDT counting circuit 200. The modulation circuit 190 can begin data transmission immediately after activating the trigger signal TRIG_RES provided by the FDT counting circuit 200. Activation of the trigger signal TRIG_RES is required to initiate a transmission operation within the FDT as specified in the ISO / IEC 14443 Type A standard. The data signal transmitted by the NFC card 100 can be an acknowledgment data frame, which can be a response to a previously received request data frame from the NFC reader.

[0045] The trigger signal TRIG_RES can also be provided to the processing circuit 170. The processing circuit 170 can control the modulation circuit 190 in response to the trigger signal TRIG_RES, and the NFC card 100 can initiate a transmission operation. In this case, the trigger signal TRIG_RES of the FDT counting circuit 200 can initiate the transmission operation of the NFC card 100 by providing the output voltage VOUT as a radio signal to the NFC reader 10. The NFC card 100 can provide a response data frame to the NFC reader 10 within the FDT starting from the last bit of the request data frame sent by the NFC reader 10.

[0046] The FDT counting circuit 200 can detect the rising portion of the last pause in the request data frame based on the envelope voltage signal VENV, and can output a trigger signal TRIG_RES from the NFC card 100 to initiate a transmission operation within a specified FDT after the rising portion of the last pause. The last pause can be the pause portion of the last data bit of the request data frame, or, when the last data bit of the request data frame does not include a pause portion, the last pause can be the pause portion of the end bit of the request data frame.

[0047] The FDT counting circuit 200 can generate a trigger signal TRIG_RES based on the envelope voltage signal VENV and provide it to the modulation circuit 190. (Refer to...) Figure 9 to Figure 13 The operation of the FDT counting circuit 200 for generating the trigger signal TRIG_RES based on the envelope voltage signal VENV is described in more detail.

[0048] According to the example embodiment, by detecting and measuring the rising slope of the final pause portion of the envelope voltage signal VENV, the NFC card 100 can compensate for the effect of the rising slope in the FDT count value. More specifically, the NFC card 100 can detect and measure the rising slope of the final pause portion of the envelope voltage signal VENV and can compensate for the trigger reference count value, thereby modifying the FDT count value required to trigger the data transmission operation of the NFC card 100. As a result of compensating for the preset time by modifying the trigger reference count value, the FDT count value required to trigger the transmission operation of the NFC card 100 can be reduced, thereby preventing timeout failures and improving the compatibility between the NFC card 100 and the NFC reader 10.

[0049] Figure 3 , Figure 4 , Figure 5 and Figure 6 This is a diagram illustrating an example of a data frame and a pause section of the Type A interface protocol of ISO / IEC 14443.

[0050] Figure 3 and Figure 4The data frames received / transmitted between an NFC reader 10 conforming to the ISO / IEC 14443 Type A standard and an NFC card 100 are shown. Figure 3 A short data frame, including a start bit S, data bits b1 to b7, and an end bit E, is shown. This short data frame can be sent from an NFC reader 10 to an NFC card 100. The low bits of the short data frame (e.g., b1, b2, b3, and b4) can be used to identify the NFC card 100 so that the NFC reader 10 can request a response data frame. The high bits of the short data frame (e.g., b5, b6, and b7) can be used to define the maximum size of the data frame for the NFC reader 10 to receive from the NFC card 100. Figure 4 A standard data frame is shown, comprising a start bit S, data bits b1 to b8, a parity bit P, and an end bit E. In response to a request from NFC reader 10, a series of standard data frames can be sent from NFC card 100 to NFC reader 10. The series of standard data frames may include data length information, parity bits, and the data bits requested by NFC reader 10. The length information identifies the total size of the series of standard data frames, which may not exceed the maximum size defined in the short data frames received by NFC card 100. The parity bit may be used for Cyclic Redundancy Check (CRC), which NFC reader 10 can use to determine whether the standard data frames received from NFC card 100 contain errors. This series of standard data frames may be a response data frame requested by the NFC reader using a request data frame.

[0051] In addition, short data frames can be used in NFC communication with a bit rate of 106kbps, which is 1 / 128th of the carrier frequency (fc / 128), and standard data frames can be used in NFC communication with bit rates of 212kbps (fc / 64), 424kbps (fc / 32), or 848kbps (fc / 16).

[0052] Figure 5 The waveform of the paused portion of the envelope voltage signal VENV in a short data frame is shown. Figure 6 The paused portion of the waveform of the envelope voltage signal VENV in a standard data frame is shown.

[0053] refer to Figure 5 and Figure 6 The horizontal axis represents time, and the vertical axis represents the field signal from the NFC reader 10 or the NFC card 100. Figure 6 The parameter "a" in the code represents the pulse shape factor for Type A communication. "H" and "H" are also relevant. INITIAL "h" represents the equivalent uniform magnetic field strength and the strength of the unmodulated RF field, respectively. ovs"Indicates envelope overshoot." Figure 5 and Figure 6 In this context, "t1" represents the length of the pause section. "t2" and "t5" represent the duration of the low level in the pause section. "t3" and "t6" represent the rise time of the pause section, and "t4" represents a partial section of the rise time of the pause section.

[0054] The demodulation circuit 130 of the NFC card 100 can extract each bit from the received radio signal synchronously with a synchronization clock signal, separate the extracted bits into a start bit S, data bits b1 to b7, and an end bit E, and detect the received data from the separated bits. When receiving a data request frame from the NFC reader 10, the NFC card 100 must initiate a transmission operation to send a response data frame to the NFC reader 10 within the FDT specified in the standard. The NFC card 100 can use an internal clock generated from the extracted clock to start measuring the FDT from the rising start time point of the last pause portion included in the last bit of the data request frame.

[0055] Figure 7 This is a diagram illustrating the encoding scheme based on the modified Miller encoding scheme.

[0056] refer to Figure 7 Data bits modulated with a carrier signal are transmitted to NFC card 100 in the form of a radio signal. The data bits modulated with the carrier signal may correspond to a request data frame. According to an example embodiment, the data bits are encoded using a modified Miller encoding scheme. When the NFC card receives the radio signal, the radio signal may be referred to as the input voltage VIN of NFC card 100.

[0057] Figure 7 The basic time unit (ETU) shown represents the period for transmitting one data bit.

[0058] According to the example embodiment, the modified Miller encoding encodes each data bit based on the previous data bits. For example, a data bit "1" is encoded by transitioning the previous data bit in the middle of the ETU. If the previous data bit is "1", the data bit "1" is encoded by transitioning to a low level in the middle of the ETU, thus forming a low pulse waveform after half a cycle of the ETU. The low pulse waveform may correspond to the pause portion of the envelope voltage VENV, which is the envelope signal of the input voltage VIN.

[0059] Depending on the value of the preceding data bit, the data bit "0" can be encoded in two different ways. When the preceding data bit is "0", the data bit "0" is encoded by transitioning to a low level at the beginning of the ETU. The low pulse waveform can correspond to a pause in the envelope voltage VENV, which is the envelope signal of the input voltage VIN. When the preceding data bit is 1, the data bit "0" is encoded by maintaining a high-level waveform during the ETU.

[0060] Figure 8 This is a diagram illustrating an example of FDT counting.

[0061] The ISO / IEC 14443 standard specifies the FDT (Functional Data Request). The FDT can be defined differently depending on the command type and the logical value of the last data bit of the data request signal sent to the NFC card 100.

[0062] refer to Figure 8 FDT can be defined as the time interval between the end point (rise start time points ts1 and ts2) of the last pause portion PLS1 included in the last data bits of the data request frame sent by the NFC reader 10 and the start point of the response data frame (SMOD) sent by the NFC card 100. Figure 7 As shown, when the last data bit of the data request signal is a data bit "0" and the previous data bit "1", the last data bit remains high during the ETU and does not include a pause portion. In this case, the FDT count can begin at the pause portion, which immediately follows the last data bit in the request data frame.

[0063] refer to Figure 7 and Figure 8 The first case, CASE1, illustrates a scenario where the last data bit of a request data frame sent by the NFC reader 10 includes a pause portion, and the FDT count begins at the rising point (ts1) of the pause portion. The two basic time units following the last data bit may not include any low pulses.

[0064] Unlike the first case, Figure 8 The second case, CASE 2, illustrates the situation where the last data bit of the request data frame is a data bit "0" and the preceding data bit is "1". The last data bit remains high during the ETU and does not include a pause portion. In this case, the FDT count can begin at the pause portion, which immediately follows the last data bit of the request data frame. The NFC reader 10 can include the pause portion at the beginning of the 2ETU immediately following the last bit of data in the data request signal.

[0065] Figure 9 and Figure 10This is a diagram illustrating a method for FDT counting according to an example embodiment.

[0066] refer to Figure 9 The FDT counting circuit 300 includes a comparator circuit 310 consisting of a single comparator CMP and a trigger generation circuit 320.

[0067] The comparator CMP compares the envelope voltage signal VENVA or VENVb with the reference voltage VREF to activate the output signal CMO. At time t1, the rise of the final pause portion of the frame transmitted by the NFC reader 10 is detected. Although the envelope signals VENVA and VENVb are received at different time points ta and tb, respectively, the FDT counting can begin at the same time point t1.

[0068] The trigger generation circuit 320 can start FDT counting in response to the transition of the output signal CMO at time point t1, and output the trigger signal TRIGER_RES when the FDT count value reaches a preset value.

[0069] like Figure 10 As shown, although the envelope signals VENVa and VENVb are received at different time points ta and tb, respectively, the FDT counting circuit 300 can start FDT counting for both the envelope voltage signals VENVa and VENVb at time point t1.

[0070] Similarly, depending on the difference in the rising slope of the last pause portion of the envelope voltage signal VENVa and the envelope voltage signal VENVb, the FDT count can start at different times, even if two envelope voltage signals can be received simultaneously.

[0071] The difference in the rising slope of the final pause section may be due to the distance or position between the antenna coil 110 of the NFC card 100 and the antenna coil 11 of the NFC reader 10.

[0072] Because the rising slope of the envelope voltage signal VENVb is slow, such as Figure 10 As shown, the FDT counting starts later and takes longer to reach the pre-designed FDT value, and the NFC card 100 may not respond to the NFC reader 10 within the FDT specified in the standard. In such a case, the NFC reader 10 can recognize that the NFC card 100 failed to receive the requested data frame, which is called a timeout failure. Therefore, due to the difference in the rising slope of the last pause portion of the envelope voltage signal VENV, some NFC cards may not become compatible with the NFC reader 10.

[0073] According to the example embodiment, the NFC card 100 can detect the rising slope of the last pause portion of the envelope voltage signal VENV, and can prevent FDT failure by compensating for the unnecessary delay of FDT caused by the slow rising slope of the last pause portion, and can improve the compatibility between the NFC reader 10 and the NFC card.

[0074] Figure 11 This is a block diagram illustrating an FDT counting circuit 200 according to an example embodiment, and Figure 12 This is a diagram illustrating a method for counting FDTs according to an example embodiment.

[0075] refer to Figure 11 The FDT counting circuit 200 may include a comparator circuit 210, a trigger generation circuit 220, an FDT compensation circuit 230, and a reference voltage generation circuit 240.

[0076] The comparator circuit 210 may include a first comparator CMP1 and a second comparator CMP2. Figure 9 The comparison circuit 310 shown includes a comparator CMP, unlike the comparison circuit 210 according to this example embodiment, which may include two comparators.

[0077] The first comparator CMP1 can compare the envelope voltage signal VENV with the first reference voltage VREF1, and can output a first comparison output signal CMO1. When the voltage level of the envelope voltage signal VENV is greater than or equal to the level of the first reference voltage VREF1, the first comparison output signal CMO1 can be converted to different logic levels.

[0078] The second comparator CMP2 can compare the envelope voltage signal VENV and the second reference voltage VREF2, and can output a second comparison output signal CMO2. When the voltage level of the envelope voltage signal VENV is greater than or equal to the level of the second reference voltage VREF2, the second comparison output signal CMO2 can be converted to different logic levels.

[0079] The reference voltage generation circuit 240 can generate a first reference voltage VREF1 and a second reference voltage VREF2. Figure 12 The level of the first reference voltage VREF1 can be greater than the level of the second reference voltage VREF2.

[0080] The trigger generation circuit 220 can output a trigger signal TRIGER_RES based on the first comparison output signal CMO1 of the first comparator CMP1 and the compensation signal COMP_OFFSET of the FDT compensation circuit 230. The trigger signal TRIGER_RES can be provided to, for example... Figure 2 The modulation circuit 190 or processing circuit 170 shown.

[0081] Reference Figure 11 and Figure 12 The trigger generation circuit 220 can start the FDT counting operation in response to the change of the first comparison output signal CMO1 of the first comparator CMP1, and output the trigger signal TRIGER_RES when the FDT count value reaches the trigger reference count value.

[0082] Trigger generation circuit 220 may include a counter and a timer. The timer may include a register storing a trigger reference count value. The counter may begin FDT counting operation in response to a change in the first compare output signal CMO1 of the first comparator CMP1, and stop when the FDT count value reaches the trigger reference count value. Immediately after the FDT count value reaches the trigger reference count value, the timer may generate a trigger signal TRIGER_RES. NFC card 100 may begin sending response data frames to NFC reader 10 in response to the trigger signal TRIGER_RES.

[0083] The counter of the trigger generation circuit 220 can start the FDT counting operation in response to the change of the first comparison output signal CMO1, and when the FDT count value reaches the trigger reference count value, the timer of the trigger generation circuit 220 can trigger the data transmission operation of the NFC card 100.

[0084] The trigger reference count value can be compensated based on the compensation signal COMP_OFFSET. (Reference) Figure 11 The trigger generation circuit 220 can perform FDT counting operations synchronously with the internal clock signal CLK_INT2.

[0085] refer to Figure 11 , Figure 12 and Figure 13 According to the example embodiment, the NFC card 100 can detect and measure the rising slope of the last pause portion of the envelope voltage signal VENV, and can compensate for the trigger reference count value, thereby modifying the FDT count value required to trigger the data transmission operation of the NFC card 100. As a result of compensating for the preset time by compensating the trigger reference count value, the FDT count value required to trigger the transmission of the data signal of the NFC card 100 can be reduced, thereby preventing timeout failures and improving the compatibility between the NFC card 100 and the NFC reader 10. Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 Detailed description of example embodiments.

[0086] In this embodiment, the trigger generation circuit 220 can update the trigger reference count value in response to the compensation signal COMP_OFFSET of the FDT compensation circuit 230.

[0087] For example, the trigger generation circuit 220 can update the trigger reference count value, as shown in Equation 1 below.

[0088] REF COUNT TRIG = COUNT 最后数据比特 - COUNT COM_OFFSET Equation 1

[0089] REF COUNT in Equation 1 TRIG This can represent the trigger reference count value, COUNT. 最后数据比特 This can represent a preset count value based on the value of the last data bit in the request data frame. For example, when the carrier frequency (fc) is 13.56 MHz, COUNT... 最后数据比特 It can be 1236 when the last bit is a logic level "1", or 1172 when the last bit is a logic level "0". COUNT COM_OFFSET It can represent the count value compensated by the compensation signal COMP_OFFSET.

[0090] The trigger generation circuit 220 can generate a count value COUNT based on the last bit value in the request data frame. 最后数据比特 Subtract the count value COUNT compensated by the compensation signal COMP_OFFSET. COM_OFFSET To update the trigger reference count value.

[0091] The FDT compensation circuit 230 can generate a compensation signal COMP_OFFSET based on the time interval between the transition point of the first comparison output signal CMO1 of the first comparator CMP1 and the transition point of the second comparison output signal CMO2 of the second comparator CMP2, and can provide the compensation signal COMP_OFFSET to the trigger generation circuit 220.

[0092] refer to Figure 11 and Figure 12 The trigger reference count value can be determined based on the time interval OFFSET1 between the transition point t2 of the first comparison output signal CMO1 of the first comparator CMP1 and the transition point t1 of the second comparison output signal CMO2 of the second comparator CMP2. For example, in Equation 1, the count value COUNT compensated by the compensation signal COMP_OFFSET is... COM_OFFSET It can be determined to be proportional to the time interval OFFSET1.

[0093] As the time interval OFFSET1 between the transition point t2 of the first comparator CMP1's first comparison output signal CMO1 and the transition point t1 of the second comparator CMP2's second comparison output signal CMO2 increases, the trigger reference count value based on the compensation signal COMP_OFFSET can decrease. The increase in OFFSET1 indicates that the rising slope of the final pause portion becomes relatively slow. As the rising slope of the final pause portion slows down, the trigger reference count value of the trigger signal TRIGER_RES should decrease.

[0094] Alternatively, as the time interval OFFSET1 between the transition point t2 of the first comparison output signal CMO1 of the first comparator CMP1 and the transition point t1 of the second comparison output signal CMO2 of the second comparator CMP2 decreases, the trigger reference count value based on the compensation signal COMP_OFFSET can be increased. The decrease in the time interval OFFSET1 between the transition point t2 of the first comparison output signal CMO1 of the first comparator CMP1 and the transition point t1 of the second comparison output signal CMO2 of the second comparator CMP2 indicates that the rising slope of the final pause portion becomes relatively steep. As the rising slope of the final pause portion becomes steeper, the trigger reference count value of the trigger signal TRIGER_RES can be relatively larger compared to the case where the rising slope of the final pause portion is slow.

[0095] The FDT compensation circuit 230 can generate a count value corresponding to the time interval OFFSET1 between the transition point t1 of the first comparison output signal CMO1 of the first comparator CMP1 and the transition point t2 of the second comparison output signal CMO2 of the second comparator CMP2, synchronized with the internal clock signal CLK_INT1. The FDT compensation circuit 230 can provide a compensation signal COMP_OFFSET to the trigger generation circuit 220. The trigger generation circuit 220 can update the trigger reference count value based on the compensation signal COMP_OFFSET to compensate for the time interval OFFSET1. The count value is COUNT. COM_OFFSET It can be the count value corresponding to the time interval OFFSET1.

[0096] According to an embodiment, a compensation signal COMP_OFFSET can be generated based on a count value corresponding to the time interval COMPENSATION OFFSET between the rise time point t0 of the last pause and the transition point t2 of the output signal CMO1 of the first comparator CMP1. Figure 12As shown, the trigger reference count value can be determined based on the count value corresponding to the time interval COMPENSATIONOFFSET.

[0097] For example, refer to Figure 11 and Figure 12 The FDT compensation circuit 230 can synchronously generate the count value of the time interval OFFSET1 between the transition point t1 of the first comparison output signal CMO1 of the first comparator CMP1 and the transition point t2 of the second comparison output signal CMO2 of the second comparator CMP2, in sync with the internal clock signal CLK_INT1.

[0098] The FDT compensation circuit 230 can determine the count value of the time interval OFFSET2 in the rising part (from time point t0 to time point t1) of the last pause before time point t1 based on the count value of the time interval OFFSET1.

[0099] For example, the FDT compensation circuit 230 may include a register that stores a count value for time interval OFFSET2 that is proportional to the count value for time interval OFFSET1. The FDT compensation circuit 230 can determine the count value for time interval OFFSET2 by referring to the count value for time interval OFFSET1.

[0100] The FDT compensation circuit 230 generates a count value corresponding to the time interval COMPENSATION OFFSET by adding the count value of the time interval OFFSET1 based on the transition time interval OFFSET1 based on the count value of the comparison output signals CMO1 and CMO2 to the count value of the time interval OFFSET2 based on the count value of time interval OFFSET1. Furthermore, the FDT compensation circuit 230 can provide the trigger generation circuit 220 with a compensation signal COMP_OFFSET for updating the trigger reference count value to compensate for the count value corresponding to the time interval COMPENSATION OFFSET.

[0101] In Equation 1, the count value COUNT is compensated by the compensation signal COMP_OFFSET. COM_OFFSET This may include the count value corresponding to the time interval COMPENSATION OFFSET (i.e., the sum of the count value corresponding to the time interval OFFSET1 and the count value corresponding to the time interval OFFSET2).

[0102] Figure 13 This is a block diagram illustrating the FDT compensation circuit 230 according to an embodiment.

[0103] The FDT compensation circuit 230 according to the embodiment may include a delay checking circuit 231, an FDT compensation determination circuit 233, and an FDT compensation update circuit 235.

[0104] refer to Figure 12 and Figure 13 The delay check circuit 231 can generate, synchronously with the internal clock signal CLK_INT1, a count value DELAY VALUE representing the time interval OFFSET1 between the transition point t1 of the first comparison output signal CMO1 of the first comparator CMP1 and the transition point t2 of the second comparison output signal CMO2 of the second comparator CMP2. The delay check circuit 231 can provide the count value DELAY VALUE to the FDT compensation determination circuit 233.

[0105] The delay check circuit 231 may include a counter. Here, the counter can perform a counting operation synchronously with the internal clock signal CLK_INT1. In response to the transition of the second comparison output signal CMO2 of the second comparator CMP2, the counter of the delay check circuit 231 can begin counting. Furthermore, in response to the transition of the first comparison output signal CMO1 of the first comparator CMP1, the counter of the delay check circuit 231 can stop counting.

[0106] The delay check circuit 231 can convert the time interval OFFSET1 into a count value DELAY VALUE.

[0107] The FDT compensation determination circuit 233 can generate a compensation count value (COMPENSATION VALUE) based on the count value DELAY VALUE of the delay check circuit 231. The FDT compensation update circuit 235 updates the trigger reference count value of the trigger signal TRIGER_RES based on the compensation count value COMPENSATION VALUE.

[0108] The FDT compensation determination circuit 233 can generate a compensation count value COMPENSATION VALUE. The FDT compensation update circuit 235 updates the compensation signal COMP_OFFSET in Equation 1 based on the compensation count value COMPENSATION VALUE, which is proportional to the time interval OFFSET1. The compensation count value COMPENSATION VALUE can be greater than the count value DELAY VALUE.

[0109] Alternatively, the compensation count value COMPENSATION VALUE can correspond to the time interval OFFSET1, in which the count value DELAY VALUE can be equal to the compensation count value COMPENSATION VALUE.

[0110] The FDT compensation determination circuit 233 may include a register, which may store the count value of time interval OFFSET2 corresponding to the count value of time interval OFFSET1. The FDT compensation determination circuit 233 may determine that the count value of time interval OFFSET2 corresponds to the count value of time interval OFFSET1.

[0111] The FDT compensation update circuit 235 can output a compensation signal COMP_OFFSET based on the compensation count value COMPNSATION VALUE. The compensation signal COMP_OFFSET can be provided to the trigger generation circuit 220.

[0112] The compensation signal COMP_OFFSET can instruct the trigger generation circuit 220 to update the trigger reference count value that reflects the compensation count value COMPENSATION VALUE.

[0113] According to the reference Figure 11 to Figure 13 In the described example embodiment, based on detecting and measuring the rising slope of the final pause portion of the envelope voltage signal VENV, the NFC card 100 can compensate for the FDT count value. Therefore, FDT fluctuations can be reduced, and compatibility between the NFC card 100 and the NFC reader 10 can be improved.

[0114] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A near field communication (NFC) card, comprising: a rectification and filtering circuit configured to receive a radio signal and generate an envelope voltage signal based on the radio signal, and the envelope voltage signal includes a plurality of pause portions; and a frame delay time (FDT) counting circuit configured to detect a rising portion of a last pause portion, measure a rising slope of the last pause portion, and generate a trigger signal triggering a transmission operation of the NFC card within a frame delay time (FDT) from the rising portion of the last pause portion, wherein the FDT counting circuit includes: a first comparator configured to compare the envelope voltage signal with a first reference voltage and output a first comparison output signal; a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal; an FDT compensation circuit configured to output a compensation signal based on the first comparison output signal and the second comparison output signal; and a trigger generation circuit configured to output the trigger signal based on the first comparison output signal and the compensation signal. the trigger generation circuit is configured to:

2. The NFC card of claim 1, wherein, perform an FDT counting operation in response to the first comparison output signal; and output the trigger signal when an FDT count value reaches a trigger reference count value, and wherein the trigger reference count value is compensated based on the compensation signal. the trigger reference count value is determined by subtracting a compensation count value from a pre-designed count value, wherein the compensation count value is a count value determined based on a measured value of the rising slope of the last pause portion.

3. The NFC card of claim 2, wherein, the compensation count value is determined based on a time interval between a transition time point of the first comparison output signal and a transition time point of the second comparison output signal.

4. The NFC card of claim 3, wherein, the compensation count value is proportional to a time interval between a transition time point of the first comparison output signal and a transition time point of the second comparison output signal.

5. The NFC card of claim 3, wherein, the compensation count value corresponds to a count value measured based on a time interval between a transition time point of the first comparison output signal and a transition time point of the second comparison output signal.

6. The NFC card of claim 3, wherein, the compensation count value is determined by adding a first count value measured based on a time interval between a transition time point of the first comparison output signal and a transition time point of the second comparison output signal to a second count value determined based on the first count value, and the second count value is proportional to the first count value.

7. The NFC card of claim 3, wherein, 8.A frame delay time (FDT) counting circuit in a near field communication (NFC) card, the FDT counting circuit comprising: a first comparator configured to compare an envelope voltage signal with a first reference voltage and output a first comparison output signal; a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal; an FDT compensation circuit configured to generate a compensation signal based on the first comparison output signal and the second comparison output signal; and a trigger generation circuit configured to output a trigger signal based on the first comparison output signal and the compensation signal, ​ ​ The trigger signal initiates a transmission operation of the NFC card.

9. The FDT counting circuit of claim 8, wherein, The trigger generation circuit is configured to: perform an FDT counting operation in response to the first comparison output signal; and output the trigger signal when an FDT count value reaches a trigger reference count value, and wherein the trigger reference count value is compensated by the compensation signal.

10. The FDT counting circuit of claim 9, wherein, The trigger reference count value is compensated by subtracting a compensation count value from a pre-designed count value, the compensation count value being measured based on a rising slope of a pause portion of a last data bit in a request data frame received by the NFC card.

11. The FDT counting circuit of claim 10, wherein, The compensation count value for compensating the trigger reference count value is determined based on a time interval between a transition point of the first comparison output signal and a transition point of the second comparison output signal.

12. The FDT counting circuit of claim 10, wherein, The compensation count value for compensating the trigger reference count value is proportional to a time interval between a transition point of the first comparison output signal and a transition point of the second comparison output signal.

13. The FDT counting circuit of claim 10, wherein, The compensation count value for compensating the trigger reference count value corresponds to a time interval between a transition point of the first comparison output signal and a transition point of the second comparison output signal.

14. The FDT counting circuit of claim 10, wherein, The compensation count value for compensating the trigger reference count value is determined by adding a first count value measured based on a time interval between a transition point of the first comparison output signal and a transition point of the second comparison output signal to a second count value determined based on the first count value, and the second count value is proportional to the first count value.

15. A near field communication (NFC) system comprising an NFC card, wherein The NFC card comprises: a rectification and filtering circuit configured to receive a radio signal and generate an envelope voltage signal based on the radio signal, the envelope voltage signal comprising a plurality of pause portions; and a frame delay time (FDT) counting circuit configured to detect a rising portion of a last pause portion, measure a rising slope of the last pause portion, and generate a trigger signal based on a measured value of the rising slope of the last pause portion, and the trigger signal triggers a transmission operation of the NFC card within a frame delay time (FDT) from the rising portion of the last pause portion, wherein the FDT counting circuit comprises: a first comparator configured to compare the envelope voltage signal with a first reference voltage and output a first comparison output signal; a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal; an FDT compensation circuit configured to output a compensation signal based on the first comparison output signal and the second comparison output signal; and a trigger generation circuit configured to output the trigger signal based on the first comparison output signal and the compensation signal.

16. The NFC system of claim 15, wherein, The trigger generation circuit is configured to: perform an FDT counting operation in response to the first comparison output signal; and output the trigger signal when an FDT count value reaches a trigger reference count value, and wherein the trigger reference count value is compensated based on the compensation signal.

17. The NFC system of claim 16, wherein, The trigger reference count value is determined by subtracting a compensation count value from a pre-design count value, the compensation count value being generated based on the rising slope of the last pause portion of a last data bit value in a request data frame received by the NFC card.

18. The NFC system of claim 17, wherein, The compensation count value is determined based on a time interval between a transition time point of the first comparison output signal and a transition time point of the second comparison output signal.

19. The NFC system of claim 17, wherein, The compensation count value is proportional to a time interval between a transition time point of the first comparison output signal and a transition time point of the second comparison output signal.

20. The NFC system of claim 17, wherein, The compensation count value comprises a count value corresponding to a time interval between a transition time point of the first comparison output signal and a transition time point of the second comparison output signal. The compensation count value comprises a count value corresponding to a time interval between a transition time point of the first comparison output signal and a transition time point of the second comparison output signal.

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