Shifting register, display panel and display device

Abstract

The invention discloses a shift register, a display panel and a display device. The shift register comprises a control unit, an output unit and a node voltage regulation unit, the control unit is used for receiving an input signal and a first clock signal and controlling the potential of a first node and the potential of a second node; the output unit comprises a first output subunit and a second output subunit; a second end of the first output subunit is connected with a second end of the second output subunit and outputs an output signal; the control end of the first output subunit is connected with a first node, and the control end of the second output subunit is connected with a second node; and the node voltage regulation unit is connected with the first node and is used for maintaining the potential of the first node as an effective level signal of the first output subunit within at least part of time when the potential of the second node is an ineffective level signal. According to the shift register, stable output of an output signal is ensured by stabilizing the potential of the first node, and the output stability of the shift register is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, more and more electronic devices with display functions are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work.

[0003] In the display field, especially in OLED (Organic Light-Emitting Diode) display technology, oxides are widely used in medium and large-sized display panels due to their good uniformity. However, for display products using oxide processes, there is currently a problem of unstable output from the shift register circuit. Specifically, when the threshold voltage of the oxide thin-film transistor (oxide TFT) in the shift register circuit is too negative, the pull-up node cannot maintain its potential due to leakage, leading to unstable output. The output signal is easily interfered with, which also affects the display quality of the display panel. Summary of the Invention

[0004] This invention provides a shift register, a display panel, and a display device. By stabilizing the potential of the first node, the output signal can maintain the effective level signal output of the first output subunit, thereby improving the output stability of the shift register and enhancing the display quality of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a shift register, comprising:

[0006] The control unit is used to receive an input signal and a first clock signal, and control the potential of the first node and the potential of the second node; wherein, the potential of the first node and the potential of the second node are either high-level signals or low-level signals.

[0007] The output unit includes a first output subunit and a second output subunit; a first terminal of the first output subunit receives a first voltage signal, a first terminal of the second output subunit receives a second voltage signal, and the second terminals of the first and second output subunits are connected to output an output signal; wherein, one of the first voltage signal and the second voltage signal is a high-level signal and the other is a low-level signal;

[0008] The control terminal of the first output subunit is connected to the first node, and outputs the first voltage signal when the potential of the first node is a valid level signal; the control terminal of the second output subunit is connected to the second node, and outputs the second voltage signal when the potential of the second node is a valid level signal.

[0009] A node voltage regulation unit, connected to the first node, is used to maintain the potential of the first node at an effective level signal of the first output subunit for at least a portion of the time when the potential of the second node is an invalid level signal.

[0010] In a second aspect, embodiments of the present invention also provide a display panel, including a driving circuit, the driving circuit including N stages of shift registers as described in any one of the first aspects, cascaded in sequence;

[0011] The output signal of the i-th stage shift register is input into the j-th stage shift register as the input signal of the j-th stage shift register; where N≥2, 1≤i≤N, 1≤j≤N.

[0012] Thirdly, embodiments of the present invention also provide a display device, including a display panel as described in any of the second aspects.

[0013] This invention provides a shift register, a display panel, and a display device. The shift register, by setting a node voltage adjustment unit on the input side of the first node and stabilizing the potential of the first node, achieves stable output of the effective pulse of the output signal, thereby improving the output stability of the shift register. This ensures that the rising edge, falling edge, and duty cycle of the effective pulse of the output signal are always within a preset accuracy range. The stable output signal can also precisely control the switching timing and current magnitude of each transistor in the pixel circuit, avoiding problems such as pixel lighting delay and brightness deviation caused by pulse abnormalities. From the shift register level, it ensures the coordinated work of each pixel unit in the display panel, achieving clear display and stable display of the display panel. This ensures that the display panel can present a clear, smooth, and stable picture effect in various display modes, meeting the application requirements of high-quality display. The shift register can use all oxide thin-film transistors, which can also achieve better image retention and reduce manufacturing costs. Attached Figure Description

[0014] Figure 1a This is a schematic diagram of the structure of a shift register in related technologies;

[0015] Figure 1b yes Figure 1a The timing diagram for driving the shift register is shown.

[0016] Figure 2This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0017] Figure 3 yes Figure 2 A schematic diagram of the driving circuit in the display panel shown.

[0018] Figure 4 yes Figure 3 A schematic diagram of the overall structure of the shift register in the driving circuit shown;

[0019] Figure 5 yes Figure 4 A schematic diagram of a specific structure of the shift register in the driving circuit shown;

[0020] Figure 6 yes Figure 5 The driving timing diagram of each stage of the shift register in the driving circuit is shown.

[0021] Figure 7 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0022] Figure 8 yes Figure 7 The driving timing diagram of each stage of the shift register in the driving circuit is shown.

[0023] Figure 9 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0024] Figure 10 yes Figure 9 The driving timing diagram of each stage of the shift register in the driving circuit is shown.

[0025] Figure 11 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0026] Figure 12 yes Figure 11 The driving timing diagram of each stage of the shift register in the driving circuit is shown.

[0027] Figure 13 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0028] Figure 14 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0029] Figure 15 yes Figure 4A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0030] Figure 16 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0031] Figure 17 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0032] Figure 18 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0033] Figure 19 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0034] Figure 20 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0035] Figure 21 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0036] Figure 22 yes Figure 4 A schematic diagram of another specific structure of the shift register in the driving circuit shown;

[0037] Figure 23 yes Figure 2 A schematic diagram of a pixel circuit in the display panel shown;

[0038] Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] Figure 1a This is a schematic diagram of the structure of a shift register in related technologies. Figure 1b yes Figure 1a The timing diagram for driving the shift register shown is as follows: Figure 1a and Figure 1bAs shown, the shift register has a 7T3C structure (T represents transistor and C represents capacitor), and all transistors can be N-channel transistors. Specifically, the first transistor T1' receives the input signal IN' at its first terminal, and its second terminal is connected to the third node Q3'. The control terminal of the first transistor T1' receives the first clock signal CK1'. The first terminal of the second transistor T2' receives the first clock signal CK1', and its second terminal is connected to the second node Q2'. The control terminal of the second transistor T2' is connected to the fifth node Q5'. The first terminal of the third transistor T3' receives the low-level signal VGL', and its second terminal is connected to the fifth node Q5'. The control terminal of the third transistor T3' receives the input signal IN'. The first terminal of the fourth transistor T4' receives the low-level signal VGL', and its second terminal is connected to the second node Q2'. The control terminal of the fourth transistor T4' is connected to the third node Q3'. The first terminal of the fifth transistor T5' is connected to the second node Q2', and its second terminal is connected to the first node Q1'. The control terminal of the fifth transistor T5' receives the high-level signal VGH'. The first terminal of the sixth transistor T6' receives the high-level signal VGH'. The second terminal of the transistor outputs the output signal OUT', and the control terminal of the sixth transistor T6' is connected to the first node Q1'; the first terminal of the seventh transistor T7' receives the low-level signal VGL', the second terminal of the seventh transistor T7' outputs the output signal OUT', and the control terminal of the seventh transistor T7' is connected to the second node Q2'. Furthermore, the two ends of the first capacitor C1' are connected to the first terminal and the control terminal of the second transistor T2', respectively; the two ends of the second capacitor C2' are connected to the first terminal and the control terminal of the sixth transistor T6', respectively; and the two ends of the third capacitor C3' are connected to the first terminal and the control terminal of the seventh transistor T7', respectively.

[0042] Figure 1a For details on the timing control process corresponding to the shift register shown, please refer to [reference needed]. Figure 1bIn phase s1, the first clock signal CK1' is high, at which time the first transistor T1' is turned on, and the high level corresponding to the input signal IN' can be transmitted to the third node Q3'. The fifth transistor T5' is normally open, so the potential of the third node Q3' and the first node Q1' are both high. At this time, the sixth transistor T6' is turned on, and the high level signal VGH' corresponding to the first terminal of the sixth transistor T6' can be transmitted to the second terminal of the sixth transistor T6', that is, the output signal OUT' of the shift register is high. Also, when the input signal IN' is high, the third transistor T3' is turned on, and the low level signal VGL' corresponding to the first terminal of the third transistor T3' can be transmitted to the fifth node Q5'. At this time, the second transistor T2' is turned off. And when the potential of the third node Q3' is high, the fourth transistor T4' is turned on, and the low level signal VGL' corresponding to the first terminal of the fourth transistor T4' can be transmitted to the second node Q2'. At this time, the seventh transistor T7' is turned off.

[0043] In stage s2, when the first clock signal CK1' is low, the first transistor T1' is off, and the high level corresponding to the input signal IN' cannot be transmitted to the third node Q3'. Simultaneously, the second capacitor C2' is regulated to the potential of the previous stage, keeping the potential of the first node Q1' high. At this time, the sixth transistor T6' continues to conduct, and the high-level signal VGH' corresponding to the first terminal of the sixth transistor T6' can be transmitted to the second terminal of the sixth transistor T6', meaning the output signal OUT' of the shift register is high. Also, when the input signal IN' is high, the third transistor T3' is on, and the low-level signal VGL' corresponding to the first terminal of the third transistor T3' can be transmitted to the fifth node Q5'. At this time, the second transistor T2' is off. Furthermore, with the fifth transistor T5' normally open, the potentials of the third node Q3' and the first node Q1' are both high. At this time, the fourth transistor T4' is turned on, and the low-level signal VGL' corresponding to the first terminal of the fourth transistor T4' can be transmitted to the second node Q2'. At this time, the seventh transistor T7' is turned off. In stage s2, when the first clock signal CK1' is high, the first transistor T1' is turned on, and the high-level signal IN' corresponding to the input signal can be transmitted to the third node Q3'. With the fifth transistor T5' normally open, the potentials of the third node Q3' and the first node Q1' are both high. At this time, the sixth transistor T6' is turned on, and the high-level signal VGH' corresponding to the first terminal of the sixth transistor T6' can be transmitted to the second terminal of the sixth transistor T6', that is, the output signal OUT' of the shift register is high.

[0044] In stage s3, the first clock signal CK1' is low, at which point the first transistor T1' is off, and the high level corresponding to the input signal IN' cannot be transmitted to the third node Q3'. Simultaneously, the second capacitor C2' is regulated to the potential of the previous stage, keeping the potential of the first node Q1' high. At this time, the sixth transistor T6' continues to conduct, and the high-level signal VGH' corresponding to the first terminal of the sixth transistor T6' can be transmitted to the second terminal of the sixth transistor T6', meaning the output signal OUT' of the shift register is high. Conversely, when the input signal IN' is low, the third transistor T3' is off, and the low-level signal VGL' corresponding to the first terminal of the third transistor T3' cannot be transmitted to the fifth node Q5'. At this time, the second transistor T2' is off. Furthermore, the fifth transistor T5' is normally open, and the potentials of the third node Q3' and the first node Q1' are both kept at a high level. At this time, the fourth transistor T4' is turned on, and the low-level signal VGL' corresponding to the first terminal of the fourth transistor T4' can be transmitted to the second node Q2'. Meanwhile, the third capacitor C3' is regulated to the potential of the previous stage, so that the potential of the second node Q2' remains at a low level. At this time, the seventh transistor T7' is turned off.

[0045] In stage s4, when the first clock signal CK1' is high, the first transistor T1' is turned on, and the low level corresponding to the input signal IN' can be transmitted to the third node Q3'. The fifth transistor T5' is normally open, so the potential of the third node Q3' and the first node Q1' are both low. At this time, the sixth transistor T6' is turned off. Conversely, when the input signal IN' is low, the third transistor T3' is turned off, and the low level signal VGL' corresponding to the first terminal of the third transistor T3' cannot be transmitted to the fifth node Q5'. However, the first capacitor C1' is regulated to the potential of the previous stage, i.e., the potential of the first clock signal CK1'. Therefore, the potential of the fifth node Q5' is the high level corresponding to the first clock signal CK1', and the second transistor T2' is turned on. The high level corresponding to the first clock signal CK1' can be transmitted to the second node Q2', and the seventh transistor T7' is turned on. The low level signal VGL' corresponding to the first terminal of the seventh transistor T7' can be transmitted to the second terminal of the seventh transistor T7', meaning the output signal OUT' of the shift register is low. In stage s4, when the first clock signal CK1' is low, the first transistor T1' is turned off, and the low level corresponding to the input signal IN' cannot be transmitted to the third node Q3'. Simultaneously, the second capacitor C2' is regulated to the potential of the previous stage, keeping the potential of the first node Q1' low. At this time, the sixth transistor T6' remains off. Also, when the input signal IN' is low, the third transistor T3' is turned off, and the low level signal VGL' corresponding to the first terminal of the third transistor T3' cannot be transmitted to the fifth node Q5'. However, the first capacitor C1' is regulated to the potential of the previous stage, i.e., the potential of the first clock signal CK1'. Therefore, the potential of the fifth node Q5' is the low level corresponding to the first clock signal CK1', and the second transistor T2' is turned off. At this time, the voltage of the third capacitor C3' is regulated to the potential of the previous stage, so that the potential of the second node Q2' remains at a high level. At this time, the seventh transistor T7' continues to conduct, and the low-level signal VGL' corresponding to the first terminal of the seventh transistor T7' can be transmitted to the second terminal of the seventh transistor T7', that is, the output signal OUT' output by the shift register is at a low level.

[0046] For the aforementioned shift register containing an N-channel transistor, according to the N-channel transistor's turn-on conditions: Vg > Vs (gate voltage greater than source voltage) and Vgs > Vth (gate-source voltage greater than threshold voltage), the problem is that during stage s2, when the threshold voltage Vth of the N-channel transistor is negative, the first transistor T1' may not be effectively turned off, meaning the first transistor T1' may turn on again. At the same time, the fifth transistor T5' is in the on state. Therefore, the first node Q1', the fifth transistor T5', the third node Q3', and the first transistor T1' form a leakage path. This leakage current will cause the high potential of the first node Q1' to be unable to be maintained. When the potential of the first node Q1' is lower than the corresponding high-level signal VGH', it will cause the potential of the sixth transistor T6' to fluctuate, resulting in unstable signal output at the second terminal of the sixth transistor T6'. In other words, the output signal OUT' of the shift register is easily interfered with. Simultaneously, when the threshold voltage Vth of the seventh transistor T7' is negative, a voltage divider will occur between the sixth transistor T6' and the seventh transistor T7', further leading to incomplete signal output of the shift register. In simpler terms, during stage s2, the weak bootstrap capability of the sixth transistor T6' during output results in an insufficiently high potential for the first node Q1'. The potential of the first node Q1' may not be able to maintain a high level continuously, and it is susceptible to leakage interference, making its own potential insufficient to ensure the stable conduction of the sixth transistor T6' and the subsequent effective level output of the second terminal output signal OUT' of the sixth transistor T6', thus causing abnormal signal output of the shift register.

[0047] To address the aforementioned technical problems, this invention provides a shift register. The shift register includes: a control unit for receiving an input signal and a first clock signal, and controlling the potential of a first node and a second node; wherein one of the potentials of the first node and the second node is a high-level signal and the other is a low-level signal; an output unit including a first output subunit and a second output subunit; a first terminal of the first output subunit receives a first voltage signal, a first terminal of the second output subunit receives a second voltage signal, and the second terminals of the first and second output subunits are connected and output an output signal; wherein one of the first and second voltage signals is a high-level signal and the other is a low-level signal; a control terminal of the first output subunit is connected to the first node, and outputs the first voltage signal when the potential of the first node is a valid level signal; a control terminal of the second output subunit is connected to the second node, and outputs the second voltage signal when the potential of the second node is a valid level signal; and a node voltage adjustment unit connected to the first node, used to maintain the potential of the first node at the valid level signal of the first output subunit for at least a portion of the time when the potential of the second node is an invalid level signal.

[0048] The technical solution in this embodiment of the invention provides a shift register that uses a node voltage adjustment unit on the input side of the first node. By stabilizing the potential of the first node, the shift register achieves stable output of the effective pulse of the output signal, thereby improving the output stability of the shift register. This ensures that the rising edge, falling edge, and duty cycle of the effective pulse of the output signal are always within a preset accuracy range. The stable output signal can also precisely control the switching timing and current magnitude of each transistor in the pixel circuit, avoiding problems such as pixel lighting delay and brightness deviation caused by pulse abnormalities. From the shift register level, this ensures the coordinated work of each pixel unit in the display panel, achieving clear display and stable display of the display panel. It ensures that the display panel can present a clear, smooth, and stable picture effect in various display modes, meeting the application requirements of high-quality display. The shift register can use all oxide thin-film transistors, which can also achieve better image retention and reduce manufacturing costs.

[0049] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0050] The shift register provided in this embodiment of the invention can be set in the display panel. The relationship between the display panel and the shift register will be briefly explained below. Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 3 yes Figure 2 The diagram shows the structure of the driving circuit in the display panel. Figure 4 yes Figure 3 The schematic diagram of the overall structure of the shift register in the driving circuit is shown below. Figure 2 , Figure 3 and Figure 4 As shown, the display panel includes a driving circuit 100, which includes N cascaded shift registers 110 as provided in any of the embodiments of the present invention; the output signal OUT of the i-th shift register 110 is input to the j-th shift register 110 as the input signal IN of the j-th shift register 110; wherein, N≥2, 1≤i≤N, 1≤j≤N.

[0051] Specifically, by Figure 2 and Figure 3It is known that the driving circuit 100 of the display panel is provided with at least two stages of shift registers 110, and the at least two stages of shift registers 110 are cascaded, that is, the output signal OUT of a certain stage of shift register 110 is the input signal IN of a certain stage of shift register 110 below. For example, Figure 3 In the example, the output signal OUT of the adjacent upstream shift register 110 serves as the input signal IN of the next-level shift register 110. Furthermore, for any shift register 110, under the control of the first clock signal CK1 and the second clock signal CK2, the output signal OUT can be shifted relative to the input signal IN. The level transitions of the input signal IN and the output signal OUT can occur at different times, achieving a delayed-effective effect. For example, the first input signal IN can also be understood as an STV signal.

[0052] Continue to refer to Figure 4 The shift register 110 includes a control unit 10, an output unit 20, and a node voltage adjustment unit 30. The control unit 10 receives an input signal IN and a first clock signal CK1, and controls the potentials of the first node Q1 and the second node Q2. One of the potentials of the first node Q1 and the second node Q2 is a high-level signal VGH, and the other is a low-level signal VGL. The output unit 20 includes a first output subunit 21 and a second output subunit 22. The first terminal of the first output subunit 21 receives a first voltage signal V1, and the first terminal of the second output subunit 22 receives a second voltage signal V2. The second terminals of the first output subunit 21 and the second output subunit 22 are connected... The output signal OUT is connected to the first output subunit 21. The first voltage signal V1 and the second voltage signal V2 are either high-level (VGH) or low-level (VGL). The control terminal of the first output subunit 21 is connected to the first node Q1, and outputs the first voltage signal V1 when the potential of the first node Q1 is an effective level signal. The control terminal of the second output subunit 22 is connected to the second node Q2, and outputs the second voltage signal V2 when the potential of the second node Q2 is an effective level signal. The node voltage adjustment unit 30 is connected to the first node Q1 and is used to maintain the potential of the first node Q1 at the effective level signal of the first output subunit 21 for at least a portion of the time when the potential of the second node Q2 is an invalid level signal.

[0053] First, it should be clarified that a valid level signal can be understood as controlling the conduction, connection, and operation of the corresponding connected sub-units, units, circuits, etc., while an invalid level signal can be understood as controlling the disconnection, cutoff, and inoperability of the corresponding connected sub-units, units, circuits, etc., such as... Figure 4The effective level signal corresponding to the potential of the first node Q1 and the effective level signal corresponding to the potential of the second node Q2 can both be set to high level, and the ineffective level signal corresponding to the potential of the first node Q1 and the ineffective level signal corresponding to the potential of the second node Q2 can both be set to low level. Furthermore, the transistors used in the control unit 10, the output unit 20, and the node voltage adjustment unit 30 can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. The control terminal of each transistor is the gate of the transistor, the first terminal is one of the source and drain of the transistor, and the second terminal is the other of the source and drain of the transistor. Since the source and drain of the transistor can be structurally symmetrical, they can be considered structurally indistinguishable. That is, the first terminal and the second terminal of the transistor in this embodiment can be structurally indistinguishable. For example, in the case of a P-type transistor, the first terminal of the transistor is the source, and the second terminal is the drain; similarly, in the case of an N-type transistor, the first terminal is the drain, and the second terminal is the source. For example, the N-type transistor and P-type transistor in this embodiment can be oxide thin film transistors, which can be selected according to design requirements and are not specifically limited thereto.

[0054] Specifically, the control unit 10 can receive an input signal IN and a first clock signal CK1 to control the potential of the first node Q1 and the potential of the second node Q2, respectively. The control terminal of the first output subunit 21 is connected to the first node Q1. The first terminal of the first output subunit 21 receives a first voltage signal V1. When the potential of the first node Q1 is at a valid level, the first output subunit 21 is turned on, and the second terminal of the first output subunit 21 outputs the first voltage signal V1. That is, the output signal OUT of the shift register is the first voltage signal V1. Similarly, the control terminal of the second output subunit 22 is connected to the second node Q2. The first terminal of the second output subunit 22 receives a second voltage signal V2. When the potential of the second node Q2 is at a valid level, the second output subunit 22 is turned on, and the second terminal of the second output subunit 22 outputs the second voltage signal V2. That is, the output signal OUT of the shift register is the second voltage signal V2. In this system, one of the potentials of the first node Q1 and the second node Q2 is a high-level signal VGH, and the other is a low-level signal VGL. When the potential of the first node Q1 is an active level signal, the potential of the second node Q2 is an inactive level signal. At this time, the second terminal of the first output subunit 21 outputs the first voltage signal V1, and the second terminal of the second output subunit 22 does not output. That is, the output signal OUT of the shift register is the first voltage signal V1. When the potential of the first node Q1 is an inactive level signal, the potential of the second node Q2 is an active level signal. At this time, the second terminal of the second output subunit 22 outputs the second voltage signal V2, and the second terminal of the first output subunit 21 does not output. That is, the output signal OUT of the shift register is the second voltage signal V2. Based on this, one of the first voltage signal V1 and the second voltage signal V2 is a high-level signal VGH, and the other is a low-level signal VGL. This further indicates that the output signal OUT of the shift register is either a high-level signal VGH or a low-level signal VGL. In other words, the level of the output signal OUT of the shift register can be switched.

[0055] Furthermore, the node voltage adjustment unit 30 is connected to the first node Q1. The node voltage adjustment unit 30 can adjust the potential of the first node Q1. For example, the node voltage adjustment unit 30 can maintain the potential of the first node Q1 at the effective level signal of the first output subunit 21 for at least a portion of the time when the potential of the second node Q2 is an invalid level signal. In a more easily understood way, by adding the node voltage adjustment unit 30, the potential of the first node Q1 can be appropriately raised for at least a portion of the time when the potential of the first node Q1 is the effective level signal of the first output subunit 21, making the potential of the first node Q1 more "effective" or ensuring "effectiveness" relative to the conduction process of the first output subunit 21. This avoids the inability to guarantee the conduction of the first output subunit 21 after the potential of the first node Q1 changes due to the formation of leakage paths and leakage current, thereby ensuring the stable output of the first voltage signal V1 corresponding to the output signal OUT. In this process, it also ensures that the second voltage signal V2 corresponding to the output signal OUT will not be output. Understandably, if the effective level signal of the first output subunit 21 is high, then the node voltage adjustment unit 30 needs to raise the potential of the first node Q1 to offset the decrease in the potential of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the first output subunit 21. Conversely, if the effective level signal of the first output subunit 21 is low, then the node voltage adjustment unit 30 needs to pull down the potential of the first node Q1 to offset the increase in the potential of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the first output subunit 21. Furthermore, after maintaining the potential of the first node Q1 at the effective level signal of the first output subunit 21, the first output subunit 21 can remain on, and the first voltage signal V1 corresponding to the first terminal of the first output subunit 21 can be continuously transmitted to the second terminal of the first output subunit 21. The shift register can stably output the first voltage signal V1, ensuring the stable output of the shift register's output signal OUT.

[0056] Optionally, Figure 5 yes Figure 4 The diagram shows a specific structure of the shift register in the driving circuit. Figure 6 yes Figure 5 The driving timing diagrams of each stage of the shift registers in the driving circuit are shown below. Figure 5 and Figure 6As shown, the effective level signal of the first node Q1 is a high level signal VGH, and the potential of the first node Q1 satisfies: U1'≤U1”; where U1' is the potential of the first node Q1 when the input signal IN is an effective level signal and the first clock signal CK1 switches to an effective level signal for the first time; U1” is the potential of the first node Q1 when the input signal IN is an effective level signal and the first clock signal CK1 is an ineffective level signal, or when the input signal IN switches from an effective level signal to an ineffective level signal and the first clock signal CK1 is an ineffective level signal.

[0057] Specifically, U1' is the potential of the first node Q1 when the input signal IN is an active level signal and the first clock signal CK1 switches to an active level signal for the first time. U1' can be understood as... Figure 6 The potential of the first node Q1 in stage t1 is shown. U1” represents the potential of the first node Q1 when the input signal IN is at an active level and the first clock signal CK1 is at an inactive level. U1” can be understood as... Figure 6 The potential of the first node Q1 in stage t2 is shown. At this time, U1' < U1", it can be clearly seen that the potential of the first node Q1 is raised, which cancels out the potential drop of the leakage current. During at least part of the time when the potential of the second node Q2 is an invalid level signal, the potential of the first node Q1 can be maintained at the level of the valid level signal of the first output sub-unit 21 to ensure the effective conduction of the first output sub-unit 21. Of course, when the potential of the first node Q1 is maintained at the level of the valid level signal of the first output sub-unit 21, U1' = U1". And, U1" is the potential of the first node Q1 in the stage when the input signal IN switches from an valid level signal to an invalid level signal and the first clock signal CK1 is an invalid level signal. U1" can also be understood as Figure 6 The potential of the first node Q1 in stage t3 is shown. At this time, U1' < U1", it can be clearly seen that the potential of the first node Q1 is raised, which cancels out the potential drop of the leakage current. During at least part of the time when the potential of the second node Q2 is an invalid level signal, the potential of the first node Q1 can be maintained at the level of the valid level signal of the first output sub-unit 21 to ensure the effective conduction of the first output sub-unit 21. Of course, when the potential of the first node Q1 is maintained at the level of the valid level signal of the first output sub-unit 21, U1' = U1 can also be used.

[0058] Alternatively, Figure 7 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit. Figure 8 yes Figure 7 The driving timing diagrams of each stage of the shift registers in the driving circuit are shown below. Figure 7 and Figure 8 As shown, the effective level signal of the first node Q1 is a low level signal VGL, and the potential of the first node Q1 satisfies: U1'≥U1”; where U1' is the potential of the first node Q1 when the input signal IN is an effective level signal and the first clock signal CK1 switches to an effective level signal for the first time; U1” is the potential of the first node Q1 when the input signal IN is an effective level signal and the first clock signal CK1 is an ineffective level signal, or when the input signal IN switches from an effective level signal to an ineffective level signal and the first clock signal CK1 is an ineffective level signal.

[0059] Specifically, the relevant content can be referred to in the above embodiments, and will not be repeated here. Figure 8 The statement "U1' < U1" clearly indicates that the potential of the first node Q1 is pulled low, offsetting the potential rise due to leakage current. For at least a portion of the time when the potential of the second node Q2 is an invalid signal, the potential of the first node Q1 can be maintained at the level of the valid signal of the first output sub-unit 21, ensuring the effective conduction of the first output sub-unit 21. Of course, when the potential of the first node Q1 is maintained at the level of the valid signal of the first output sub-unit 21, "U1' = U1" is also possible.

[0060] Optionally, continue to refer to Figure 5 and Figure 7 The control unit 10 includes a third node Q3, the potential of the third node Q3 and the potential of the second node Q2 are respectively a high-level signal VGH and a low-level signal VGL; the control terminal of the node voltage adjustment unit 30 is connected to the third node Q3 and is used to maintain the potential of the first node Q1 as the effective level signal of the first output subunit 21 for at least a part of the time when the potential of the third node Q3 is an effective level signal.

[0061] Specifically, the control terminal of the node voltage regulation unit 30 is connected to the third node Q3, and the node voltage regulation unit 30 is also connected to the first node Q1. Therefore, the potential of the third node Q3 can control the on / off state of the node voltage regulation unit 30, thereby affecting the potential of the first node Q1. For example, when the potential of the third node Q3 is a valid level signal, the node voltage regulation unit 30 is turned on accordingly. The node voltage regulation unit 30 can adjust the magnitude / level of the potential of the first node Q1 to maintain the potential of the first node Q1 at the level of the valid level signal of the first output subunit 21. Furthermore, if the potential of the third node Q3 is a high-level signal VGH and the potential of the second node Q2 is a low-level signal VGL, then when the potential of the third node Q3 is an active level signal, the potential of the second node Q2 is an inactive level signal and the potential of the first node Q1 is an active level signal. At this time, the second terminal of the first output subunit 21 outputs the first voltage signal V1, and the second terminal of the second output subunit 22 does not output. That is, the output signal OUT of the shift register is the first voltage signal V1. When the potential of the third node Q3 is an inactive level signal, the potential of the second node Q2 is an active level signal and the potential of the first node Q1 is an inactive level signal. At this time, the second terminal of the second output subunit 22 outputs the second voltage signal V2, and the second terminal of the first output subunit 21 does not output. That is, the output signal OUT of the shift register is the second voltage signal V2.

[0062] Optionally, continue to refer to Figure 5 and Figure 6 The effective level signal of the first node Q1 is a high level signal VGH. During the period when the first node Q1 is an effective level signal, U1≥U3; where U1 is the potential of the first node Q1 and U3 is the potential of the third node Q3.

[0063] Specifically, Figure 6 It is clear from stage t1 that U1 = U3. Figure 6 It is clear from stage t2 that U1 = U3. Figure 6 It is clear from stage t2 that U1 > U3. Figure 6 As can be clearly seen in stage t3, U1 = U3. It is understandable that when U1 ≥ U3, the potential of the first node Q1 is significantly raised, which can offset the decrease in the potential of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the first output sub-unit 21, so that the first output sub-unit 21 is effectively turned on, and the output signal OUT corresponding to the shift register stably outputs the first voltage signal V1.

[0064] Alternatively, you can continue to refer to Figure 7 and Figure 8The effective level signal of the first node Q1 is a low level signal VGL. During the period when the first node Q1 is an effective level signal, U1≤U3; where U1 is the potential of the first node Q1 and U3 is the potential of the third node Q3.

[0065] Specifically, the relevant content can be referred to in the above embodiments, and will not be repeated here. Figure 8 It is clear from stage t1 that U1 = U3. Figure 8 It is clear from stage t2 that U1 = U3. Figure 8 It is clear from stage t2 that U1 < U3. Figure 8 As can be clearly seen in stage t3, U1 = U3. It is understandable that when U1 ≤ U3, the potential of the first node Q1 is significantly lowered, which can offset the rise in the potential of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the first output sub-unit 21, so that the first output sub-unit 21 is effectively turned on, and the output signal OUT corresponding to the shift register stably outputs the first voltage signal V1.

[0066] Optionally, continue to refer to Figure 5 and Figure 7 The node voltage regulation unit 30 includes a first switching subunit 31, a second switching subunit 32, and a first energy storage subunit 33. The first terminal of the first switching subunit 31 receives a second clock signal CK2, and the second terminal is connected to the first terminal of the first energy storage subunit 33. The second terminal of the first energy storage subunit 33, the control terminal of the first switching subunit 31, and the first and control terminals of the second switching subunit 32 are connected to a fourth node Q4, which is connected to a third node Q3. The second terminal of the second switching subunit 32 is connected to the first node Q1. The second clock signal CK2 and the first clock signal CK1 are out of phase. The first switching subunit 31 and the second switching subunit 32 are turned on when the third node Q3 is a valid level signal. When the first clock signal CK1 is a valid level signal, the first energy storage subunit 33 receives the second clock signal CK2 to charge. When the first clock signal CK1 switches from a valid level signal to an invalid level signal, it discharges to the first node Q1 through the turned-on second switching subunit 32 to maintain the potential of the first node Q1.

[0067] Specifically, the first terminal of the first switching subunit 31 receives the second clock signal CK2, the second terminal of the first switching subunit 31 is connected to the first terminal of the first energy storage subunit 33, and the control terminal of the first switching subunit 31 is connected to the fourth node Q4. The fourth node Q4 is connected to the third node Q3. Therefore, the first switching subunit 31 can be turned on or off under the influence of the potential of the fourth node Q4, and the potential of the third node Q3 will also affect the potential of the fourth node Q4, and vice versa. For example, the first switching subunit 31 can be turned on when the third node Q3 is a valid level signal, at which time the fourth node Q4 is also a valid level signal. Furthermore, the first terminal of the second switch subunit 32 is connected to the fourth node Q4, the second terminal of the second switch subunit 32 is connected to the first node Q1, and the control terminal of the second switch subunit 32 is connected to the fourth node Q4. Therefore, the second switch subunit 32 can be turned on or off under the influence of the potential of the fourth node Q4. The potential of the third node Q3 also affects the potential of the fourth node Q4, and vice versa. For example, the second switch subunit 32 can be turned on when the third node Q3 is a valid level signal, at which time the fourth node Q4 is also a valid level signal.

[0068] The first terminal of the first energy storage sub-unit 33 is connected to the second terminal of the first switching sub-unit 31, and the second terminal of the first energy storage sub-unit 33 is connected to the fourth node Q4. The first energy storage sub-unit 33 can maintain a stable voltage across itself, meaning the voltage difference across it remains constant. The first energy storage sub-unit 33 can change the potential of the fourth node Q4 through the charging and discharging process, thereby changing the potential of the third node Q3. The second clock signal CK2 and the first clock signal CK1 are out of phase. When the first clock signal CK1 is an active level signal, the second clock signal CK2 is an inactive level signal. For example, when the first clock signal CK1 is an active level signal, the third node Q3 is also an active level signal, and both the first switching sub-unit 31 and the second switching sub-unit 32 are turned on. When the first clock signal CK1 is an inactive level signal, the third node Q3 is floating, and its potential remains in the previous state, meaning it is still an active level signal, and both the first switching sub-unit 31 and the second switching sub-unit 32 remain on. That is, the first energy storage sub-unit 33 can receive the second clock signal CK2 for charging when the first clock signal CK1 is an effective level signal. The first energy storage sub-unit 33 can also discharge to the first node Q1 through the activated second switch sub-unit 32 when the first clock signal CK1 switches from an effective level signal to an ineffective level signal, thereby maintaining the potential of the first node Q1. In other words, the potential of the first node Q1 is maintained through the discharge process of the first energy storage sub-unit 33, and the charging capacity of the first energy storage sub-unit 33 originates from the potential signal of the second clock signal CK2. For example, Figure 5 During the discharge process of the first energy storage sub-unit 33 shown, the potential of the first node Q1 is significantly raised, realizing the bootstrapping of the first node Q1. This cancels out the potential drop of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the first output sub-unit 21, thus enabling the first output sub-unit 21 to effectively conduct. The output signal OUT corresponding to the shift register stably outputs the first voltage signal V1. And, exemplarily, Figure 7 During the discharge process of the first energy storage sub-unit 33 shown, the potential of the first node Q1 is significantly lowered, realizing the bootstrapping of the first node Q1. This can offset the rising potential of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the first output sub-unit 21, so that the first output sub-unit 21 is effectively turned on, and the output signal OUT corresponding to the shift register stably outputs the first voltage signal V1.

[0069] Optionally, Figure 9 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit. Figure 10 yes Figure 9The driving timing diagrams of each stage of the shift registers in the driving circuit are shown below. Figure 9 and Figure 10 As shown, the node voltage regulation unit 30 also includes a third switch subunit 34, which is connected between the fourth node Q4 and the third node Q3; the control terminal of the third switch subunit 34 receives the first voltage signal V1.

[0070] Specifically, the control terminal of the third switching subunit 34 receives the first voltage signal V1. The first terminal of the third switching subunit 34 is connected to the fourth node Q4, and the second terminal of the third switching subunit 34 is connected to the third node Q3. Therefore, the third switching subunit 34 can be turned on or off under the influence of the potential of the first voltage signal V1. For example, if the first voltage signal V1 is a valid level signal, the third switching subunit 34 is normally open; if the first voltage signal V1 is an invalid level signal, the third switching subunit 34 is normally closed. For example, the third switching subunit 34 can also switch between normally open and normally closed states by reasonably adjusting the first voltage signal V1 to a high level signal VGH or a low level signal VGL. It is understood that the configuration of the third switching subunit 34 can effectively prevent leakage current from the fourth node Q4 towards the third node Q3 and other transistors, blocking the transmission of leakage current between the fourth node Q4 and the third node Q3.

[0071] Further reference Figure 5 and Figure 9 The first switching subunit 31 includes a first transistor T1, the second switching subunit 32 includes a second transistor T2, the third switching subunit 34 includes a third transistor T3, and the first energy storage subunit 33 includes a first capacitor C1. The first terminal of the first transistor T1 receives a second clock signal CK2, and the second terminal is connected to the first plate of the first capacitor C1. The second plate of the first capacitor C1, the gate of the first transistor T1, and the gate and first terminal of the second transistor T2 are all connected to the fourth node Q4. The second terminal of the second transistor T2 is connected to the first node Q1. The third transistor T3 is connected between the fourth node Q4 and the third node Q3. The first terminal of the third transistor T3 is connected to the fourth node Q4, the second terminal receives an input signal IN, and the gate receives a first voltage signal V1. The first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type.

[0072] The first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type. Optionally, the first transistor T1, the second transistor T2, and the third transistor T3 are all N-channel transistors. In this case, the effective level signals corresponding to the first transistor T1, the second transistor T2, and the third transistor T3 are all high level, and the first transistor T1, the second transistor T2, and the third transistor T3 can be turned on under the influence of a high level potential. The ineffective level signals corresponding to the first transistor T1, the second transistor T2, and the third transistor T3 are all low level, and the first transistor T1, the second transistor T2, and the third transistor T3 can be turned off under the influence of a low level potential. For example, the effective level signal of the third node Q3 and the fourth node Q4 can be a high level signal VGH, and the ineffective level signal of the third node Q3 and the fourth node Q4 can be a low level signal VGL. The effective level signal of the first clock signal CK1 can be a high level signal VGH, and the ineffective level signal of the first clock signal CK1 can be a low level signal VGL. Specifically, when the first clock signal CK1 is an active level signal, that is, when the first clock signal CK1 is high, the potentials of the third node Q3 and the fourth node Q4 can also be high. In this case, the first transistor T1 and the second transistor T2 are turned on, the third transistor T3 is normally open, and the first capacitor C1 can receive the second clock signal CK2 for charging. When the first clock signal CK1 switches from an active level signal to an inactive level signal, that is, when the first clock signal CK1 changes from high to low, the third node Q3 and the fourth node Q4 are floating. The potentials of the third node Q3 and the fourth node Q4 maintain the state of the previous stage, that is, the potentials of the third node Q3 and the fourth node Q4 are still high. The first transistor T1 and the second transistor T2 remain on. The first capacitor C1 can then discharge to the first node Q1 through the on-state second transistor T2 to raise the potential of the first node Q1 and maintain the conduction of the first output sub-unit 21.

[0073] In another specific embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type. Optionally, Figure 11 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit. Figure 12 yes Figure 11 The driving timing diagrams of each stage of the shift registers in the driving circuit are shown below. Figure 7 , Figure 11 and Figure 12 As shown, the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type channel transistors. Related details can be found in the above embodiment; they will not be repeated here.

[0074] Alternatively, Figure 13 yes Figure 4The diagram shows another specific structure of the shift register in the driving circuit, as follows: Figure 13 As shown, the node voltage regulation unit 30 also includes a third switch subunit 34, which is connected between the fourth node Q4 and the third node Q3; the control terminal of the third switch subunit 34 receives the first clock signal CK1.

[0075] Specifically, the control terminal of the third switching subunit 34 receives the first clock signal CK1. The first terminal of the third switching subunit 34 is connected to the fourth node Q4, and the second terminal of the third switching subunit 34 is connected to the third node Q3. Therefore, the third switching subunit 34 can be turned on or off under the influence of the potential of the first clock signal CK1. For example, if the first clock signal CK1 is a valid level signal, the third switching subunit 34 is normally open; if the first clock signal CK1 is an invalid level signal, the third switching subunit 34 is normally closed. For example, the third switching subunit 34 can switch between normally open and normally closed states depending on whether the first clock signal CK1 is valid or invalid. It is understood that the configuration of the third switching subunit 34 can effectively prevent leakage current from the fourth node Q4 towards the third node Q3 and other transistors, blocking the transmission of leakage current between the fourth node Q4 and the third node Q3.

[0076] Further reference Figure 5 and Figure 13 The first switching subunit 31 includes a first transistor T1, the second switching subunit 32 includes a second transistor T2, the third switching subunit 34 includes a third transistor T3, and the first energy storage subunit 33 includes a first capacitor C1. The first terminal of the first transistor T1 receives a second clock signal CK2, and the second terminal is connected to the first plate of the first capacitor C1. The second plate of the first capacitor C1, the gate of the first transistor T1, and the gate and first terminal of the second transistor T2 are all connected to the fourth node Q4. The second terminal of the second transistor T2 is connected to the first node Q1. The third transistor T3 is connected between the fourth node Q4 and the third node Q3. The first terminal of the third transistor T3 is connected to the fourth node Q4, the second terminal receives an input signal IN, and the gate receives the first clock signal CK1. The first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type.

[0077] The first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type. Optionally, all three transistors are N-channel transistors. Refer to the above embodiments for related details; they will not be repeated here. It should also be noted that when the first clock signal CK1 is active (i.e., when CK1 is high), the potentials of the third node Q3 and the fourth node Q4 can also be high. In this case, the first transistor T1 and the second transistor T2 are turned on, and the third transistor T3 is also turned on under the influence of the high level of the first clock signal CK1. The first capacitor C1 can then receive the second clock signal CK2 for charging. When the first clock signal CK1 switches from an active level to an inactive level, that is, when the first clock signal CK1 changes from a high level to a low level, the third node Q3 and the fourth node Q4 are floating. The potentials of the third node Q3 and the fourth node Q4 maintain the state of the previous stage, that is, the potentials of the third node Q3 and the fourth node Q4 are still at a high level. The first transistor T1 and the second transistor T2 remain on. Under the action of the low level of the first clock signal CK1, the third transistor T3 is turned off. Then, the first capacitor C1 can discharge to the first node Q1 through the on conducting second transistor T2 to raise the potential of the first node Q1 and keep the first output sub-unit 21 on. At this time, the turn-off of the third transistor T3 can make the potential of the fourth node Q4 more stable. The fourth node Q4 cannot form a leakage path to the third node Q3 through the third transistor T3. The first capacitor C1 can discharge to the first node Q1 through the fourth node Q4 and the second transistor T2, effectively reducing discharge loss and further stabilizing the potential of the first node Q1, ensuring the effective conduction of the first output sub-unit 21.

[0078] In another specific embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type. Optionally, Figure 14 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit, as follows: Figure 7 and Figure 14 As shown, the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type channel transistors. Related details can be found in the above embodiment; they will not be repeated here.

[0079] Optionally, Figure 15 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit, as follows: Figure 15As shown, the control terminal of the node voltage adjustment unit 30 receives the input signal IN and is used to maintain the potential of the first node Q1 at the effective level of the first output subunit 21 for at least the time when the potential of the input signal IN is an effective level signal and the first clock signal CK1 is an invalid level signal.

[0080] Specifically, the control terminal of the node voltage adjustment unit 30 receives the input signal IN. The node voltage adjustment unit 30 is also connected to the first node Q1. The node voltage adjustment unit 30 can adjust the potential of the first node Q1 according to the received input signal IN. For example, the node voltage adjustment unit 30 can maintain the potential of the first node Q1 at the effective level signal of the first output subunit 21 for at least the time when the potential of the input signal IN is an effective level signal and the first clock signal CK1 is an ineffective level signal. In a more easily understood way, by adding an additional node voltage adjustment unit 30, during the time when the input signal IN is at a valid level and the first clock signal CK1 is at an invalid level, the potential fluctuation of the first node Q1 caused by the first clock signal CK1 being at an invalid level can be reduced. This appropriately raises the potential of the first node Q1, making its potential more "effective" or ensuring its "effectiveness" relative to the conduction process of the first output subunit 21. This avoids the inability to guarantee the conduction of the first output subunit 21 after the potential of the first node Q1 changes due to leakage paths and leakage current, thereby ensuring the stable output of the first voltage signal V1 corresponding to the output signal OUT. During this process, it also ensures that the second voltage signal V2 corresponding to the output signal OUT will not be output. It can be understood that if the valid level signal of the first output subunit 21 can be high, then the node voltage adjustment unit 30 needs to raise the potential of the first node Q1 to offset the decrease in the potential of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the first output subunit 21. Conversely, if the effective level signal of the first output subunit 21 is also low, then the node voltage adjustment unit 30 needs to pull down the potential of the first node Q1 to cancel out the rising portion of the potential of the first node Q1 caused by leakage current, and maintain the potential of the first node Q1 at the potential level corresponding to the conduction of the first output subunit 21. Furthermore, after maintaining the potential of the first node Q1 at the effective level signal of the first output subunit 21, the first output subunit 21 can remain on, and the first voltage signal V1 corresponding to the first terminal of the first output subunit 21 can be continuously transmitted to the second terminal of the first output subunit 21. The shift register can stably output the first voltage signal V1, ensuring the stable output of the shift register's output signal OUT.

[0081] Optionally, continue to refer to Figure 15The node voltage regulation unit 30 includes a first switching subunit 31, a second switching subunit 32, a third switching subunit 34, and a first energy storage subunit 33. The first terminal of the first switching subunit 31 receives a second clock signal CK2, and its second terminal is connected to the first terminal of the first energy storage subunit 33. The second terminal of the first energy storage subunit 33, the control terminal of the first switching subunit 31, and the first and control terminals of the second switching subunit 32 are connected to the fourth node Q4. The second terminal of the second switching subunit 32 is connected to the first node Q1. The second clock signal CK2 and the first clock signal CK1 are inverted. The first terminal of the third switching subunit 34 is connected to the fourth node Q1. 4. Connection; the second terminal receives the input signal IN, and the control terminal of the third switch subunit 34 receives the first clock signal CK1; the third switch subunit 34 is turned on when the first clock signal CK1 is an effective level signal, and the first switch subunit 31 and the second switch subunit 32 are turned on when the input signal IN is an effective level signal; the first energy storage subunit 33 receives the second clock signal CK2 and the input signal IN at its two ends respectively when the first clock signal CK1 is an effective level signal, and discharges to the first node Q1 through the turned-on second switch subunit 32 to maintain the potential of the first node Q1.

[0082] Specifically, the first terminal of the third switch subunit 34 is connected to the fourth node Q4, the second terminal of the third switch subunit 34 receives the input signal IN, and the control terminal of the third switch subunit 34 receives the first clock signal CK1. Therefore, the third switch subunit 34 can be turned on or off under the potential of the first clock signal CK1. For example, the third switch subunit 34 can be turned on when the first clock signal CK1 is a valid level signal. At this time, the input signal IN corresponding to the second terminal of the third switch subunit 34 can be transmitted to the fourth node Q4, where the fourth node Q4 is the potential of the input signal IN. Also, the first terminal of the first switch subunit 31 receives the second clock signal CK2, the second terminal of the first switch subunit 31 is connected to the first terminal of the first energy storage subunit 33, and the control terminal of the first switch subunit 31 is connected to the fourth node Q4. Therefore, the first switch subunit 31 can be turned on or off under the potential of the fourth node Q4. For example, after the third switch subunit 34 is turned on, the first switch subunit 31 can also be turned on or off under the potential of the input signal IN. Furthermore, the first terminal of the second switch subunit 32 is connected to the fourth node Q4, the second terminal of the second switch subunit 32 is connected to the first node Q1, and the control terminal of the second switch subunit 32 is connected to the fourth node Q4. Therefore, the second switch subunit 32 can be turned on or off under the influence of the potential of the fourth node Q4. For example, after the third switch subunit 34 is turned on, the second switch subunit 32 can also be turned on or off under the influence of the potential of the input signal IN.

[0083] The first terminal of the first energy storage sub-unit 33 is connected to the second terminal of the first switching sub-unit 31, and the second terminal of the first energy storage sub-unit 33 is connected to the fourth node Q4. The first energy storage sub-unit 33 can maintain a stable voltage across itself, that is, the voltage difference across itself remains constant. The first energy storage sub-unit 33 can change the potential of the fourth node Q4 through the charging and discharging process. The second clock signal CK2 is out of phase with the first clock signal CK1. When the first clock signal CK1 is an active level signal, the second clock signal CK2 is an inactive level signal. For example, when the first clock signal CK1 is a valid level signal, the third switch subunit 34 is turned on, and when the input signal IN is a valid level signal, both the first switch subunit 31 and the second switch subunit 32 are turned on; when the first clock signal CK1 is an invalid level signal, the third switch subunit 34 is turned off, the fourth node Q4 is floating, and the potential of the fourth node Q4 maintains the state of the previous stage, that is, the fourth node Q4 is still a valid level signal, and both the first switch subunit 31 and the second switch subunit 32 remain on. In other words, when the first clock signal CK1 is a valid level signal, the first energy storage subunit 33 can receive the second clock signal CK2 and the input signal IN at its two ends for charging, respectively. When the first clock signal CK1 is an invalid level signal, the first energy storage subunit 33 can also discharge to the first node Q1 through the turned-on second switch subunit 32 to maintain the potential of the first node Q1. That is, the potential of the first node Q1 is maintained through the discharge process of the first energy storage sub-unit 33, and the charging capacity of the first energy storage sub-unit 33 comes from the potential signal of the second clock signal CK2 and the potential signal of the input signal IN. For example, Figure 15 During the discharge process of the first energy storage sub-unit 33 shown, the potential of the first node Q1 is significantly raised, realizing the bootstrapping of the first node Q1. This can offset the decrease in the potential of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the first output sub-unit 21, so that the first output sub-unit 21 is effectively turned on, and the output signal OUT corresponding to the shift register stably outputs the first voltage signal V1.

[0084] It should also be noted that continued reference... Figure 15In this embodiment, the control terminal of the node voltage regulation unit 30 receives the input signal IN, and a third switch subunit 34 is provided between the fourth node Q4 and the input signal IN. The third switch subunit 34 can be turned on or off according to the transition between the effective and ineffective levels of the first clock signal CK1, thereby ensuring that the first energy storage subunit 33 is charging when the third switch subunit 34 is on and discharging when the third switch subunit 34 is off, so as to maintain the potential of the first node Q1. If the third switch subunit 34 is not provided between the fourth node Q4 and the input signal IN, the potential of the fourth node Q4 will be completely synchronized with the potential change of the input signal IN, and the charging and discharging process of the first energy storage subunit 33 and the bootstrapping effect of the first node Q1 cannot be achieved, and the first output subunit 21 cannot be kept in an effective conducting state.

[0085] Further reference Figure 15 The first switching subunit 31 includes a first transistor T1, the second switching subunit 32 includes a second transistor T2, the third switching subunit 34 includes a third transistor T3, and the first energy storage subunit 33 includes a first capacitor C1. The first terminal of the first transistor T1 receives a second clock signal CK2, and the second terminal is connected to the first plate of the first capacitor C1. The second plate of the first capacitor C1, the gate of the first transistor T1, and the gate and first terminal of the second transistor T2 are all connected to the fourth node Q4. The second terminal of the second transistor T2 is connected to the first node Q1. The first terminal of the third transistor T3 is connected to the fourth node Q4, the second terminal receives an input signal IN, and the gate receives the first clock signal CK1. The first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type.

[0086] The first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type. Optionally, the first transistor T1, the second transistor T2, and the third transistor T3 are all N-channel transistors. In this case, the effective level signals corresponding to the first transistor T1, the second transistor T2, and the third transistor T3 are all high level, and the first transistor T1, the second transistor T2, and the third transistor T3 can be turned on under the influence of a high level potential. The ineffective level signals corresponding to the first transistor T1, the second transistor T2, and the third transistor T3 are all low level, and the first transistor T1, the second transistor T2, and the third transistor T3 can be turned off under the influence of a low level potential. For example, the effective level signal of the fourth node Q4 can be a high level signal VGH, and the ineffective level signal of the fourth node Q4 can be a low level signal VGL. The effective level signal of the first clock signal CK1 can be a high level signal VGH, and the ineffective level signal of the first clock signal CK1 can be a low level signal VGL. The effective level signal of the input signal IN can be a high level signal VGH, and the ineffective level signal of the input signal IN can be a low level signal VGL. Specifically, when the first clock signal CK1 is active (i.e., high), the third transistor T3 is turned on, and the input signal IN corresponding to the second terminal of the third transistor T3 can be transmitted to the fourth node Q4, which is the potential of the input signal IN. When the input signal IN is active (i.e., high), the first transistor T1 and the second transistor T2 are turned on, and the first capacitor C1 can receive the second clock signal CK2 and the input signal IN for charging. When the first clock signal CK1 is inactive (i.e., low), the fourth node Q4 is floating, and its potential remains in the previous state (high). The first transistor T1 and the second transistor T2 remain on, and the first capacitor C1 can discharge to the first node Q1 through the on-state second transistor T2, thereby raising the potential of the first node Q1 and maintaining the conduction of the first output sub-unit 21.

[0087] In another specific embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 have the same channel type. Optionally, Figure 16 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit, as follows: Figure 16 As shown, the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type channel transistors. Related details can be found in the above embodiment; they will not be repeated here.

[0088] Optionally, continue to refer to Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figures 13-16 The first output subunit 21 includes a fourth switching subunit 211 and a second energy storage subunit 212, and the second output subunit 22 includes a fifth switching subunit 221 and a third energy storage subunit 222. The first terminal of the fourth switching subunit 211 receives a first voltage signal V1, and the control terminal of the fourth switching subunit 211 and the first terminal of the second energy storage subunit 212 are both connected to a first node Q1. The first terminal of the fifth switching subunit 221 receives a second voltage signal V2, and the control terminal of the fifth switching subunit 221 and the first terminal of the third energy storage subunit 222 are both connected to a second node Q2. The second terminals of the fourth switching subunit 211, the second terminal of the second energy storage subunit 212, the second terminal of the fifth switching subunit 221, and the third energy storage subunit 222 are all connected to a second node Q2. The second terminals of unit 222 are interconnected and output an output signal OUT; the fourth switch subunit 211 is turned on when the first node Q1 is an effective level signal; the second energy storage subunit 212 is charged at least when the first clock signal CK1 is an effective level signal, and discharges to the first node Q1 when the first clock signal CK1 switches from an effective level signal to an ineffective level signal, so as to maintain the potential of the first node Q1; the fifth switch subunit 221 is turned on when the second node Q2 is an effective level signal; the third energy storage subunit 222 is charged at least when the first clock signal CK1 is an ineffective level signal, and discharges to the second node Q2 when the first clock signal CK1 switches from an ineffective level signal to an effective level signal, so as to maintain the potential of the second node Q2.

[0089] Specifically, the first output subunit 21 includes a fourth switching subunit 211 and a second energy storage subunit 212. The control terminal of the fourth switching subunit 211 is connected to the first node Q1. The first terminal of the fourth switching subunit 211 receives a first voltage signal V1, and the second terminal of the fourth switching subunit 211 can output an output signal OUT. Thus, the fourth switching subunit 211 can be turned on or off under the influence of the potential of the first node Q1. For example, the fourth switching subunit 211 can be turned on when the first node Q1 is at a valid level signal. The first voltage signal V1 corresponding to the first terminal of the fourth switching subunit 211 can be transmitted to the second terminal of the fourth switching subunit 211, that is, the second terminal of the fourth switching subunit 211 outputs the first voltage signal V1, and the output signal OUT of the shift register is the first voltage signal V1. Furthermore, the two ends of the second energy storage sub-unit 212 are respectively connected to the first node Q1 and the second end of the fourth switch sub-unit 211. The second energy storage sub-unit 212 can receive the input signal IN and / or the second clock signal CK2 for charging, at least when the first clock signal CK1 is an effective level signal. The second energy storage sub-unit 212 can also directly discharge to the first node Q1 when the first clock signal CK1 switches from an effective level signal to an ineffective level signal, so as to maintain the potential of the first node Q1. That is, the potential of the first node Q1 is maintained through the discharge process of the second energy storage sub-unit 212, and the charging capacity of the second energy storage sub-unit 212 comes from the potential signal of the input signal IN and / or the second clock signal CK2. For example, Figure 5 During the discharge process of the second energy storage sub-unit 212 shown, the potential of the first node Q1 is significantly raised, realizing the bootstrapping of the first node Q1. This cancels out the potential drop of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the fourth switching sub-unit 211, thus enabling the fourth switching sub-unit 211 to effectively conduct. The output signal OUT of the shift register stably outputs the first voltage signal V1. And, exemplarily, Figure 7 During the discharge process of the second energy storage sub-unit 212 shown, the potential of the first node Q1 is significantly pulled down, realizing the bootstrapping of the first node Q1. This can offset the rising potential of the first node Q1 caused by leakage current, maintaining the potential of the first node Q1 at the potential level corresponding to the conduction of the fourth switch sub-unit 211, so that the fourth switch sub-unit 211 is effectively turned on, and the output signal OUT corresponding to the shift register stably outputs the first voltage signal V1.

[0090] Similarly, the second output subunit 22 includes a fifth switching subunit 221 and a third energy storage subunit 222. The control terminal of the fifth switching subunit 221 is connected to the second node Q2. The first terminal of the fifth switching subunit 221 receives the second voltage signal V2, and the second terminal of the fifth switching subunit 221 can output an output signal OUT. Thus, the fifth switching subunit 221 can be turned on or off under the influence of the potential of the second node Q2. For example, the fifth switching subunit 221 can be turned on when the second node Q2 is at a valid level signal. The second voltage signal V2 corresponding to the first terminal of the fifth switching subunit 221 can be transmitted to the second terminal of the fifth switching subunit 221, that is, the second terminal of the fifth switching subunit 221 outputs the second voltage signal V2, and the output signal OUT of the shift register is the second voltage signal V2. Furthermore, the two ends of the third energy storage sub-unit 222 are respectively connected to the second node Q2 and the second end of the fifth switching sub-unit 221. The third energy storage sub-unit 222 can receive input signal IN, second clock signal CK2, and / or first clock signal CK1 for charging, at least when the first clock signal CK1 is an invalid level signal. The third energy storage sub-unit 222 can also directly discharge to the second node Q2 when the first clock signal CK1 switches from an invalid level signal to an valid level signal, so as to maintain the potential of the second node Q2. That is, the potential of the second node Q2 is maintained through the discharge process of the third energy storage sub-unit 222, and the charging capacity of the third energy storage sub-unit 222 comes from the potential signals of input signal IN, second clock signal CK2, and / or first clock signal CK1. For example, Figure 5 During the discharge process of the third energy storage sub-unit 222 shown, the potential of the second node Q2 is significantly raised, realizing the bootstrapping of the second node Q2. This cancels out the potential drop of the second node Q2 caused by leakage current, maintaining the potential of the second node Q2 at the potential level corresponding to the conduction of the fifth switching sub-unit 221, thus enabling the fifth switching sub-unit 221 to effectively conduct. The output signal OUT of the shift register stably outputs the second voltage signal V2. And, exemplarily, Figure 7 During the discharge process of the third energy storage sub-unit 222 shown, the potential of the second node Q2 is significantly pulled down, realizing the bootstrapping of the second node Q2. This can offset the rise in the potential of the second node Q2 caused by leakage current, maintaining the potential of the second node Q2 at the potential level corresponding to the conduction of the fifth switch sub-unit 221, so that the fifth switch sub-unit 221 is effectively turned on. The output signal OUT corresponding to the shift register stably outputs the second voltage signal V2.

[0091] It should also be noted that the second terminal of the fourth switch subunit 211 is connected to the second terminal of the fifth switch subunit 221 and outputs an output signal OUT. One of the potentials of the first node Q1 and the second node Q2 is a high-level signal VGH, and the other is a low-level signal VGL. When the potential of the first node Q1 is an effective level signal, the potential of the second node Q2 is an ineffective level signal. At this time, the second terminal of the first output subunit 21 outputs a first voltage signal V1, and the second terminal of the second output subunit 22 does not output anything. That is, the output signal OUT of the shift register is the first voltage signal V1. When the potential of the first node Q1 is an ineffective level signal, the potential of the second node Q2 is an effective level signal. At this time, the second terminal of the second output subunit 22 outputs a second voltage signal V2, and the second terminal of the first output subunit 21 does not output anything. That is, the output signal OUT of the shift register is the second voltage signal V2. That is, by reasonably setting the potential of the first node Q1 and the potential of the second node Q2, the on and off states of the fourth switch subunit 211 and the fifth switch subunit 221 are adjusted accordingly. On the one hand, it can be ensured that the output signal OUT of the shift register will not be interfered with by the two and will not be abnormally output. On the other hand, it can be ensured that the output signal OUT of the shift register can switch between a valid level signal and an invalid level signal. The driving timing of the input signal IN and the output signal OUT is not synchronized, so as to achieve a delayed and effective shift register effect.

[0092] Optionally, continue to refer to Figure 5 , Figure 9 , Figure 13 and Figure 15 The fourth switching subunit 211 includes a fourth transistor T4, and the second energy storage subunit 212 includes a second capacitor C2; the fifth switching subunit 221 includes a fifth transistor T5, and the third energy storage subunit 222 includes a third capacitor C3; the fourth transistor T4 and the fifth transistor T5 have the same channel type; the first electrode of the fourth transistor T4 receives a first voltage signal V1, and the gate of the fourth transistor T4 and the first plate of the second capacitor C2 are both connected to the first node Q1; the first electrode of the fifth transistor T5 receives a second voltage signal V2, and the gate of the fifth transistor T5 and the first plate of the third capacitor C3 are both connected to the second node Q2; the second electrode of the fourth transistor T4, the second plate of the second capacitor C2, the second electrode of the fifth transistor T5, and the second plate of the third capacitor C3 are interconnected and output an output signal OUT.

[0093] The fourth transistor T4 and the fifth transistor T5 have the same channel type. Optionally, both the fourth transistor T4 and the fifth transistor T5 are N-channel transistors. Therefore, the effective level signals corresponding to the fourth transistor T4 and the fifth transistor T5 are both high level, and the fourth transistor T4 and the fifth transistor T5 can be turned on under the influence of a high potential. The ineffective level signals corresponding to the fourth transistor T4 and the fifth transistor T5 are both low level, and the fourth transistor T4 and the fifth transistor T5 can be turned off under the influence of a low potential. For example, the effective level signals of the first node Q1 and the second node Q2 can be high level signals VGH, and the ineffective level signals of the first node Q1 and the second node Q2 can be low level signals VGL. The first voltage signal V1 can be high level signals VGH, the second voltage signal V2 can be low level signals VGL, the effective level signal of the first clock signal CK1 can be high level signals VGH, and the ineffective level signal of the first clock signal CK1 can be low level signals VGL. Specifically, when the first clock signal CK1 is an active level signal, that is, when the first clock signal CK1 is high, the potential of the first node Q1 can also be high. In this case, the fourth transistor T4 is turned on, and the high-level signal VGH corresponding to the first voltage signal V1 can be transmitted to the second terminal of the fourth transistor T4, outputting the output signal OUT. At this time, the output signal OUT is a high-level signal VGH, and the second capacitor C2 can be charged. Conversely, when the first clock signal CK1 is an active level signal, that is, when the first clock signal CK1 is high, the potential of the second node Q2 can also be low. In this case, the fifth transistor T5 is turned off. When the first clock signal CK1 switches from an active level signal to an inactive level signal, that is, when the first clock signal CK1 changes from a high level to a low level, the first node Q1 is floating, and the potential of the first node Q1 maintains the state of the previous stage, that is, the potential of the first node Q1 is still at a high level. The second capacitor C2 discharges to the first node Q1 to raise the potential of the first node Q1 to a high level, keeping the fourth transistor T4 on, and avoiding the drop in the potential of the first node Q1 due to leakage current, which would prevent the fourth transistor T4 from being unable to maintain its on state.

[0094] Furthermore, when the first clock signal CK1 is an invalid level signal, that is, when the first clock signal CK1 is at a low level, the potential of the second node Q2 can also be at a low level, then the fifth transistor T5 is turned off, and the third capacitor C3 can be charged. Also, when the first clock signal CK1 is an invalid level signal, that is, when the first clock signal CK1 is at a low level, the potential of the first node Q1 can also be at a high level, then the fourth transistor T4 is turned on. When the first clock signal CK1 switches from an invalid level signal to an valid level signal, that is, when the first clock signal CK1 changes from a low level to a high level, the second node Q2 is floated, and the potential of the second node Q2 maintains the state of the previous stage, that is, the potential of the second node Q2 is still at a low level, and the third capacitor C3 discharges to the second node Q2 to maintain the potential of the second node Q2, keeping the fifth transistor T5 off, and preventing the potential of the second node Q2 from changing due to leakage current, thus ensuring the off state of the fifth transistor T5.

[0095] In yet another specific embodiment, the fourth transistor T4 and the fifth transistor T5 have the same channel type. Optionally, refer to... Figure 7 , Figure 11 , Figure 14 and Figure 16 The fourth transistor T4 and the fifth transistor T5 are both P-type channel transistors. The first voltage signal V1 is a low-level signal VGL, and the second voltage signal V2 is a high-level signal VGH. Related details can be found in the above embodiment, and will not be repeated here.

[0096] Optionally, continue to refer to Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figures 13-16The control unit 10 includes a sixth switch subunit 11, a seventh switch subunit 12, an eighth switch subunit 13, a ninth switch subunit 14, a tenth switch subunit 15, and a fourth energy storage subunit 16. The first terminal of the sixth switch subunit 11 is connected to the control terminal of the seventh switch subunit 12 and receives the input signal IN. The second terminal of the sixth switch subunit 11, the first terminal of the eighth switch subunit 13, and the control terminal of the ninth switch subunit 14 are connected to the third node Q3. The control terminal of the sixth switch subunit 11 receives the first clock signal CK1. The first terminal of the seventh switch subunit 12 receives the second voltage signal V2. The second terminal of the seventh switch subunit 12, the control terminal of the tenth switch subunit 15, and the first terminal of the fourth energy storage subunit 16 are connected to the fifth node Q5. The eighth switch subunit 13's... The first terminal of the eighth switch subunit 13 is connected to the first node Q1. The control terminal of the eighth switch subunit 13 receives the first voltage signal V1. The first terminal of the ninth switch subunit 14 receives the second voltage signal V2. The second terminal of the ninth switch subunit 14 and the first terminal of the tenth switch subunit 15 are connected to the second node Q2. The second terminal of the tenth switch subunit 15 is connected to the second terminal of the fourth energy storage subunit 16. The sixth switch subunit 11 is turned on when the first clock signal CK1 is an effective level signal. The seventh switch subunit 12 is turned on when the input signal IN is an effective level signal. The fourth energy storage subunit 16 is used to receive the second voltage signal V2 for charging when the input signal IN is an effective level signal, and to discharge to the fifth node Q5 when the input signal IN switches from an effective level signal to an ineffective level signal, so as to maintain the potential of the fifth node Q5.

[0097] Specifically, the control terminal of the sixth switch subunit 11 receives the first clock signal CK1, the first terminal of the sixth switch subunit 11 receives the input signal IN, and the second terminal of the sixth switch subunit 11 is connected to the third node Q3. Thus, the sixth switch subunit 11 can be turned on or off under the influence of the potential of the first clock signal CK1. For example, the sixth switch subunit 11 can be turned on when the first clock signal CK1 is a valid level signal, and the input signal IN corresponding to the first terminal of the sixth switch subunit 11 can be transmitted to the third node Q3. Similarly, the control terminal of the eighth switch subunit 13 receives the first voltage signal V1, the first terminal of the eighth switch subunit 13 is connected to the third node Q3, and the second terminal of the eighth switch subunit 13 is connected to the first node Q1. Thus, the eighth switch subunit 13 can be turned on or off under the influence of the potential of the first voltage signal V1. For example, the eighth switch subunit 13 can be turned on when the first voltage signal V1 is a valid level signal. The eighth switch subunit 13 can be understood as normally open. The input signal IN corresponding to the first terminal of the sixth switch subunit 11 can be transmitted to the first node Q1 via the third node Q3 and the eighth switch subunit 13, so that the first output subunit 21 can be turned on or off according to the potential of the input signal IN, thereby controlling the output signal OUT of the shift register. Furthermore, the control terminal of the ninth switch subunit 14 is connected to the third node Q3, the first terminal of the ninth switch subunit 14 receives the second voltage signal V2, and the second terminal of the ninth switch subunit 14 is connected to the second node Q2. Thus, the ninth switch subunit 14 can be turned on or off under the influence of the potential of the third node Q3. For example, the ninth switch subunit 14 can be turned on when the third node Q3 is a valid level signal. The input signal IN corresponding to the first terminal of the sixth switch subunit 11 can be transmitted to the second node Q2 via the third node Q3 and the ninth switch subunit 14, so that the second output subunit 22 can be turned on or off according to the potential of the input signal IN, thereby controlling the output signal OUT of the shift register.

[0098] The control terminal of the seventh switch subunit 12 receives the input signal IN, the first terminal of the seventh switch subunit 12 receives the second voltage signal V2, and the second terminal of the seventh switch subunit 12 is connected to the fifth node Q5. Thus, the seventh switch subunit 12 can be turned on or off under the influence of the potential of the input signal IN. For example, the seventh switch subunit 12 can be turned on when the input signal IN is a valid level signal, and the second voltage signal V2 corresponding to the first terminal of the seventh switch subunit 12 can be transmitted to the fifth node Q5. Furthermore, the control terminal of the tenth switch subunit 15 is connected to the fifth node Q5, the first terminal of the tenth switch subunit 15 is connected to the second node Q2, and the two ends of the fourth energy storage subunit 16 are respectively connected to the fifth node Q5 and the second terminal of the tenth switch subunit 15. Thus, the tenth switch subunit 15 can be turned on or off under the influence of the potential of the fifth node Q5. For example, the tenth switch subunit 15 can be turned on when the fifth node Q5 is a valid level signal. The capacitor storage signal corresponding to the second terminal of the tenth switch subunit 15 can be transmitted to the second node Q2 so that the second output subunit 22 can be turned on or off according to the potential of the input signal IN, thereby controlling the output signal OUT of the shift register.

[0099] Understandably, when the input signal IN is at a valid level, the seventh switch subunit 12 is turned on, and the second voltage signal V2 corresponding to the first terminal of the seventh switch subunit 12 can be transmitted to one terminal of the fourth energy storage subunit 16, allowing the fourth energy storage subunit 16 to receive the second voltage signal V2 for charging. When the input signal IN switches from a valid level to an invalid level, the seventh switch subunit 12 is turned off, and the second voltage signal V2 corresponding to the first terminal of the seventh switch subunit 12 cannot be transmitted to one terminal of the fourth energy storage subunit 16. Therefore, the fourth energy storage subunit 16 can maintain the state of the previous stage and discharge to the fifth node Q5 to maintain the potential of the fifth node Q5. The connection node between the second terminal of the seventh switch subunit 12 and one terminal of the fourth energy storage subunit 16 is the fifth node Q5. That is, the fourth energy storage sub-unit 16 can receive the second voltage signal V2 for charging when the input signal IN is an active level signal. The fourth energy storage sub-unit 16 can also discharge to the fifth node Q5 when the input signal IN switches from an active level signal to an inactive level signal, thereby maintaining the potential of the fifth node Q5. In other words, the potential of the fifth node Q5 is maintained through the discharge process of the fourth energy storage sub-unit 16, and the charging capacity of the fourth energy storage sub-unit 16 originates from the potential signal of the second voltage signal V2. Furthermore, the potential of the second node Q2 can be maintained accordingly through the potential of the fifth node Q5, causing the second output sub-unit 22 to remain off or on, thereby controlling the output signal OUT of the shift register.

[0100] Optionally, continue to refer to Figure 5 , Figure 9 , Figure 13 and Figure 15 The sixth switching subunit 11 includes a sixth transistor T6, the seventh switching subunit 12 includes a seventh transistor T7, the eighth switching subunit 13 includes an eighth transistor T8, the ninth switching subunit 14 includes a ninth transistor T9, the tenth switching subunit 15 includes a tenth transistor T10, and the fourth energy storage subunit 16 includes a fourth capacitor C4; the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 have the same channel type; the first terminal of the sixth transistor T6 and the gate of the seventh transistor T7 are connected and receive the input signal IN, and the second terminal of the sixth transistor T6, the first terminal of the eighth transistor T8, and the ninth transistor T10 are connected... The gate of transistor T9 is connected to the third node Q3, and the gate of the sixth transistor T6 receives the first clock signal CK1; the first terminal of the seventh transistor T7 receives the second voltage signal V2, and the second terminal of the seventh transistor T7, the gate of the tenth transistor T10, and the first plate of the fourth capacitor C4 are connected to the fifth node Q5; the second terminal of the eighth transistor T8 is connected to the first node Q1, and the gate of the eighth transistor T8 receives the first voltage signal V1; the first terminal of the ninth transistor T9 receives the second voltage signal V2, and the second terminal of the ninth transistor T9 and the first terminal of the tenth transistor T10 are connected to the second node Q2; the second terminal of the tenth transistor T10 is connected to the second plate of the fourth capacitor C4.

[0101] The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 have the same channel type. Optionally, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all N-channel transistors. In this case, the effective level signals corresponding to the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all high level, and the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be turned on under the influence of a high level potential. The ineffective level signals corresponding to the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all low level, and the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be turned off under the influence of a low level potential. For example, the effective level signals of the first node Q1, the second node Q2, the third node Q3, and the fifth node Q5 can be high level signals VGH, and the ineffective level signals of the first node Q1, the second node Q2, the third node Q3, and the fifth node Q5 can be low level signals VGL. The first voltage signal V1 can be high level signals VGH, the second voltage signal V2 can be low level signals VGL, the effective level signal of the first clock signal CK1 can be high level signals VGH, the ineffective level signal of the first clock signal CK1 can be low level signals VGL, the effective level signal of the input signal IN can be high level signals VGH, and the ineffective level signal of the input signal IN can be low level signals VGL. Specifically, when the first clock signal CK1 is active and the input signal IN is active (i.e., when both are high), the sixth transistor T6 is turned on, the potential of the third node Q3 is high, the eighth transistor T8 is normally open, and the potential of the first node Q1 is also high. Therefore, the first output sub-unit 21 is turned on, and its second terminal outputs the first voltage signal V1. This means the output signal OUT of the shift register is the first voltage signal V1, which is also the high-level output signal VGH of the shift register. Simultaneously, when the input signal IN is active (i.e., high), the seventh transistor T7 is turned on, the potential of the fifth node Q5 is low, and the fourth capacitor C4 receives the second voltage signal V2 for charging. Furthermore, when the input signal IN switches from an active level signal to an inactive level signal, that is, when the input signal IN changes from a high level to a low level, the seventh transistor T7 is turned off, the fifth node Q5 is floated, the potential of the fifth node Q5 maintains the state of the previous stage, that is, the potential of the fifth node Q5 is still low, and the fourth capacitor C4 discharges to the fifth node Q5 to maintain the potential of the fifth node Q5, thereby keeping the seventh transistor T7 stably turned off.Subsequently, the potential of the second node Q2 can be adjusted according to the conduction or deactivation of the ninth transistor T9. When the potential of the first node Q1 is high, the ninth transistor T9 is turned on, and the potential of the second node Q2 is the low-level signal VGL corresponding to the second voltage signal V2. Then the second output sub-unit 22 is turned off, and the second terminal of the second output sub-unit 22 will not output the second voltage signal V2. The output of this shift register can be determined according to the conduction or deactivation state of the first output sub-unit 21.

[0102] In yet another specific embodiment, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 have the same channel type. Optionally, refer to... Figure 7 , Figure 11 , Figure 14 and Figure 16 The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all P-type channel transistors. Related details can be found in the above embodiments, and will not be repeated here.

[0103] Optionally, Figure 17 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit. Figure 18 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit, as follows: Figure 17 and Figure 18 As shown, the sixth switch subunit 11 also includes an eleventh transistor T11, which has the same channel type as the sixth transistor T6; the first terminal of the eleventh transistor T11 is connected to the second terminal of the sixth transistor T6, and the second terminal is connected to the third node Q3. The eleventh transistor T11 receives the first clock signal CK1.

[0104] Specifically, the sixth switching subunit 11 includes a sixth transistor T6 and an eleventh transistor T11. The first terminal of the sixth transistor T6 receives the input signal IN, the second terminal of the sixth transistor T6 is connected to the first terminal of the eleventh transistor T11, the second terminal of the eleventh transistor T11 is connected to the third node Q3, and the gate of the sixth transistor T6 is connected to the gate of the eleventh transistor T11 and receives the first clock signal CK1. That is, the sixth transistor T6 and the eleventh transistor T11 form a dual-gate transistor, which can further prevent the first node Q1 from forming a leakage path through the third node Q3, the eleventh transistor T11, and the sixth transistor T6. This avoids the leakage current from causing the potential of the first node Q1 to fail to be maintained, thereby leading to abnormal output of the first output subunit 21 and the output signal OUT. In addition, the eleventh transistor T11 and the sixth transistor T6 have the same channel type. For example, Figure 17Both the eleventh transistor T11 and the sixth transistor T6 shown are N-channel transistors. Figure 18 The eleventh transistor T11 and the sixth transistor T6 shown are both P-type channel transistors.

[0105] Optionally, Figure 19 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit. Figure 20 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit, as follows: Figure 19 and Figure 20 As shown, the sixth switch sub-unit 11 also includes a twelfth transistor T12, which has the same channel type as the sixth transistor T6; the second terminal of the sixth transistor T6 and the first terminal of the eleventh transistor T11 are connected to the sixth node Q6, and the first terminal of the twelfth transistor T12 is connected to the sixth node Q6; the second terminal of the twelfth transistor T12 receives the first voltage signal V1, and its gate is connected to the third node Q3.

[0106] Specifically, the sixth switching subunit 11 includes a sixth transistor T6, an eleventh transistor T11, and a twelfth transistor T12. The second terminal of the sixth transistor T6, the first terminal of the eleventh transistor T11, and the first terminal of the twelfth transistor T12 are interconnected and connected to the sixth node Q6. The second terminal of the twelfth transistor T12 receives the first voltage signal V1, and the gate of the twelfth transistor T12 is connected to the third node Q3. Thus, the twelfth transistor T12 can be turned on or off under the influence of the potential of the third node Q3. It is understood that if the voltage difference between the third node Q3 and the sixth node Q6 is too large, a leakage path is easily formed between the third node Q3 and the sixth node Q6. At this time, the setting of the twelfth transistor T12, after the eleventh transistor T11 is turned off, can reduce the voltage difference between the third node Q3 and the sixth node Q6, further preventing the first node Q1 from forming a leakage path through the third node Q3, the eleventh transistor T11, and the sixth transistor T6, thereby causing abnormalities in the output of the first output subunit 21 and the output signal OUT. Furthermore, the twelfth transistor T12 has the same channel type as the sixth transistor T6, for example, Figure 19 The sixth transistor T6, the eleventh transistor T11, and the twelfth transistor T12 shown are all N-channel transistors, and Figure 19 The first voltage signal V1 shown is a high-level signal VGH. Figure 19 The active level signals of the first node Q1 and the third node Q3 shown are also high. Figure 20 The sixth transistor T6, the eleventh transistor T11, and the twelfth transistor T12 shown are all P-type channel transistors, and Figure 20The first voltage signal V1 shown is a low-level signal VGL. Figure 20 The effective level signals of the first node Q1 and the third node Q3 shown are also low.

[0107] Alternatively, Figure 21 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit. Figure 22 yes Figure 4 The diagram shows another specific structure of the shift register in the driving circuit, as follows: Figure 21 and Figure 22 As shown, the sixth switch sub-unit 11 also includes a twelfth transistor T12, which has the same channel type as the sixth transistor T6; the second terminal of the sixth transistor T6 and the first terminal of the eleventh transistor T11 are connected to the sixth node Q6, and the first terminal of the twelfth transistor T12 is connected to the sixth node Q6; the second terminal of the twelfth transistor T12 receives the third voltage signal V3, and its gate is connected to the first node Q1.

[0108] Specifically, the sixth switching subunit 11 includes a sixth transistor T6, an eleventh transistor T11, and a twelfth transistor T12. The second terminal of the sixth transistor T6, the first terminal of the eleventh transistor T11, and the first terminal of the twelfth transistor T12 are interconnected and connected to the sixth node Q6. The second terminal of the twelfth transistor T12 receives the third voltage signal V3, and the gate of the twelfth transistor T12 is connected to the first node Q1. Thus, the twelfth transistor T12 can be turned on or off under the potential of the first node Q1. It is understood that if the voltage difference between the first node Q1 and the sixth node Q6 is too large, a leakage path is easily formed between the first node Q1 and the sixth node Q6. At this time, the setting of the twelfth transistor T12, after the eleventh transistor T11 is turned off, can reduce the voltage difference between the first node Q1 and the sixth node Q6, further preventing the first node Q1 from forming a leakage path through the third node Q3, the eleventh transistor T11, and the sixth transistor T6, thereby causing abnormalities in the output of the first output subunit 21 and the output signal OUT.

[0109] Furthermore, the twelfth transistor T12 has the same channel type as the sixth transistor T6, for example, Figure 21 The sixth transistor T6, the eleventh transistor T11, and the twelfth transistor T12 shown are all N-channel transistors, and Figure 21 The third voltage signal V3 shown can be interpreted as HVGH. Figure 21 The potential of the third voltage signal V3 shown is greater than Figure 19 The potential of the first voltage signal V1 shown. Figure 21The effective level signals of the first node Q1 and the third node Q3 shown are also high. In some embodiments, the potential of the third voltage signal V3 is higher, so that the voltages of the sixth node Q6 and the first node Q1 are both higher than the voltage of the control terminal of the eleventh transistor T11. According to the conduction condition Vg > Vs of the N-channel transistor, it can be known that the eleventh transistor T11 will be completely turned off, thereby better maintaining the high voltage state of the first node Q1, and thus maintaining the output of the first output sub-unit 21 corresponding to the first node Q1. That is, the output signal OUT of the shift register is the potential signal corresponding to the first voltage signal V1. The stable output of the output signal OUT of the shift register can also improve the display quality of the display panel. In addition, the twelfth transistor T12 has the same channel type as the sixth transistor T6. For example, Figure 22 The sixth transistor T6, the eleventh transistor T11, and the twelfth transistor T12 shown are all P-type channel transistors, and Figure 22 The third voltage signal V3 shown can be understood as LVGL. Figure 22 The potential of the third voltage signal V3 shown is less than Figure 20 The potential of the first voltage signal V1 shown. Figure 22 The effective level signals of the first node Q1 and the third node Q3 shown are also low. In some embodiments, the potential of the third voltage signal V3 is low, so that the voltages of the sixth node Q6 and the first node Q1 are both lower than the voltage of the control terminal of the eleventh transistor T11. According to the conduction condition Vg < Vs of the P-type channel transistor, it can be known that the eleventh transistor T11 will be completely turned off, thereby better maintaining the low voltage state of the first node Q1, and thus maintaining the output of the first output sub-unit 21 corresponding to the first node Q1. That is, the output signal OUT of the shift register is the potential signal corresponding to the first voltage signal V1. The stable output of the output signal OUT of the shift register can also improve the display quality of the display panel.

[0110] Based on the detailed description of the specific structures of the control unit 10, output unit 20, and node voltage adjustment unit 30 described above, please refer to... Figure 5 and Figure 6Here is an example illustrating a specific driving process of the driving circuit 100. In stage t1, the first clock signal CK1 is high, at which time the sixth transistor T6 is turned on, and the high level corresponding to the input signal IN can be transmitted to the third node Q3. The eighth transistor T8 is normally open, so the potential of the third node Q3 and the first node Q1 are both high. At this time, the fourth transistor T4 is turned on, and the high-level signal VGH corresponding to the first terminal of the fourth transistor T4 can be transmitted to the second terminal of the fourth transistor T4, meaning the output signal OUT of the shift register is high. Simultaneously, the potential of the third node Q3 is high, and both the first transistor T1 and the second transistor T2 are turned on. The second clock signal CK2 corresponding to the first terminal of the first transistor T1 can be transmitted to the second terminal of the first transistor T1, causing the first capacitor C1 to charge. Also, the input signal IN is high, at which time the seventh transistor T7 is turned on, and the low-level signal VGL corresponding to the first terminal of the seventh transistor T7 can be transmitted to the fifth node Q5. At this time, the tenth transistor T10 is turned off. Furthermore, the potential of the third node Q3 is high, at which time the ninth transistor T9 is turned on, and the low-level signal VGL corresponding to the first terminal of the ninth transistor T9 can be transmitted to the second node Q2, at which time the fifth transistor T5 is turned off.

[0111] In stage s2, when the first clock signal CK1 is low, the sixth transistor T6 is off, and the high level corresponding to the input signal IN cannot be transmitted to the third node Q3. Simultaneously, the first capacitor C1 is regulated to the potential of the previous stage, maintaining a constant voltage difference across itself, ensuring that the potential of the third node Q3 remains high. The second transistor T2 remains on, and the energy stored in the first capacitor C1 can discharge to the first node Q1 via the second transistor T2, raising the potential of Q1. At this time, the fourth transistor T4 continues to conduct, and the high-level signal VGH corresponding to the first terminal of the fourth transistor T4 can be transmitted to the second terminal of the fourth transistor T4. This means that the output signal OUT of the shift register remains high, ensuring the stability of the output signal OUT. Furthermore, when the input signal IN is high, the seventh transistor T7 is on, and the low-level signal VGL corresponding to the first terminal of the seventh transistor T7 can be transmitted to the fifth node Q5. At this time, the tenth transistor T10 is off. Furthermore, with the eighth transistor T8 normally open, the potentials of the third node Q3 and the first node Q1 remain high. At this time, the ninth transistor T9 is turned on, and the low-level signal VGL corresponding to the first terminal of the ninth transistor T9 can be transmitted to the second node Q2. Meanwhile, the fifth transistor T5 is turned off and will not output, thus not affecting the high-level output of the shift register's output signal OUT. In stage s2, when the first clock signal CK1 is high, the sixth transistor T6 is turned on, and the high-level signal IN corresponding to the input signal can be transmitted to the third node Q3. With the eighth transistor T8 normally open, the potentials of the third node Q3 and the first node Q1 are both high. The second capacitor C2 can also be regulated to the potential of the previous stage. The second capacitor C2 discharges the first node Q1, maintaining its potential. At this time, the fourth transistor T4 is turned on, and the high-level signal VGH corresponding to the first terminal of the fourth transistor T4 can be transmitted to the second terminal of the fourth transistor T4, meaning the shift register's output signal OUT continues to be a high-level output.

[0112] In stage s3, the first clock signal CK1 is low. At this time, the sixth transistor T6 is turned off, and the high level corresponding to the input signal IN cannot be transmitted to the third node Q3. Meanwhile, the first capacitor C1 is regulated to the potential of the previous stage, so that the potential of the third node Q3 remains high. The second transistor T2 is still conducting, and the electrical energy stored in the first capacitor C1 can be discharged to the first node Q1 through the second transistor T2, raising the potential of the first node Q1. At this time, the fourth transistor T4 continues to conduct, and the high level signal VGH corresponding to the first terminal of the fourth transistor T4 can be transmitted to the second terminal of the fourth transistor T4. That is, the output signal OUT of the shift register is still high. Furthermore, when the input signal IN is low, the seventh transistor T7 is off. The low-level signal VGL corresponding to the first terminal of the seventh transistor T7 cannot be transmitted to the fifth node Q5. The fourth capacitor C4 can be charged according to the first clock signal CK1 and discharged to the fifth node Q5. However, since the fourth capacitor C4 is regulated at the potential of the previous stage, the high or low level of the first clock signal CK1 is irrelevant. At this time, the tenth transistor T10 remains off. Also, the eighth transistor T8 is normally open, and the potentials of the third node Q3 and the first node Q1 are both high. At this time, the ninth transistor T9 is on, and the low-level signal VGL corresponding to the first terminal of the ninth transistor T9 can be transmitted to the second node Q2. Simultaneously, the third capacitor C3 is regulated at the potential of the previous stage, keeping the potential of the second node Q2 low. At this time, the fifth transistor T5 is off.

[0113] In stage s4, when the first clock signal CK1 is high, the sixth transistor T6 is turned on, and the low level corresponding to the input signal IN can be transmitted to the third node Q3. The fifth transistor T5 is normally open, so the potentials of the third node Q3 and the first node Q1 are both low. At this time, the sixth transistor T6 is turned off. Also, when the input signal IN is low, the seventh transistor T7 is turned off, and the low level signal VGL corresponding to the first terminal of the seventh transistor T7 cannot be transmitted to the fifth node Q5. However, the fourth capacitor C4 is regulated to the potential of the previous stage, which is the potential of the first clock signal CK1. Therefore, the potential of the fifth node Q5 is the high level corresponding to the first clock signal CK1, and the tenth transistor T10 is turned on. The high level corresponding to the first clock signal CK1 can be transmitted to the second node Q2. At this time, the fifth transistor T5 is turned on, and the low level signal VGL corresponding to the first terminal of the fifth transistor T5 can be transmitted to the second terminal of the fifth transistor T5. That is, the output signal OUT of the shift register is low. In stage s4, when the first clock signal CK1 is low, the sixth transistor T6 is turned off, and the low level corresponding to the input signal IN cannot be transmitted to the third node Q3. Simultaneously, the second capacitor C2 is regulated to the potential of the previous stage, keeping the potential of the first node Q1 low. The sixth transistor T6 remains off. Also, when the input signal IN is low, the seventh transistor T7 is turned off, and the low level signal VGL corresponding to the first terminal of the seventh transistor T7 cannot be transmitted to the fifth node Q5. However, the first capacitor C1 is still regulated to the potential of the previous stage, i.e., the potential of the first clock signal CK1. Therefore, the potential of the fifth node Q5 is the low level corresponding to the first clock signal CK1, and the tenth transistor T10 is turned off. At this time, the voltage of the third capacitor C3 is regulated to the potential of the previous stage. The third capacitor C3 discharges the second node Q2 to maintain the potential of the second node Q2, so that the potential of the second node Q2 remains at a high level. At this time, the fifth transistor T5 continues to conduct. The low-level signal VGL corresponding to the first terminal of the fifth transistor T5 can be transmitted to the second terminal of the fifth transistor T5, that is, the output signal OUT of the shift register is low.

[0114] Similarly, continue to refer to Figure 7 and Figure 8Here is an example illustrating another specific driving process of the driving circuit 100. In stage t1, the first clock signal CK1 is low. At this time, the sixth transistor T6 is turned on, and the low level corresponding to the input signal IN can be transmitted to the third node Q3. The eighth transistor T8 is normally open, so the potential of the third node Q3 and the first node Q1 are both low. At this time, the fourth transistor T4 is turned on, and the low level signal VGL corresponding to the first terminal of the fourth transistor T4 can be transmitted to the second terminal of the fourth transistor T4, meaning the output signal OUT of the shift register is low. Simultaneously, the potential of the third node Q3 is low, and both the first transistor T1 and the second transistor T2 are turned on. The second clock signal CK2 corresponding to the first terminal of the first transistor T1 can be transmitted to the second terminal of the first transistor T1, causing the first capacitor C1 to charge. Also, the input signal IN is low, and the seventh transistor T7 is turned on. The high level signal VGH corresponding to the first terminal of the seventh transistor T7 can be transmitted to the fifth node Q5, and the tenth transistor T10 is turned off. Furthermore, when the potential of the third node Q3 is low, the ninth transistor T9 is turned on, and the high-level signal VGH corresponding to the first terminal of the ninth transistor T9 can be transmitted to the second node Q2. At this time, the fifth transistor T5 is turned off.

[0115] In stage s2, when the first clock signal CK1 is high, the sixth transistor T6 is off, and the low level corresponding to the input signal IN cannot be transmitted to the third node Q3. Simultaneously, the first capacitor C1 is regulated to the potential of the previous stage, maintaining a constant voltage difference across itself, thus keeping the potential of the third node Q3 low. The second transistor T2 remains on, and the energy stored in the first capacitor C1 discharges through the second transistor T2 to the first node Q1, pulling down its potential. At this time, the fourth transistor T4 continues to conduct, and the low-level signal VGL corresponding to the first terminal of the fourth transistor T4 can be transmitted to the second terminal of the fourth transistor T4. This means the output signal OUT of the shift register remains low, ensuring the stability of the output signal OUT. Furthermore, when the input signal IN is low, the seventh transistor T7 is on, and the high-level signal VGH corresponding to the first terminal of the seventh transistor T7 can be transmitted to the fifth node Q5. At this time, the tenth transistor T10 is off. Furthermore, with the eighth transistor T8 normally open, the potentials of the third node Q3 and the first node Q1 remain low. At this time, the ninth transistor T9 is turned on, and the high-level signal VGH corresponding to the first terminal of the ninth transistor T9 can be transmitted to the second node Q2. Meanwhile, the fifth transistor T5 is turned off and will not output, thus not affecting the low-level output of the shift register's output signal OUT. In stage s2, when the first clock signal CK1 is low, the sixth transistor T6 is turned on, and the low-level signal IN corresponding to the input signal can be transmitted to the third node Q3. With the eighth transistor T8 normally open, the potentials of the third node Q3 and the first node Q1 are both low. The second capacitor C2 can also be regulated to the potential of the previous stage. The second capacitor C2 discharges the first node Q1, maintaining its potential. At this time, the fourth transistor T4 is turned on, and the low-level signal VGL corresponding to the first terminal of the fourth transistor T4 can be transmitted to the second terminal of the fourth transistor T4, meaning the shift register's output signal OUT continues to be low.

[0116] In stage s3, the first clock signal CK1 is high. At this time, the sixth transistor T6 is turned off, and the high level corresponding to the input signal IN cannot be transmitted to the third node Q3. Meanwhile, the first capacitor C1 is regulated to the potential of the previous stage, so that the potential of the third node Q3 remains low. The second transistor T2 is still conducting, and the electrical energy stored in the first capacitor C1 can be discharged to the first node Q1 through the second transistor T2, pulling down the potential of the first node Q1. At this time, the fourth transistor T4 continues to conduct, and the low level signal VGL corresponding to the first terminal of the fourth transistor T4 can be transmitted to the second terminal of the fourth transistor T4. That is, the output signal OUT of the shift register is still low. Furthermore, when the input signal IN is high, the seventh transistor T7 is off. The high-level signal VGH corresponding to the first terminal of the seventh transistor T7 cannot be transmitted to the fifth node Q5. The fourth capacitor C4 can be charged according to the first clock signal CK1 and discharged to the fifth node Q5. However, since the fourth capacitor C4 is regulated at the potential of the previous stage, the high or low level of the first clock signal CK1 is irrelevant. At this time, the tenth transistor T10 remains off. Also, the eighth transistor T8 is normally open, and the potentials of the third node Q3 and the first node Q1 are both low. At this time, the ninth transistor T9 is on, and the high-level signal VGH corresponding to the first terminal of the ninth transistor T9 can be transmitted to the second node Q2. Simultaneously, the third capacitor C3 is regulated at the potential of the previous stage, keeping the potential of the second node Q2 high. At this time, the fifth transistor T5 is off.

[0117] In stage s4, when the first clock signal CK1 is low, the sixth transistor T6 is turned on, and the high level corresponding to the input signal IN can be transmitted to the third node Q3. The fifth transistor T5 is normally open, so the potentials of the third node Q3 and the first node Q1 are both high. At this time, the sixth transistor T6 is turned off. Also, when the input signal IN is high, the seventh transistor T7 is turned off, and the high level signal VGH corresponding to the first terminal of the seventh transistor T7 cannot be transmitted to the fifth node Q5. However, the fourth capacitor C4 is regulated to the potential of the previous stage, which is the potential of the first clock signal CK1. Therefore, the potential of the fifth node Q5 is the low level corresponding to the first clock signal CK1, and the tenth transistor T10 is turned on. The low level corresponding to the first clock signal CK1 can be transmitted to the second node Q2. At this time, the fifth transistor T5 is turned on, and the high level signal VGH corresponding to the first terminal of the fifth transistor T5 can be transmitted to the second terminal of the fifth transistor T5, meaning the output signal OUT of the shift register is high. In stage s4, when the first clock signal CK1 is high, the sixth transistor T6 is off, and the high level corresponding to the input signal IN cannot be transmitted to the third node Q3. Simultaneously, the second capacitor C2 is regulated to the potential of the previous stage, keeping the potential of the first node Q1 low. The sixth transistor T6 remains off. Also, when the input signal IN is high, the seventh transistor T7 is off, and the high level signal VGH corresponding to the first terminal of the seventh transistor T7 cannot be transmitted to the fifth node Q5. However, the first capacitor C1 is still regulated to the potential of the previous stage, i.e., the potential of the first clock signal CK1. Therefore, the potential of the fifth node Q5 is the high level corresponding to the first clock signal CK1, and the tenth transistor T10 is off. At this time, the voltage of the third capacitor C3 is regulated to the potential of the previous stage. The third capacitor C3 discharges the second node Q2 to maintain the potential of the second node Q2, so that the potential of the second node Q2 remains at a low level. At this time, the fifth transistor T5 continues to conduct. The high-level signal VGH corresponding to the first terminal of the fifth transistor T5 can be transmitted to the second terminal of the fifth transistor T5, that is, the output signal OUT of the shift register is high.

[0118] Optionally, Figure 23 yes Figure 2 The diagram shows a schematic of a pixel circuit in a display panel, as shown below. Figure 2 and Figure 23 As shown, the display panel also includes a pixel circuit 200. The output signal OUT of the driving circuit 100 is a control signal for a preset unit in the pixel circuit 200. When the output signal OUT is a valid level signal, the preset unit is turned on; when the output signal OUT is an invalid level signal, the preset unit is turned off.

[0119] Optionally, the preset unit includes a P-channel transistor, and the output signal OUT is a control signal for the P-channel transistor; wherein, when the output signal OUT is a low-level signal VGL, the P-channel transistor is turned on; or, the preset unit includes an N-channel transistor, and the output signal OUT is a control signal for the N-channel transistor; wherein, when the output signal OUT is a high-level signal VGH, the N-channel transistor is turned on.

[0120] Specifically, when the preset unit includes a P-channel transistor, the effective level signal of the output signal OUT is a low-level signal VGL, and when the output signal OUT is a low-level signal VGL, the P-channel transistor can be turned on accordingly. Similarly, when the preset unit includes an N-channel transistor, the effective level signal of the output signal OUT is a high-level signal VGH, and when the output signal OUT is a high-level signal VGH, the N-channel transistor can be turned on accordingly. It is understood that the preset unit may include only P-channel transistors, only N-channel transistors, or both P-channel and N-channel transistors. This embodiment is merely an example and not a limitation. The pixel circuit 200 in the display panel can also have other structures and is not limited to these. Figure 23 In the structural diagram shown, those skilled in the art can make reasonable selections and settings according to actual needs.

[0121] Optionally, continue to refer to Figure 2 and Figure 23The pixel circuit 200 includes a data writing unit 210, a driving unit 220, a gate reset unit 230, an initialization unit 240, a light-emitting control unit 250, and an energy storage unit 260. The light-emitting control unit 250 includes a first light-emitting control subunit 251 and a second light-emitting control subunit 252. The driving unit 220 includes a driving transistor M1, which provides driving current to the light-emitting element 300. The first terminal of the data writing unit 210 receives a data signal Vdata, and the second terminal is connected to the gate of the driving transistor M1. The control terminal receives a data writing control signal G1. The first terminal of the gate reset unit 230 receives a gate reset signal Vref, and the second terminal is connected to the gate of the driving transistor M1. The control terminal receives a gate reset control signal G2. The first terminal of the initialization unit 240 receives an initialization signal Vini, and the second terminal receives an initialization signal Vref. The first terminal of the first light-emitting control subunit 251 is connected to the anode of the light-emitting element 300, and the control terminal receives the initialization control signal G3; the first terminal of the first light-emitting control subunit 251 receives the first power supply voltage signal ELVDD, the second terminal is connected to the first electrode of the driving transistor M1, and the control terminal receives the light-emitting control signal EM; the first terminal of the second light-emitting control subunit 252 is connected to the second electrode of the driving transistor M1, the second terminal is connected to the anode of the light-emitting element 300, and the control terminal receives the light-emitting control signal EM; the first terminal of the energy storage unit 260 is connected to the gate of the driving transistor M1, and the second terminal is connected to the second electrode of the driving transistor M1; the cathode of the light-emitting element 300 receives the second power supply voltage signal ELVSS; the preset unit includes at least one of the following: data writing unit 210, gate reset unit 230, initialization unit 240, first light-emitting control subunit 251, and second light-emitting control subunit 252.

[0122] Specifically, see the following reference. Figure 23 The process by which the pixel circuit 200 drives the preset units within the driving circuit 100 will be described. First, those skilled in the art will understand that, as... Figure 23The pixel circuit 200 shown may include a data writing unit 210, a driving unit 220, a gate reset unit 230, an initialization unit 240, a light-emitting control unit 250, and an energy storage unit 260. The driving unit 220 includes a driving transistor M1, which provides driving current to the light-emitting elements 300 of the display panel. The first terminal of the data writing unit 210 receives a data signal Vdata, and the second terminal of the data writing unit 210 is connected to the gate of the driving transistor M1. The control terminal of the data writing unit 210 receives a data writing control signal G1. That is, the data writing unit 210 can be turned on or off under the potential of the data writing control signal G1. In other words, the data writing control signal G1 controls the turning on and off of the data writing unit 210, which provides the data signal Vdata to the driving transistor M1. The first terminal of the gate reset unit 230 receives the gate reset signal Vref, and the second terminal of the gate reset unit 230 is connected to the gate of the driving transistor M1. The control terminal of the gate reset unit 230 receives the gate reset control signal G2. That is, the gate reset unit 230 can be turned on or off under the potential of the gate reset control signal G2. The gate reset control signal G2 controls the turning on and off of the gate reset unit 230. The gate reset unit 230 is used to provide the reset signal Vref to the gate of the driving transistor M1. The first terminal of the initialization unit 240 receives the initialization signal Vini, and the second terminal of the initialization unit 240 is connected to the anode of the light-emitting element 300. The control terminal of the initialization unit 240 receives the initialization control signal G3. That is, the initialization unit 240 can be turned on or off under the potential of the initialization control signal G3. The initialization control signal G3 controls the turning on and off of the initialization unit 240. The initialization unit 240 is used to provide the initialization signal Vini to the anode of the light-emitting element 300. The first end of the energy storage unit 260 is connected to the gate of the driving transistor M1, and the second end is connected to the second electrode of the driving transistor M1. The energy storage unit 260 is used to store the signal transmitted to the gate of the driving transistor M1.

[0123] The light-emitting control unit 250 is used to selectively allow the light-emitting element 300 to enter the light-emitting stage. Optionally, the light-emitting control unit 250 includes a first light-emitting control subunit 251 and a second light-emitting control subunit 252. The first light-emitting control subunit 251 is connected between the first power supply voltage signal ELVDD and the first electrode of the driving transistor M1, and the second light-emitting control subunit 252 is connected between the second electrode of the driving transistor M1 and the anode of the light-emitting element 300. The cathode of the light-emitting element 300 receives the second power supply voltage signal ELVSS. Furthermore, the control terminal of the first light-emitting control subunit 251 receives a light-emitting control signal EM, and the control terminal of the second light-emitting control subunit 252 also receives a light-emitting control signal EM. That is, the first light-emitting control subunit 251 can be turned on or off under the potential of the light-emitting control signal EM, and the second light-emitting control subunit 252 can also be turned on or off under the potential of the light-emitting control signal EM. In other words, the light-emitting control signal EM controls the on and off of the first light-emitting control subunit 251 and the second light-emitting control subunit 252. For example, turning on the first light-emitting control subunit 251 and the second light-emitting control subunit 252 can cause the corresponding light-emitting element 300 to enter the light-emitting stage. More specifically, in this embodiment, the pixel circuit 200 receives a first power supply voltage signal ELVDD and a second power supply voltage signal ELVSS. Through the potential difference between the first power supply voltage signal ELVDD and the second power supply voltage signal ELVSS, and simultaneously controlling the driving current through the data signal Vdata written to the gate of the driving transistor M1, the light-emitting element 300 is driven to emit light. For example, the first power supply voltage signal ELVDD can be a positive power supply signal, and the second power supply voltage signal ELVSS can be a negative power supply signal.

[0124] Furthermore, exemplarily, the pixel circuit 200 may also include a compensation unit, which may be connected between the gate of the driving transistor M1 and the second terminal of the driving transistor M1. The compensation unit is used to compensate for the threshold voltage of the driving transistor M1. Exemplarily, the pixel circuit 200 may also include a bias adjustment unit, which is connected to the first terminal of the driving transistor M1, or the bias adjustment unit is connected to the second terminal of the driving transistor M1. The bias adjustment unit is used to provide a bias adjustment signal to the driving transistor M1. Exemplarily, the control terminal of the bias adjustment unit receives a bias adjustment control signal, which controls the turning on and off of the bias adjustment unit.

[0125] Based on the pixel circuit 200 described above, the driving circuit 100 in this embodiment of the invention can provide control signals to the data writing unit 210, gate reset unit 230, initialization unit 240, first light emission control subunit 251, and second light emission control subunit 252. That is, the preset unit of the pixel circuit 200 can be any one of the data writing unit 210, gate reset unit 230, initialization unit 240, first light emission control subunit 251, and second light emission control subunit 252, and the output signal OUT of the driving circuit 100 can be a control signal of at least one of the above units. Taking the output signal OUT of the driving circuit 100 as a control signal of the data writing unit 210 as an example, the driving principle of the pixel circuit 200 will be described below.

[0126] Continue to refer to Figures 2-6 Generally, shift registers 110 at different levels provide drive signals to pixel circuits 200 in different rows, that is, they provide data write control signals G1 to data write units 210 in pixel circuits 200 in different rows. Taking the i-th level shift register 110 as an example, for at least a portion of the time when the potential of the second node Q2 is an invalid level signal, the potential of the first node Q1 is maintained at an effective level signal of the first output sub-unit 21 to ensure that the output signal OUT is an effective level signal, that is, the output signal OUT outputs a valid pulse. At this time, the data write unit 210 is turned on, the pixel circuit 200 begins to write data signals, and the energy storage capacitor C0 in the energy storage unit 260 begins to charge. Furthermore, since the output signal OUT outputs a complete effective pulse, the energy storage capacitor C0 can be fully charged, allowing the light-emitting element 300 to emit light normally as required during the light-emitting stage. Taking another level shift register 110 as an example, the output signal OUT does not output a valid pulse. At this time, the data writing unit 210 is turned off, the pixel circuit 200 cannot write data signals, and the energy storage capacitor C01 in the energy storage unit 260 begins to discharge. Therefore, the shift register 110 can control whether the light-emitting elements 300 in different rows emit light. A storage capacitor C02 can also be provided between the anode and cathode of the light-emitting element 300.

[0127] Those skilled in the art will understand that the activation process of other units in the pixel circuit 200 during each data refresh cycle directly affects whether the pixel circuit 200 can drive the corresponding light-emitting element 300 to emit light. In other words, except for the data writing unit 210, when the output signal OUT is used as the control signal, the shift register 110 can control whether the corresponding light-emitting element 300 can emit light normally. Those skilled in the art can deduce this based on the specific implementation of each unit's function, which will not be elaborated here. It should be noted that the preset units in the pixel circuit 200 here refer more to signals whose control signals are directly input from the outside, such as the data writing unit 210, the gate reset unit 230, the initialization unit 240, the first light-emitting control subunit 251, and the second light-emitting control subunit 252. For the driving unit 220, which is controlled to be turned on or off by the input data signal, it is not directly controlled by the external signal. Therefore, the output signal OUT of the driving circuit 100 in this invention cannot be used as the control signal for the preset units of the pixel circuit 200.

[0128] Optionally, continue to refer to Figure 23 The data writing unit 210, the gate reset unit 230, the initialization unit 240, the first light emission control subunit 251, and the second light emission control subunit 252 all include P-type channel transistors or N-type channel transistors.

[0129] For example, the driving unit 220 includes a driving transistor M1; the data writing unit 210 includes a data writing transistor M2, and the data writing control signal G1 can control the turning on and off of the data writing transistor M2; the gate reset unit 230 includes a gate reset transistor M3, and the gate reset control signal G2 controls the turning on and off of the gate reset transistor M3; the initialization unit 240 includes an initialization transistor M4, and the initialization control signal G3 controls the turning on and off of the initialization transistor M4; the first light emission control subunit 251 includes a first light emission control transistor M5, and the light emission control signal EM controls the turning on and off of the first light emission control transistor M5; the second light emission control subunit 252 includes a second light emission control transistor M6, and the light emission control signal EM controls the turning on and off of the second light emission control transistor M6. For example, the driving transistor M1, data writing transistor M2, gate reset transistor M3, initialization transistor M4, first light-emitting control transistor M5, and second light-emitting control transistor M6 can all be N-channel transistors; or, the driving transistor M1, data writing transistor M2, gate reset transistor M3, initialization transistor M4, first light-emitting control transistor M5, and second light-emitting control transistor M6 can all be P-channel transistors; or, some of the transistors in the driving transistor M1, data writing transistor M2, gate reset transistor M3, initialization transistor M4, first light-emitting control transistor M5, and second light-emitting control transistor M6 can be N-channel transistors, and the remaining transistors can be P-channel transistors. Figure 23 The types of transistors shown are for illustrative purposes only and are not intended to be limiting.

[0130] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 24 As shown, the display device includes a display panel 1 as provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention possesses the corresponding beneficial effects of the display panel provided in the embodiments of the present invention, which will not be elaborated here. Exemplarily, the display device may be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device, and the embodiments of the present invention do not limit it in this regard.

[0131] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0132] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A shift register, characterized by, The application relates to a voltage level shifter, comprising: a control unit for receiving an input signal and a first clock signal, and controlling the potential of a first node and the potential of a second node; wherein one of the potential of the first node and the potential of the second node is a high-level signal, and the other is a low-level signal; an output unit comprising a first output subunit and a second output subunit; a first end of the first output subunit receives a first voltage signal, a first end of the second output subunit receives a second voltage signal, and a second end of the first output subunit and a second end of the second output subunit are connected and output an output signal; wherein one of the first voltage signal and the second voltage signal is a high-level signal, and the other is a low-level signal; a control end of the first output subunit is connected to the first node, and outputs the first voltage signal when the potential of the first node is a valid-level signal; a control end of the second output subunit is connected to the second node, and outputs the second voltage signal when the potential of the second node is a valid-level signal; a node voltage regulating unit connected to the first node, for maintaining the potential of the first node as a valid-level signal of the first output subunit in at least part of the time when the potential of the second node is an invalid-level signal.

2. The shift register of claim 1, wherein, The valid-level signal of the first node is a high-level signal, and the potential of the first node satisfies U1' <= U1''; or the valid-level signal of the first node is a low-level signal, and the potential of the first node satisfies U1' >= U1''; wherein U1' is the potential of the first node in the stage when the input signal is a valid-level signal and the first clock signal is switched to a valid-level signal for the first time; and U1'' is the potential of the first node in the stage when the input signal is a valid-level signal and the first clock signal is an invalid-level signal, or in the stage when the input signal is switched from a valid-level signal to an invalid-level signal and the first clock signal is an invalid-level signal. The control unit comprises a third node, and one of the potential of the third node and the potential of the second node is a high-level signal, and the other is a low-level signal; 3. The shift register of claim 1, wherein, a control end of the node voltage regulating unit is connected to the third node, for maintaining the potential of the first node as a valid-level signal of the first output subunit in at least part of the time when the potential of the third node is a valid-level signal. The valid-level signal of the first node is a high-level signal, and U1 >= U3 in the stage when the first node is a valid-level signal; or the valid-level signal of the first node is a low-level signal, and U1 <= U3 in the stage when the first node is a valid-level signal; wherein U1 is the potential of the first node, and U3 is the potential of the third node.

4. The shift register of claim 3, wherein, The node voltage regulating unit comprises a first switch subunit, a second switch subunit and a first energy storage subunit; ​ 5. The shift register of claim 3, wherein, ​ The first end of the first switch sub-unit receives a second clock signal, and the second end is connected to the first end of the first energy storage sub-unit; the second end of the first energy storage sub-unit, the control end of the first switch sub-unit, and the first end and the control end of the second switch sub-unit are connected to a fourth node, and the fourth node is connected to the third node; the second end of the second switch sub-unit is connected to the first node; wherein the second clock signal and the first clock signal are opposite to each other. The first switch sub-unit and the second switch sub-unit are turned on when the third node is an effective level signal. The first energy storage sub-unit receives the second clock signal to charge when the first clock signal is an effective level signal, and discharges to the first node through the turned-on second switch sub-unit to maintain the potential of the first node when the first clock signal is switched from the effective level signal to an ineffective level signal.

6. The shift register of claim 5, wherein, The node voltage regulating unit further comprises a third switch sub-unit connected between the fourth node and the third node. The control end of the third switch sub-unit receives the first voltage signal; or the control end of the third switch sub-unit receives the first clock signal.

7. The shift register of claim 6, wherein, The third switch sub-unit comprises a third transistor. The third transistor is connected between the fourth node and the third node, and the gate receives the first voltage signal or the first clock signal.

8. The shift register of claim 1, wherein, The control end of the node voltage regulating unit receives the input signal, and is used to maintain the potential of the first node as the effective level signal of the first output sub-unit at least in the time when the potential of the input signal is the effective level signal and the first clock signal is the ineffective level signal.

9. The shift register of claim 8, wherein, The node voltage regulating unit comprises a first switch sub-unit, a second switch sub-unit, a third switch sub-unit, and a first energy storage sub-unit. The first end of the first switch sub-unit receives a second clock signal, and the second end is connected to the first end of the first energy storage sub-unit; the second end of the first energy storage sub-unit, the control end of the first switch sub-unit, and the first end and the control end of the second switch sub-unit are connected to a fourth node; the second end of the second switch sub-unit is connected to the first node; wherein the second clock signal and the first clock signal are opposite to each other. The first end of the third switch sub-unit is connected to the fourth node; the second end receives the input signal, and the control end of the third switch sub-unit receives the first clock signal. The third switch sub-unit is turned on when the first clock signal is an effective level signal, and the first switch sub-unit and the second switch sub-unit are turned on when the input signal is an effective level signal. The first energy storage sub-unit receives the second clock signal and the input signal to charge at both ends when the first clock signal is an effective level signal, and discharges to the first node through the turned-on second switch sub-unit to maintain the potential of the first node when the first clock signal is an ineffective level signal.

10. The shift register according to claim 6 or 9, characterized in that, The first switch subunit comprises a first transistor, the second switch subunit comprises a second transistor, the third switch subunit comprises a third transistor, and the first energy storage subunit comprises a first capacitor; The first pole of the first transistor receives the second clock signal, the second pole is connected to the first pole plate of the first capacitor, the second pole plate of the first capacitor, the gate of the first transistor, and the gate and first pole of the second transistor are all connected to the fourth node; the second pole of the second transistor is connected to the first node; the first pole of the third transistor is connected to the fourth node, the second pole receives the input signal, and the gate receives the first clock signal; The channel types of the first transistor, the second transistor, and the third transistor are the same.

11. The shift register of claim 10, wherein, The first transistor, the second transistor, and the third transistor are all P-type channel transistors or N-type channel transistors.

12. The shift register of claim 1, wherein, The first output subunit comprises a fourth switch subunit and a second energy storage subunit, and the second output subunit comprises a fifth switch subunit and a third energy storage subunit; The first end of the fourth switch subunit receives the first voltage signal, and the control end of the fourth switch subunit and the first end of the second energy storage subunit are both connected to the first node; The first end of the fifth switch subunit receives the second voltage signal, and the control end of the fifth switch subunit and the first end of the third energy storage subunit are both connected to the second node; The second end of the fourth switch subunit, the second end of the second energy storage subunit, the second end of the fifth switch subunit, and the second end of the third energy storage subunit are connected to each other and output the output signal; The fourth switch subunit is turned on when the first node is an effective level signal; The second energy storage subunit is charged at least when the first clock signal is an effective level signal, and is discharged to the first node when the first clock signal is switched from an effective level signal to an ineffective level signal, so as to maintain the potential of the first node; The fifth switch subunit is turned on when the second node is an effective level signal; The third energy storage subunit is charged at least when the first clock signal is an ineffective level signal, and is discharged to the second node when the first clock signal is switched from an ineffective level signal to an effective level signal, so as to maintain the potential of the second node.

13. The shift register of claim 12, wherein, The fourth switch subunit comprises a fourth transistor, the second energy storage subunit comprises a second capacitor; the fifth switch subunit comprises a fifth transistor, and the third energy storage subunit comprises a third capacitor; the channel types of the fourth transistor and the fifth transistor are the same; The first pole of the fourth transistor receives the first voltage signal, and the gate of the fourth transistor and the first pole plate of the second capacitor are both connected to the first node; The first pole of the fifth transistor receives the second voltage signal, and the gate of the fifth transistor and the first pole plate of the third capacitor are both connected to the second node; The second electrode of the fourth transistor, the second electrode plate of the second capacitor, the second electrode of the fifth transistor and the second electrode plate of the third capacitor are connected with each other and output the output signal.

14. The shift register of claim 13, wherein, The fourth transistor and the fifth transistor are N-type channel transistors, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; or, The fourth transistor and the fifth transistor are P-type channel transistors, the first voltage signal is a low-level signal, and the second voltage signal is a high-level signal.

15. The shift register of claim 1, wherein, The control unit comprises a sixth switching subunit, a seventh switching subunit, an eighth switching subunit, a ninth switching subunit, a tenth switching subunit and a fourth energy storage subunit; The first end of the sixth switching subunit and the control end of the seventh switching subunit are connected and receive the input signal, the second end of the sixth switching subunit, the first end of the eighth switching subunit and the control end of the ninth switching subunit are connected to a third node, and the control end of the sixth switching subunit receives the first clock signal; The first end of the seventh switching subunit receives the second voltage signal, the second end of the seventh switching subunit, the control end of the tenth switching subunit and the first end of the fourth energy storage subunit are connected to a fifth node; The second end of the eighth switching subunit is connected to the first node, and the control end of the eighth switching subunit receives the first voltage signal; The first end of the ninth switching subunit receives the second voltage signal, and the second end of the ninth switching subunit and the first end of the tenth switching subunit are connected to the second node; The second end of the tenth switching subunit is connected to the second end of the fourth energy storage subunit; The sixth switching subunit is turned on when the first clock signal is a valid level signal; The seventh switching subunit is turned on when the input signal is a valid level signal; The fourth energy storage subunit is used to receive the second voltage signal for charging when the input signal is a valid level signal, and discharge to the fifth node when the input signal is switched from a valid level signal to an invalid level signal, so as to maintain the potential of the fifth node.

16. The shift register of claim 15, wherein, The sixth switching subunit comprises a sixth transistor, the seventh switching subunit comprises a seventh transistor, the eighth switching subunit comprises an eighth transistor, the ninth switching subunit comprises a ninth transistor, the tenth switching subunit comprises a tenth transistor, and the fourth energy storage subunit comprises a fourth capacitor; the channel types of the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are the same; The first electrode of the sixth transistor and the gate of the seventh transistor are connected and receive the input signal, the second electrode of the sixth transistor, the first electrode of the eighth transistor and the gate of the ninth transistor are connected to a third node, and the gate of the sixth transistor receives the first clock signal; A first electrode of the seventh transistor receives the second voltage signal, a second electrode of the seventh transistor, a gate electrode of the tenth transistor and a first plate of the fourth capacitor are connected to a fifth node; A second electrode of the eighth transistor is connected to the first node, and a gate electrode of the eighth transistor receives the first voltage signal; A first electrode of the ninth transistor receives the second voltage signal, and a second electrode of the ninth transistor and a first electrode of the tenth transistor are connected to the second node; A second electrode of the tenth transistor is connected to a second plate of the fourth capacitor.

17. The shift register of claim 16, wherein, The sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are P-type channel transistors or N-type channel transistors.

18. The shift register of claim 16, wherein, The sixth switch sub-unit further comprises an eleventh transistor, which has the same channel type as the sixth transistor; A first electrode of the eleventh transistor is connected to a second electrode of the sixth transistor, a second electrode of the eleventh transistor is connected to the third node, and a gate electrode of the eleventh transistor receives the first clock signal.

19. The shift register of claim 18, wherein, The sixth switch sub-unit further comprises a twelfth transistor, which has the same channel type as the sixth transistor; A second electrode of the sixth transistor and a first electrode of the eleventh transistor are connected to a sixth node, and a first electrode of the twelfth transistor is connected to the sixth node; A second electrode of the twelfth transistor receives the first voltage signal, and a gate electrode of the twelfth transistor is connected to the third node; or, a second electrode of the twelfth transistor receives a third voltage signal, and a gate electrode of the twelfth transistor is connected to the first node; The first voltage signal is a high-level signal, and the third voltage signal is greater than the first voltage signal, or the first voltage signal is a low-level signal, and the third voltage signal is less than the first voltage signal.

20. A display panel comprising: The driving circuit comprises N stages of shift registers as claimed in any one of claims 1-19 in cascade; The output signal of the shift register of the i-th stage is input into the shift register of the j-th stage as the input signal of the shift register of the j-th stage; wherein N≥2, 1≤i≤N, and 1≤j≤N.

21. The display panel of claim 20, wherein, The driving circuit further comprises a pixel circuit, and the output signal of the driving circuit is a control signal of a preset unit in the pixel circuit; When the output signal is a valid level signal, the preset unit is turned on; When the output signal is an invalid level signal, the preset unit is turned off.

22. The display panel of claim 21, wherein, The preset unit comprises a P-type channel transistor, and the output signal is a control signal of the P-type channel transistor; wherein when the output signal is a low-level signal, the P-type channel transistor is turned on; or, The preset unit comprises an N-type channel transistor, and the output signal is a control signal of the N-type channel transistor; wherein when the output signal is a high-level signal, the N-type channel transistor is turned on.

23. The display panel of claim 22, wherein, The pixel circuit comprises a driving unit, a data writing unit, a gate reset unit, an initialization unit, a light emitting control unit and an energy storage unit; The light emitting control unit comprises a first light emitting control sub-unit and a second light emitting control sub-unit; The driving unit comprises a driving transistor for providing a driving current for the light emitting element; The first end of the data writing unit receives a data signal, the second end is connected with the gate of the driving transistor, and the control end receives a data writing control signal; The first end of the gate reset unit receives a gate reset signal, the second end is connected with the gate of the driving transistor, and the control end receives a gate reset control signal; The first end of the initialization unit receives an initialization signal, the second end is connected with the anode of the light emitting element, and the control end receives an initialization control signal; The first end of the first light emitting control sub-unit receives a first power voltage signal, the second end is connected with the first electrode of the driving transistor, and the control end receives a light emitting control signal; The first end of the second light emitting control sub-unit is connected with the second electrode of the driving transistor, the second end is connected with the anode of the light emitting element, and the control end receives the light emitting control signal; The first end of the energy storage unit is connected with the gate of the driving transistor, and the second end is connected with the second electrode of the driving transistor; The cathode of the light emitting element receives a second power voltage signal; The preset unit comprises at least one of the data writing unit, the gate reset unit, the initialization unit, the first light emitting control sub-unit and the second light emitting control sub-unit.

24. The display panel of claim 23, wherein, The data writing unit, the gate reset unit, the initialization unit, the first light emitting control sub-unit and the second light emitting control sub-unit all comprise a P-type channel transistor or an N-type channel transistor.

25. A display device comprising: The display panel comprises any one of the display panels of claims 20-24.

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