Electrical protection circuit, integrated circuit and mobile communication device

Abstract

The invention provides an electrical protection circuit, an integrated circuit and a mobile communication device. The present disclosure relates to electrical protection, in particular an electrical clamping circuit, comprising a protection device electrically coupled between a supply voltage input and a reference potential, and having a control gate for selectively activating a discharge path. The clamp circuit further includes an RC circuit electrically coupled between the supply voltage input and a reference potential and having a first internal node for providing the control voltage; a first control path electrically coupled between the first internal node and a control gate of the protection device and having a first trigger element for triggering the protection device, the first trigger element configured to act as a digital control element; and a second control path electrically coupled between the first internal node and the control gate of the protection device and having a second trigger element for triggering the protection device, the second trigger element configured to act as a progressive control element. The disclosure also relates to an integrated circuit and a communication device comprising the electrical protection circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates to an electrical protection circuit, in particular an electrical clamp circuit, comprising a protection device connected between a supply voltage input and a reference potential and having a control gate for selectively activating a discharge path. The invention further relates to an integrated circuit comprising the electrical protection circuit and a mobile communication device comprising the integrated circuit. BACKGROUND

[0002] For example, clamp circuits are used to protect other circuits and devices, such as system on chip (SoC) devices, from damage caused by certain external events.

[0003] Different types of clamp circuits are known from the prior art, such as RC-NMOS voltage clamps (often simply referred to as RC-clamps). Such clamp circuits are designed to limit the input supply voltage to a safe operating area (SOA) corresponding to a maximum input voltage acceptable for a given electrical load connected to the supply voltage. An increase of the supply voltage can for example be triggered by a so-called (unintentional) electrostatic discharge (ESD) event, which is for example caused in case the device is accidentally touched by a charged body. For this purpose, so-called RC-clamps are used to provide a discharge path between the supply voltage input and a reference potential.

[0004] However, the functionality of conventional clamp circuits is limited to protecting the circuit from damage caused by ESD discharges only. In particular, they can not be tuned to react to other overvoltage (OV) conditions caused during normal operation of the circuit, for example when an internal load is powered up by the supply voltage connected thereto during normal operation. For example, the supply voltage can start ringing when the input current of an internal load or another electrical load of the supply changes suddenly, for example caused by a response of a DC / DC converter to a load change. Electromagnetic interference can cause a similar effect due to an electromagnetic coupling into the supply line. Furthermore, power surges can also occur due to hot plugging or network overload, which can cause the supply to increase above its maximum rating for a short time. Moreover, a power-up ESD event can occur if the device is handled during operation. Such power-up overvoltage conditions can lead to a latch-up in the circuit to be protected. Relatively small voltage variations encountered during operation can cause a device in the system to leave its SOA. Such voltage variations can be smaller than the relatively high voltage variations encountered during an ESD event. Therefore, conventional clamp circuits can not react at all, or at least not fast enough to reliably protect the internal load from OV events encountered during operation. SUMMARY

[0005] It is therefore an object of the present disclosure to provide improved circuits and devices for protecting circuits such as SoCs, thereby further improving their electrical robustness and reliability, in particular during their operation, i.e. in the powered state.

[0006] The present disclosure provides an electrical protection circuit, in particular an electrical clamp circuit, comprising a protection device, an RC circuit, a first control path and a second control path. The protection device is electrically coupled between a supply voltage input and a reference potential and has a control gate for selectively activating a discharge path. The RC circuit is electrically coupled between the supply voltage input and the reference potential and has a first internal node for providing a control voltage. The first control path is electrically coupled between the first internal node and the control gate of the protection device and has a first trigger element for triggering the protection device, wherein the first trigger element is configured to act as a digital control element, in particular as a switch. The second control path is electrically coupled between the first internal node and the control gate and has a second trigger element for triggering the protection device, wherein the second trigger element is configured to act as a gradual control element, in particular as a tunable current source or resistor.

[0007] Wherein the inventors have found that an electrical clamp or similar protection circuit can be further improved if different control paths are provided to handle disturbances in the supply voltage of different amplitudes and / or speeds. In particular, by using a first control path comprising a first switch element configured to act as a digital control element, the discharge path can be quickly activated in case of a relatively high, fast increase of the supply voltage, e.g. in case of an ESD event. By using a second control path comprising a trigger element configured to act as a gradual control element, a more fine-grained control of the discharge path can be achieved in case of a relatively small increase of the supply voltage during operation, e.g. caused by ringing of a DC / DC converter or another transient OV event.

[0008] Optionally, the first control path is configured to have a first output current response to a transient voltage at the supply voltage input for triggering the protection device in case of an unpowered OV event, in particular an ESD event, and the second control path is configured to have a second output current response to a transient voltage at the supply voltage input for triggering the protection device in case of a powered OV event.

[0009] For example, the first control path can be fully off or fully on, thereby effectively providing a digital control signal to the protection device. Such a response is particularly useful for preventing ESD events by means of a high discharge current to quickly route the charge accumulated on the supply terminal to the reference terminal thereby clamping the input supply voltage to a tolerable level according to the SOA.

[0010] While such an output current response provides a high level of protection against ESD events, it can require a relatively high power supply voltage variation to activate the trigger element. Moreover, the protection device is fully on and operates like a resistive switch, resulting in a fast drop of the power supply voltage. Therefore, it can not be suitable to react to OV events encountered during normal operation of the circuit, for example, in a power-up state when the power supply voltage is applied to the circuit to be protected. Therein, the inventors have found that the tolerable power supply voltage variation before triggering can be low to prevent power-up OV events and that it can be undesirable to have the protection device fully on as this can result in an under-voltage or damage of the circuit of the protection device itself. Therefore, the second control path is configured to have a higher sensitivity and / or to provide a different output current response.

[0011] For example, if the power supply voltage corresponds to an acceptable window around a nominal power supply voltage, for example, plus / minus 10% or 20% of the nominal power supply voltage, the protection device is not triggered or only triggered to a minimum extent that does not affect the operation of the circuit. However, under transient overstress, for example, if the power supply voltage increases by a fixed amount, such as 1 V, or exceeds a given SOA window, the protection device is gradually operated into an on state corresponding to a deviation from the nominal voltage to reduce the OV event to an acceptable extent. Note that in this case, the protection device can not be fully activated to prevent a sudden drop of the power supply voltage under the under-voltage threshold voltage. Such an overcompensation of the OV will result in a reset or chip failure.

[0012] Optionally, the first control path comprises at least one inverter for providing the digital control signal to the control gate of the first trigger element. By means of the inverter, the analog input signal can be easily converted into a digital control signal, thereby influencing the desired full activation of the protection device.

[0013] Optionally, the first trigger element is a first enhancement mode field effect transistor (FET), in particular a first p-channel MOSFET, and the first control path comprises an even number of inverters electrically coupled in series between the first internal node and the control gate of the first FET. For example, two inverters can be directly connected in series to convert the analog input signal into a digital output signal of the same polarity for controlling the first control path. Based on such a digital input signal, the FET can be fully on to provide the required control signal to the protection device.

[0014] Optionally, the second control path is configured for providing an analog control signal to the second trigger element by tracking a difference between an instantaneous power supply voltage provided at the power supply voltage input and a filtered power supply voltage provided by the RC circuit. Such an analog control signal can be used to control the protection device according to transient OV seen at the power supply input.

[0015] Optionally, the second power path is configured to stop triggering the protection device if the voltage difference between the power supply voltage input and the first internal node falls below a predefined threshold voltage. In particular, voltage variations within a defined acceptable window around the nominal power supply voltage should not lead to triggering of the protection device to avoid unwanted and energy-wasting activation of the protection device.

[0016] Optionally, the second triggering element is a second enhancement-mode FET, in particular a second p-channel MOSFET, and the first internal node is directly electrically connected to the gate of the second FET. In such a configuration, the second FET essentially acts as a tunable current source for partially activating the protection device once a certain threshold voltage is exceeded.

[0017] Optionally, the electrical protection circuit further comprises a discharge element electrically coupled to the control gate of the protection device for discharging the control gate of the protection device in case both the first control path and the second control path are disabled. For example, the discharge element can comprise at least one of a resistor or a FET with a dynamically driven gate. Such an element can easily be integrated into the electrical protection circuit to provide the desired functionality. This discharge element can be used to automatically deactivate the protection device once the triggering condition is no longer fulfilled.

[0018] Optionally, a first time constant defined by the RC circuit is larger than a second time constant defined by the discharge element and a capacitive element associated with the protection device, in particular a parasitic capacitance of the control gate of the protection device. This ensures, among others, that the protection device can be turned off in time to avoid an undesired drop of the power supply voltage, in particular during normal operation of the circuit. This in turn helps to prevent potential resets or damages of the internal load.

[0019] Optionally, the electrical protection circuit further comprises a combining element, in particular a logic OR gate, a first input of the combining element being electrically coupled to the first triggering element, a second input of the combining element being electrically coupled to the second triggering element, and an output of the combining element being electrically coupled to the control gate of the protection device. Note that in this case the essentially digital control signal provided by the first control path and the analog control signal provided by the second control path will be combined into a single digital control signal driving the protection device. Nonetheless, the output current responses of the first control path and the second control path can be designed to be different, thereby maintaining the desired different response characteristics of the protection device to different types of disturbances. In this case, the second path is designed to react fast enough to turn off the control signal at the protection device to avoid power undervoltage in case the RC clamp triggers due to a power-on OV event.

[0020] Optionally, the RC circuit comprises a resistive element electrically coupled between the supply voltage input and the first internal node, and a capacitive element electrically coupled between the first internal node and the reference voltage potential. For example, the resistive element comprises at least one of a resistor or a MOSFET, and / or the capacitive element comprises at least one of a capacitor or a MOSFET, which can be easily integrated into the electrical protection circuit. In this configuration, the signal provided at the first internal node initially corresponds to the supply voltage before the disturbance, and then slowly follows any variations of the supply voltage.

[0021] Alternatively, the RC circuit can comprise a capacitive element electrically coupled between the supply voltage input and the first internal node, and a resistive element electrically coupled between the first internal node and the reference voltage potential. In this configuration, the voltage provided by the internal node substantially follows the reference voltage.

[0022] In one particular embodiment of the above alternative, the electrical protection circuit is configured to invert the control signal provided by the first and / or second trigger element before it is provided to the control gate of the protection device. In order to activate the protection device as previously described, the control signal is inverted.

[0023] Optionally, the electrical protection circuit further comprises a second internal node electrically coupled to the supply voltage input through one or more diodes, switches and / or current sources for providing a second supply voltage monitored by the RC circuit, wherein the supply voltage input of at least one of the first and second trigger elements is electrically coupled to the second supply voltage. For example, this configuration is useful if some or all of the trigger elements and other components of the clamping circuit are designed to operate at a lower voltage than the external supply voltage provided to the electrical protection circuit.

[0024] The present disclosure also provides an integrated circuit (IC), in particular a system on chip (SoC). The IC comprises a first voltage rail for providing a supply voltage, a second voltage rail for providing a reference voltage, an internal circuit configured to be supplied by the supply voltage, and an electrical protection circuit as described above. The electrical protection circuit is electrically coupled between the first voltage rail and the second voltage rail, and is configured to protect the internal circuit from both unpowered OV events, in particular ESD events, and powered OV events.

[0025] The present disclosure also provides a mobile communication device, in particular a user equipment (UE) or a global navigation satellite navigation (GNSS) device. The mobile communication device comprises an integrated circuit according to the second aspect and a power supply circuit, in particular a DC / DC converter circuit, wherein the output terminals of the power supply circuit are electrically coupled to the first and second voltage rails of the IC.

[0026] As described above, the ICs and mobile communication devices can operate safely under various power supply configurations and provide improved protection against various disturbances in the power supply voltage, including ESD and other OV events, during operation (i.e., in the powered-on state as well as in the powered-off, unpowered, or floating state). These contribute to improved electrical robustness and operational reliability of the corresponding devices. Attached Figure Description

[0027] Various embodiments of the disclosed circuits and devices are described in more detail below. For better understanding, embodiments are described with reference to the accompanying drawings, wherein the same or similar reference numerals are used for similar components in different embodiments. However, this does not mean that these components must be identical in every embodiment.

[0028] Figure 1 The first clamping circuit is shown.

[0029] Figure 2A and Figure 2B The various currents and voltages in the first clamping circuit during an ESD event are shown.

[0030] Figure 3A and Figure 3B The various currents and voltages in the first clamping circuit during a transient power-on OV event are shown.

[0031] Figure 4 A mobile communication device including an IC with a second clamping circuit is shown.

[0032] Figure 5 The third clamping circuit is shown.

[0033] Figure 6 The fourth clamping circuit is shown.

[0034] List of reference numerals

[0035] 10 (First) Clamping Circuit

[0036] 12 Input Terminals

[0037] 14 Reference Nodes

[0038] 16. Protection Devices

[0039] 18 First Control Path

[0040] 20 Second Control Path

[0041] 22 (Control gate of protection device)

[0042] 24 First internal node

[0043] 26 RC circuits

[0044] 28 First Inverter

[0045] 30 Second Inverter

[0046] 32 First trigger element

[0047] 34 Second trigger element

[0048] 36 Discharge elements

[0049] 40. Communication equipment

[0050] 42 Power Supply

[0051] 44 Power Supply Circuit

[0052] 46 IC

[0053] 48 Internal Circuit

[0054] 50 (Second) Clamping Circuit

[0055] 52 First Selling

[0056] 54 Second Selling

[0057] 56 Second internal node

[0058] 60 (Third) Clamping Circuit

[0059] 62 Inverter

[0060] 64 Buffer

[0061] 66 Inverting RC Circuit

[0062] 80 (Fourth) Clamping Circuit

[0063] 82 Buffer

[0064] 84 Combined Components

[0065] 86 inverter

[0066] C1 Capacitor Component

[0067] diodes D1 and D2

[0068] I1 First control current

[0069] I2 Second Control Current

[0070] M0 (BigMOS)FET

[0071] M1 (p-channel) MOSFET

[0072] M2 (p-channel) MOSFET

[0073] R1 resistor element

[0074] R2 resistor

[0075] VDD (external) power supply voltage

[0076] VDD_L (Internal) Power Supply Voltage

[0077] VSS reference potential Detailed Implementation

[0078] Figure 1 An electrical protection circuit in the form of a first clamping circuit 10 is shown. The clamping circuit 10 is connected to input 12 to provide a power supply voltage VDD and a reference potential VSS provided at a reference node 14 (such as electrical ground (GND)). The clamping circuit 10 is designed to protect the load ( Figure 1 (Not shown) is protected from excessively high or low (negative) transients in the power supply voltage VDD.

[0079] For this purpose, clamping circuit 10 includes protection device 16. In the described embodiment, protection device 16 is configured as FET M0 (referred to as BigMOS FET) because M0 is typically very large compared to most other FETs on a SoC. The source and drain terminals of protection device 16 are connected between the supply voltage VDD and the reference potential VSS, and can be selectively closed by providing an appropriate signal to the control gate 22 of protection device 16.

[0080] Triggering of the protection device 16 can be achieved through one of two different control paths 18 and 20, both of which are connected to the first internal node 24 of the RC circuit 26 that provides a control voltage to the control gate 22. The RC circuit 26 is also connected between the power supply voltage VDD and the reference potential VSS. Figure 1 In the illustrated embodiment, a resistor R1 is connected between the power supply voltage VDD and the internal node 24, and a capacitor C1 is connected between the first internal node 24 and the reference potential VSS. Therefore, in a steady state, the voltage at the internal node 24 substantially corresponds to the power supply voltage VDD. However, in the case of transient voltages at the power supply voltage VDD, the RC circuit 26 acts as a filter, particularly a low-pass filter, and provides a filtered version of the power supply voltage VDD at the internal node 24 as the input signal to the first control path 18 and the second control path 20. Although only a relatively simple RC circuit 26 forming a single filter is shown, multiple or different types of filters can be used to generate one or more control voltages for the first control path 18 and / or the second control path 20.

[0081] The described first control path 18 includes: a first inverter 28, whose input is connected to internal node 24; a second inverter 30, whose input is connected to the output of the first inverter 28; and a first trigger element 32 with a control gate, connected to the output of the second inverter 30. Note that in the described embodiment, inverters 28 and 30 operate using a power supply voltage VDD. Assuming the inverters are symmetrical, their switching voltage thresholds are located at half the difference between VDD and VSS at the input voltage. Therefore, once the voltage at the first internal node 24 exceeds half the power supply voltage VDD at input 12, the first inverter 28 will output the power supply voltage VDD at its output. Conversely, if the voltage at the first internal node 24 drops below half the power supply voltage VDD at input 12, the first inverter 28 will output a reference voltage VSS at its output. In either case, the second inverter 30 will also flip, thus providing the opposite output voltage. The switching voltage thresholds can be designed to be different, making the inverters more or less sensitive to transient power supply changes. Together, the first inverter 28 and the second inverter 30 essentially convert the analog input signal provided by the internal node 24 into a corresponding digital control signal for the first trigger element 32.

[0082] In the described embodiment, the first trigger element 32 is a p-channel MOSFET M1. Once the output of the second inverter 30 is toggled to a logic low state, the gate-source voltage difference switches the p-channel MOSFET M1 to the on state. Conversely, if the output of the second inverter 30 is toggled to a logic high state, the source-gate voltage difference at MOSFET M1 collapses, and it completely blocks any current flowing through it. This means that MOSFET M1 operates like a switch, turning on and off the electrical path between input 12 and the control gate 22 of protection device 16, respectively.

[0083] The second control path 20 includes only the second trigger element 34, whose control gate is directly connected to the first internal node 24. The second trigger element 34 is configured as a p-channel MOSFET M2. Therefore, the voltage provided by the internal node 24 is used as an analog control signal to control the current through the second trigger element 34 in a substantially proportional manner. Note that the drain and source terminals of the two trigger elements 32 and 34 are connected in parallel to provide a corresponding trigger voltage to the protection device 16. Therefore, activation of either the first control path 18 or the second control path 20 will activate the protection device 16.

[0084] The first clamping circuit 10 also includes a discharge element 36 in the form of a resistor R2 connected between the control gate 22 of the protection device 16 and the reference potential VSS. The discharge element 36 pulls the voltage at the control gate 22 back to the reference potential VSS, thereby activating the protection device 16 when the triggering condition is no longer met.

[0085] The following is for reference. Figures 2A to 3B The operation of the first clamping circuit 10 is described in further detail under different operating conditions.

[0086] Figure 2A and Figure 2B Various voltages and currents flowing through the first clamping circuit 10 during an ESD event are illustrated. In the described scenario, the circuitry including the first clamping circuit 10 is turned off. That is, the supply voltage VDD is initially zero. Charge is then rapidly injected onto the VDD terminal 12, resulting in a relatively high, sharp voltage spike that could endanger the circuit components of the circuit to be protected. To prevent gate oxide, semiconductor junction breakdown, or other physical damage, the first clamping circuit 10 needs to react quickly to absorb the charge associated with the ESD event.

[0087] like Figure 2B As shown, in the first stage ①, the power supply voltage VDD corresponds to the reference voltage VSS. Therefore, the power supply voltage VDD, the voltage N1 at the first internal node 24, the voltage N2 at the control gate of the first trigger element 34, the voltage N3 at the control gate 22 of the protection device 16, and the current IDS(M0) through the protection device 16 are also zero in the initial stage ①.

[0088] In the second stage ②, charge accumulates rapidly at input terminal 12. Therefore, the potential at VDD increases relatively quickly. The shape of the power supply voltage at input terminal 12 can correspond to electrostatic discharge caused by input terminal 12 of the human body touch circuit 10, or it can correspond to a corresponding charge injection profile, for example, based on a human body model (HBM) test. The voltage N1 at internal node 24 slowly follows the increase of the power supply voltage VDD, as... Figure 2B As shown.

[0089] At the end of the second phase ② (typically lasting less than 1 ns), the supply voltage is high enough to initiate operation of circuit 10, allowing the chain of inverters 28 and 30 to convert the analog voltage at N1 to its digital equivalent at N2, with VDD and VSS as references. This provides the corresponding control voltage for activating the first trigger element 32. Specifically, the gate of the p-channel MOSFET M1 will be pulled to VSS, while its source is connected to the supply voltage VDD. Note that the switching thresholds of inverters 28 and 30 (e.g., half the supply voltage VDD) affect the total switching delay. Choosing a very low threshold for inverter 28 might seem like a good idea for fast ESD event detection. However, this could also cause false triggering during normal chip power-up. This could also cause the first control path 18 to turn on due to negligible supply voltage disturbances.

[0090] Therefore, at the start of the third stage ③, the first trigger element 32 is fully turned on, resulting in a relatively large first control current I1 flowing through the first trigger element 32. Note that in the third stage ③, the second trigger element 34 is also partially triggered by the voltage difference between the power supply voltage VDD and the control voltage N1 at the first internal node 34. Therefore, the second trigger element 34 also provides a second control current I2, which contributes to the trigger current used to activate the protection device. However, since there is no inverter circuit, the second control current I2 provided by the second control path 20 is smaller than the first control current I1 provided by the first control path 18, and therefore can be considered negligible.

[0091] Due to the high control currents I1 and I2, the control voltage N3 at the control gate 22 of the protection device 16 quickly reaches a high voltage level, typically close to or at the VDD voltage level. The protection device 16 then clamps the power supply voltage VDD to the reference voltage VSS, thereby limiting the power supply voltage VDD to a safe voltage level. Figure 2B As shown. Note that during the third stage ③, the control voltage at the control gate 22 of the protection device 16 is high enough to fully turn on the protection device 16.

[0092] At the end of the third stage ③, when the control voltage N1 at the first internal node 24 has been recharged to a level higher than the switching threshold (e.g., half of VDD at that moment), the chains of inverters 28 and 30 flip back, thereby completely deactivating the first trigger element 32. As the control voltage N1 gradually increases, the current through the second trigger element 34 also slowly decreases and is eventually completely blocked at the end of the third stage ③ or the beginning of the fourth stage ④, so that the protection device 16 will be deactivated at the beginning of the fourth stage ④.

[0093] Figure 3A and Figure 3BThe operation of the first clamping circuit 10 during a transient OV event is illustrated when the chip is powered on. Electronic devices typically remain safe at the absolute maximum supply voltage, which is a function of the duration of stress. Therefore, in general, the triggering of the protection device should depend on the shape of the waveform of the OV event. Note that for a given OV event, the chip may need to respond to a smaller relative voltage increase in the powered-on state of the circuit to be protected compared to the unpowered state, because the initially stable supply voltage is closer to the SOA limit when the device is powered on.

[0094] In the first stage ①, the power supply voltage VDD corresponds to or is at least close to the nominal power supply voltage of the load. In this case, the voltage N1 at the first internal node 24 is also constant and substantially corresponds to the power supply voltage VDD. Therefore, the voltage difference between the power supply voltage VDD and the voltage N1 is practically zero, so that neither the first trigger element 32 nor the second trigger element 34 is triggered in this stage.

[0095] In the second stage ②, a sudden 0V occurs at the power supply voltage VDD. For example, due to ringing of the DC / DC converter, the power supply voltage VDD supplied at input 12 may increase by a few volts. In this stage, the power supply voltage VDD increases until the voltage difference between VDD 12 and the internal voltage 24 is large enough to satisfy the propagation time of the trigger circuit so that the control paths 18 and / or 20 of the clamping circuit 10 react.

[0096] At the end of the second stage ②, the difference between the power supply voltage VDD at input 12 and the voltage N1 at the first internal node 24 is sufficient to turn on the second trigger element 34 of the second control path 20, but still low enough not to flip inverters 28 and 30. Therefore, the voltage at node N2 remains high, and the first trigger element 32 of the first control path 18 remains off. The first control path 18 is unlikely to turn on because, assuming the inverter voltage threshold is set to half of VDD, the power supply voltage would need to be doubled to flip the inverter chain. In many cases, this would be too high. A possible solution is to reduce the switching voltage of the first inverter 28. However, this would introduce the risk of unwanted triggering during normal power-on. Furthermore, if the first control path 18 is used during power-on at 0V, the loop response time needs to be very fast to shut it off in time to prevent undervoltage.

[0097] Therefore, at the start of the third stage ③, the second control current I2 flows through the second trigger element 34, gradually disconnecting the discharge path through the protection device 16. Note that, compared with... Figure 2BCompared to the situation shown, the maximum current IDS(M0) through the protection device 16 is lower than in the case of an ESD event. This is due to the fact that both the second trigger element 34 and the protection device 16 are controlled in an analog manner in an OV event to prevent sudden breakdown of the power supply voltage VDD.

[0098] Once the externally supplied (over)voltage or charge is absorbed by the protection device through clamping, the power supply voltage VDD will begin to gradually decrease, as shown in the latter part of stage ③. This, in turn, leads to the gradual deactivation of the second trigger element 34 and a corresponding decrease in the second control current I2 to the control gate 22 of the protection device. Once the second trigger element 34 is fully deactivated, the gate voltage N3 will decrease as the charge stored at the control gate 22 is discharged through the discharge element 36. This, in turn, reduces the power supply voltage VDD as the charge stored at the control gate 22 is discharged through the discharge element 36. Figure 3B The discharge current IDS(M0) of the protection device is shown. Note that triggering the second control path 20 during 0V power-on allows current directly related to the 0V level to be absorbed through M0. This feature would not be available if the first control path 18 were used instead, where turn-on / turn-off speed would be critical to avoid circuit undervoltage. Also note that the maximum turn-on time of the protection device 16 is limited by the RC time constant for ESD events. Maximum turn-on time action is a safety mechanism to prevent thermal decomposition of the protection device 16 in the event of a prolonged 0V event. In this case, the internal load circuitry could therefore remain under stress and be damaged, as if no clamping circuit 10 were provided.

[0099] At the beginning of the final stage ④, when the voltage difference VDD-N1 drops below a given threshold voltage Vt2, trigger element 34 turns off, which in turn completely turns off protection device 16 again. For conventional chip designs (e.g., manufacturing processes allowing minimum MOSFET lengths of 130nm to 180nm), Vt2 can be in the range of 0.6V to 0.8V for a supply voltage of 1.5V to 1.8V. For more recent manufacturing processes (e.g., with a minimum permissible MOSFET length of 22nm), Vt2 can be closer to 0.4V for a supply voltage of 0.8V. Note that Vt2 can also be controlled during the design phase, for example, by adding appropriate injection to the semiconductor material used, to achieve a desired trade-off between low leakage current of protection device 16 in the off state, low resistivity of protection device 16 in the on state, and / or fast response time of clamping circuit 10.

[0100] Therefore, the control gate 22 is fully discharged via the discharge element 36. Once the gate voltage N3 drops below the minimum threshold voltage of the protection device 16, the protection device 16 blocks the discharge path, and the power supply voltage VDD returns to a stable state close to its nominal voltage.

[0101] Note that the first control path 18 uses a relatively strong trigger branch that will fully turn on the first trigger element 32 if an ESD event is detected by pulling the gate of the protection device 16 to the supply voltage VDD. Conversely, the second control path 20 is designed so that the protection device 16 gradually returns the supply voltage VDD to the pre-stress voltage level, thereby preventing reset or damage to the associated load.

[0102] As described above, the first control path 18 is turned on when the absolute voltage at node N1, representing the low-pass filtered version of the power supply voltage VDD, is lower than a first threshold level Vt1 given by a portion of the instantaneous VDD voltage. This means N1 < Vt1 = a·VDD, where a is a constant. The absolute value of VDD is relevant because it defines the first threshold level Vt1. When VDD - N1 > Vt2, the second control path 20 is turned on, where Vt2 is a second threshold given by the threshold voltage of MOSFET M2, independent of VDD. Typically, the first control path 18 is less likely to be triggered under power-on conditions due to its higher threshold, while the second control path 20 will be triggered with the same probability, independent of a stable VDD voltage. Therefore, the second control path 20 is more sensitive to voltage changes in the power supply voltage VDD when the clamping circuit 10 and any internal load circuitry are powered on. Simultaneously, it provides a smaller second control current I2 for charging the control gate 22 of the protection device 16, which can be more easily overcome by the discharge current through the discharge element 36. In this way, the current response of the second control path 20 is more subtle than that of the first control path 18. Note that the above design allows for a limitation on the size of the second MOSFET M2 compared to a protection circuit that only includes the second control path 20. This solution would require a relatively wide FET M2 to strongly drive node N3 to reliably protect the load circuit during an ESD event. A drawback is that any harmless disturbance to the power supply will result in significant leakage through MOSFET M2, which in turn increases the control voltage on FET M0 and its leakage, unacceptable in many applications. Furthermore, MOSFET M2 may be too easily triggered during normal power-up or due to harmless voltage disturbances, potentially triggering the protection device 16 unintentionally.

[0103] Note that the RC circuit 10, including the resistive element R1 and the capacitor element C1, corresponds to the first time constant τ1 = R1·C1. Furthermore, the discharge path provided by the capacitor associated with the resistor R2 and the protection device 16 (specifically, the parasitic capacitance Cpar of the control gate 22 of the BigMOS FET M0) corresponds to the second associated time constant τ2 = R2·Cper. In other embodiments, another capacitor element may be connected in parallel to the discharge element 36 and / or connected between the control gate 22 and the drain terminal of the FET M0 to modify the capacitance as needed. τ2 is typically chosen to be much smaller than τ1, meaning that the value of R2 must be small, so that M1 and M2 are wide enough to deliver sufficient current when triggered, thereby increasing the voltage of node N3 above the threshold of the FET M0.

[0104] Figure 4 Communication device 40 is shown, such as a user equipment (UE) device for a mobile telecommunications network. Alternatively, communication device 40 could also be another electronic device, such as a Global Navigation Satellite System (GNSS) receiver.

[0105] The communication device 40 includes a power supply 42 (e.g., a rechargeable battery), a power supply circuit 44 (particularly a DC / DC converter), and an integrated circuit (IC) 46. In other configurations, the power supply 42, such as an AC / DC adapter, may be external to the communication device and may be connected to the communication device via a plug connection or an inductive connection.

[0106] IC 46 may be a so-called System-on-a-Chip (SoC) and includes internal circuitry 48, such as the core of a microcontroller performing a device-specific function. IC 46 includes electrical protection circuitry in the form of a second clamping circuit 50, a first pin 52 for connecting IC 46 to the power supply voltage VDD provided by the power supply circuit 44, and a second pin 54 for connecting IC 46 to the reference potential VSS of the power supply circuit 44. Figure 4 As shown, an external power supply circuit 44 provides the power supply voltage VDD to IC 46 via pins 52 and 54. Alternatively, the power supply circuit 44 may be part of IC 46. In this case, pins 52 and 54 may be used to provide an external, potentially unregulated power supply voltage to the power supply circuit 44. The internal circuitry 48 operates from the power supply voltage VDD provided by the power supply circuit 44 via an internal voltage rail, and is protected from variations in the regulated power supply voltage VDD by a clamping circuit 50 connected between the power supply circuit 44 and the internal circuitry 48.

[0107] The second clamping circuit 50 has a reference Figures 1 to 3B The first clamping circuit 10 described is a similar design. Therefore, in the following text, only the differences in its design will be described.

[0108] and Figure 1 Conversely, as shown, IC 46 utilizes a second, lower supply voltage VDD_L provided at the second internal node 56. In the described embodiment, the corresponding voltage rails of the external supply voltage VDD and the second internal supply voltage VDD_L are electrically connected via two diodes D1 and D2, which establishes a predefined voltage difference between the first pin 52 and the second internal node 56. For example, a 5V external supply voltage VDD can be converted to a 3V internal supply voltage VDD_L. Instead of diodes D1 and D2, a series-connected controllable switch or current source can be used to connect the supply voltages VDD and VDD_L.

[0109] Note that the operating voltages of the first inverter 28 and the second inverter 30 are provided by the second internal node 56. Therefore, the first trigger element 32 and the second trigger element 34 are based on the voltage difference between the voltage VDD_L at the second internal node 56 and the first internal node 24, rather than through the voltage difference as previously referenced. Figure 1 The described voltage difference between the power supply voltage VDD and the first internal node 24 is used for triggering. Otherwise, the operation and settings of the clamping circuit 50 correspond to the settings and operation of the clamping circuit 10 as previously described. Although the clamping circuit 50 only monitors the internal power supply voltage VDD_L, it clamps the external power supply voltage VDD and thus effectively protects both current rails and any further operating voltages derived from them.

[0110] Figure 5 and Figure 6 It shows the relationship with Figure 1 and Figure 4 The embodiments shown are compared to the other two electrical protection circuits in the form of clamping circuits 60 and 80, which have a flip filter or RC circuit design.

[0111] In particular, Figure 5In the third clamping circuit 60 shown, the inverting RC circuit 66 includes a capacitor C1 connected between the power supply voltage VDD and the first internal node 24, and a resistor R1 connected between the first internal node 24 and the reference voltage VSS. Therefore, the voltage at the first internal node 24 substantially follows the reference voltage VSS, and the corresponding control voltages provided through the first control path 18 and the second control path 20 must also be inverted. Therefore, on the output sides of the two trigger elements 32 and 34, an inverter 62 is provided to invert the output signals provided by the first control path 18 and the second control path 20 before providing the inverting control signal to the protection device 16. Note that resistor R2 is also connected to the power supply voltage VDD to return the input of inverter 62 to a high voltage level, thereby resetting the clamping circuit 60. Inverter 62 can be instantiated using a CMOS logic gate with a load resistor or an NMOS / PMOS-only logic gate to maintain the correlation between the draw current at FET M0 and the magnitude of the power supply overvoltage.

[0112] Note that in Figure 5 In the illustrated embodiment, n-channel MOSFETs are used as the first trigger element 32 and the second trigger element 34. Furthermore, in Figure 5 In the first control path 18, only a single buffer 64 is shown, which internally contains an even number of inverters, as referenced above. Figure 1 The second control path 20 remains unchanged.

[0113] Figure 6 A possible implementation of the fourth clamping circuit 80 is shown, which has the same characteristics as described above. Figure 5 The inverting RC circuit 66 is configured in a similar way and described in detail.

[0114] Similarly, the first control path 18 includes an even number of inverters, shown as a single buffer 82, configured to provide a digital output signal to the combination element 84 in the form of an OR gate. The voltage provided by the second control path 20 is input to the inverter 86 to perform the desired inversion of the control signal provided at the first internal node 24. The output of the OR gate 84 is a digital signal. Therefore, the protection device 16 is always fully on and off. By designing the protection circuit 80, an OV event can be quenched without causing undervoltage, such that the feedback loop from the power supply through resistor R2, inverter 86, and OR gate 84 is fast enough to turn off the control gate 22 of the protection device 16 in time before the power supply voltage VDD drops below the undervoltage threshold voltage.

[0115] Note that the second control path 20 includes a MOSFET M2 as the first trigger element 34, as detailed previously, and an inverter 86. The MOSFET M2 essentially digitizes the control voltage provided at the first internal node 24 and provides a digital input control signal to the inverter 86. Note that the first control path 18 no longer includes any MOSFETs and is implemented entirely in the digital domain. Therefore, in this embodiment, the buffer 82 itself acts as the first trigger element 32. If at least one of the inputs of the combined element 84 is triggered via the first control path 18 or the second control path 20, the control gate 22 of the protection device 16 is pulled to the power supply voltage VDD provided as the operating voltage to the combined element 84, thereby activating the discharge path through it. In an alternative embodiment, the buffer 82 can be omitted, and the first internal node 24 can be directly connected to the corresponding input of the OR gate 84. In this case, the corresponding circuit portion of the OR gate 84 directly digitizes the provided control signal and acts as the first trigger element 32.

[0116] Notice, Figure 6 The fourth clamping circuit 80 shown works in conjunction with fully digital control signals from buffer 82 and inverter 86, causing the protection device to be fully turned on when one of trigger elements 32 or 34 is triggered. Nevertheless, the second control path 20 is still triggered based on an absolute change in the supply voltage VDD exceeding a fixed threshold Vt2, due to the gradual operation of MOSFET M2 as a tunable current source and the discharge path provided via resistor R2. In contrast, in the first control path 18, triggering occurs if the supply voltage VDD rapidly increases above a supply voltage-related threshold Vt1, rendering the first control path 18 ineffective for power-on OV events.

Claims

1. An electrical protection circuit, in particular an electrical clamping circuit (10, 50, 60, 80), the electrical protection circuit comprising: a protection device (16) electrically coupled between a supply voltage (VDD) input (12) and a reference potential (VSS) and having a control gate (22) for selectively activating a discharge path; an RC circuit (26, 66) electrically coupled between the supply voltage (VDD) input (12) and the reference potential (VSS) and having a first internal node (24) for providing a control voltage; a first control path (18) electrically coupled between the first internal node (24) and the control gate (22) of the protection device (16) and having a first triggering element (32) for triggering the protection device (16), wherein the first triggering element (32) is configured to act as a digital control element, in particular as a switch; and a second control path (20) electrically coupled between the first internal node (24) and the control gate (22) of the protection device (16) and having a second triggering element (34) for triggering the protection device (16), wherein the second triggering element (34) is configured to act as a gradual control element, in particular as a tunable current source or resistor.

2. The electrical protection circuit according to claim 1, wherein the first control path (18) is configured to have a first output current response to a transient voltage at the supply voltage (VDD) input (12) for triggering the protection device (16) in case of an unenergized overvoltage (OV) event, in particular an electrostatic discharge (ESD) event; and the second control path (20) is configured to have a second output current response to a transient voltage at the supply voltage (VDD) input (12) for triggering the protection device (16) in case of an energized OV event.

3. The electrical protection circuit of claim 1 or 2, wherein, the first control path (18) comprises at least one inverter (28, 30) for providing a digital control signal to a control gate of the first triggering element (32).

4. The electrical protection circuit of claim 3, wherein, the first triggering element (32) is a first enhancement mode field effect transistor (FET), in particular a first p-channel MOSFET (Ml), and the first control path (18) comprises an even number of inverters (28, 30) electrically coupled in series between the first internal node (24) and the control gate of the first FET.

5. The electrical protection circuit of claim 1, wherein, the second control path (20) is configured for providing an analog control signal to the second triggering element (34) by tracking a difference between an instantaneous supply voltage provided at the supply voltage (VDD) input (12) and a filtered supply voltage provided by the RC circuit (26, 66).

6. The electrical protection circuit of claim 1, wherein, The second control path (20) is configured to stop triggering the protection device (16) if a voltage difference between the power supply voltage (VDD) input (12) and the first internal node (24) falls below a predefined threshold voltage.

7. The electrical protection circuit of claim 1, wherein, The second triggering element (34) is a second enhancement mode field effect transistor, FET, in particular a second p-channel MOSFET (M2), and the first internal node (24) is directly electrically connected to a control gate of the second FET.

8. The electrical protection circuit according to claim 1, further comprising a discharge element (36), in particular a resistor (R2) or a FET element with a dynamic drive gate, electrically coupled to the control gate (22) of the protection device (16) for discharging the control gate (22) of the protection device (16) in case both the first control path (18) and the second control path (20) are disabled.

9. The electrical protection circuit of claim 8, wherein, A first time constant defined by the RC circuit (26, 66) is greater than a second time constant defined by the discharge element (36) and a capacitive element associated with the protection device (16), in particular a parasitic capacitance of the control gate (22) of the protection device (16).

10. The electrical protection circuit according to claim 1, further comprising a combining element (84), in particular a logic OR gate, a first input of the combining element (84) being electrically coupled to the first triggering element (32), a second input of the combining element (84) being electrically coupled to the second triggering element (34), and an output of the combining element (84) being electrically coupled to the control gate (22) of the protection device (16).

11. The electrical protection circuit of claim 1, wherein, The RC circuit (26) comprises a resistive element (R1) electrically coupled between the power supply voltage (VDD) input (12) and the first internal node (24), and a capacitive element (C1) electrically coupled between the first internal node (24) and the reference potential (VSS).

12. The electrical protection circuit of claim 1, wherein, The RC circuit (66) comprises a capacitive element (C1) electrically coupled between the power supply voltage (VDD) input (12) and the first internal node (24), and a resistive element (R1) electrically coupled between the first internal node (24) and the reference potential (VSS).

13. The electrical protection circuit according to any one of claims 11 or 12, further comprising a second internal node (56) electrically coupled to the power supply voltage (VDD) input (12) by means of one or more diodes (D1, D2), switches and / or current sources for providing a second power supply voltage (VDD L) monitored by the RC circuit (26, 66), wherein, A power supply voltage input of at least one of the first triggering element (32) and the second triggering element (34) is electrically coupled to the second power supply voltage (VDD_L).

14. An integrated circuit, IC (46), in particular a system on chip, SoC, the integrated circuit comprising: a first voltage rail for providing a power supply voltage (VDD); a second voltage rail for providing a reference voltage (VSS); an internal circuit (48) configured to be powered by the power supply voltage (VDD); and The electrical protection circuit according to any one of claims 1 to 13, electrically coupled between the first voltage rail and the second voltage rail and configured to protect the internal circuit (48) against unpowered overvoltage, OV, events, in particular electrostatic discharge, ESD, events and powered OV events.

15. A mobile communication device (40), in particular a user equipment, UE, or a global navigation satellite system, GNSS, device, comprising: The integrated circuit (46) according to claim 14; and a power supply circuit (44), in particular a DC / DC converter circuit, wherein output terminals of the power supply circuit (44) are electrically coupled to the first voltage rail and to the second voltage rail of the integrated circuit (46).

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