A three-level seven-phase inverter

Abstract

The application discloses a three-level seven-phase inverter, which comprises a direct-current voltage source, two voltage division capacitors, a three-level T-type bridge arm, six two-level half bridge arms and corresponding loads; the positive and negative poles of the direct-current voltage source are connected with two ends of the two voltage division capacitors respectively, the three-level T-type bridge arm comprises four switch tubes, three ports of the three-level T-type bridge arm are connected with a neutral point between the two voltage division capacitors and two ends of the two voltage division capacitors respectively, and the three-level T-type bridge arm realizes three switching states; the six two-level half bridge arms are of the same structure, comprise two switch tubes, form half bridge arms, and two ports of the half bridge arms are connected with two ends of the two voltage division capacitors respectively; each two-level half bridge arm realizes two switching states; and the three-level T-type bridge arm and the six two-level half bridge arms are connected with corresponding loads of each phase respectively. The application is suitable for high-voltage and high-power industrial scenes and high-reliability fields, and can reduce harmonic interference and loss of a motor and a power network.

Description

Technical Field

[0001] This invention relates to the field of power electronic systems, and more specifically to a three-level seven-phase inverter. Background Technology

[0002] The demand for high reliability, low interference, and high power density in power conversion systems is increasingly urgent in high-voltage, high-power applications such as heavy-duty electric vehicles, rail transit, and wind power converters. Inverters, as the core power conversion unit in these applications, directly determine the system's operating efficiency, equipment lifespan, and safety stability. Therefore, developing inverter topologies that are adaptable to high-voltage, high-power scenarios and balance performance and economy has significant engineering value and practical implications.

[0003] While traditional three-phase inverters are relatively mature in application, they have significant limitations in high-voltage, high-power scenarios. On one hand, the switching transistors of three-phase inverters must withstand the full DC bus voltage, resulting in high voltage stress. In high-voltage scenarios, special high-voltage components must be selected, significantly increasing costs. On the other hand, the magnetomotive force waveform output by a three-phase inverter is close to a square wave, with high harmonic content, easily generating strong electromagnetic interference, leading to excessive motor bearing current, accelerated insulation aging, and shortened motor lifespan. Traditional low-phase inverters have poor fault tolerance; a single-phase failure can easily cause system shutdown or derating. Furthermore, the high harmonic content of the output magnetomotive force waveform easily generates electromagnetic interference and bearing current, and the switching transistors withstand significant current or voltage stress, making them unsuitable for the demands of high-voltage, high-power scenarios.

[0004] To address these issues, multiphase inverters have gradually become a research hotspot due to their multiphase redundancy and current distribution advantages. Compared to three-phase systems, multiphase systems have lower switching current stress, stronger fault tolerance, and a magnetomotive force waveform that is closer to a sine wave, effectively reducing torque ripple and harmonic interference.

[0005] Therefore, developing a novel multiphase inverter topology that can balance common-mode voltage (CMV) suppression, number of switches, and control complexity is of great research significance and application value for promoting the technological upgrading and industrial application of high-voltage, high-power power conversion systems. Summary of the Invention

[0006] The purpose of this invention is to provide a three-level seven-phase inverter that adopts a hybrid topology structure of one three-level bridge arm combined with six two-level bridge arms, and with an optimized space vector pulse width modulation strategy, to achieve multi-phase collaborative control and precise common-mode voltage suppression.

[0007] To achieve the above functions, this invention designs a three-level seven-phase inverter, characterized in that it includes a DC voltage source, two voltage dividing capacitors, a three-level T-bridge arm, six two-level half-bridge arms, and corresponding loads;

[0008] The DC voltage source's positive and negative terminals are connected to the two ends of two equal-capacitive voltage-dividing capacitors, respectively. The three-level T-arm comprises four switching transistors, forming the T-arm. The three ports of the T-arm are connected to the neutral point between the two voltage-dividing capacitors and the two ends of the two voltage-dividing capacitors, respectively. The three-level T-arm achieves three switching states, corresponding to phase A of the three-level seven-phase inverter. The six two-level half-arms have identical structures, each containing two switching transistors, forming a half-arm. The two ports of the half-arm are connected to the two ends of the two voltage-dividing capacitors, respectively. Each two-level half-arm achieves two switching states, corresponding sequentially to phases B, C, D, E, F, and G of the three-level seven-phase inverter. One three-level T-arm and six two-level half-arms are connected to the corresponding loads of each phase.

[0009] As a preferred embodiment of the present invention: the two voltage-dividing capacitors are two equal-capacitance voltage-dividing capacitors, including voltage-dividing capacitor C1 and voltage-dividing capacitor C2; the four switching transistors in the three-level T-type bridge arm are four IGBT switching transistors, which are respectively the upper switch transistors S. A1 The switching transistor S acts as the lower switch. A2 The switching transistor S acts as a bidirectional switch. A3 Switch S A4 Two of the six two-level half-bridge arms are IGBT switches, with the B-phase half-bridge arm containing switch S. B1 Switch S B2 The C-phase half-bridge arm includes the switching transistor S. C1 Switch S C2 The D-phase half-bridge arm includes the switching transistor S. D1 Switch S D2 The E-phase half-bridge arm includes the switching transistor S. E1 Switch S E2 The F-phase half-bridge arm includes the switching transistor S. F1 Switch S F2 The G-phase half-bridge arm includes the switching transistor S. G1 Switch S G2 ;

[0010] In this configuration, the positive terminal of the DC voltage source is connected to one end of the voltage-dividing capacitor C1, and the negative terminal of the DC voltage source is connected to one end of the voltage-dividing capacitor C2. The other ends of the voltage-dividing capacitors C1 and C2 are connected together as a neutral point. Simultaneously, the positive terminal of the DC voltage source is connected to the switching transistor S in the three-level T-bridge arm. A1 The drain of the bridge, and the switching transistor S in the six two-level half-bridge arms. B1 Switch S C1 Switch S D1 Switch S E1 Switch S F1 Switch S G1The drain of the DC voltage source and the negative terminal of the DC voltage source are respectively connected to the switching transistor S in the three-level T-bridge arm. A2 The source of the bridge, and the switching transistor S in the six two-level half-bridge arms. B2 Switch S C2 Switch S D2 Switch S E2 Switch S F2 Switch S G2 The source; in the three-level T-bridge arm, the switching transistor S A4 The drain of the transistor is connected to the neutral point between the voltage divider capacitors C1 and C2, and the switching transistor S... A4 The source and the switch S A3 The source of the switch is connected to the source of the switch S. A3 The drain and the switching transistor S A1 The source and switch S A2 The drains are connected;

[0011] In the six two-level half-bridge arms, the switching transistor S B1 The source and the switch S B2 The drains of the switching transistor S are connected. C1 The source and the switch S C2 The drains of the switching transistor S are connected. D1 The source and the switch S D2 The drains of the switching transistor S are connected. E1 The source and the switch S E2 The drains of the switching transistor S are connected. F1 The source and the switch S F2 The drains of the switching transistor S are connected. G1 The source and the switch S G2 The drains are connected;

[0012] The loads of phases A, B, C, D, E, F, and G are respectively load L. A Load L B Load L C Load L D Load L E Load L F Load L G Among them, the load L A Load L B Load L C Load L D Load L E Load L F Load L G One end is connected to the corresponding switching transistor S. A1 Switch S B1 Switch S C1 Switch SD1 Switch S E1 Switch S F1 Switch S G1 The source and the other end are connected to each other.

[0013] As a preferred embodiment of the present invention, the gate of each switching transistor is connected to an isolated gate driver.

[0014] As a preferred embodiment of the present invention: the three-level T-shaped bridge arm has three switching states, namely switching state 0, switching state 1, and switching state 2, to achieve three-level adjustment; wherein, the switching state 0 of the three-level T-shaped bridge arm specifically refers to the switching transistor S A1 Turn off, switch S A2 On, switch S A3 When turned off, the phase voltage V of phase A An =-0.5V dc V dc This indicates the voltage value of the DC voltage source; switch state 1 specifically refers to the switching transistor S. A1 Turn off, switch S A2 Turn off, switch S A3 When the circuit is turned on, the phase voltage V of phase A is... An =0; Switch state 2 specifically refers to the switching transistor S. A1 On, switch S A2 Turn off, switch S A3 When turned off, the phase voltage V of phase A An =0.5V dc .

[0015] As a preferred embodiment of the present invention: each half-bridge arm in the two-level half-bridge arm has two switching states, namely switching state 0 and switching state 2, to achieve two-level adjustment; wherein, the switching state 0 of the two-level half-bridge arm specifically refers to the switching transistor S. l1 Turn off, switch S l2 When the circuit is turned on, the phase voltage V of phase l is... ln =-0.5V dc V dc This indicates the voltage value of the DC voltage source; switch state 2 specifically refers to the switching transistor S. l1 On, switch S l2 When turned off, the phase voltage V of phase l ln =0.5V dc ,in .

[0016] As a preferred technical solution of the present invention: reference output voltage vector ( Calculate according to the following formula:

[0017] ;

[0018] ;

[0019] in, , These are the reference output voltage vectors ( )exist , Components of the axis, The value is , indicating that the reference output voltage vector is The angle formed by the axis; This indicates the sector number in a three-level seven-phase inverter; The reference voltage is calculated using the following formula:

[0020] ;

[0021] ;

[0022] in, Indicates the modulation index. This represents the floor function; This indicates the voltage value of the DC voltage source.

[0023] As a preferred technical solution of the present invention: a three-level seven-phase inverter in Large vectors in a coordinate system and zero voltage vector The corresponding conduction time , , , , , , The mathematical expression is as follows:

[0024] ;

[0025] ;

[0026] ;

[0027] ;

[0028] ;

[0029] ;

[0030] ;

[0031] in, It's the on / off time. , , ; , These are the reference output voltage vectors ( )exist , The components of the axis;

[0032] The duration of action of the intermediate voltage vector is calculated as follows:

[0033] ;

[0034] in, , Represents two intermediate voltage vectors The corresponding duration of action.

[0035] Beneficial effects: Compared with the prior art, the advantages of the present invention include:

[0036] The fault tolerance of the three-level seven-phase inverter designed in this invention is significantly improved. It can still operate stably at full power even in the event of a single-phase fault. At the same time, it effectively reduces output harmonics and electromagnetic interference, reduces the stress on the switching transistors, and takes into account system reliability, operational stability and adaptability to high-voltage and high-power scenarios.

[0037] This invention uses a total of 16 IGBT devices. Through the midpoint voltage regulation of the three-level bridge arm and the coordinated control of the two-level bridge arm, it has the ability to self-balance the midpoint voltage. It is suitable for industrial scenarios with high voltage, high power and high electromagnetic compatibility requirements. Compared with the traditional two-level seven-phase inverter, it performs better in common-mode voltage suppression and device stress optimization. Attached Figure Description

[0038] Figure 1 This is a topology diagram of a three-level seven-phase inverter provided according to an embodiment of the present invention. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0040] Compared to traditional three-phase inverters, multiphase inverters offer significant advantages. Common multiphase topologies include five-phase full-bridge, seven-phase mixed-level, or nine-phase cascaded half-bridge. Multiphase inverters not only enable power output from more phases, thus reducing current stress on the switching transistors, but also achieve higher fault tolerance and power density, while reducing the size of the motor and inverter system and losses during energy conversion.

[0041] Among them, the seven-phase inverter is a special type of inverter used to convert direct current (DC) power to alternating current (AC) power. Unlike traditional three-phase inverters, seven-phase inverters have seven independent phase windings and corresponding power conversion arms, enabling them to output seven AC voltages with phase differences of a specific angle, thereby achieving a magnetomotive force waveform that more closely approximates a sine wave. Seven-phase inverters typically require more complex circuit topologies and control strategies because precise combinations of various switching states are needed to ensure current balance among multiple phases. They have important applications in high-voltage, high-power industrial scenarios and high-reliability fields to improve system fault tolerance, reduce switching transistor stress, and minimize harmonic interference and losses to motors and power networks.

[0042] The present invention provides a three-level seven-phase inverter, comprising a DC voltage source, two voltage dividing capacitors, a three-level T-bridge arm, six two-level half-bridge arms, and corresponding loads;

[0043] Reference Figure 1 , Figure 1 The left side of the diagram represents the DC voltage input, which consists of two equal-capacitance voltage-dividing capacitors connected in parallel to form the DC bus. The midpoint O is the neutral point. Figure 1 The right side of the diagram represents a seven-phase AC load. The positive and negative terminals of the DC voltage source are connected to the two ends of two equal-capacitive voltage-dividing capacitors, respectively. The three-level T-arm consists of four switching transistors forming a T-arm. The three ports of the T-arm are connected to the neutral point between the two voltage-dividing capacitors and the two ends of the two voltage-dividing capacitors, respectively. The three-level T-arm achieves three switching states, corresponding to phase A of the three-level seven-phase inverter. The six two-level half-arms have the same structure, each containing two switching transistors forming a half-arm. The two ports of the half-arm are connected to the two ends of the two voltage-dividing capacitors, respectively. Each switching transistor is an IGBT, and the gate of each switching transistor needs to be connected to an isolated gate driver to provide the drive voltage and current required by the device, ensuring that the switching transistor can be turned on or off quickly and reliably. At the same time, PWM signals are used to achieve complementary conduction of the upper and lower switching transistors of each phase arm, and a dead time needs to be set to avoid arm shoot-through. The input control signal terminal is the input interface for the PWM drive signal, used to receive the switching control signal output by the controller, and then drive the auxiliary switches in the topology to realize the voltage division and level adjustment of the DC bus. Each two-level half-bridge arm realizes two switching states, and each two-level half-bridge arm corresponds to the B, C, D, E, F, and G phases of the three-level seven-phase inverter in sequence to control the basic phase voltage output; one three-level T-type bridge arm and six two-level half-bridge arms are connected to the corresponding loads of each phase; without the need for multiple independent DC power supplies, only a single DC bus is used for power supply. Combined with precise control of the switching states, CMV suppression is achieved, which improves performance while simplifying system complexity and reducing the number of switching transistors.

[0044] The two voltage-dividing capacitors are two equal-capacitance voltage-dividing capacitors, including voltage-dividing capacitor C1 and voltage-dividing capacitor C2; the four switching transistors in the three-level T-bridge arm are four IGBT switching transistors, namely the upper switch S. A1 The switching transistor S acts as the lower switch. A2 The switching transistor S acts as a bidirectional switch. A3 Switch S A4 Two of the six two-level half-bridge arms are IGBT switches, with the B-phase half-bridge arm containing switch S. B1 Switch S B2 The C-phase half-bridge arm includes the switching transistor S. C1 Switch S C2 The D-phase half-bridge arm includes the switching transistor S. D1 Switch S D2 The E-phase half-bridge arm includes the switching transistor S. E1 Switch S E2 The F-phase half-bridge arm includes the switching transistor S. F1 Switch S F2 The G-phase half-bridge arm includes the switching transistor S. G1 Switch S G2 ;

[0045] In this configuration, the positive terminal of the DC voltage source is connected to one end of the voltage-dividing capacitor C1, and the negative terminal of the DC voltage source is connected to one end of the voltage-dividing capacitor C2. The other ends of the voltage-dividing capacitors C1 and C2 are connected together as a neutral point. Simultaneously, the positive terminal of the DC voltage source is connected to the switching transistor S in the three-level T-bridge arm. A1 The drain of the bridge, and the switching transistor S in the six two-level half-bridge arms. B1 Switch S C1 Switch S D1 Switch S E1 Switch S F1 Switch S G1 The drain of the DC voltage source and the negative terminal of the DC voltage source are respectively connected to the switching transistor S in the three-level T-bridge arm. A2 The source of the bridge, and the switching transistor S in the six two-level half-bridge arms. B2 Switch S C2 Switch S D2 Switch S E2 Switch S F2 Switch S G2 The source; in the three-level T-bridge arm, the switching transistor S A4 The drain of the transistor is connected to the neutral point between the voltage divider capacitors C1 and C2, and the switching transistor S... A4 The source and the switch S A3 The source of the switch is connected to the source of the switch S. A3 The drain and the switching transistor S A1The source and switch S A2 The drains are connected;

[0046] In the six two-level half-bridge arms, the switching transistor S B1 The source and the switch S B2 The drains of the switching transistor S are connected. C1 The source and the switch S C2 The drains of the switching transistor S are connected. D1 The source and the switch S D2 The drains of the switching transistor S are connected. E1 The source and the switch S E2 The drains of the switching transistor S are connected. F1 The source and the switch S F2 The drains of the switching transistor S are connected. G1 The source and the switch S G2 The drains are connected;

[0047] The loads of phases A, B, C, D, E, F, and G are respectively load L. A Load L B Load L C Load L D Load L E Load L F Load L G Among them, the load L A Load L B Load L C Load L D Load L E Load L F Load L G One end is connected to the corresponding switching transistor S. A1 Switch S B1 Switch S C1 Switch S D1 Switch S E1 Switch S F1 Switch S G1 The source and the other end are connected to each other.

[0048] Each switch's gate is connected to an isolated gate driver.

[0049] The three-level T-bridge arm has three switching states: switching state 0, switching state 1, and switching state 2, realizing three-level adjustment; specifically, switching state 0 of the three-level T-bridge arm is achieved by switching transistor S. A1 Turn off, switch S A2 On, switch S A3 When turned off, the phase voltage V of phase A An =-0.5V dcV dc This indicates the voltage value of the DC voltage source; switch state 1 specifically refers to the switching transistor S. A1 Turn off, switch S A2 Turn off, switch S A3 When the circuit is turned on, the phase voltage V of phase A is... An =0; Switch state 2 specifically refers to the switching transistor S. A1 On, switch S A2 Turn off, switch S A3 When turned off, the phase voltage V of phase A An =0.5V dc Achieving three-level regulation; The switching states and phase voltages of the A-phase three-level T-type bridge arm are shown in Table 1 below:

[0050] Table 1. Switching states and phase voltages of the three-level bridge arm in phase A

[0051]

[0052] The BG phase is a traditional two-level half-bridge arm. Each half-bridge arm in the two-level half-bridge arm has two switching states: switching state 0 and switching state 2, to achieve two-level adjustment. Specifically, switching state 0 of the two-level half-bridge arm is the switching transistor S. l1 Turn off, switch S l2 When the circuit is turned on, the phase voltage V of phase l is... ln =-0.5V dc V dc This indicates the voltage value of the DC voltage source; switch state 2 specifically refers to the switching transistor S. l1 On, switch S l2 When turned off, the phase voltage V of phase l ln =0.5V dc ,in Short circuits in the bridge arms are avoided through complementary conduction; the switching states and phase voltages of the two-level half-bridge arms of the BG phase are shown in Table 2 below:

[0053] Table 2. Switching states and phase voltages of the two-level bridge arms in phase BG

[0054]

[0055] Therefore, the unified expression for phase voltage is:

[0056] ;

[0057] As shown in Tables 1 and 2, the A-phase bridge arm has Three valid states, BG phase has There are two valid states, therefore the total theoretical number of switching states is To generate the desired output voltage of a three-level seven-phase inverter, the switching states need to be filtered and the duration of each state calculated. The phase voltage of the three-level seven-phase inverter can be expressed as:

[0058] (1);

[0059] In the formula This indicates the phase relationship between two adjacent phases in a three-level seven-phase inverter. Represents the reference output voltage vector and The angle formed by the axis; For reference voltage, , , , , , , These are the phase voltages of phases A, B, C, D, E, F, and G, respectively.

[0060] The voltage space vector of the three-level seven-phase inverter is evenly divided into 14 sectors according to angle, with each sector having an angle of [missing information]. The first sector is a sector. , by sector For example, in this sector, Substituting this into equation (1), the phase voltage must satisfy the following condition: Therefore, the polarity must also meet the following requirements. In one embodiment, for switch state 2200002, the phase voltage magnitude is 0.5. 0.5 -0.5 -0.5 -0.5 -0.5 0.5 .

[0061] The control objective of a three-level seven-phase inverter is to make the sum of the voltage components in subspaces xy and uv zero, thereby eliminating harmonics. The xy subspace is used to map components that do not participate in electromechanical energy conversion. The second harmonic components (k=1,3,5…); the uv subspace is used to map another set of orthogonal harmonic components, which are then combined with… The subspaces together constitute the decoupled coordinate system of the seven-phase inverter, achieving separate control of harmonics and the fundamental frequency. To achieve this, a zero-vector action is required within each switching cycle; the synthesized space vector volt-second is defined as follows:

[0062] (2);

[0063] (3);

[0064] in, It is the switching time, where the vector These correspond to three-level seven-phase inverters respectively. Large vectors in a coordinate system This represents the zero-voltage vector. (Vector) , , , , , , The conduction times are respectively , , , , , , .also, , , , , , as well as , , , , , These are the switching vectors. , , , , , Related Quantity, and Quantity and The components are respectively , , , , , , , , , , , as well as , , , , , , , , , , , . of , as well as The component is zero, assuming The shaft is located at Therefore Reference output voltage vector ( )exist , The components of the shaft can be calculated according to equations (4) and (5) respectively:

[0065] (4);

[0066] (5);

[0067] in, The value is , indicating that the reference output voltage vector is The angle formed by the axis; Indicates the sector number in a three-level seven-phase inverter; reference voltage As shown in equation (6), where Indicates the modulation index:

[0068] (6);

[0069] (7);

[0070] in, This represents the floor function, used to discretize the calculated switching state duration.

[0071] By combining equations (2) and (7), the conduction time can be obtained. , , , , , , The mathematical expression:

[0072] (8);

[0073] (9);

[0074] (10);

[0075] (11);

[0076] (12);

[0077] (13);

[0078] (14);

[0079] in , , To reduce common-mode voltage, the embodiment uses... Instead of the traditional zero vector, where Two intermediate voltage vectors are represented by subscripts. , Each element in the distinguishing vector represents the conduction state of each phase switch. Therefore, the duration of the two intermediate voltage vectors... The calculation is as follows:

[0080] (15);

[0081] The seven-phase inverter designed in this invention is compared with a conventional inverter, and the results are shown in Table 3 below:

[0082] Table 3. Comparison between the three-level seven-phase inverter of this invention and a conventional seven-phase inverter.

[0083]

[0084] In summary, this invention designs a three-level seven-phase inverter topology. This topology employs a hybrid architecture of one three-level T-arm and six two-level half-arms, utilizing a total of 16 IGBT devices. Through midpoint voltage regulation of the three-level arm and coordinated control of the two-level arms, the peak-to-peak common-mode voltage can be reduced to a minimum. Common-mode voltage variation as low as It also has the ability to self-balance the midpoint voltage, making it suitable for high-voltage, high-power industrial scenarios with high electromagnetic compatibility requirements. Compared with traditional two-level seven-phase inverters, it performs better in common-mode voltage suppression and device stress optimization.

[0085] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A three-level seven-phase inverter, characterized in that, It includes a DC voltage source, two voltage divider capacitors, a three-level T-bridge arm, six two-level half-bridge arms, and corresponding loads; The DC voltage source's positive and negative terminals are connected to the two ends of two equal-capacitive voltage-dividing capacitors, respectively. The three-level T-arm comprises four switching transistors, forming the T-arm. The three ports of the T-arm are connected to the neutral point between the two voltage-dividing capacitors and the two ends of the two voltage-dividing capacitors, respectively. The three-level T-arm achieves three switching states, corresponding to phase A of the three-level seven-phase inverter. The six two-level half-arms have identical structures, each containing two switching transistors, forming a half-arm. The two ports of the half-arm are connected to the two ends of the two voltage-dividing capacitors, respectively. Each two-level half-arm achieves two switching states, and each two-level half-arm corresponds sequentially to phases B, C, D, E, F, and G of the three-level seven-phase inverter. One three-level T-arm and six two-level half-arms are connected to the corresponding loads of each phase. The aforementioned three-level seven-phase inverter in Large vectors in a coordinate system and zero voltage vector The corresponding conduction time , , , , , , The mathematical expression is as follows: ； ； ； ； ； ； ； in, It's the on / off time. , , ; , These are the reference output voltage vectors ( )exist , The components of the axis; The duration of action of the intermediate voltage vector is calculated as follows: ； in, , Represents two intermediate voltage vectors The corresponding duration of action.

2. The three-level seven-phase inverter according to claim 1, characterized in that, The two voltage-dividing capacitors are two equal-capacitance voltage-dividing capacitors, including voltage-dividing capacitor C1 and voltage-dividing capacitor C2; the four switching transistors in the three-level T-bridge arm are four IGBT switching transistors, namely the upper switch S. A1 The switching transistor S acts as the lower switch. A2 The switching transistor S acts as a bidirectional switch. A3 Switch S A4 Two of the six two-level half-bridge arms are IGBT switches, with the B-phase half-bridge arm containing switch S. B1 Switch S B2 The C-phase half-bridge arm includes the switching transistor S. C1 Switch S C2 The D-phase half-bridge arm includes the switching transistor S. D1 Switch S D2 The E-phase half-bridge arm includes the switching transistor S. E1 Switch S E2 The F-phase half-bridge arm includes the switching transistor S. F1 Switch S F2 The G-phase half-bridge arm includes the switching transistor S. G1 Switch S G2 ; In this configuration, the positive terminal of the DC voltage source is connected to one end of the voltage-dividing capacitor C1, and the negative terminal of the DC voltage source is connected to one end of the voltage-dividing capacitor C2. The other ends of the voltage-dividing capacitors C1 and C2 are connected together as a neutral point. Simultaneously, the positive terminal of the DC voltage source is connected to the switching transistor S in the three-level T-bridge arm. A1 The drain of the bridge, and the switching transistor S in the six two-level half-bridge arms. B1 Switch S C1 Switch S D1 Switch S E1 Switch S F1 Switch S G1 The drain of the DC voltage source and the negative terminal of the DC voltage source are respectively connected to the switching transistor S in the three-level T-bridge arm. A2 The source of the bridge, and the switching transistor S in the six two-level half-bridge arms. B2 Switch S C2 Switch S D2 Switch S E2 Switch S F2 Switch S G2 The source; in the three-level T-bridge arm, the switching transistor S A4 The drain of the transistor is connected to the neutral point between the voltage divider capacitors C1 and C2, and the switching transistor S... A4 The source and the switch S A3 The source of the switch is connected to the source of the switch S. A3 The drain and the switching transistor S A1 The source and switch S A2 The drains are connected; In the six two-level half-bridge arms, the switching transistor S B1 The source and the switch S B2 The drains of the switching transistor S are connected. C1 The source and the switch S C2 The drains of the switching transistor S are connected. D1 The source and the switch S D2 The drains of the switching transistor S are connected. E1 The source and the switch S E2 The drains of the switching transistor S are connected. F1 The source and the switch S F2 The drains of the switching transistor S are connected. G1 The source and the switch S G2 The drains are connected; The loads of phases A, B, C, D, E, F, and G are respectively load L. A Load L B Load L C Load L D Load L E Load L F Load L G Among them, the load L A Load L B Load L C Load L D Load L E Load L F Load L G One end is connected to the corresponding switching transistor S. A1 Switch S B1 Switch S C1 Switch S D1 Switch S E1 Switch S F1 Switch S G1 The source and the other end are connected to each other.

3. A three-level seven-phase inverter according to claim 2, characterized in that, Each switch's gate is connected to an isolated gate driver.

4. A three-level seven-phase inverter according to claim 2, characterized in that, The three-level T-bridge arm has three switching states: switching state 0, switching state 1, and switching state 2, realizing three-level adjustment; specifically, switching state 0 of the three-level T-bridge arm is achieved by switching transistor S. A1 Turn off, switch S A2 On, switch S A3 When turned off, the phase voltage V of phase A An =-0.5V dc V dc This indicates the voltage value of the DC voltage source; switch state 1 specifically refers to the switching transistor S. A1 Turn off, switch S A2 Turn off, switch S A3 When the circuit is turned on, the phase voltage V of phase A is... An =0; Switch state 2 specifically refers to the switching transistor S. A1 On, switch S A2 Turn off, switch S A3 When turned off, the phase voltage V of phase A An =0.5V dc .

5. A three-level seven-phase inverter according to claim 4, characterized in that, Each half-bridge arm in the two-level half-bridge has two switching states: switching state 0 and switching state 2, to achieve two-level adjustment; specifically, switching state 0 of the two-level half-bridge arm is achieved by switching transistor S. l1 Turn off, switch S l2 When the circuit is turned on, the phase voltage V of phase l is... ln =-0.5V dc V dc This indicates the voltage value of the DC voltage source; switch state 2 specifically refers to the switching transistor S. l1 On, switch S l2 When turned off, the phase voltage V of phase l ln =0.5V dc ,in .

6. A three-level seven-phase inverter according to claim 5, characterized in that, Reference output voltage vector ( Calculate according to the following formula: ； ； in, , These are the reference output voltage vectors ( )exist , Components of the axis, The value is , indicating that the reference output voltage vector is The angle formed by the axis; This indicates the sector number in a three-level seven-phase inverter; The reference voltage is calculated using the following formula: ； ； in, Indicates the modulation index. This represents the floor function; This indicates the voltage value of the DC voltage source.

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