Digitally controlled oscillator

Abstract

The present disclosure relates to an oscillator, such as a digitally controlled oscillator (DCO), having a first capacitor bank coupled to a first path connecting a first node to a first output node and a second path connecting a second node to a second output node; and a second capacitor bank coupled to a third path and a fourth path, the third path being connected to the first node, the fourth path being connected to the second node, the first path and the second path being separate from the third path and the fourth path, and the second capacitor bank comprises at least one modulation capacitor bank.

Description

TECHNICAL FIELD

[0001] Embodiments of the subject matter described herein relate generally to oscillators, such as digitally controlled oscillators that can be used in phase-locked loop (PLL) circuitry. BACKGROUND

[0002] Phase-locked loops (PLLs) are widely used in radio, telecommunications, computers, and other electronic applications. PLLs can be used to demodulate signals, recover signals from noisy communication channels, generate stable frequencies at multiple input frequencies, or distribute accurate timing clock pulses in digital logic circuits such as microprocessors. For example, in ranging applications using radar technology, a linear frequency modulated signal is used, which is generated by a PLL containing a frequency modulated oscillator. Distances to objects or people are determined based on the frequency difference between the transmitted and reflected waves. The accuracy of these distance measurements is very sensitive to deviations and errors in the linear frequency modulated signal (e.g., chirp) generated by the oscillator of the PLL. SUMMARY

[0003] An oscillator includes a first plurality of capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node, and the second path connecting a second node to a second output node, and a second plurality of capacitor banks coupled to a third path and a fourth path, the third path connected to the first node, the fourth path connected to the second node, the first and second paths separate from the third and fourth paths, and the second plurality of capacitor banks including at least one modulating capacitor bank.

[0004] In one or more embodiments, the at least one modulating capacitor bank is configured to receive at least a first control signal that modifies at least one capacitance of the at least one modulating capacitor bank, and the at least one modulating capacitor bank is configured to cause a frequency modulation of an output signal of the oscillator.

[0005] In one or more embodiments, the first plurality of capacitor banks includes a process-voltage-temperature (PVT) capacitor bank configured to receive a second control signal, a acquisition capacitor bank configured to receive a third control signal, and a tracking capacitor bank configured to receive a fourth control signal. The second, third, and fourth control signals modify capacitances of the PVT capacitor bank, the acquisition capacitor bank, and the tracking capacitor bank, respectively, to achieve phase locking of a phase-locked loop (PLL) including the oscillator, and to at least partially compensate for variations in process, supply voltage, or temperature of the oscillator.

[0006] In one or more embodiments, at least one modulation capacitor bank includes a fine modulation capacitor bank having a first discrete step length and a coarse modulation capacitor bank having a second discrete step length greater than the first discrete step length.

[0007] In one or more embodiments, a first plurality of capacitor banks are arranged in parallel between a first path and a second path, and a second plurality of capacitor banks are arranged in parallel between a third path and a fourth path.

[0008] In one or more embodiments, the first plurality of capacitor banks and the second plurality of capacitor banks are arranged from the first node and the second node to the output node in an order of decreasing discrete step size, and the discrete step size of a given capacitor bank in the first plurality of capacitor banks or the second plurality of capacitor banks is based on the block size of the given capacitor bank.

[0009] In one or more embodiments, the oscillator further includes a current source, a first inductor, a negative transconductance stage, and a second inductor, the first inductor being coupled to the current source and between a first node and a second node, the negative transconductance stage being coupled between the first node and the second node, and the second inductor being located between the negative transconductance stage and a reference node.

[0010] In one or more embodiments, the oscillator is a digitally controlled oscillator (DCO).

[0011] In an example embodiment, a phase-locked loop (PLL) circuit system includes an oscillator comprising: a first plurality of capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node and the second path connecting a second node to a second output node; and a second plurality of capacitor banks coupled to a third path and a fourth path, the third path connecting to the first node and the fourth path connecting to the second node, the first and second paths being separate from the third and fourth paths, and the second plurality of capacitor banks including at least one modulation capacitor bank.

[0012] In one or more embodiments, at least one modulation capacitor bank is configured to receive at least a first control signal that modulates at least one capacitance of the at least one modulation capacitor bank, and the at least one modulation capacitor bank is configured to cause frequency modulation of the output signal of the oscillator.

[0013] In one or more embodiments, the first plurality of capacitor banks includes a process-voltage-temperature (PVT) capacitor bank, an acquisition capacitor bank, and a tracking capacitor bank. The PVT capacitor bank is configured to receive a second control signal, the acquisition capacitor bank is configured to receive a third control signal, and the tracking capacitor bank is configured to receive a fourth control signal. The second, third, and fourth control signals modify the capacitances of the PVT capacitor bank, the acquisition capacitor bank, and the tracking capacitor bank, respectively, to achieve phase-locked looping (PLL) in the PLL circuit system.

[0014] In one or more embodiments, the PLL circuit system further includes a digital loop filter circuit system, a chirp generation circuit system, and a control circuit system. The digital loop filter circuit system is configured to generate a second control signal, a third control signal, and a fourth control signal and provide the second control signal, the third control signal, and the fourth control signal to an oscillator. The chirp generation circuit system is configured to generate a ramp signal. The control circuit system is configured to generate a first control signal based on the ramp signal and provide the first control signal to the oscillator.

[0015] In one or more embodiments, at least one modulation capacitor bank includes a fine modulation capacitor bank having a first discrete step length and a coarse modulation capacitor bank having a second discrete step length greater than the first discrete step length.

[0016] In one or more embodiments, a first plurality of capacitor banks are arranged in parallel between a first path and a second path, and a second plurality of capacitor banks are arranged in parallel between a third path and a fourth path.

[0017] In one or more embodiments, the first plurality of capacitor banks and the second plurality of capacitor banks are arranged from the first node and the second node to the output node in an order of decreasing discrete step size, and the discrete step size of a given capacitor bank in the first plurality of capacitor banks or the second plurality of capacitor banks is based on the block size of the given capacitor bank.

[0018] In one or more embodiments, the oscillator further includes a current source, a first inductor, a negative transconductance stage, and a second inductor, the first inductor being coupled to the current source and between a first node and a second node, the negative transconductance stage being coupled between the first node and the second node, and the second inductor being located between the negative transconductance stage and a reference node.

[0019] In one or more embodiments, the oscillator is a digitally controlled oscillator (DCO).

[0020] In an example embodiment, a digitally controlled oscillator (DCO) includes: a negative transconductance stage coupled to a first node, a second node, and a reference node; a first plurality of capacitor banks coupled to a first path and a second path, the first path connecting the first node to a first output node and the second path connecting the second node to a second output node, at least one of the first plurality of capacitor banks being controlled to achieve phase-locked loop (PLL) incorporating the DCO; and a second plurality of capacitor banks coupled to a third path and a fourth path, the third path connecting to the first node and the fourth path connecting to the second node, the first and second paths being separate from the third and fourth paths, and the second plurality of capacitor banks including at least one modulation capacitor bank controlled to modulate at least one output signal of the DCO.

[0021] In one or more embodiments, the first plurality of capacitor banks includes a first capacitor bank having a first step size, a second capacitor bank having a second step size, and a third capacitor bank having a third step size; the second plurality of capacitor banks includes a fine modulation capacitor bank having a fourth step size and a coarse modulation capacitor bank having a fifth step size; the first step size is greater than the second step size, the second step size is greater than the fourth step size, the fourth step size is greater than the fifth step size, and the fifth step size is greater than the third step size; and the first plurality of capacitor banks and the second plurality of capacitor banks are arranged between the negative transconductance stage and the first output node and the second output node in a step size decreasing order.

[0022] In one or more embodiments, a first plurality of capacitor banks are arranged in parallel between a first path and a second path, and a second plurality of capacitor banks are arranged in parallel between a third path and a fourth path. Attached Figure Description

[0023] A more complete understanding of the subject matter can be derived by considering the following figures and referring to the specific embodiments and claims. The same reference numerals throughout the figures refer to similar elements. Elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. The figures, together with the specific embodiments, are incorporated into and form a part of this specification and are used to further illustrate examples, embodiments, etc., and to explain various principles and advantages according to this disclosure. In the figures:

[0024] Figure 1 An illustrative block diagram of a phase-locked loop (PLL) circuit system including a digitally controlled oscillator (DCO) is shown according to various embodiments;

[0025] Figure 2 Examples of various embodiments are shown. Figure 1An illustrative circuit diagram of a DCO, such as a DCO having a modulation capacitor bank coupled between a first pair of traces and other capacitor banks coupled between a second pair of traces (e.g., a process-voltage-temperature (PVT) capacitor bank, an acquisition (ACQ) capacitor bank, and a tracking (TR) capacitor bank); and

[0026] Figure 3 Examples of various embodiments are shown. Figure 1 or Figure 2 An illustrative top view of a DCO, such as a DCO having a modulation capacitor bank coupled between a first pair of traces and other capacitor banks coupled between a second pair of traces (e.g., a process-voltage-temperature (PVT) capacitor bank, an acquisition (ACQ) capacitor bank, and a tracking (TR) capacitor bank). Detailed Implementation

[0027] The following detailed descriptions are merely illustrative in nature and are not intended to limit the use of the embodiments described herein or such embodiments. Furthermore, one should not be bound by any express or implied theory presented in the prior art, background art, or the following detailed descriptions.

[0028] For the sake of simplicity and clarity, the drawings illustrate a general construction. Descriptions and details of well-known features and techniques may be omitted from the following detailed description to avoid unnecessarily obscuring this disclosure. For example, the dimensions of some elements or regions in the drawings may be exaggerated relative to other elements or regions to aid in understanding the embodiments described herein.

[0029] The terms “first,” “second,” “third,” “fourth,” etc. (if present) used in the description and claims are used to distinguish similar elements and are not necessarily used to describe a particular sequence or time order. It should be understood that the terms thus used are interchangeable where appropriate, such that the embodiments described herein can be operated, for example, in sequences other than those shown or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. As used herein, the terms “generally,” “substantially,” “largely,” and “substantially” mean sufficient to practically achieve the stated purpose, and minor defects (if present) are not important to the stated purpose.

[0030] In accordance with these principles, when referring to measurable quantities (including but not limited to dimensions), these terms mean that the quantity is equal to the value of the acceptable tolerances stated by any method or apparatus selected to manufacture the described structure or measure the quantity or dimension described. Unless otherwise stated, orientations to references, such as “top,” “bottom,” “left,” “right,” “above,” “below,” etc., are not intended to require any preferred orientation, but are for illustrative purposes and refer to the orientation corresponding to one or more drawings. As used herein, the terms “exemplary” and “example” mean “serving as an example, case study, or illustration.” Any embodiment described herein as exemplary or illustrative is not necessarily to be construed as preferred or advantageous over other embodiments. Additionally, certain terms may be used herein for illustrative purposes only and are therefore not intended to be restrictive.

[0031] As used herein, the terms “circuit” and “circuitry,” and related terms, mean any suitable combination of analog or digital circuit elements. In this document, elements or nodes or features are sometimes referred to as “connected” or “coupled” together. As used herein, unless explicitly stated otherwise, “connected” means that one element is directly joined to (or in direct communication with) another element in an electrical or non-electrical manner, and not necessarily mechanically joined. Similarly, unless explicitly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or in direct or indirect communication with) another element in an electrical or non-electrical manner, and not necessarily mechanically joined. Therefore, although the schematic diagrams shown in the figures depict exemplary arrangements of elements, additional intermediate elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter.

[0032] The various embodiments described herein relate to an oscillator, such as a digitally controlled oscillator (DCO), having a modulation capacitor bank and other capacitor banks (e.g., capacitor banks for process-voltage-temperature (PVT) compensation, capacitor banks for phase-locked loops (PLLs) incorporating the DCO, or combinations thereof) coupled to nodes of a transconductance stage along different paths (e.g., in a star configuration). Such an arrangement of capacitor banks can reduce or mitigate the effects of parasitic inductance from other capacitor banks on the modulation capacitor bank, where calibration of the modulation capacitor bank might otherwise fail due to such parasitic inductance when the state of other capacitor banks changes (e.g., due to a change in the locked state of the PLL). In one or more embodiments, the DCO may be implemented as part of a phase-locked loop (PLL) circuit system having an all-digital PLL (ADPLL) architecture.

[0033] In one or more embodiments, the DCO includes a fine modulation capacitor bank, a coarse modulation capacitor bank, a PVT capacitor bank, an acquisition capacitor bank, a tracking capacitor bank, and a negative transconductance stage. The PVT capacitor bank, acquisition capacitor bank, and tracking capacitor bank can each be coupled to a first path and a second path, wherein the first path connects the positive node at the negative transconductance stage to a first output node, and the second path connects the negative node at the negative transconductance stage to a second output node. The PVT capacitor bank can be controlled to compensate for variations in the DCO's process, supply voltage, and temperature. The acquisition capacitor bank and tracking capacitor bank can be controlled (using different offline lengths) to achieve phase-locked loop (PLL). The fine modulation capacitor bank and coarse modulation capacitor bank can be coupled to a third path and a fourth path, wherein the third path connects to the positive node, and the fourth path connects to the negative node. The fine modulation capacitor bank and coarse modulation capacitor bank can be controlled to induce modulation (e.g., linear frequency modulation; chirping) of one or more output signals provided at the first and second output nodes of the DCO. The third and fourth paths are decoupled from the first and second paths.

[0034] In one or more embodiments, the capacitor bank of the DCO may be arranged between the negative transconductance block and the output node in descending order of step size, wherein the step size of a given capacitor bank may correspond to the size of the capacitor block of the capacitor bank, and the capacitance of the capacitor bank may be defined by a minimum discrete amount by which it may be increased or decreased.

[0035] Figure 1 A block diagram of a phase-locked loop (PLL) circuit system 100 with an all-digital phase-locked loop (ADPLL) architecture is shown. The PLL circuit system 100 includes a digitally controlled oscillator (DCO) 110, a piecewise linear (PWL) control circuit system 120, a PWL calibration circuit system 121, a chirp generation circuit system 123, a frequency divider 130, a frequency divider control circuit system 131, a successive approximation register (SAR) time-to-digital converter (TDC) 140 (e.g., which can act as a phase detector), a quantization noise cancellation circuit system 144, a digital loop filter circuit system 146, multiplexers (MUX) 148 and 150, and an adder circuit system 152.

[0036] A clock reference input 141 (“ref_p”) and a frequency-divided output signal 134 (“clk_div_p”) are provided to the corresponding inputs of the SAR TDC 140. The SAR TDC determines the time difference between the clock reference input 141 and the frequency-divided output signal 134. The frequency-divided output signal 134 is provided to the SAR TDC 140 by a frequency divider 130. The frequency divider 130 receives an output signal 112 (“PLL_out”) corresponding to the output of the PLL circuit system 100 from the DCO 110 and divides its frequency such that the clock reference input 141 can still be used to generate a relatively high-frequency output signal 112 with appropriate accuracy when provided at a relatively low frequency. In one or more embodiments, the output signal 112 is a differential output signal comprising a pair of signals with opposite polarities (“differential pair”). The frequency divider 130 is controlled by a frequency divider control circuit system 131, which may include a trigonometric integral modulator. In this way, the frequency divider 130 and the frequency divider control circuit system 131 together provide fractional frequency division (e.g., allowing fractional n frequency control).

[0037] The divider control circuitry 131 provides a divider value 132 (“div”) to the divider 130 and provides the accumulated trigonometric integral error 170 (“SD acc. error”) to the quantization noise cancellation block 144. The divider control circuitry 131 is configured to receive a frequency control word 168 (“FCW”) from the PWL control circuitry 120 or the PWL calibration circuitry 121 via the MUX 150. The divider control circuitry 131 is then configured to control the divider 130 to provide an output signal 112 from the ADPLL (reference clock reference input 141) at the desired output frequency. The divider control circuitry 131 receives a re-timing reference signal 158 (“ref_sample”) from the SARTDC 140 and a divided output signal 134 from the divider 130.

[0038] A phase offset signal 154 (“phase_offset”) is added by adder circuitry 152 to the SAR TDC signal 156 (“sar_tdc_raw”) provided by SAR TDC 140, and the resulting phase-offset SAR TDC signal is provided to quantization noise cancellation circuitry 144. Quantization noise cancellation circuitry 144 is configured to reduce quantization noise that may be introduced, for example, by frequency divider 130. Quantization noise cancellation circuitry 144 can be configured to eliminate or reduce such noise in the digital domain.

[0039] A noise-reduced phase error signal 160 (“phe_error_norm”) is provided by quantization noise cancellation circuitry 144 to digital loop filter circuitry 146. This noise-reduced phase error signal corresponds to the phase offset SAR TDC signal after quantization noise cancellation or reduction by quantization noise cancellation circuitry 144. For example, the noise-reduced phase error signal 160 may represent the phase error of clock reference input 141 as determined by SAR TDC 140. Digital loop filter circuitry 146 is configured to convert the noise-reduced phase error signal 160 into a digital output signal for controlling DCO 110 to minimize or reduce the phase error represented by the noise-reduced phase error signal 160.

[0040] During normal operation, the PLL circuitry 100 is configured to compare the phase of the clock reference signal 141 with the phase of the divided output signal 134 (derived from the output signal 112 of the PLL circuitry 100), and adjust the DCO 110 to maintain phase matching between the two signals (e.g., within a predetermined tolerance, which may be defined based on a predetermined phase difference threshold). The PLL circuitry 100 also supports two-point modulation via chirp generation circuitry 123, PWL control circuitry 120, and PWL control circuitry 121. For example, chirp generation circuitry 123 may generate a ramp signal 122 (ramp(k)) based at least in part on a re-timing reference signal 158 provided to chirp generation circuitry 123 by SARTDC 140. Chirp generation circuitry 123 provides ramp signal 122 to PWL control circuitry 120. The PWL control circuitry generates coarse and fine modulation control codes based on ramp signal 122. These codes are selectively provided to DCO 110 via MUX 148 as modulation input 111 (MOD). Modulation input 111 modulates and controls one or more modulation capacitor banks to induce frequency modulation (e.g., linear frequency modulation / chirping) of output signal 112. DCO 110 receives PLL lock-in and compensation inputs from digital loop filter circuitry 146, which may include an acquire (ACQ) signal 162, a track (TR) signal 164, and a process-voltage-temperature (PVT) signal 166. These PLL lock-in inputs control corresponding capacitor banks (sometimes referred to as "compensation capacitor banks"), selectively modifying their respective capacitances to control the phase of output signal 112 (e.g., to compensate for variations in process, supply voltage, and temperature).

[0041] DCO 110 can receive modulation input 111 (MOD), which may include coarse modulation control code 128 and fine modulation control code 129, and can control the modulation capacitor bank of DCO 110. For example, coarse modulation control code 128 and fine modulation control code 129 can be provided to control the coarse modulation capacitor bank and the fine modulation capacitor bank, respectively (e.g., Figure 2 The coarse modulation capacitor bank 212 and the fine modulation capacitor bank 214; Figure 3 The coarse modulation capacitor bank 312 and the fine modulation capacitor bank 314 are described below.

[0042] In one or more embodiments, the PWL calibration circuitry 121 may be configured to provide coarse modulation control codes 128 and fine modulation control codes 129 as the frequency of each control code from the modulation capacitor bank of the DCO 110 changes when the PLL circuitry 100 is locked to a fixed frequency. The calibration of the coarse modulation control codes 128 and fine modulation control codes 129, determined using the PWL calibration circuitry 121, can be utilized during subsequent frequency modulation (e.g., “chirping”) operation of the PLL circuitry 100. If the PLL circuitry becomes locked to different combinations of PVT, ACQ, and TR capacitors, the calibration of the coarse modulation control codes 128 and fine modulation control codes 129 may undesirably fail, even at the same locked frequency, if there is a significant lock-in state dependency between the compensation capacitor bank and the modulation capacitor bank. In one or more embodiments, the DCO 110 is arranged to avoid or mitigate lock-in state dependencies to reduce the likelihood of such calibration failures. This arrangement of the DCO 110 is described in more detail below.

[0043] In one or more embodiments, the compensation capacitor bank and modulation capacitor bank of DCO 110 can be arranged in a "star configuration", wherein the modulation capacitor bank is connected via a first path or a first pair of paths (e.g., Figure 2 Paths 230 and 232; Figure 3 Paths 330, 332) are connected to the negative transconductance stage (e.g., Figure 2 206 negative transconductance stage; Figure 3 The negative transconductance stage 306; sometimes referred to herein as the “negative gm stage” or “negative gm block”), and the compensation capacitor bank via a second path or a second pair of paths (e.g., Figure 2 Paths 234 and 236; Figure 3Paths 334 and 336) are connected to the negative transconductance stage. By arranging and connecting the compensation capacitor bank and the modulation capacitor bank of the DCO110 in such a star configuration, the parasitic inductance between the compensation capacitor bank and the modulation capacitor bank can be advantageously reduced, and this reduction in parasitic capacitance can mitigate the effect of changes in the state of the compensation capacitor bank on the calibration of the modulation capacitor bank, as described in more detail below.

[0044] Figure 2 A circuit diagram of a DCO 200 is shown, which includes a modulation capacitor bank and a compensation capacitor bank connected in a star configuration to a negative transconductance stage. In one or more embodiments, the DCO 200 may be implemented as part of a PLL, such as an ADPLL. In one or more embodiments, the DCO 200 may correspond to Figure 1 The PLL circuit system 100 includes a DCO 110. As shown, the DCO 200 comprises a current source 202, an inductor 204 (sometimes referred to as a "tank inductor 204"), a negative transconductance stage 206, and an adjustable capacitor C. PVT Process-voltage-temperature (PVT) capacitor bank 208, with adjustable capacitance C ACQ Acquisition (ACQ) capacitor bank 210, with adjustable capacitance C TRK Tracking (TRK) capacitor bank 216, with adjustable capacitance C mod_coarse Coarse modulation capacitor bank 212, with adjustable capacitance C mod_fine The fine-tuned capacitor bank 214, positive node 218, negative node 220, inductor 222, reference node 224 (sometimes referred to herein as "ground node 224" or "common node 224" according to various embodiments), positive output node 226, negative output node 228, and paths 230, 232, 234 and 236.

[0045] As shown, current source 202 can be coupled to inductor 204 and can provide current to inductor 204. Inductor 204 can be coupled (e.g., directly connected) between positive node 218(p) and negative node 220(n). Negative transconductance stage 206 can be coupled (e.g., directly connected) between positive node 218 and negative node 220. In one or more embodiments, negative transconductance stage 206 may include a cross-coupled pair of transistors, wherein positive node 218 is connected to a first current-carrying terminal of a first transistor of the cross-coupled pair and a control (e.g., gate) terminal of a second transistor of the cross-coupled pair, wherein negative node 220 is connected to a first current-carrying terminal of the second transistor and a control (e.g., gate) terminal of the first transistor, and reference node 224 is coupled via inductor 222 to a second current-carrying terminal of the first transistor and a second current-carrying terminal of the second transistor. Inductor 222 can be coupled between negative transconductance stage 206 and reference node 224. DCO 200 may provide output signals (e.g., differential pairs of output signals) at output nodes 226 and 228. In one or more embodiments, the output signals provided at output nodes 226 and 228 may correspond to Figure 1 The output signal is 112.

[0046] In one or more embodiments, the negative transconductance stage 361 may include a pair of transistors (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor, an n-type metal-oxide-semiconductor (NMOS) transistor, or a bipolar transistor) constructed using negative feedback (-R) to achieve DC oscillation conditions and may be in various configurations (e.g., cross-coupled, as shown in this example). In one or more embodiments, the coarse modulation capacitor bank 212 and the fine modulation capacitor bank 214 may be one or more capacitor-based frequency divider groups with programmable resolution. The capacitor frequency divider group may include different types of capacitor elements (e.g., as non-limiting examples, capacitors, PMOS, NMOS, or bipolar-based variable capacitors). The dynamic capacitor bank may be controlled by the modulation type (e.g., as non-limiting examples, frequency-modulated continuous wave (FMCW) or binary phase-shift keying). In one or more embodiments, capacitor banks 208, 210, and 216 may include several compensating capacitor banks (static), such as static compensation (e.g., band selection, process recentering, or offset correction due to the programmability of the modulation capacitor bank resolution, as a non-limiting example), and may be fabricated using any suitable capacitor element association. Inductor element 204 utilizes a capacitive load (LC tank) to generate a resonant frequency and may be constructed using a ground reference, power reference, center-tapped signal / differential inductor, 8-shaped or other shaped inductor or transformer, depending on the various embodiments.

[0047] The connections between capacitor banks 208, 210, 212, 214, and 216 may have a star configuration (sometimes referred to as a "star connection") relative to positive node 218 and negative node 220. For example, a first star configuration relative to positive node 218 may include a first branch and a second branch, wherein the first branch includes a path 230 from node 218 to coarse modulation capacitor bank 212 and fine modulation capacitor bank 214, and the second branch includes a path 234 from node 218 to capacitor banks 208, 210, and 216. For example, a second star configuration relative to negative node 220 may include at least a first branch and a second branch, wherein the first branch includes a path 232 from node 220 to coarse modulation capacitor bank 212 and fine modulation capacitor bank 214, and the second branch includes a path 236 from node 220 to capacitor banks 208, 210, and 216. As shown in the figure, capacitor banks 208, 210 and 216 are arranged in parallel with each other between paths 234 and 236, and capacitor banks 212 and 214 are arranged in parallel with each other between paths 230 and 232.

[0048] Each of capacitor banks 208, 210, 212, 214, and 216 may contain a plurality of switchable capacitor blocks, each containing one or more capacitive elements. The capacitance of each of capacitor banks 208, 210, 212, 214, and 216 may be controlled in response to a corresponding control signal (e.g., a control code) provided to each of the capacitor banks. For example, a PVT control signal (e.g., by...) Figure 1 The PVT signal 166 provided by the digital loop filter circuit system 146 can be provided to the PVT capacitor bank 208 to control (e.g., tune) the capacitance of the PVT capacitor bank 208. For example, a control signal (e.g., provided by...) can be obtained. Figure 1 The acquisition signal 162 provided by the digital loop filter circuit system 146 can be provided to the acquisition capacitor bank 210 to control the capacitance of the acquisition capacitor bank 210. For example, a tracking control signal (e.g., provided by...) Figure 1 The tracking signal 164 provided by the digital loop filter circuit system 146 can be provided to the tracking capacitor bank 216 to control the capacitance of the tracking capacitor bank 216. For example, a coarse modulation control signal (e.g., provided by...) Figure 1 The coarse modulation control code 128 provided by the PWL control circuit system 120 can be provided to the coarse modulation capacitor bank 212 and can control the capacitance of the coarse modulation capacitor bank 212. For example, the fine modulation control signal (e.g., by...) Figure 1 The fine modulation control code 129 provided by the PWL control circuit system 120 can be provided to the fine modulation capacitor bank 214 and can control the capacitance of the fine modulation capacitor bank 214.

[0049] The capacitance of a given capacitor bank among capacitor banks 208, 210, 212, 214, and 216 can be modified in discrete steps based on an associated control signal, wherein the step size (sometimes referred to herein as a “tuning step size” or “discrete step size”; the amount by which the capacitance of the capacitor bank can be discretely increased or decreased) is determined at least in part based on the size of the capacitor blocks of the capacitor bank (e.g., the block capacitance). In one or more embodiments, all capacitor blocks of a given capacitor bank may have equal or substantially equal sizes (e.g., equal or substantially equal capacitances). As seen from the negative transconductance stage 206 via positive node 218(p) and negative node 220(n), the effective step size of modulation capacitor banks 212 and 214 may be affected by parasitic inductance from capacitor banks 208, 210, and 216.

[0050] For example, in some conventional DCOs, all capacitor banks are coupled along the same path leading to the DCO's output. In such configurations, parasitic inductance exists between the compensation capacitor bank and the modulation capacitor bank. This parasitic inductance between the compensation and modulation capacitor banks can further introduce lock-in dependency. If the compensation capacitor bank of such a conventional DCO locks in a combination different from the combination used during calibration, the calibration fails. This can lead to a degradation in chirp linearity during modulation (e.g., "chirping") of the output signal provided at the output node of such a conventional DCO.

[0051] Conversely, by arranging capacitor banks 208, 210, 212, 214, and 216 in a star configuration, as shown in this example, the dependency between modulation capacitor banks 212 and 214 and compensation capacitor banks 208, 210, and 216 can be advantageously reduced. At least in part due to this reduction in interconnect parasitic inductance, changing the state of any or all of capacitor banks 208, 210, and 216 (e.g., causing a change in the lock-in state, which is common during the generation and transmission of chirped signals in the DCO 200) has a desiredly reduced effect on the step size and calibration of modulation capacitor banks 212 and 214. Hereinafter, “lock-in state” may refer to a combination of capacitors used to lock the PLL to a fixed frequency in the compensation capacitor banks (e.g., compensation capacitor banks 208, 210, and 216), where different capacitor combinations correspond to different lock-in states. For the same lock-in frequency, the compensation capacitor banks may have different lock-in states (different frequency combinations) that can be difficult to control.

[0052] For example, if all capacitor banks 208, 210, 212, 214, and 216 were directly coupled along paths 234 and 236, a change in the locking state of capacitor banks 208, 210, and 216 would typically result in a failure of the calibration of modulation capacitor banks 212 and 214. However, by arranging capacitor banks 208, 210, 212, 214, and 216 in the star configuration of this example, such calibration failures can be mitigated or completely avoided. By protecting the calibration of modulation capacitor banks 212 and 214 in this manner, frequency errors that might otherwise degrade chirp linearity can be advantageously reduced or avoided, thereby providing relatively high chirp linearity with improved robustness.

[0053] Figure 3 A top view of a DCO 300 is shown, which includes a modulation capacitor bank and a compensation capacitor bank connected in a star configuration to a negative transconductance stage. In one or more embodiments, the DCO 300 may be implemented as part of a PLL, such as an ADPLL. In one or more embodiments, the DCO 300 may correspond to Figure 1 The DCO 110 of the PLL circuit system 100. In one or more embodiments, the DCO 300 may correspond to Figure 2 The DCO 200, in which various aspects of the DCO 300 are similar Figure 2 The aspects of the DCO 200 will not be repeated here for the sake of brevity. As shown in the figure, the DCO 300 includes a current source 302, an inductor 304, a negative transconductance stage 306, and an adjustable capacitor C. PVT PVT capacitor bank 308, with adjustable capacitance C ACQ Acquisition (ACQ) capacitor bank 310, with adjustable capacitor C TRK Tracking (TRK) capacitor bank 316, with adjustable capacitance C mod_coarse Coarse modulation capacitor bank 312, with adjustable capacitor C mod_fine The fine-tuned capacitor bank 314, positive node 318, negative node 320, inductor 322, reference node 324 (sometimes referred to herein as "ground node 324" or "common node 324" according to various embodiments), positive output node 326, negative output node 328, and paths 330, 332, 334 and 336.

[0054] As shown, current source 302 may be coupled to inductor element 304 and may provide current to inductor element 304. In one or more embodiments, as shown in this example, inductor element 304 includes an inductor loop, and current source 302 is coupled to the midpoint of the inductor loop (“center tap”). Inductor element 304 may be coupled (e.g., directly connected to) positive node 318 and negative node 320. Negative transconductance stage 306 may be coupled (e.g., directly connected to) positive node 318 and negative node 320. In one or more embodiments, negative transconductance stage 306 may include a cross-coupled pair of transistors, wherein positive node 318 is connected to a first current-carrying terminal of a first transistor of the cross-coupled pair and a control (e.g., gate) terminal of a second transistor of the cross-coupled pair, wherein negative node 320 is connected to a first current-carrying terminal of the second transistor and a control (e.g., gate) terminal of the first transistor, and reference node 324 is coupled via inductor element 322 to a second current-carrying terminal of the first transistor and a second current-carrying terminal of the second transistor. In one or more embodiments, as shown in this example, inductor element 322 may comprise an inductor ring. Inductor element 322 may be coupled (e.g., directly connected in one or more embodiments) between negative transconductance stage 306 and reference node 324. DCO 300 may provide output signals (e.g., output signal differential pairs) at output nodes 326 and 328. In one or more embodiments, the output signals provided at output nodes 326 and 328 may correspond to Figure 1 The output signal is 112.

[0055] The connections between capacitor banks 308, 310, 312, 314, and 316 may have a star configuration (sometimes referred to as a "star connection") relative to positive node 318 and negative node 320. For example, a first star configuration relative to positive node 318 may include a first branch and a second branch, wherein the first branch includes a path 330 from node 318 to coarse modulation capacitor bank 312 and fine modulation capacitor bank 314, and the second branch includes a path 334 from node 318 to capacitor banks 308, 310, and 316. For example, a second star configuration relative to negative node 320 may include a first branch and a second branch, wherein the first branch includes a path 332 from node 320 to coarse modulation capacitor bank 312 and fine modulation capacitor bank 314, and the second branch includes a path 336 from node 320 to capacitor banks 308, 310, and 316.

[0056] In one or more embodiments, paths 330, 332, 334, and 336 may be conductive traces. In one or more embodiments, the DCO 300 may use multiple metal layers (e.g., a “multilayer metal stack”) formed on or above a substrate (e.g., a semiconductor substrate, such as a silicon substrate). For example, paths 330, 332, 334, and 336 may be formed in a first (e.g., top) metal layer above the substrate. For example, capacitor banks 308, 310, 312, 314, and 316 may be formed in one or more other metal layers disposed above the substrate and below the first metal layer in which paths 330, 332, 334, and 336 are formed. In one or more such embodiments, capacitor banks 312 and 314 may be connected to paths 330 and 332 using conductive vias, and capacitor banks 308, 310, and 316 may be connected to paths 334 and 336 using conductive vias.

[0057] Each of capacitor banks 308, 310, 312, 314, and 316 may include multiple switchable capacitor blocks, each containing one or more capacitive elements. The capacitance of each of capacitor banks 308, 310, 312, 314, and 316 may be controlled in response to a corresponding control signal (e.g., a control code) provided to each of the capacitor banks. For example, a PVT control signal (e.g., provided by...) Figure 1 The PVT signal 166 provided by the digital loop filter circuit system 146 can be provided to the PVT capacitor bank 308 to control (e.g., tune) the capacitance of the PVT capacitor bank 308. For example, a control signal (e.g., provided by...) can be obtained. Figure 1 The acquisition signal 162 provided by the digital loop filter circuit system 146 can be provided to the acquisition capacitor bank 310 to control the capacitance of the acquisition capacitor bank 310. For example, a tracking control signal (e.g., provided by...) Figure 1 The tracking signal 164 provided by the digital loop filter circuit system 146 can be provided to the tracking capacitor bank 316 to control the capacitance of the tracking capacitor bank 316. For example, a coarse modulation control signal (e.g., provided by...) Figure 1 The coarse modulation control code 128 provided by the PWL control circuit system 120 can be provided to the coarse modulation capacitor bank 312 and can control the capacitance of the coarse modulation capacitor bank 312. For example, the fine modulation control signal (e.g., by...) Figure 1 The fine modulation control code 129 provided by the PWL control circuit system 120 can be provided to the fine modulation capacitor bank 314 and can control the capacitance of the fine modulation capacitor bank 314.

[0058] The capacitance of a given capacitor bank in capacitor banks 308, 310, 312, 314, and 316 can be modified based on an associated control signal in discrete step sizes, wherein the step size (sometimes referred to herein as the “tuning step size”; the amount by which the capacitance of the capacitor bank can be discretely increased or decreased) is determined at least in part based on the size of the capacitor blocks of the capacitor bank (e.g., the block capacitance). In one or more embodiments, all capacitor blocks of a given capacitor bank may have equal or substantially equal sizes (e.g., equal or substantially equal capacitances).

[0059] In this example, the capacitor blocks of capacitor banks 308, 310, 312, 314, and 316 are shown as corresponding square arrays, where the comparative size of the squares of one capacitor bank indicates a relatively larger or smaller capacitor block size compared to other capacitor banks represented by relatively smaller or larger squares. In one or more embodiments, capacitor banks 308, 310, 312, 314, and 316 may be arranged in order of tuning step size (e.g., capacitor block size) to minimize or otherwise reduce phase noise compared to other arrangements. For example, the capacitor block size and therefore tuning step size of PVT capacitor bank 308 may be larger than the capacitor block size and therefore tuning step size of acquisition capacitor bank 310. The capacitor block size and therefore tuning step size of acquisition capacitor bank 310 may be larger than the capacitor block size and therefore tuning step size of coarse modulation capacitor bank 312. The capacitor block size and therefore tuning step size of coarse modulation capacitor bank 312 may be larger than the capacitor block size and therefore tuning step size of fine modulation capacitor bank 314. The size of the capacitor block of the fine modulation capacitor bank 314, and therefore the tuning step size, can be larger than the size of the capacitor block of the tracking capacitor bank 316, and therefore the tuning step size. As shown in the figure, capacitor banks 308, 310, 312, 314, and 316 can be arranged in the following order: PVT capacitor bank 308 (closest to the negative transconductance stage 306), followed by acquisition capacitor bank 310, followed by coarse modulation capacitor bank 312, followed by fine modulation capacitor bank 314, followed by tracking capacitor bank 316 (closest to output nodes 326 and 328 and furthest from the negative transconductance stage 306).

[0060] As can be seen from the negative transconductance stage 306 via positive node 318 and negative node 320, the effective step size of modulation capacitor banks 312 and 314 may be affected by parasitic inductances from capacitor banks 308, 310, and 316. However, this effect can be reduced by a star configuration of capacitor banks 308, 310, 312, 314, and 316. For example, due to the reduced effect of parasitic inductances from capacitor banks 308, 310, and 316 on modulation capacitor banks 312 and 314, a star configuration of capacitor banks 308, 310, 312, 314, and 316 is superior to a conventional arrangement where all capacitor banks are coupled to the DCO output along the same path. This reduction in the effect of parasitic inductances on modulation capacitor banks 312 and 314 can advantageously avoid or reduce the possibility of modulation capacitor bank calibration and associated frequency errors and chirp linearity degradation, as described above.

[0061] Various exemplary embodiments are presented below. Some simplifications and omissions may have been made in the following examples to highlight and illustrate aspects of the various exemplary embodiments, rather than to limit the scope.

[0062] While at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that the exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed descriptions will provide a convenient guide for those skilled in the art to implement one or more of the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. An oscillator characterized by, comprises: a first plurality of capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node and the second path connecting a second node to a second output node; and a second plurality of capacitor banks coupled to a third path and a fourth path, the third path connected to the first node, the fourth path connected to the second node, the first and second paths separate from the third and fourth paths, and the second plurality of capacitor banks including at least one modulating capacitor bank.

2. The oscillator of claim 1, wherein The at least one modulating capacitor bank is configured to receive at least a first control signal that modifies at least one capacitance of the at least one modulating capacitor bank, and the at least one modulating capacitor bank is configured to cause a frequency modulation of an output signal of the oscillator.

3. The oscillator of claim 2, wherein, The first plurality of capacitor banks comprises: a process-voltage-temperature (PVT) capacitor bank configured to receive a second control signal; a acquisition capacitor bank configured to receive a third control signal; and a tracking capacitor bank configured to receive a fourth control signal, wherein the second, third, and fourth control signals modify capacitances of the PVT, acquisition, and tracking capacitor banks, respectively, to achieve phase locking of a phase-locked loop (PLL) including the oscillator, and to at least partially compensate for process, supply voltage, or temperature variations of the oscillator.

4. The oscillator of claim 1, wherein The at least one modulating capacitor bank includes a fine modulating capacitor bank having a first discrete step size and a coarse modulating capacitor bank having a second discrete step size that is greater than the first discrete step size.

5. The oscillator of claim 1, wherein The first plurality of capacitor banks is arranged in parallel between the first and second paths, and the second plurality of capacitor banks is arranged in parallel between the third and fourth paths.

6. The oscillator of claim 1, wherein The first and second pluralities of capacitor banks are arranged in order of decreasing discrete step size from the first and second nodes to the output nodes, and the discrete step size of a given capacitor bank of the first or second plurality of capacitor banks is based on a capacitance bin size of the given capacitor bank.

7. The oscillator of claim 1, wherein The oscillator additionally comprises: a current source; a first inductive element coupled to the current source and between the first and second nodes; a negative transconductance stage coupled between the first and second nodes; and a second inductive element between the negative transconductance stage and a reference node.

8. The oscillator of claim 1, wherein The oscillator is a digitally controlled oscillator (DCO).

9. Phase-locked loop, PLL, circuitry, characterized in that comprises: an oscillator comprising: a first plurality of capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node and the second path connecting a second node to a second output node; and a second plurality of capacitor banks coupled to a third path connected to the first node and a fourth path connected to the second node, the first and second paths being separate from the third and fourth paths, and the second plurality of capacitor banks including at least one modulating capacitor bank controlled to modulate at least one output signal of the DCO.

10. A digitally controlled oscillator (DCO), comprising: comprising: a negative transconductance stage coupled to a first node, a second node, and a reference node; a first plurality of capacitor banks coupled to a first path connecting the first node to a first output node and a second path connecting the second node to a second output node, wherein at least one of the first plurality of capacitor banks is controlled to achieve phase locking of a phase-locked loop (PLL) including the DCO; and a second plurality of capacitor banks coupled to a third path connected to the first node and a fourth path connected to the second node, the first and second paths being separate from the third and fourth paths, and the second plurality of capacitor banks including at least one modulating capacitor bank controlled to modulate at least one output signal of the DCO.

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