Sampled signal synchronization method and system

Abstract

The invention relates to a sampling signal synchronization method and system, and the method comprises the steps: responding to a synchronization triggering event, and generating and transmitting a current synchronization signal frame; determining the dynamic compensation amount of the current synchronization period; and sending the dynamic compensation quantity to a plurality of sampling terminals, so that the plurality of sampling terminals can determine sampling starting time according to the time of receiving the current synchronization signal frame and the dynamic compensation quantity, and the sampling time of the plurality of sampling terminals is kept synchronous. According to the scheme, high-precision time synchronization of multi-channel voltage and current signals is achieved through an improved closed-loop fine tuning mechanism, the synchronization precision is within + / -0.5 microseconds, and the verification requirement of a 0.05-level electric energy meter is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electric energy meter on-site calibration, in particular to a sampling signal synchronization method and system. BACKGROUND

[0002] Electric energy meter on-site calibration is an important part of power system operation and maintenance, which is used to ensure the accuracy of electric energy metering. Traditional electric energy meter on-site calibrators mostly use wired connection mode, but the on-site environment is complex, and there are problems such as complicated wiring and susceptibility to electromagnetic interference, which affect the calibration results. Although wireless technology simplifies wiring, it is difficult to synchronize the sampling time of each collection module, and transmission delay leads to inaccurate data time alignment, which seriously affects the calibration accuracy.

[0003] In the prior art, some schemes use GPS synchronization, but the cost is high and it cannot be used in indoor or sheltered environments; another scheme uses software synchronization, but the synchronization accuracy is insufficient (usually >100μs), which cannot meet the 0.2 level and above electric energy meter calibration requirements. According to IEC62053-22 standard, the 0.05 level electric energy meter calibration requires that the phase synchronization error is <0.01° (0.56μs for 50Hz system), and the existing wireless synchronization technology cannot meet this accuracy requirement.

[0004] Therefore, there is an urgent need for a low-cost, high-precision, and complex on-site environment adaptive signal synchronization method. SUMMARY

[0005] In order to solve the problem of insufficient synchronization accuracy in the prior art when calibrating electric energy meters on-site, the present application provides a sampling signal synchronization method and system for an electric energy meter on-site calibrator.

[0006] According to a first aspect of the present application, a sampling signal synchronization method is provided, applied to a host, characterized by comprising:

[0007] generating and sending a current synchronization signal frame in response to a synchronization trigger event; determining a dynamic compensation amount of a current synchronization period; and sending the dynamic compensation amount to a plurality of sampling terminals, so that the plurality of sampling terminals can determine a sampling start time according to the time of receiving the current synchronization signal frame and the dynamic compensation amount, and the sampling time of the plurality of sampling terminals is kept synchronized.

[0008] According to a second aspect of the present application, a sampling signal synchronization system is provided, characterized by comprising: a host for executing the method according to the first aspect; and A sampling terminal is configured to receive the current synchronization signal frame and the dynamic compensation amount sent by the host, and determine a sampling start time according to a receiving time of the current synchronization signal frame and the dynamic compensation amount.

[0009] According to the sampling signal synchronization method and system provided in the application, the high-precision time synchronization of multi-channel voltage and current signals is realized through the improved closed-loop fine-tuning mechanism, and the synchronization precision is within ±0.5 μs, which meets the 0.05-level electric energy meter calibration requirement (phase error <0.01°, corresponding to 50 Hz, system time error <0.56 μs). BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to these drawings without departing from the scope of the present application.

[0011] Figure 1 is a schematic diagram of a sampling signal synchronization system according to an embodiment of the present application.

[0012] Figure 2 is a flowchart of a sampling signal synchronization method according to an embodiment of the present application.

[0013] Figure 3 is a flowchart of a sampling signal synchronization method according to another embodiment of the present application.

[0014] Figure 4 is a flowchart of a sampling signal synchronization method according to still another embodiment of the present application.

[0015] Figure 5 is a flowchart of a sampling signal synchronization method according to still another embodiment of the present application. DETAILED DESCRIPTION

[0016] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments may, however, be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same or similar elements can be omitted or simplified in some instances.

[0017] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.

[0018] The block diagrams in the drawings show only the functionality and the relation between the functional entities, and not necessarily the physical arrangement of the entities. That is, the functional entities can be implemented in software, or in hardware, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0019] The flow diagrams shown in the drawings are merely examples of possible flow diagrams, and not necessarily all of the content and operations / steps, and not necessarily executed in the order described. For example, some operations / steps can be broken down, and some operations / steps can be combined or partially combined, so the actual execution order can be changed according to the actual situation.

[0020] It should be understood that although the terms first, second, third, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] Those skilled in the art can understand that the modules or flowcharts in the drawings are only schematic diagrams of the example embodiments, and the modules or flowcharts in the drawings do not necessarily have to be implemented in order to implement the present application, and therefore cannot be used to limit the protection scope of the present application.

[0022] To solve the problem of insufficient synchronization accuracy in the prior art when a radio energy meter is calibrated in the field, the present application provides a sampling signal synchronization system for an energy meter field calibrator. As shown in Figure 1 the system includes a host computer, a sampling terminal, and an energy meter to be tested.

[0023] In one embodiment, the host computer serves as the system control center and can communicate with the sampling terminal through a wireless communication module, for example, a 2.4 GHz frequency band wireless communication module. The host computer can include a central processing unit, a high-precision real-time clock module, a wireless communication module, and a storage unit.

[0024] In one embodiment, the collection terminal includes one or more voltage collection modules and one or more current collection modules (e.g., wireless current clamp meter). In one specific embodiment, the voltage collection module can be connected to the voltage terminal of the measured line through an insulated wire, acquire the voltage signal and transmit to the host computer. The voltage collection module can include a voltage sensor, an analog-to-digital converter (ADC), a high-precision real-time clock module, and a wireless communication module. The voltage collection module can use a 10 kHz sampling rate, a clock accuracy of ±1 ppm, and a working frequency band of 2.4 GHz (IEEE 802.15.4 protocol). In one specific embodiment, the current collection module can be clamped on the incoming current line of the measured electric energy meter in a non-intrusive manner, acquire the current signal and transmit to the host computer. The structure of the current collection module can be similar to that of the voltage collection module, with a consistent sampling rate (e.g., 10 kHz) and synchronization with the voltage collection module.

[0025] In one embodiment, the measured electric energy meter can output a standard pulse signal, which is input to the host computer through an opto-coupler for result comparison and calculation of energy error.

[0026] In one embodiment, during system startup, the host computer and each collection terminal perform power-on self-test, establish a wireless communication connection, and perform initial clock coarse synchronization.

[0027] In one embodiment, the host computer generates and sends a synchronization signal frame upon detection of a synchronization trigger event. In one specific embodiment, the synchronization trigger event can include initial power-on synchronization, periodic trigger synchronization, and event trigger synchronization. The initial power-on synchronization refers to the host computer sending a network-wide synchronization signal upon system power-on, and all sampling terminals performing initial clock calibration. The periodic trigger synchronization refers to performing periodic synchronization every fixed time interval (e.g., 10 ms, corresponding to 100 sampling points, with a sampling rate of 10 kHz) during normal system operation. The event trigger synchronization refers to triggering emergency synchronization when the power grid frequency fluctuation exceeds a preset value (e.g., ±0.05 Hz). Generally, the priority of event trigger synchronization is higher than that of periodic trigger synchronization, and the priority of periodic trigger synchronization is higher than that of initial power-on synchronization.

[0028] In the presence of a synchronization trigger event, the host computer can generate a synchronization signal through a high-precision clock source and broadcast the synchronization signal to each collection terminal. The signal contains the current precise timestamp T0 of the host computer. In one embodiment, the timestamp can use 64-bit nanosecond-level precision, with a format of T0 = second part (32 bits) + nanosecond part (32 bits). The synchronization signal frame structure can be: [Preamble 4B][Frame Header 2B][Synchronization Flag 1B][Host Timestamp T0 (8B)][Synchronization Period ID (4B)][Trigger Condition Parameters (4B)][CRC-32 (4B)].

[0029] After generating a synchronization signal frame, the host can broadcast the synchronization signal frame. In one specific embodiment, the host can broadcast the synchronization signal through a 2.4GHz wireless module, while recording the host's transmission time T0. In addition, a receive acknowledgment timeout timer can be started to determine whether the acquisition terminal receives the synchronization signal frame within a preset time.

[0030] In one embodiment, after receiving the synchronization signal from the host, the acquisition terminal can execute the synchronization signal processing procedure and the sampling start mechanism.

[0031] In one specific embodiment, the synchronization signal processing procedure may include the following steps: 1) Verify the frame header, synchronization flag, and CRC-32 checksum to confirm the signal validity; 2) Record the time T_rx when the synchronization signal reception is completed (accurately recorded by a local high-precision real-time clock with an accuracy of ±10ns); 3) Calculate the deviation θ between the local clock and the host clock; 4) The sampling terminal calculates the sampling start delay locally: T_delay=T_base+Δt.

[0032] Where T_base = T_processing + T_propagation, T_base is the base delay, which is a fixed value; T_processing represents the fixed delay of signal processing (e.g., 50μs), which is a characteristic of the terminal hardware and varies due to differences in chip and PCB layout; T_propagation represents the distance transmission delay, which is dynamically calculated from the actual distance between the host and the acquisition terminal. For example, in a typical field distance of about 30 meters, T_propagation can take a typical value of 0.2μs. Δt represents the dynamic compensation amount, which the host can send to the corresponding acquisition terminal via wireless commands; the determination of this dynamic compensation amount Δt will be described in detail below.

[0033] In one specific embodiment, the sampling initiation mechanism may include the following steps: The sampling terminal starts synchronous AD sampling (analog-to-digital sampling) at T_start = T_rx + T_delay, and the sampling rate can be precisely controlled at 10kHz (sampling interval of 100μs). The sampling process is triggered by a hardware timer to avoid software delay uncertainties.

[0034] In one embodiment, after determining the start sampling time T_start, the sampling terminal acquires electrical signals (the voltage acquisition module and the current acquisition module acquire voltage and current signals, respectively). In a specific implementation, the sampling terminal can acquire 100 points at a sampling rate of 10kHz (i.e., 100 sampling points × 100μs = 10000μs = 10ms of data). Here, the timestamp t1 of each data frame represents the precise time of the first sampling point (t1 = T_start); the time tn of the nth sampling point is tn = t1 + (n-1). T_sample, where n is the intra-frame sampling point number, n=1,2,...,100, T_sample=100μs; the timestamp precision is in the nanosecond range (64-bit integer, unit 1ns).

[0035] In one specific embodiment, the structure of the acquired electrical signal data frames for three-phase voltage and three-phase current is optimized as follows: [Module ID (2B)][Synchronization Period ID (4B)][Timestamp t1 (8B, nanoseconds)][Channel 1 Data (24 bits × 100 points)][Channel 2 Data (24 bits × 100 points)]...[Channel 6 Data (24 bits × 100 points)][Frame Sequence Number (4B)][CRC-32 (4B)].

[0036] Each data frame contains 100 sampling points (10ms of data); the synchronization period ID can use a 32-bit incrementing counter to ensure correct association of data frames; the frame sequence number is used to detect data loss and supports automatic retransmission requests. The sampling terminal can also send the collected electrical signal data frames, the reception time T_rx of the current synchronization signal frame, and the time of sending the electrical signal data frames to the host.

[0037] Next, we will introduce how to dynamically compensate for the amount Δt.

[0038] In one embodiment, the host obtains the precise timestamps (corresponding to the first timestamp) of the natural zero-crossing points of the multi-phase voltage waveforms. For example, for three-phase voltage, t_A, t_B, and t_C represent the precise timestamps of the natural zero-crossing points of the A, B, and C phase voltage waveforms, respectively. In a specific embodiment, the zero-crossing time can be accurately calculated using the synchronized voltage sampling data of each channel through an interpolation algorithm. Calculate the first difference between the zero-crossing timestamps of each pair of phase voltage waveforms. For example, for three-phase voltages t_A, t_B, and t_C, calculate the first difference between the zero-crossing timestamps of each pair of phase voltages, such as t_A - t_B, t_B - t_C, and t_C - t_A. Compare the maximum absolute value of the first difference between the zero-crossing timestamps, e = max(|t_A - t_B|, |t_B - t_C|, |t_C - t_A|), with the first preset time difference. If the maximum absolute value of the first difference between the zero-crossing timestamps is not greater than the first preset time difference, the dynamic compensation amount is the dynamic compensation amount of the previous synchronization cycle. Otherwise, the host uses closed-loop PID (Proportional, Integral, Differential) control based on the dynamic compensation amount of the previous synchronization cycle to determine a new dynamic compensation amount, which is then used as the dynamic compensation amount for the current synchronization cycle.

[0039] In one specific embodiment, the first preset time difference is preset, for example, it can be 0.833μs (corresponding to a phase difference of 0.015°). When the maximum value of the absolute value of the first difference is greater than the first preset time difference, it indicates that the synchronization accuracy does not meet the requirements, and the closed-loop fine-tuning mechanism is triggered.

[0040] Under the condition that the closed-loop fine-tuning mechanism is triggered, the host will execute the following complete post-trigger action flow to ensure that synchronization accuracy is quickly restored and remains stable. In one embodiment, the closed-loop fine-tuning mechanism includes closed-loop PID control.

[0041] Under closed-loop PID control, an adaptive PID controller can be used to adjust the clock compensation parameter. The new dynamic compensation calculation formula can be: Δt_new=Δt_old+Kp·e+Ki·∫e·dt+Kd·de / dt Where e is the time deviation of the current synchronization error, in microseconds (μs). As mentioned above, e is obtained by calculating the zero-crossing detection time difference of multiphase voltage (e.g., three-phase voltage) and the phase standard deviation of each channel fundamental wave (e.g., 50Hz fundamental wave). Where Kp, Ki, and Kd are adaptive PID parameters, which can be dynamically adjusted according to the time difference e, for example: ①|e|>5.6, which corresponds to a large error and requires fast convergence. The values ​​of Kp, Ki and Kd are 0.8, 0.05 and 0.1, respectively. ②1.0<|e|≤5.6, corresponding to the mean square error, requires balancing speed and stability, with Kp, Ki and Kd taking values ​​of 0.5, 0.1 and 0.05 respectively; ③|e|≤1.0, which corresponds to a small error and requires fine adjustment. The values ​​of Kp, Ki and Kd are 0.3, 0.15 and 0.02, respectively.

[0042] Among them, Δt_new and Δt_old are essentially dynamic adjustment components of T_delay. Δt_old is the dynamic compensation amount of the previous synchronization cycle, and Δt_new is the dynamic compensation amount of the current synchronization cycle obtained by PID calculation of the current control cycle.

[0043] In one specific embodiment, Where T_sync can be 10ms, and the unit is μs·s. For example, if the average phase error over the past 20 cycles is 1.2μs, then ∫e·dt = 1.2 0.01 20 = 0.24 μs·s.

[0044] In one specific embodiment, de / dt = [e(k) - e(k-1)] / T_sync; where e(k) represents the synchronization error measured in the k-th synchronization cycle; and e(k-1) represents the synchronization error measured in the (k-1)-th synchronization cycle. For example, if e changes from 1.0 μs to 1.5 μs (within 10 ms), de / dt = (0.5) / 0.01 = 50 μs / s.

[0045] Substitute each parameter into the formula to calculate the new dynamic compensation amount Δt_new.

[0046] After determining the new dynamic compensation amount, a safety limit is implemented to prevent overcompensation. In one embodiment, the values ​​of the single compensation amount and / or the cumulative compensation amount can be set (preset single compensation limit MAX_STEP and / or preset cumulative compensation limit MAX_TOTAL). For example, the single compensation amount does not exceed 2μs, and the cumulative compensation amount does not exceed ±10μs, i.e.: MAX_STEP=2.0 is the maximum step size for a single adjustment (μs); MAX_TOTAL=10.0 Maximum cumulative compensation amount (μs).

[0047] After determining the temporary dynamic compensation amount using a closed-loop fine-tuning mechanism, the temporary dynamic compensation amount can be limited according to the preset single compensation limit and / or preset cumulative compensation limit to determine a new dynamic compensation amount, which will be used as the dynamic compensation amount for the current synchronization cycle.

[0048] In one specific embodiment, the limiting process may include: When |Δt_new-Δt_old|>MAX_STEP Δt_new=Δt_old+sign(Δt_new-Δt_old) MAX_STEP; When |Δt_new|>MAX_TOTAL Δt_new=sign(Δt_new) MAX_TOTAL; Update Δt_old = Δt_new.

[0049] After determining the dynamic compensation amount for the current synchronization period, the host sends the dynamic compensation amount for the current synchronization period to all acquisition terminals. The acquisition terminals calculate the new sampling start delay T_delay_new = T_base + Δt_new, and then update the hardware timer time to T_start = T_rx + T_delay_new, and start sampling at time T_start.

[0050] To verify the compensation effect, in one embodiment, the sampling terminal performs three-phase voltage zero-crossing detection again after updating the sampling start time, obtains the second timestamp of the natural zero-crossing point of each phase voltage waveform, and calculates the second difference between the pairwise zero-crossing point timestamps in each phase voltage waveform. As described above, the second difference is obtained by calculating the zero-crossing detection time difference of multi-phase voltage (e.g., three-phase voltage) and the phase standard deviation of each channel fundamental wave (e.g., 50Hz fundamental wave).

[0051] The maximum value of the absolute values ​​of the second differences between the pairwise zero-crossing timestamps, e_new = max(|t_A-t_B|, |t_B-t_C|, |t_C-t_A|), is compared with the second preset time difference. If the maximum value of the absolute values ​​of the second differences between the pairwise zero-crossing timestamps is not greater than the second preset time difference, the synchronization compensation is determined to be successful; otherwise, the synchronization compensation is determined to be unsuccessful. In an optional embodiment, a secondary synchronization compensation strategy can be initiated.

[0052] For example, the second preset time difference is 0.56 μs. When |e_new| ≤ 0.56 μs, the compensation is considered successful, and the system resumes normal monitoring. When |e_new| > 0.56 μs, the secondary compensation strategy can be activated. Compensation effect data can be recorded for subsequent adaptive optimization of PID parameters.

[0053] In one embodiment, the secondary synchronization compensation strategy may include the following steps: a) First, perform a forced synchronization across the entire network: The host sends an emergency synchronization signal, and all acquisition terminals recalibrate their clocks. b) Enable high-precision verification mode: Input a 100Hz sine wave (2 times the fundamental frequency) through a standard signal source and calculate the phase difference of each channel at the same physical moment. For example, a 100Hz signal with a period of 10ms will have a more significant time error for the same phase error than a 50Hz signal, thus improving detection resolution. c) Adjust PID parameters: Switch to a finer set of control parameters based on the error magnitude (e.g., Kp=0.2, Ki=0.2, Kd=0.01). d) Perform multi-step progressive compensation: Decompose the compensation amount into 3 consecutive synchronous cycles and apply them step by step, for example, each step not exceeding 1μs; e) If the requirements are still not met after a preset number of (e.g., 3) cycles of secondary compensation, the system will automatically downgrade to a lower operating mode, limit the accuracy level, and issue an alarm.

[0054] In an optional embodiment, to further improve synchronization accuracy, the host and the acquisition terminal can use a two-way timestamping method to accurately separate transmission delay and clock deviation: Step 1: The host sends a synchronization signal (host clock) at T0. Step 2: The acquisition terminal receives the synchronization signal (local clock of the acquisition terminal) at T1. Step 3: The acquisition terminal sends a data frame at T2 (acquisition terminal local clock); Step 4: The host receives data frames (host clock) at T3.

[0055] After determining the first time T0 when the host sends the synchronization signal frame in the previous synchronization cycle, the second time T1 when any of the multiple acquisition terminals receives the synchronization signal frame, the third time T2 when any acquisition terminal sends the acquisition data frame, and the fourth time T3 when the host receives the acquisition data frame, the host determines the clock deviation based on the first time, the second time, the third time, and the fourth time.

[0056] In one specific implementation, the clock skew can be calculated using θ=[(T3-T2) -(T1-T0)] / 2.

[0057] Then, based on the clock offset and the second time, the corrected time base is determined.

[0058] In one embodiment, the sampling times of different acquisition terminals (voltage acquisition module, current acquisition module) can be mapped to a unified time base. The corrected t_corrected_final is the only reference for data association and can be called the corrected time base.

[0059] The original reception time T1 includes transmission delay and clock skew. The systematic error is corrected by the clock skew θ: t_corrected = T1 + θ. This is the basic correction used to eliminate the systematic clock skew and transmission delay. θ is the clock skew, which already includes the systematic effect of transmission delay.

[0060] For example, T0 = 1600000000.000000s (host sends); T1 = 1600000000.000005s (terminal reception); T2 = 1600000000.002000s (Terminal sends data); T3 = 1600000000.002004s (host receives); Calculate the clock deviation θ using the following formula: θ=[(T3-T2) -(T1-T0)] / 2=-0.5μs; The corrected timestamp = T1 + θ = 5μs - 0.5μs = 4.5μs.

[0061] To address dynamic errors (clock drift, environmental changes, device aging, etc.) and improve the accuracy of transmission delay calculation, a dynamic compensation amount Δt can be added to compensate for dynamic errors: t_corrected_final = (T1 +θ) +Δt, where Δt is the dynamic compensation amount for the current synchronization cycle.

[0062] The above methods can further improve the alignment accuracy between the sampling terminal and the host sampling time. For example, the alignment accuracy between the sampling terminal and the host sampling time at a distance of 30 meters can reach within ±0.56μs.

[0063] In an optional embodiment, after determining the corrected time base, the first timestamp of the natural zero-crossing point of each phase voltage waveform can be obtained based on the corrected time base.

[0064] In an optional embodiment, after determining the corrected time base, the second timestamp of the natural zero-crossing point of each phase voltage waveform can be obtained based on the corrected time base.

[0065] After the data acquisition terminal collects the electrical signals, it sends the collected data frames to the host. After receiving the current and voltage signals, the host calculates the theoretical electrical energy value based on the synchronized voltage and current signals. E 理 =∫(u(t)×i(t))dt, where u(t) and i(t) are the instantaneous values ​​of voltage and current after time alignment, respectively.

[0066] Calculate the number of pulses m0: m0 = C0 × E 理 Where C0 is the energy meter constant.

[0067] In addition, the host acquires the pulse signal m1 of the tested energy meter through a photoelectric sampler, compares the measured pulse number m1 with the calculated pulse number m0, and calculates the energy error according to the following formula: Error = (m1 - m0) / m0 × 100%.

[0068] exist Figure 1 Based on the system shown, this application provides a method for synchronizing sampling signals, such as... Figure 2 As shown, the method includes the following steps: Step S201: In response to the synchronization trigger event, generate and send the current synchronization signal frame.

[0069] In one embodiment, upon detecting a synchronization trigger event, the host generates and sends a synchronization signal frame. In a specific embodiment, the synchronization trigger event may include initial power-on synchronization, periodic trigger synchronization, and event-triggered synchronization. Initial power-on synchronization occurs when the system powers on, and the host sends a network-wide synchronization signal, causing all sampling terminals to perform initial clock calibration. Periodic trigger synchronization refers to periodic synchronization performed at fixed intervals during normal system operation. Event-triggered synchronization refers to emergency synchronization triggered when a grid frequency fluctuation exceeds a preset value. Generally, event-triggered synchronization has a higher priority than periodic trigger synchronization, and periodic trigger synchronization has a higher priority than initial power-on synchronization.

[0070] In the event of a synchronization triggering event, the host can generate a synchronization signal through a high-precision clock source and broadcast the synchronization signal to each acquisition terminal. This signal contains the host's current precise timestamp T0.

[0071] After generating a synchronization signal frame, the host can broadcast the synchronization signal frame. In one specific embodiment, the host broadcasts the synchronization signal through a 2.4GHz wireless module, and simultaneously records the host's transmission time T0. In addition, a receive acknowledgment timeout timer can be started to determine whether the acquisition terminal receives the synchronization signal frame within a preset time.

[0072] Step S202: Determine the dynamic compensation amount for the current synchronization cycle.

[0073] In one embodiment, the host obtains the precise timestamps (corresponding to the first timestamp) of the natural zero-crossing points of the multi-phase voltage waveforms. For example, for three-phase voltage, t_A, t_B, and t_C represent the precise timestamps of the natural zero-crossing points of the A, B, and C phase voltage waveforms, respectively. In a specific embodiment, the zero-crossing time can be accurately calculated using the synchronized voltage sampling data of each channel through an interpolation algorithm. Calculate the first difference between the zero-crossing timestamps of each pair of phase voltage waveforms. For example, for three-phase voltages t_A, t_B, and t_C, calculate the first difference between the zero-crossing timestamps of each pair of phase voltages, such as t_A - t_B, t_B - t_C, and t_C - t_A. Compare the maximum absolute value of the first difference between the zero-crossing timestamps of each pair of phases, e = max(|t_A - t_B|, |t_B - t_C|, |t_C - t_A|), with the first preset time difference. If the maximum absolute value of the first difference between the zero-crossing timestamps of each pair of phases is not greater than the first preset time difference, the dynamic compensation amount is the dynamic compensation amount of the previous synchronization cycle. Otherwise, the host uses closed-loop PID control based on the dynamic compensation amount of the previous synchronization cycle to determine a new dynamic compensation amount, which is then used as the dynamic compensation amount for the current synchronization cycle.

[0074] In one specific embodiment, the first preset time difference is preset, for example, it can be 0.833μs (corresponding to a phase difference of 0.015°). When the maximum value of the absolute value of the first difference is greater than the first preset time difference, it indicates that the synchronization accuracy does not meet the requirements, and the closed-loop fine-tuning mechanism is triggered.

[0075] Under the condition that the closed-loop fine-tuning mechanism is triggered, the host will execute the following complete post-trigger action flow to ensure that synchronization accuracy is quickly restored and remains stable. In one embodiment, the closed-loop fine-tuning mechanism includes closed-loop PID control.

[0076] Under closed-loop PID control, an adaptive PID controller can be used to adjust the clock compensation parameter. The new dynamic compensation calculation formula can be: Δt_new=Δt_old+Kp·e+Ki·∫e·dt+Kd·de / dt; Where e is the time deviation of the current synchronization error, in microseconds (μs). As mentioned above, e is obtained by calculating the zero-crossing detection time difference of multiphase voltage (e.g., three-phase voltage) and the phase standard deviation of each channel fundamental wave (e.g., 50Hz fundamental wave).

[0077] Among them, Kp, Ki, and Kd are adaptive PID parameters that can be dynamically adjusted according to the time difference e.

[0078] Δt_new and Δt_old are essentially dynamic adjustment components of T_delay. Δt_old is the dynamic compensation amount of the previous synchronization cycle, and Δt_new is the dynamic compensation amount of the current synchronization cycle obtained by PID calculation of the current control cycle.

[0079] In an optional embodiment, step S202 may include: Obtain the first timestamp of the natural zero-crossing point of the voltage waveform of each phase; Calculate the first difference between the zero-crossing timestamps of each pair of phase voltage waveforms; If the maximum value of the absolute values ​​of the first differences between the pairwise zero-crossing timestamps is not greater than the first preset time difference, the dynamic compensation amount adopts the dynamic compensation amount of the previous synchronization cycle; and If the maximum value of the absolute value of the first difference between the two zero-crossing timestamps is greater than the first preset time difference, a new dynamic compensation amount is determined based on the dynamic compensation amount of the previous synchronization cycle using a closed-loop fine-tuning mechanism, and used as the dynamic compensation amount of the current synchronization cycle.

[0080] Step S203: The dynamic compensation amount is sent to multiple sampling terminals so that the multiple sampling terminals can determine the sampling start time based on the time of receiving the current synchronization signal frame and the dynamic compensation amount, and keep the sampling time of the multiple sampling terminals synchronized.

[0081] In one embodiment, after determining the start sampling time T_start=T_rx+T_delay, the sampling terminal starts synchronous AD sampling (analog-digital sampling), and the sampling rate can be precisely controlled at 10kHz (sampling interval is 100μs) to acquire electrical signals (the voltage acquisition module and the current acquisition module acquire voltage signals and current signals respectively).

[0082] Figure 3 This is a flowchart of a method for synchronizing sampling signals according to another embodiment of this application. Figure 2 compared to, Figure 3 Steps S301 to S303 of the method shown are Figure 2 Steps S201 to S203 of the method shown are the same, except that, Figure 3 The method shown also includes: Step S304: Obtain the second timestamp of the natural zero-crossing point of the voltage waveform of each phase; Step S305: Calculate the second difference between the zero-crossing timestamps of each pair of phase voltage waveforms; Step S306: If the maximum value of the absolute values ​​of the second differences between the pairwise zero-crossing timestamps is not greater than the second preset time difference, then the synchronization compensation is determined to be successful; and Step S307: If the maximum value of the absolute values ​​of the second differences between the two zero-crossing timestamps is greater than the second preset time difference, the secondary synchronization compensation strategy is activated.

[0083] In one embodiment, to verify the compensation effect, the sampling terminal can perform three-phase voltage zero-crossing detection, obtain the second timestamp of the natural zero-crossing point of each phase voltage waveform, and calculate the second difference between the pairwise zero-crossing point timestamps in each phase voltage waveform. As described above, the second difference is obtained by calculating the zero-crossing detection time difference of multi-phase voltage (e.g., three-phase voltage) and the phase standard deviation of each channel fundamental wave (e.g., 50Hz fundamental wave).

[0084] The maximum value of the absolute values ​​of the second differences between the pairwise zero-crossing timestamps, e_new = max(|t_A-t_B|, |t_B-t_C|, |t_C-t_A|), is compared with the second preset time difference. If the maximum value of the absolute values ​​of the second differences between the pairwise zero-crossing timestamps is not greater than the second preset time difference, the synchronization compensation is determined to be successful; otherwise, the synchronization compensation is determined to be unsuccessful. In an optional embodiment, a secondary synchronization compensation strategy can be initiated.

[0085] Figure 4 This is a flowchart of a method for synchronizing sampling signals according to yet another embodiment of this application. Figure 2 compared to, Figure 4 Steps S401 to S403 of the method shown are Figure 2 Steps S201 to S203 of the method shown are the same, except that, Figure 4 The method shown also includes: Step S404: Obtain the first time when the host sends the synchronization signal frame in the previous synchronization cycle, the second time when any one of the plurality of acquisition terminals receives the synchronization signal frame, the third time when any one of the acquisition terminals sends the acquisition data frame, and the fourth time when the host receives the acquisition data frame. Step S405: Determine the clock offset based on the first time, the second time, the third time, and the fourth time; and Step S406: Determine the corrected time base based on the clock deviation and the second time.

[0086] In an optional embodiment, to further improve synchronization accuracy, the host and the acquisition terminal can use a two-way timestamping method to accurately separate transmission delay and clock deviation: Step 1: The host sends a synchronization signal (host clock) at T0. Step 2: The acquisition terminal receives the synchronization signal (local clock of the acquisition terminal) at T1. Step 3: The acquisition terminal sends a data frame at T2 (acquisition terminal local clock); Step 4: The host receives data frames (host clock) at T3.

[0087] After determining the first time T0 when the host sends the synchronization signal frame in the previous synchronization cycle, the second time T1 when any of the multiple acquisition terminals receives the synchronization signal frame, the third time T2 when any acquisition terminal sends the acquisition data frame, and the fourth time T3 when the host receives the acquisition data frame, the host determines the clock deviation based on the first time, the second time, the third time, and the fourth time.

[0088] In one specific implementation, the clock skew can be calculated using θ=[(T3-T2) -(T1-T0)] / 2.

[0089] Then, based on the clock offset and the second time, the corrected time base is determined.

[0090] In one embodiment, the sampling times of different acquisition terminals (voltage acquisition module, current acquisition module) can be mapped to a unified time base. The corrected t_corrected_final is the only reference for data association and can be called the corrected time base.

[0091] The original reception time T1 includes transmission delay and clock skew. The systematic error is corrected by the clock skew θ: t_corrected = T1 + θ. This is the basic correction used to eliminate the systematic clock skew and transmission delay. θ is the clock skew, which already includes the systematic effect of transmission delay.

[0092] To address dynamic errors (clock drift, environmental changes, device aging, etc.) and improve the accuracy of transmission delay calculation, a dynamic compensation amount Δt is added to compensate for dynamic errors: t_corrected_final = (T1 +θ) +Δt, where Δt is the dynamic compensation amount for the current synchronization cycle.

[0093] The above methods can further improve the alignment accuracy between the sampling terminal and the host sampling time. For example, the alignment accuracy between the sampling terminal and the host sampling time at a distance of 30 meters can reach within ±0.56μs.

[0094] Figure 5 This is a flowchart of a method for synchronizing sampling signals according to another embodiment of this application. Figure 2 compared to, Figure 5 Steps S501 to S503 of the method shown are Figure 2 Steps S201 to S203 of the method shown are the same, except that, Figure 5 The method shown also includes: Step S504: Receive the current signal and voltage signal synchronously collected by the multiple sampling terminals; Step S505: Calculate the theoretical electrical energy value based on the current signal and the voltage signal; Step S506: Calculate the number of pulses based on the theoretical electrical energy value; and Step S507: Calculate the power error using the calculated pulse count and the measured pulse count.

[0095] In one embodiment, after the acquisition terminal acquires the electrical signal, it sends the acquired data frame to the host. After receiving the current signal and voltage signal, the host calculates the theoretical electrical energy value based on the synchronized voltage and current signals. E 理 =∫(u(t)×i(t))dt; where u(t) and i(t) are the instantaneous values ​​of voltage and current after time alignment, respectively.

[0096] Calculate the number of pulses m0: m0 = C0 × E 理 Where C0 is the energy meter constant.

[0097] In addition, the host acquires the pulse signal m1 of the tested energy meter through a photoelectric sampler, compares the measured pulse number m1 with the calculated pulse number m0, and calculates the energy error according to the following formula: Error = (m1 - m0) / m0 × 100%.

[0098] According to the sampling signal synchronization method and system provided in this application, high-precision time synchronization of multi-channel voltage and current signals is achieved through an improved closed-loop fine-tuning mechanism, with a synchronization accuracy of within ±0.5μs, meeting the calibration requirements of 0.05-level energy meters (phase error <0.01°, corresponding to 50Hz, system time error <0.56μs).

[0099] Compared to traditional wireless synchronization methods (with an accuracy typically >100μs), this application integrates a pre-compensation mechanism with a PID closed-loop control dynamic compensation strategy, adapting to complex field environments and improving synchronization accuracy by more than 200 times. Even without GPS, a 0.05-level energy meter verification capability is achieved through a dual guarantee mechanism of bidirectional timestamps and closed-loop fine-tuning.

[0100] In addition, this application supports indoor and outdoor full-scene applications, solves the problem of traditional GPS synchronization failing in obstructed environments, and avoids the cumbersome wiring of wired connections, greatly improving on-site verification efficiency and reducing labor and equipment costs.

[0101] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this application, and on the specific implementation methods and application scope of this application, are all within the scope of protection of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for synchronizing sampling signals, applied to a host computer, characterized in that, The method comprises: generating and sending a current synchronization signal frame in response to a synchronization trigger event; determining a dynamic compensation amount of a current synchronization period; sending the dynamic compensation amount to a plurality of sampling terminals, so that the plurality of sampling terminals can determine a sampling start time according to a time of receiving the current synchronization signal frame and the dynamic compensation amount, and the sampling time of the plurality of sampling terminals is kept synchronized. The determination of the dynamic compensation amount of the current synchronization period comprises:

2. The method of claim 1, wherein, obtaining first time stamps of natural zero-crossing points of each phase voltage waveform; calculating first difference values of two-by-two zero-crossing point time stamps in the each phase voltage waveform; in a case where a maximum value in absolute values of the first difference values of the two-by-two zero-crossing point time stamps is not greater than a first preset time difference, the dynamic compensation amount adopts a dynamic compensation amount of a last synchronization period; and in a case where the maximum value in the absolute values of the first difference values of the two-by-two zero-crossing point time stamps is greater than the first preset time difference, a new dynamic compensation amount is determined based on a closed-loop fine-tuning mechanism and the dynamic compensation amount of the last synchronization period, as the dynamic compensation amount of the current synchronization period. After determining the dynamic compensation amount of the current synchronization period, the method further comprises:

3. The method of claim 2, wherein, obtaining second time stamps of natural zero-crossing points of each phase voltage waveform; calculating second difference values of two-by-two zero-crossing point time stamps in the each phase voltage waveform; in a case where a maximum value in absolute values of the second difference values of the two-by-two zero-crossing point time stamps is not greater than a second preset time difference, determining that the synchronization compensation is successful; and in a case where the maximum value in the absolute values of the second difference values of the two-by-two zero-crossing point time stamps is greater than the second preset time difference, starting a secondary synchronization compensation strategy. The determination of the new dynamic compensation amount based on the dynamic compensation amount of the last synchronization period by using the closed-loop fine-tuning mechanism, as the dynamic compensation amount of the current synchronization period, comprises:

4. The method of claim 2, wherein, determining a temporary dynamic compensation amount by using the closed-loop fine-tuning mechanism; and amplitude-limiting the temporary dynamic compensation amount according to a preset single compensation limit value and / or a preset cumulative compensation limit value to determine the new dynamic compensation amount, as the dynamic compensation amount of the current synchronization period. The method further comprises:

5. The method of claim 3, wherein, obtaining a first time at which the host sends a synchronization signal frame in a last synchronization period, a second time at which any one of the plurality of collection terminals receives the synchronization signal frame, a third time at which the any one of the plurality of collection terminals sends a collection data frame, and a fourth time at which the host receives the collection data frame; determining a clock deviation according to the first time, the second time, the third time, and the fourth time; and determining a corrected time reference according to the clock deviation and the second time. The obtaining of the first time stamps of the natural zero-crossing points of each phase voltage waveform comprises: obtaining the first time stamps of the natural zero-crossing points of each phase voltage waveform according to the corrected time reference.

6. The method of claim 5, wherein, The obtaining of the second time stamps of the natural zero-crossing points of each phase voltage waveform comprises: obtaining the second time stamps of the natural zero-crossing points of each phase voltage waveform according to the corrected time reference.

7. The method of claim 5, wherein, The method further comprises: receiving current signals and voltage signals synchronously collected by the plurality of sampling terminals; 8. The method of claim 1, wherein, calculating a theoretical electric energy value according to the current signals and the voltage signals; and calculating a sampling start time according to the theoretical electric energy value and the dynamic compensation amount. ​ calculating the number of pulses according to the theoretical electric energy value; and calculating the electric energy error through the calculated number of pulses and the measured number of pulses.

9. The method of claim 1, wherein, The synchronous trigger event includes an initial power-on synchronization, a periodic trigger synchronization, and an event trigger synchronization, and the sampling terminal includes a voltage acquisition module and a wireless current clamp meter.

10. A synchronization system for a sampled signal, characterized by comprising: a host configured to perform the method according to any one of claims 1 to 9; and a sampling terminal configured to receive the current synchronization signal frame and the dynamic compensation amount sent by the host, and determine a sampling start time according to a receiving time of the current synchronization signal frame and the dynamic compensation amount.

11. The system of claim 10, wherein, The sampling terminal is further configured to: send the acquired electric signal data frame, the receiving time of the current synchronization signal frame, and a sending time of the electric signal data frame to the host.

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