Data compression circuit and method suitable for single photon avalanche diode array

Abstract

The invention relates to a data compression circuit and method suitable for a single photon avalanche diode array, and the circuit comprises a pixel array which is provided with M rows and N columns of pixels; the multi-stage compression circuit comprises a plurality of compression cache circuits connected in sequence, each stage of compression cache circuit comprises a plurality of first storage areas used for storing TDC data and address bits used for storing the positions of pixels corresponding to the TDC data in the pixel array, and the multi-stage compression circuit reads the TDC data of the pixel array line by line. And after multi-stage compression, the signals are output to a post-stage circuit. Compared with the prior art, the pixel data in a digital form is greatly compressed, the data transmission quantity is reduced, the data transmission bottleneck problem of a large-scale array is solved, and a key technical support is provided for a high-performance single-photon detection system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of laser radar, and in particular to a data compression circuit and method suitable for a single-photon avalanche diode array. BACKGROUND

[0002] Single-photon detection technology has shown significant advantages in modern optics and electronics due to its extremely high sensitivity and excellent time resolution. Single-photon avalanche diode (SPAD) detectors can capture signals at the single-photon level, meeting the detection needs of extremely low light intensity environments, with picosecond to nanosecond time resolution, supporting high-speed photon counting and high-precision three-dimensional imaging. Traditional analog methods have the problem of excessive data volume. Although some existing technologies use some compression methods to compress pulse width, the data volume is still large. In order to reduce the amount of information, digital output signals are generally used at present, thereby simplifying the subsequent processing process and reducing the complexity of the detection system. Based on these advantages, single-photon detection is widely used in quantum communication and computing, laser radar (LiDAR), low-light biomedical imaging, astronomical observation, spectral analysis, and environmental monitoring. Although single-photon detection technology brings stronger detection capability, it also brings a serious challenge - the generation of massive data. A typical SPAD array may contain hundreds or even thousands of pixels, and each pixel will generate a digital signal when detecting a photon, indicating the photon arrival time or photon counting. Taking a 128x128 SPAD array as an example, if each pixel generates 1 million events per second, the entire array will generate about 16 billion events per second. Such a huge amount of raw data poses extremely high requirements for data transmission, storage, and subsequent processing.

[0003] With the continuous expansion of the scale of the SPAD array, the data volume of the array has also experienced explosive growth, which has led to the following problems: First, the bottleneck of data transmission bandwidth: the data interface between the SPAD array chip and the subsequent processing unit often cannot withstand such a high data rate, leading to data congestion or limited system throughput; second, the increase in data storage costs: storing massive amounts of raw event data requires a large amount of storage space and high-speed storage devices, which is unacceptable in many portable or resource-constrained applications; finally, the complexity of subsequent data processing: whether based on FPGA, GPU, or application-specific integrated circuit (ASIC) for data processing, high-dimensional and high-throughput data will bring great pressure to algorithm implementation and allocation of computing resources, prolonging processing time and even making real-time processing impossible.

[0004] Currently, two strategies are usually adopted to process the data generated by SPAD array: one is to directly transmit all raw event data to the backend for processing; the other is to perform a certain degree of preprocessing and data screening on-chip or near the chip. However, even if preprocessing is performed, when the SPAD array works in a high-background-noise or high-reflectivity scene, the photon event density is high, and both the effective data and the background noise events will increase a lot, resulting in a very large amount of data. Some existing data compression methods mainly focus on the field of CMOS image sensors, such as JPEG, MPEG, etc. These methods usually use the spatial redundancy and temporal redundancy in images for compression, but the data generated by SPAD array is significantly different from traditional image data: SPAD array outputs discrete and sparse photon events, rather than continuous gray-scale images. Therefore, traditional image compression methods are often difficult to be directly applied to SPAD array data, or will cause unacceptable information loss when applied. SUMMARY

[0005] The purpose of the present application is to provide a data compression circuit and method suitable for single-photon avalanche diode array to solve the above-mentioned defects of the prior art.

[0006] The purpose of the present application can be achieved by the following technical solutions: A data compression circuit suitable for single-photon avalanche diode array, comprising: a pixel array, having M rows and N columns of pixels; a multi-stage compression circuit, comprising a plurality of compression buffer circuits connected in sequence, each compression buffer circuit comprising a plurality of first storage areas for storing TDC data, and address bits for storing the positions of the pixels corresponding to the TDC data in the pixel array, the multi-stage compression circuit reading the TDC data of the pixel array row by row, and outputting to the next stage circuit after multi-stage compression.

[0007] In the multi-stage compression circuit, the number of first storage areas of each compression buffer circuit is half of the number of first storage areas of the previous compression buffer circuit, and the number of first storage areas of the first compression buffer circuit is N / 2.

[0008] Each compression buffer circuit is configured to: read step: read the TDC data of all pixels in the previous compression buffer circuit; fuse the TDC data in the jth first storage area and the TDC data in the j+N k / 2th first storage area of the previous compression buffer circuit, and write the fused TDC data into the jth first storage area of the current compression buffer circuit, where N kThe number of the first storage area in the upper-level compression buffer circuit, j is in the range of 1 to N k / 2.

[0009] When it is the first-level compression buffer circuit, all pixels in a row of the pixel array are read in the reading step, k=0, and the total number of columns of the pixel array is taken.

[0010] The elements of the jth column and the elements of the j+N k / 2th column are fused in a manner comprising: If both TDC data represent invalid, the fused TDC data is all 0, wherein the TDC data is multi-bit data, the first bit is 1, indicating that an avalanche trigger event is detected in the whole detection time window, recorded as valid data, and the first bit is 0, indicating that no avalanche trigger event is detected in the whole detection time window, recorded as invalid data; If one of the two TDC data represents invalid and the other represents valid, the fused TDC data is the TDC data representing valid; If both TDC data represent valid, the fused TDC data is any one of the TDC data.

[0011] A method of the circuit as described above, comprising: Step S1: obtaining TDC data of a pixel array and constructing an original TDC data array; Step S2: determining a compression level K based on the size of the pixel array; Step S3: for each row of the original TDC data array, sequentially performing multi-level compression to obtain a compressed row; Step S4: splicing all the compressed rows to obtain a compressed TDC data array and outputting.

[0012] The step S3 comprises: Step S3-1: selecting a first row in the original TDC data array as a current target row and initializing the compression level k=0; Step S3-2: fusing the elements of the jth column and the elements of the j+N k / 2th column of the current target row as the elements of the jth column of the buffer row, wherein N k is the number of columns of the buffer row after the k+1th level compression, and j is in the range of 1 to N k / 2. Step S3-3: increasing the compression level k by 1, and determining whether the compression level is equal to the total compression level K, if yes, executing step S3-5, otherwise, executing step S3-4; Step S3-4: updating the buffer row as the current target row and returning to step S3-2; Step S3-5: Use the cached line as the compressed line, determine whether there are any uncompressed lines in the original TDC data array. If yes, select the next line in the original TDC data array as the current target line, initialize the compression level k=0, and execute step S3-2. Otherwise, execute step S4.

[0013] Step S3-2 includes: Step S3-2-1: Determine whether the first bit of the element in the j-th column of the current target row indicates validity. If yes, proceed to step S3-2-2; otherwise, proceed to step S3-2-3. The element in the j-th column of the current target row is multi-bit data. When the first bit is 1, it indicates that an avalanche triggering event was detected in the entire detection time window and is recorded as valid data. When the first bit is 0, it indicates that no avalanche triggering event was detected in the entire detection time window and is recorded as invalid data. Step S3-2-2: Determine the (j+N)th row of the current target row. k If the element in column / 2 is valid, proceed to step S3-2-5; otherwise, proceed to step S3-2-4. Step S3-2-3: Determine the (j+N)th row of the current target row. k If the element in column / 2 is valid, proceed to step S3-2-4; otherwise, proceed to step S3-2-6. Step S3-2-4: Use the valid element as the element in the j-th column of the cache row, and write the address information of the valid element into the element address bit of the j-th column of the cache row; Step S3-2-5: Find the element in the j-th column of the current target row and the (j+N)-th element. k Randomly select one element from the elements in column / 2 as the element in column j of the cache row, and write its address information into the address bit of the element in column j of the cache row; Step S3-2-6: Output all zeros as the element in the j-th column of the cache row.

[0014] When in the first compression level, in step S3-2-4, after taking the valid element as the element of the j-th column of the cache row, address information is generated according to the position of the valid element in the original TDC data array and written into the element address bit of the j-th column of the cache row. In step S3-2-5, the element in the j-th column of the current target row and the (j+N)-th element... k After randomly selecting one element from the elements in column / 2 as the element in column j of the cache row, the address information is generated based on the position of this element in the original TDC data array and written into the element address bit of column j of the cache row.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. By designing a multi-stage compression circuit, the TDC data in the original digital signal format output by the pixel array can be compressed. The line-by-line compression method is compatible with existing line-by-line scanning processing modes, requiring minimal modification to the radar main control. Furthermore, each compression buffer circuit, in addition to the first storage area, is equipped with address bits to store address information, indicating which pixel the compressed TDC data corresponds to, facilitating processing by subsequent circuits and the application layer. Due to the large-scale compression of digital signal format data through multi-stage compression circuits, the amount of data transmitted by the array can be significantly reduced in applications with sparse signals, solving the data transmission bottleneck problem of large-scale arrays.

[0016] 2. The distance between the merged pixels is as large as possible to reduce the amount of information lost during the compression process.

[0017] 3. Fusion methods were designed for the three scenarios. Data loss occurs when both TDCs are valid, while fusion methods using the j-th and j+N-th TDCs... k Merging two data points can reduce the probability of data loss. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall structure of the present invention; Figure 2 This is a schematic diagram of the multi-stage compression process of the present invention; Figure 3 This is a schematic diagram illustrating the specific compression process of the present invention; Among them: 1. Pixel array, 2. Multi-level compression circuit. Detailed Implementation

[0019] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0020] A data compression circuit suitable for single-photon avalanche diode arrays, such as Figure 1 As shown, it includes: A pixel array with M rows and N columns of pixels; Multi-stage compression circuits, such as Figure 2 As shown, it includes multiple compression buffer circuits connected in sequence. Each compression buffer circuit includes multiple first storage areas for storing TDC data and address bits for storing the position of the pixel corresponding to the TDC data in the pixel array. The multi-stage compression circuit reads the TDC data of the pixel array line by line, performs multi-stage compression, and outputs it to the subsequent stage circuit.

[0021] For an M×N pixel array, specifically a single-photon avalanche diode array, each pixel incorporates a multi-bit timing circuit to collect photon time-of-flight (TDC) data. When the single-photon avalanche diode array operates in 3D windowed detection mode, it effectively detects the TDC data of each pixel. The highest bit of the pixel data is set as the FLAG valid flag, with a value of 0 or 1. A FLAG valid flag of 0 indicates that the pixel did not trigger an event within the detection window, marking the data as an invalid signal. A FLAG valid flag of 1 indicates that the pixel triggered an event within the detection window, with the data being a photon arrival signal or an avalanche signal triggered by dark counting, indicating that the data is a valid signal.

[0022] In a multi-stage compression circuit, the number of first storage areas in each stage of the compression buffer circuit is half the number of first storage areas in the previous stage of the compression buffer circuit. Specifically, the number of first storage areas in the first stage of the compression buffer circuit is N / 2.

[0023] In this embodiment, each compression buffer circuit is configured as follows: Reading steps: Read the TDC data of all pixels in the previous level compression buffer circuit; The TDC data in the j-th first storage area of ​​the previous level compression cache circuit and the j+N-th... k The TDC data in the two first storage areas are merged, and the merged TDC data is written into the j-th first storage area of ​​the current compression cache circuit, where N k The value of j represents the number of the first storage areas in the next-level compression cache circuit, and the value of j ranges from 1 to N. k A positive integer equal to 2.

[0024] When it is the first-level compression buffer circuit, the TDC data of all pixels in a row of the pixel array is read in the reading step, k=0, and the total number of columns of the pixel array is taken.

[0025] Here, the elements of the j-th column and the (j+N)-th column are... k The methods for merging elements in column / 2 include: If both TDC data points indicate invalidity, the merged TDC data will be all zeros. TDC data consists of multiple bits. When the first bit is 1, it indicates that an avalanche triggering event was detected in the entire detection time window, and it is recorded as valid data. When the first bit is 0, it indicates that no avalanche triggering event was detected in the entire detection time window, and it is recorded as invalid data. If one TDC data point represents invalidity and the other represents validity, then the merged TDC data point represents the valid TDC data point. If both TDC data points are valid, the merged TDC data point is either one of them. In this embodiment, if both TDC data points are valid, one of them is selected randomly as the merged TDC data point.

[0026] Furthermore, a method based on the above-described circuit includes: Step S1: Obtain the TDC data of the pixel array and construct the original TDC data array; Step S2: Determine the compression level K based on the size of the pixel array; Step S3: For each row of the original TDC data array, perform multi-level compression sequentially to obtain the compressed row, including: Step S3-1: Select the first row in the original TDC data array as the current target row, and initialize the compression level k=0; Step S3-2: Combine the elements in the j-th column of the current target row with the (j+N)-th element. k The elements of column / 2 are merged and used as the element of the j-th column of the cache row, where N k Let j be the column number of the cache row after the (k+1)th level of compression, where j ranges from 1 to N. k A positive integer equal to 2; Step S3-2 includes: Step S3-2-1: Determine whether the first bit of the element in the j-th column of the current target row indicates validity. If yes, proceed to step S3-2-2; otherwise, proceed to step S3-2-3. The element in the j-th column of the current target row is multi-bit data. When the first bit is 1, it indicates that an avalanche triggering event was detected in the entire detection time window and is recorded as valid data. When the first bit is 0, it indicates that no avalanche triggering event was detected in the entire detection time window and is recorded as invalid data. Step S3-2-2: Determine the (j+N)th row of the current target row. k If the element in column / 2 is valid, proceed to step S3-2-5; otherwise, proceed to step S3-2-4. Step S3-2-3: Determine the (j+N)th row of the current target row. k If the element in column / 2 is valid, proceed to step S3-2-4; otherwise, proceed to step S3-2-6. Step S3-2-4: Use the valid element as the element in the j-th column of the cache row, and write the address information of the valid element into the element address bit of the j-th column of the cache row; When in the first compression level, in step S3-2-4, after taking the valid element as the element of the j-th column of the cache row, address information is generated according to the position of the valid element in the original TDC data array and written into the element address bit of the j-th column of the cache row. Step S3-2-5: Find the element in the j-th column of the current target row and the (j+N)-th element. k Randomly select one element from the elements in column / 2 as the element in column j of the cache row, and write its address information into the address bit of the element in column j of the cache row; When in the first compression stage, in step S3-2-5, the element in the j-th column of the current target row and the (j+N)-th element... k After randomly selecting one element from the elements in column / 2 as the element in column j of the cache row, the address information is generated based on the position of this element in the original TDC data array and written into the element address bit of column j of the cache row.

[0027] Step S3-2-6: Output all zeros as the element in the j-th column of the cache row.

[0028] Step S3-3: Increment the compression level k by 1, and determine whether the compression level is equal to the total compression level K. If yes, proceed to step S3-5; otherwise, proceed to step S3-4. Step S3-4: Update the cached line to the current target line and return to step S3-2; Step S3-5: Use the cached line as the compressed line, determine whether there are any uncompressed lines in the original TDC data array. If yes, select the next line in the original TDC data array as the current target line, initialize the compression level k=0, and execute step S3-2. Otherwise, execute step S4.

[0029] Step S4: Concatenate all the compressed rows to obtain the compressed TDC data array and output it.

[0030] like Figure 2The three-level data compression process in this embodiment is illustrated below. In this embodiment, a row of TDC data for the pixel array contains 64 data points. Due to the sparsity of photon events, gray boxes represent valid data for the corresponding column positions of a row of pixels, while white boxes represent invalid data. The first-level compression compares and compresses the data in the first column and the 33rd column of the original TDC data for each row of pixels, outputting the resulting data to the first column of the first-level compression buffer. Similarly, the second and 34th columns of the original TDC data for each row of pixels are compared and compressed, outputting the resulting data to the second column of the first-level compression buffer. This process continues, with the 32nd and 64th columns of the original TDC data for each row of pixels being compared and compressed, outputting the resulting data to the 32nd column of the first-level compression buffer. The first-level compression requires 32 compression module units working in parallel. After the first-level compression, the amount of original TDC data for a row of pixels in this embodiment is reduced from 64 to 32. Next, the second level of compression is performed. The data in the first-level compression buffer is compared and compressed with the data in the first-level compression buffer, and the resulting data is output to the first column of the second-level compression buffer. The data in the second-level compression buffer is compared and compressed with the data in the first-level compression buffer, and the resulting data is output to the second column of the second-level compression buffer. And so on, the data in the 16th column of the first-level compression buffer is compared and compressed with the data in the 32nd column of the second-level compression buffer, and the resulting data is output to the 32nd column of the second-level compression buffer. The second-level compression requires 16 compression module units to work in parallel. After the second-level compression, the amount of original TDC data for one row of pixels in the embodiment is compressed from 64 to 16. Finally, a third level of compression is performed. The data in columns 1 and 9 of the second-level compression buffer are compared and compressed, and the resulting data is output to column 1 of the third-level compression buffer. Similarly, the data in columns 2 and 10 of the first-level compression buffer are compared and compressed, and the resulting data is output to column 2 of the third-level compression buffer. This process continues, with columns 8 and 16 of the second-level compression buffer being compared and compressed, and the resulting data is output to column 8 of the third-level compression buffer. This third-level compression requires eight compression module units working in parallel. After the third-level compression, the original TDC data volume of one row of pixels in this embodiment is compressed from 64 to 8. When the array size increases in this embodiment, the number of compression levels can be increased by multiple levels, achieving a significant improvement in data compression rate and effectively increasing the readout rate of single-photon avalanche diode array data.

[0031] like Figure 3As shown, the compression module in the embodiment will be described in detail. For two input data points to the compression module, if input IN1 is valid (data A) and input IN2 is invalid (data 0), then the output data OUT after compression and comparison is valid data, and its content is the data A from input IN1. If input IN1 is invalid (data 0) and input IN2 is valid (data B), then the output data OUT after compression and comparison is valid data, and its content is the data B from input IN2. Similarly, if both input IN1 and IN2 are valid (data A and B), then the output data OUT after compression and comparison is valid data, and its content is the data A from input IN1. Conversely, if both input IN1 and IN2 are invalid (data 0), then the output data OUT after compression and comparison is invalid data, and its content is 0.

[0032] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A data compression circuit suitable for a single-photon avalanche diode array, comprising: a pixel array having M rows and N columns of pixels; characterized in that it further comprises: a multi-stage compression circuit comprising a plurality of compression buffer circuits connected in sequence, each compression buffer circuit comprising a plurality of first storage areas for storing TDC data and address bits for storing the positions of the pixels corresponding to the TDC data in the pixel array, the multi-stage compression circuit reading the TDC data of the pixel array row by row, performing multi-stage compression, and outputting to a subsequent circuit.

2. A data compression circuit suitable for use with a single photon avalanche diode array according to claim 1, wherein, In the multi-stage compression circuit, the number of first storage areas of each compression buffer circuit is half the number of first storage areas of the previous compression buffer circuit, and the number of first storage areas of the first compression buffer circuit is N / 2.

3. The data compression circuit for a single photon avalanche diode array according to claim 1, wherein, Each compression buffer circuit is configured to: read step: read the TDC data of all pixels in the previous compression buffer circuit; TDC data in the jth first storage area in the compression cache circuit of the previous stage and TDC data in the jth+N k / 2 first storage areas are fused, and the fused TDC data is written into the jth first storage area of the compression cache circuit of the present stage, wherein N k is the number of first storage areas in the compression cache circuit of the previous stage, and j has a value range of 1 to N k / 2 is a positive integer.

4. A data compression circuit suitable for use with a single photon avalanche diode array according to claim 3, wherein, when it is the first compression buffer circuit, the read step reads the TDC data of all pixels in a row of the pixel array, k = 0, and the total number of columns of the pixel array is taken.

5. A data compression circuit suitable for use with a single photon avalanche diode array according to claim 3, wherein, The elements of the jth column are fused with the elements of the j+N k th column in a manner that includes: If both TDC data represent invalid, the fused TDC data is all 0, wherein the TDC data is multi-bit data, the first bit is 1, indicating that an avalanche trigger event is detected in the entire detection time window, and is recorded as valid data, and the first bit is 0, indicating that no avalanche trigger event is detected in the entire detection time window, and is recorded as invalid data; If one of the two TDC data represents invalid and the other represents valid, the fused TDC data is the TDC data representing valid; If both TDC data represent valid, the fused TDC data is any one of the TDC data.

6. A method based on the circuit according to any one of claims 1 to 5, characterized in that, comprising: Step S1: obtaining the TDC data of the pixel array and constructing an original TDC data array; Step S2: determining the compression stage number K based on the size of the pixel array; Step S3: for each row of the original TDC data array, sequentially performing multi-stage compression to obtain a compressed row; Step S4: concatenating all compressed rows to obtain a compressed TDC data array and outputting.

7. The method of claim 6, wherein, The step S3 comprises: Step S3-1: selecting the first row in the original TDC data array as the current target row and initializing the compression stage number k = 0; Step S3-2: fuse the element of the jth column of the current target row and the element of the j+N k / 2 column as the element of the jth column of the cache row, where N k is the column number of the cache row after the k+1 level compression, j is an integer ranging from 1 to N k / 2; Step S3-3: increasing the compression stage number k by 1 and determining whether the compression stage number is equal to the total compression stage number K, if yes, executing step S3-5, otherwise, executing step S3-4; Step S3-4: updating the cache row to the current target row and returning to step S3-2; Step S3-5: taking the cache row as the compressed row, determining whether there are still uncompressed rows in the original TDC data array, if yes, selecting the next row in the original TDC data array as the current target row, initializing the compression stage number k = 0, and executing step S3-2, otherwise, executing step S4.

8. The method of claim 7, wherein, The step S3-2 comprises: Step S3-2-1: judging whether the first bit of the element in the jth column of the current target row indicates validity, if yes, executing step S3-2-2, otherwise, executing step S3-2-3, wherein the element in the jth column of the current target row is multi-bit data, when the first bit is 1, it indicates that the avalanche trigger event is detected in the whole detection time window, and is recorded as valid data, and when the first bit is 0, it indicates that the avalanche trigger event is not detected in the whole detection time window, and is recorded as invalid data; Step S3-2-2: judging whether the element in the (j+N)th column of the current target row represents a valid value, if yes, executing step S3-2-5, otherwise, executing step S3-2-4. k Step S3-2-5: judging whether the element in the (j+N)th column of the current target row represents a valid value, if yes, executing step S3-2-6, otherwise, executing step S3-2-4. Step S3-2-3: judging whether the element in the (j+N)th column of the current target row represents a valid value, if yes, executing step S3-2-4, otherwise, executing step S3-2-6. k Step S3-2-3: judging whether the element in the (j+N)th column of the current target row represents a valid value, if yes, executing step S3-2-4, otherwise, executing step S3-2-6. Step S3-2-4: taking the element indicating validity as the element in the jth column of the cache row, and writing the address information of the element indicating validity into the element address bit in the jth column of the cache row; Step S3-2-5: randomly select one between the element in the jth column of the current target row and the element in the j+N k / 2th column as the element in the jth column of the cache line, and write the address information of the element into the element address bit of the jth column of the cache line; Step S3-2-6: outputting all 0 values as the element in the jth column of the cache row.

9. The method of claim 8, wherein, When being in the 1st compression level, after taking the element indicating validity as the element in the jth column of the cache row in step S3-2-4, the address information is generated according to the position of the element indicating validity in the original TDC data array and is written into the element address bit in the jth column of the cache row; In step S3-2-5, one of the elements in the jth column of the current target row and the j+N k After one of the elements in the jth column of the current target row and the j+N / 2 column is randomly selected as the element in the jth column of the cache row, address information is generated according to the position of the element in the original TDC data array and written into the element address bit of the jth column of the cache row.

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