Memory device and manufacturing method thereof

Abstract

The invention discloses a memory device and a manufacturing method thereof, and the memory device comprises a magnetic tunneling junction (MTJ) structure, an upper electrode, and a first cap layer. The MTJ structure is disposed over the substrate and includes a first sloped sidewall. The upper electrode is disposed on the MTJ structure in the vertical direction and includes a second sloped sidewall. The first cap layer covers the upper electrode and the MTJ structure. The first cap layer includes a first portion covering the first inclined sidewall in the horizontal direction and a second portion covering the second inclined sidewall in the horizontal direction. The first portion is partially below the first inclined sidewall in the vertical direction. The second portion is partially located below the second inclined side wall in the vertical direction. And the thickness of the first part in the horizontal direction is greater than that of the second part in the horizontal direction.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory device and a method of fabricating the same, and more particularly to a memory device including a magnetic tunneling junction (MTJ) structure and a method of fabricating the same. BACKGROUND

[0002] There are basically two types of data storage devices used in electronic products, namely non-volatile and volatile memory devices. Magnetic random access memory (MRAM) is a non-volatile memory technology. Unlike the current general standard memory devices, MRAM uses magnetism to store data instead of using electric charge for data storage. Generally, an MRAM cell includes a data layer and a reference layer. The data layer is composed of a magnetic material, and the magnetization state of the data layer can be switched between two opposite states by an applied magnetic field, thereby storing binary information. The reference layer can be composed of a magnetized material, and its magnetization state can be locked. During a read operation, the resistance of the MRAM cell is different when the magnetization state directions of the data layer and the reference layer are the same or different, so the magnetization polarity of the data layer can be identified accordingly. The structure of the MRAM device will differ depending on the technology used to magnetize the data layer. Currently, the more common ones are spin-transfer torque (STT) MRAM and spin-orbit torque (SOT) MRAM, and how to improve the operating performance or / and manufacturing yield of the MRAM device through structural or / and fabrication process design is the continuous research direction of relevant persons in the field. SUMMARY

[0003] The present application provides a memory device and a method of fabricating the same, which uses an upper electrode with an inclined sidewall to improve the relevant fabrication process conditions, and a first cap layer with different thickness portions can be used to improve the protection or / and isolation effect on the magnetic tunneling structure.

[0004] One embodiment of the present disclosure provides a memory device including a magnetic tunneling junction (MTJ) structure, an upper electrode, and a first cap layer. The MTJ structure is disposed over a substrate, and the MTJ structure includes a first sloped sidewall. The upper electrode is disposed over the MTJ structure in a vertical direction, and the upper electrode includes a second sloped sidewall. The first cap layer covers the upper electrode and the MTJ structure, and the first cap layer includes a first portion and a second portion. The first portion covers the first sloped sidewall in a horizontal direction, and the first portion is partially under the first sloped sidewall in the vertical direction. The second portion covers the second sloped sidewall in the horizontal direction, and the second portion is partially under the second sloped sidewall in the vertical direction. A thickness of the first portion in the horizontal direction is greater than a thickness of the second portion in the horizontal direction.

[0005] One embodiment of the present disclosure provides a method of fabricating a memory device including the following steps. A magnetic tunneling junction (MTJ) structure and an upper electrode are formed over a substrate. The MTJ structure includes a first sloped sidewall, and the upper electrode is disposed over the MTJ structure in a vertical direction, and the upper electrode includes a second sloped sidewall. A first cap layer is formed to cover the upper electrode and the MTJ structure, and the first cap layer includes a first portion and a second portion. The first portion covers the first sloped sidewall in a horizontal direction, and the first portion is partially under the first sloped sidewall in the vertical direction. The second portion covers the second sloped sidewall in the horizontal direction, and the second portion is partially under the second sloped sidewall in the vertical direction. A thickness of the first portion in the horizontal direction is greater than a thickness of the second portion in the horizontal direction. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A schematic diagram of a memory device of one embodiment of the present disclosure;

[0007] Figures 2 to 10 A schematic diagram of a method of fabricating a memory device of one embodiment of the present disclosure, wherein

[0008] Figure 3 A schematic diagram of Figure 2 A subsequent condition;

[0009] Figure 4 A schematic diagram of Figure 3 A subsequent condition;

[0010] Figure 5 A schematic diagram of Figure 4 A subsequent condition;

[0011] Figure 6 A schematic diagram of Figure 5 A subsequent condition;

[0012] Figure 7 for Figure 6 A diagram illustrating the subsequent situation;

[0013] Figure 8 for Figure 7 A diagram illustrating the subsequent situation;

[0014] Figure 9 for Figure 8 A diagram illustrating the subsequent situation;

[0015] Figure 10 for Figure 9 A diagram illustrating the subsequent situation.

[0016] Symbol Explanation

[0017] 10: Base

[0018] 10BS: Bottom surface

[0019] 10TS: Top surface

[0020] 12: Dielectric layer

[0021] 14: Dielectric layer

[0022] 16: Connection Structure

[0023] 18: Stop Layer

[0024] 20: Dielectric layer

[0025] 20SW: Inclined sidewall

[0026] 24: Bottom electrode

[0027] 24M: Conductive material

[0028] 24SW: Inclined sidewall

[0029] 26: SOT layer

[0030] 26M:SOT material

[0031] 26SW: Inclined sidewall

[0032] 28: Free Layer

[0033] 28M: Ferromagnetic material

[0034] 30: Barrier Layer

[0035] 30M: Barrier Material

[0036] 32: Reference Layer

[0037] 32M: Ferromagnetic material

[0038] 34: Cap layer

[0039] 34M: Covering material

[0040] 35: MTJ Structure

[0041] 35SW: Inclined sidewall

[0042] 36: Upper electrode

[0043] 36P: Patterned conductive material

[0044] 36SW: Inclined sidewall

[0045] 36TS: Curved upper surface

[0046] 38: Mask layer

[0047] 40: First cap layer

[0048] 40A: Part 1

[0049] 40B: Part Two

[0050] 40M: Covering material

[0051] 42: Oxide mask layer

[0052] 42M: Oxide Materials

[0053] 42SW: Concave sidewall

[0054] 42TS: Curved upper surface

[0055] 44: Second cap layer

[0056] 44M: Covering material

[0057] 46: Interlayer dielectric layer

[0058] 80: Patterned mask layer

[0059] 91: Etching process

[0060] 92: Wet Etching Process

[0061] 93: Etching process

[0062] 100: Memory device

[0063] D1: Vertical direction

[0064] D2: Horizontal direction

[0065] SW1: Inclined sidewall

[0066] SW2: Inclined sidewall

[0067] SW3: Inclined sidewall

[0068] SW4: Inclined sidewall

[0069] TK1: Thickness

[0070] TK2: Thickness

[0071] TS1: Top surface

[0072] TS2: Top surface

[0073] TS3: Top surface

[0074] TS4: Top surface

[0075] W11: Width

[0076] W12: Width

[0077] W21: Width

[0078] W22: Width

[0079] W31: Width

[0080] W32: Width

[0081] W41: Width

[0082] W42: Width

[0083] W51: Width

[0084] W52: Width Detailed Implementation

[0085] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0086] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0087] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0088] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0089] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term that includes etching.

[0090] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0091] Please see Figure 1 . Figure 1 This is a schematic diagram of a memory device 100 according to an embodiment of the present invention. Figure 1 As shown, the memory device 100 includes a magnetic tunneling junction (MTJ) structure (e.g., MTJ structure 35), an upper electrode 36, and a first capping layer 40. The MTJ structure 35 is disposed on a substrate 10 and includes a first inclined sidewall (e.g., inclined sidewall 35SW). The upper electrode 36 is disposed on the MTJ structure 35 in a vertical direction D1 and includes a second inclined sidewall (e.g., inclined sidewall 36SW). The first capping layer 40 covers the upper electrode 36 and the MTJ structure 35, and includes a first portion 40A and a second portion 40B. The first portion 40A covers the inclined sidewall 35SW in a horizontal direction (e.g., horizontal direction D2), and the portion of the first portion 40A in the vertical direction D1 is located below the inclined sidewall 35SW. The second portion 40B covers the inclined sidewall 36SW in the horizontal direction D2, and the portion of the second portion 40B in the vertical direction D1 is located below the inclined sidewall 36SW. The thickness TK1 of the first part 40A in the horizontal direction D2 is greater than the thickness TK1 of the second part 40B in the horizontal direction D2. By controlling the shape of the MTJ structure 35 and the upper electrode 36, the relevant manufacturing process conditions can be improved, and the first capping layer 40 with different thicknesses can be used to improve the protection and / or isolation effect of the MTJ structure 35.

[0092] In some embodiments, the vertical direction D1 can be considered as the thickness direction of the substrate 10. The substrate 10 may have an upper surface 10TS and a bottom surface 10BS opposite to each other in the vertical direction D1, and the aforementioned MTJ structure 35, upper electrode 36, and first capping layer 40 may be disposed on one side of the upper surface 10TS. A horizontal direction that is substantially orthogonal to the vertical direction D1 (e.g., horizontal direction D2 or other horizontal directions) may be substantially parallel to the upper surface 10TS and / or the bottom surface 10BS of the substrate 10, but is not limited thereto. Furthermore, the distance in the vertical direction D1 between a relatively high position in the vertical direction D1 and / or between a component and the bottom surface 10BS of the substrate 10 may be greater than the distance in the vertical direction D1 between a relatively low position in the vertical direction D1 and / or between a component and the bottom surface 10BS of the substrate 10. The lower part or bottom of each component may be closer to the bottom surface 10BS of the substrate 10 in the vertical direction D1 than the upper part or top of that component. Another component above a certain component may be considered relatively far from the bottom surface 10BS of the substrate 10 in the vertical direction D1, while another component below a certain component may be considered relatively close to the bottom surface 10BS of the substrate 10 in the vertical direction D1. It is worth noting that the upper surface of a component described herein may include, but is not limited to, the topmost surface of that component in the vertical direction D1, and the bottom surface of a component may include, but is not limited to, the bottommost surface of that component in the vertical direction D1. Furthermore, the situation described herein where a particular component is positioned between two other objects in a certain direction may include, but is not limited to, the situation where the component is sandwiched between the two objects in that direction.

[0093] It should be noted that each inclined sidewall described herein may include at least a portion of an inverted chamfer structure, thus the width of the object corresponding to this inclined sidewall may gradually and / or continuously decrease from the uppermost to the lowermost end of the inclined sidewall in the vertical direction D1. Furthermore, the width of each object described herein may include, but is not limited to, the width in the horizontal direction D2, and the width of an object in the horizontal direction D2 may also be considered as the length of the object in the horizontal direction D2. For example, the width of the upper electrode 36 may gradually and / or continuously decrease from the uppermost to the lowermost end of the inclined sidewall 36SW in the vertical direction D1. In some embodiments, the upper electrode 36 may further include an arcuate upper surface 36TS, which may convex upward along the vertical direction D1, and the arcuate upper surface 36TS may be directly connected to the inclined sidewall 36SW. Therefore, the width of the arcuate upper surface 36TS can be approximately equal to the width of the upper electrode 36 at the uppermost end of the inclined sidewall 36SW, and the width of the arcuate upper surface 36TS can be greater than the bottom width of the upper electrode 36. Furthermore, the width of the MTJ structure 35 can gradually and / or continuously decrease from the uppermost to the lowermost end of the inclined sidewall 35SW in the vertical direction D1, the upper width of the MTJ structure 35 can be less than or approximately equal to the bottom width of the upper electrode 36, and the upper width of the MTJ structure 35 can be greater than the bottom width of the MTJ structure 35. In some embodiments, the MTJ structure 35 may include, but is not limited to, a free layer 28, a barrier layer 30, a reference layer 40, and a capping layer 34 stacked sequentially from bottom to top. The upper width of the MTJ structure 35 can be considered as the length of the upper surface of the capping layer 34 in the horizontal direction D2, and the bottom width of the MTJ structure 35 can be considered as the length of the bottom surface of the free layer 28 in the horizontal direction D2, but is not limited to. Furthermore, the sidewalls of the free layer 28, the barrier layer 30, the reference layer 40, and the capping layer 34 can each be part of the inclined sidewall 35SW, so the free layer 28, the barrier layer 30, the reference layer 40, and the capping layer 34 can each have a structure that is wider at the top and narrower at the bottom.

[0094] Due to the influence of the inclined sidewall 36SW of the upper electrode 36 and the inclined sidewall 35SW of the MTJ structure 35, the first portion 40A of the first cover layer 40 covering the inclined sidewall 35SW can be located directly below the inclined sidewall 35SW in the vertical direction D1, while the second portion 40B of the first cover layer 40 covering the inclined sidewall 36SW can be located directly below the inclined sidewall 36SW in the vertical direction D1. Furthermore, the first portion 40A of the first cover layer 40 may include a third inclined sidewall (e.g., inclined sidewall SW1) and an upper surface TS3, and the second portion 40B of the first cover layer 40 may include a fourth inclined sidewall (e.g., inclined sidewall SW2), and the upper surface TS3 can be directly connected to both inclined sidewall SW1 and inclined sidewall SW2. The inclined sidewall SW1 may be substantially parallel to the inclined sidewall 35SW of the MTJ structure 35, and the inclined sidewall SW2 may be substantially parallel to the inclined sidewall 36SW of the upper electrode 36, but is not limited thereto. The inclined sidewall SW1 may be located directly below the upper surface TS3 in the vertical direction D1, and the inclined sidewall SW2 may be located directly above the upper surface TS3 in the vertical direction D1. In some embodiments, the first cover layer 40 covering the upper electrode 36 in the vertical direction D1 may include an upper surface TS4 directly connected to the inclined sidewall SW2, and the upper surface TS4 may include an arcuate upper surface, but is not limited thereto.

[0095] In some embodiments, the memory device 100 may further include a bottom electrode 24 and a spin-orbit torque (SOT) layer (e.g., SOT layer 26) disposed on the substrate 10. An MTJ structure 35 may be disposed on the SOT layer 26 in the vertical direction D1, while the bottom electrode 24 may be disposed below the SOT layer 26 in the vertical direction D1. The SOT layer 26 may include a fifth inclined sidewall (e.g., inclined sidewall 26SW), and the bottom electrode 24 may include a sixth inclined sidewall (e.g., inclined sidewall 24SW). The inclined sidewall 26SW may be located below the first portion 40A of the first capping layer 40 in the vertical direction D1 (e.g., the first portion 40A is directly below in the vertical direction D1), and the inclined sidewall 24SW is located below the SOT layer 26 in the vertical direction D1 (e.g., the SOT layer 26 is directly below in the vertical direction D1). The width of the SOT layer 26 may gradually or / and continuously decrease from the uppermost to the lowermost point of the inclined sidewall 26SW in the vertical direction D1, while the width of the bottom electrode 24 may gradually or / and continuously decrease from the uppermost to the lowermost point of the inclined sidewall 24SW in the vertical direction D1. The upper width of the SOT layer 26 may be greater than the bottom width of the SOT layer 26, the upper width of the bottom electrode 24 may be greater than the bottom width of the bottom electrode 24, the upper width of the SOT layer 26 may be greater than the width of the MTJ structure 35, and the upper width of the bottom electrode 24 may be less than or approximately equal to the bottom width of the SOT layer 26, but is not limited thereto. The first portion 40A of the first capping layer 40 may be sandwiched between the inclined sidewall 35SW and the SOT layer 26 in the upper part of the vertical direction D1, and may also be sandwiched between the inclined sidewall 36SW and the SOT layer 26 in the upper part of the vertical direction D1.

[0096] In some embodiments, the memory device 100 may further include a dielectric layer 12, a dielectric layer 14, a connection structure 16, a stop layer 18, a dielectric layer 20, a second capping layer 44, and an interlayer dielectric layer 46. The dielectric layer 12 is disposed on the substrate 10, the dielectric layer 14 is disposed on the dielectric layer 12, and the connection structure 16 is disposed within the dielectric layer 14. The stop layer 18 may cover the connection structure 16 and the dielectric layer 14, the dielectric layer 20 is disposed on the stop layer 18, and the bottom electrode 24 may be disposed on the dielectric layer 20. In some embodiments, the bottom electrode 24 may be electrically connected to the connection structure 16 via a connection structure (not shown) disposed in the dielectric layer 20 and the stop layer 18. The connection structure 16 and the connection structure disposed in the dielectric layer 20 and the stop layer 18 may be considered as a trench conductor and a via conductor, respectively, but are not limited thereto. In some embodiments, the upper surface TS1 of the dielectric layer 20 located below the bottom electrode 24 in the vertical direction D1 may be higher than the upper surface of other portions of the dielectric layer 20 (e.g., upper surface TS2) in the vertical direction D1. The second capping layer 44 may cover the first capping layer 40, the inclined sidewall 26SW of the SOT layer 26, the inclined sidewall 24SW of the bottom electrode 24, and the inclined sidewall 20SW of the dielectric layer 20 located below the bottom electrode 24 in the vertical direction D1. The interlayer dielectric layer 46 may cover the second capping layer 44 and the upper surface TS2 of the dielectric layer 20. The second capping layer 44 may cover the upper surface TS4, inclined sidewall SW2, upper surface TS3, and inclined sidewall SW1 of the first capping layer 40, and the second capping layer 44 may include, but is not limited to, the inclined sidewall SW3 corresponding to the inclined sidewall SW1, inclined sidewall 26SW, inclined sidewall 24SW, and inclined sidewall 20SW, and the inclined sidewall SW4 corresponding to the inclined sidewall SW2. The inclined sidewall SW3 may be substantially parallel to the inclined sidewalls SW1, 26SW, 24SW, and / or 20SW, while the inclined sidewall SW4 may be substantially parallel to the inclined sidewall SW2, but is not limited thereto. Furthermore, the second cover layer 44 may be partially disposed below the inclined sidewalls SW1, 26SW, 24SW, and 20SW in the vertical direction D1 (for example, partially disposed directly below each of the aforementioned inclined sidewalls in the vertical direction D1).

[0097] In some embodiments, substrate 10 may include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate may include, for example, a silicon substrate, a silicon-germanium semiconductor substrate, or a silicon-on-insulator (SOI) substrate, while the non-semiconductor substrate may include a glass substrate, a plastic substrate, or a ceramic substrate, but is not limited thereto. For example, when substrate 10 includes a semiconductor substrate, multiple field-effect transistors (not shown), dielectric layers covering the field-effect transistors (e.g., dielectric layers 12 and 14), and connection structures 16 electrically connected to the field-effect transistors may be disposed on the semiconductor substrate as needed. The bottom electrode 24 can be electrically connected to a specific transistor through the connection structure 16, but is not limited thereto. In some embodiments, current can be formed in the bottom electrode 24 through two connection structures connected to it (e.g., connection structures disposed in dielectric layer 20 and stop layer 18), and the current passing through SOT layer 26 can form a magnetic moment and magnetization effect that influences the MTJ structure 35. SOT layer 26 may include SOT material, which is a material capable of generating a spin Hall effect and / or having a large spin-orbit coupling strength, used to generate a spin-orbit torque on free layer 28 and change its magnetic torque direction. For example, SOT material may include hafnium (Hf), rhenium (Re), ruthenium (Ru), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), iridium (Ir), palladium (Pd), alloys of the above materials (e.g., IrPt, PtAu, PtPd, BiSb, etc.), compounds of the above materials (e.g., PtS, WTe2, etc.), or other suitable materials (e.g., BiSb, Bi x Se 1-x The free layer 28 and the reference layer 32 may comprise ferromagnetic materials, such as iron, cobalt, nickel, cobalt-iron (CoFe) alloy, cobalt-iron-boron (CoFeB) or other suitable ferromagnetic materials. In some embodiments, the reference layer 32 may form a pinned layer with an antiferromagnetic layer (not shown) to have a fixed magnetic torque direction. The antiferromagnetic layer may comprise antiferromagnetic materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), cobalt / platinum (Co / Pt) composite layers or other suitable antiferromagnetic materials. The barrier layer 30 may comprise an insulating material, such as magnesium oxide (MgO), aluminum oxide or other suitable insulating materials, while the capping layer 34 may comprise ruthenium or other suitable conductive materials.

[0098] In some embodiments, the first capping layer 40 and the second capping layer 44 may include silicon nitride or other suitable masking materials, and the material composition of the first capping layer 40 may be the same as or different from that of the second capping layer 44 as required by design. Dielectric layers 12, 14, and 20 may each include oxide dielectric materials, low dielectric constant dielectric materials (e.g., but not limited to dielectric materials with a dielectric constant below 2.9), or other suitable dielectric materials, while the interlayer dielectric layer 46 may include low dielectric constant dielectric materials or ultra-low dielectric constant (ULK) dielectric materials (e.g., but not limited to dielectric materials with a dielectric constant below 2.7). The connection structure 16 may include a barrier layer and a conductive material disposed on the barrier layer. The barrier layer may include titanium (Ti), titanium nitride, tantalum, tantalum nitride, or other suitable conductive barrier materials, while the conductive material may include tungsten, copper, aluminum, titanium-aluminum alloy, cobalt-tungsten phosphide, or other suitable conductive materials with relatively low resistivity. The stop layer 18 may include a nitrogen-doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or other suitable materials. The bottom electrode 24 may include tantalum, tantalum nitride, platinum, copper, gold, aluminum, or other suitable conductive materials, while the top electrode 36 may include tantalum, tantalum nitride, titanium, titanium nitride, platinum, copper, gold, aluminum, or other suitable conductive materials.

[0099] In some embodiments, the bottom electrode 24, SOT layer 26, MTJ structure 35, and top electrode 36 described above can constitute a memory cell. Multiple memory cells can be disposed on the substrate 10. The MTJ structure 35 with its inclined sidewalls, the top electrode 36, and the corresponding first capping layer 40 with different thicknesses can improve the protection and / or isolation effect of the MTJ structure 35 without increasing the area occupied by each memory cell. Furthermore, the top electrode 36, with its arc-shaped upper surface 36TS and inclined sidewalls 36SW, can have a relatively large contact range, thus improving the process window for the contact structure of the corresponding top electrode 36, thereby increasing the manufacturing yield. The contact structure can also be relatively larger, reducing contact resistance.

[0100] Please see Figures 1 to 10 . Figures 2 to 10 The illustration shows a method for manufacturing a memory device according to an embodiment of the present invention, wherein... Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustratedFigure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 A diagram illustrating the subsequent situation. Figure 7 It is illustrated Figure 6 A diagram illustrating the subsequent situation. Figure 8 It is illustrated Figure 7 A diagram illustrating the subsequent situation. Figure 9 It is illustrated Figure 8 The following is a diagram illustrating the situation, and Figure 10 It is illustrated Figure 9 A schematic diagram of the subsequent situation. In some embodiments, Figure 1 It can be regarded as a drawing Figure 10 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 1 As shown, the fabrication method of this embodiment includes the following steps: A magnetic tunneling junction structure (e.g., MTJ structure 35) and an upper electrode 36 are formed on a substrate 10. The MTJ structure 35 includes a first inclined sidewall (e.g., inclined sidewall 35SW), the upper electrode 36 is located on the MTJ structure 35 in the vertical direction D1, and the upper electrode 36 includes a second inclined sidewall (e.g., inclined sidewall 36SW). A first capping layer 40 is formed to cover the upper electrode 36 and the MTJ structure 35. The first capping layer 40 includes a first portion 40A and a second portion 40B. The first portion 40A covers the inclined sidewall 35SW in the horizontal direction D2, and the portion of the first portion 40A in the vertical direction D1 is located below the inclined sidewall 35SW. The second portion 40B covers the inclined sidewall 36SW in the horizontal direction D2, and the portion of the second portion 40B in the vertical direction D1 is located below the inclined sidewall 36SW. The thickness TK1 of the first portion 40A in the horizontal direction D2 is greater than the thickness TK2 of the second portion 40B in the horizontal direction D2.

[0101] To further explain, the manufacturing method of this embodiment may include, but is not limited to, the following steps. For example... Figure 2As shown, active components (such as the transistors described above), passive components, or other desired circuit structures can be formed on the substrate 10, and the dielectric layer 12, dielectric layer 14, connection structure 16, stop layer 18, and dielectric layer 20 described above can be formed. Then, a conductive material 24M, an SOT material 26M, a ferromagnetic material 28M, a barrier material 30M, a ferromagnetic material 32M, and a masking material 34M can be sequentially formed on the dielectric layer 20. Subsequently, a patterned conductive material 36P can be formed on the masking material 34M. In some embodiments, a conductive material can be formed on the masking material 34M, and a mask layer 38 can be formed on this conductive material. Then, a patterning process, such as but not limited to reactive ion etching (RIE), can be performed on the mask layer 38 and the conductive material using a patterned mask layer (e.g., a patterned photoresist layer, not shown) as a mask, to form the patterned conductive material 36P. The mask layer 38 can be removed or retained on the patterned conductive material 36P after this patterning process, as needed. The mask layer 38 may include an oxide mask material (e.g., silicon oxide) or other suitable mask materials. Then, as... Figure 2 and Figure 3 As shown, an etching process 91 can be performed using patterned conductive material 36P and / or mask layer 38 as a mask to pattern the masking material 34M, ferromagnetic material 32M, barrier material 30M, and ferromagnetic material 28M, thereby forming an MTJ structure 35 on SOT material 26M, including a capping layer 34, a reference layer 32, a barrier layer 30, and a free layer 28. The patterned conductive material 36P can be partially etched by the etching process 91 to become the upper electrode 36 located on the MTJ structure 35. In other words, SOT material 26M can be formed on substrate 10 before the formation of MTJ structure 35, and conductive material 24M can be formed on substrate 10 before the formation of SOT material 26M. SOT material 26M can be formed on conductive material 24M, and MTJ structure 35 and upper electrode 36 can be formed on SOT material 26M. In some embodiments, the etching process 91 may include a tilted ion beam etching (IBE) process or other suitable etching methods to form an MTJ structure 35 with tilted sidewalls 35SW and an upper electrode 36 with tilted sidewalls 36SW. The upper electrode 36 may have an upwardly convex arcuate upper surface 36TS by adjusting the parameters of the etching process 91, thereby improving the sidewall etching efficiency of the IBE process, but this is not a limitation. In some embodiments, the width W22 of the arcuate upper surface 36TS may be greater than the bottom width (e.g., width W21) of the upper electrode 36, and the upper width (e.g., width W12) of the MTJ structure 35 may be greater than the bottom width (e.g., width W11) of the MTJ structure 35.

[0102] like Figures 2 to 4 As shown, after the MTJ structure 35 and the upper electrode 36 are formed, a covering material 40M can be formed to cover the SOT material 26M, the MTJ structure 35, and the upper electrode 36. The covering material 40M can be formed substantially conformally on the upper surface of the SOT material 26M, the inclined sidewall 35SW of the MTJ structure 35, the inclined sidewall 36SW of the upper electrode 36, and the arcuate upper surface 36TS of the upper electrode 36. Then, as... Figure 7 and Figure 8 As shown, an oxide mask layer 42 can be formed on the masking material 40M, and an etching process 93 can be performed on the masking material 40M, the SOT material 26M, and the conductive material 24M using the oxide mask layer 42 as a mask. The masking material 40M can be patterned by the etching process 93 to become the first capping layer 40, the SOT material 26M can be patterned by the etching process 93 to become the SOT layer 26, and the conductive material 24M can be patterned by the etching process 93 to become the bottom electrode 24. In some embodiments, the oxide mask layer 42 may include a recessed sidewall 42SW and an arcuate upper surface 42TS. The arcuate upper surface 42TS may protrude upward along the vertical direction D1 and be directly connected to the recessed sidewall 42SW, and the width W32 of the arcuate upper surface 42TS may be greater than the bottom width (e.g., width W31) of the oxide mask layer 42. Furthermore, the width W31 can also be considered as the length of the portion of the masking material 40M that is in direct contact with the oxide mask layer 42 in the horizontal direction D2, but it is not limited to this. The etching process 93 includes a tilted ion beam etching process or other suitable etching methods to etch the masking material 40M, the SOT material 26M, and the conductive material 24M in accordance with the shape of the oxide mask layer 42 to form a first capping layer 40, an SOT layer 26, and a bottom electrode 24 having the above-mentioned shape characteristics.

[0103] In this invention, the method for forming the oxide mask layer 42 may include, but is not limited to, the following steps. For example... Figure 5 As shown, an oxide material 42M can be formed on the cover material 40M, and a patterned mask layer 80 can be formed on the oxide material 42M. The oxide material 42M can be formed substantially conformally on the cover material 40M, and the patterned mask layer 80 may include a photoresist or other suitable mask material. Then, as... Figure 5 and Figure 6As shown, a wet etching process 92 is performed on oxide material 42M using a patterned mask layer 80 as a mask. The oxide material 42M can be patterned by the wet etching process 92 to become oxide mask layer 42. Oxide material 42M may include tetraethoxysilane (TEOS) oxide or other suitable oxides. The patterned mask layer 80 can be removed after the wet etching process 92, which may include a buffer oxide etchant (BOE) etching process or other wet etching methods with a high etch selectivity for oxide material 42M, in order to reduce the etch damage to mask material 40M caused by the process of forming oxide mask layer 42 and form oxide mask layer 42 with the above-mentioned shape characteristics. An oxide mask layer 42 with the aforementioned recessed sidewalls 42SW can be formed using a wet etching process 92 with isotropic etching characteristics. By controlling the width of the patterned mask layer 80 and combining it with the wet etching process 92, the width W32 of the arcuate upper surface 42TS can be made greater than the bottom width of the oxide mask layer 42. Furthermore, as... Figure 7 and Figure 8 As shown, in order to ensure the patterning effect of the conductive material 24M, the etching process 93 can etch further down to the dielectric layer 20 to form the inclined sidewall 20SW. Therefore, a part of the dielectric layer 20 can be removed by the etching process 93, and the upper surface TS1 of the dielectric layer 20 located below the bottom electrode 24 in the vertical direction D1 can be higher than the upper surface TS2 of other parts of the dielectric layer 20 in the vertical direction D1.

[0104] It is worth noting that, using the above-described fabrication method, the fabrication process for forming the oxide mask layer 42 (e.g., Figure 5 The wet etching process 92 shown reduces etching damage to the masking material 40M, making it easier to control the etching depth in the subsequent etching process 93. Therefore, it eliminates the need to increase the thickness of the dielectric layer 20 to compensate for the etching load, positively impacting the etching condition control in the etching process 93. In contrast, when a dry etching process is used with a patterned photoresist layer and a bottom anti-reflective layer to define the oxide mask layer, it is susceptible to loading effects, resulting in uneven etching loss of the masking material 40M in different areas, thus affecting the etching condition control during the subsequent IBE process. Furthermore, the method for forming the first capping layer 40 in this invention may include, but is not limited to, the above-described methods. Figures 4 to 8 The steps shown can also be adapted to other suitable methods as required by the design, such as... Figure 8 The first capping layer 40, the SOT layer 26, and the bottom electrode 24 are shown in the diagram.

[0105] likeFigure 7 and Figure 8 As shown, using an oxide mask layer 42 with the aforementioned shape characteristics in conjunction with a tilted IBE fabrication process, a first capping layer 40 with tilted sidewalls SW1 and SW2, an SOT layer 26 with tilted sidewalls 26SW, a bottom electrode 24 with tilted sidewalls 24SW, and tilted sidewalls 20SW can be formed. The upper width (e.g., width W52) of the SOT layer 26 can be greater than the bottom width (e.g., width W51) of the SOT layer 26, and the upper width (e.g., width W42) of the bottom electrode 24 can be greater than the bottom width (e.g., width W41) of the bottom electrode 24. Figure 9 and Figure 10 As shown, after the first capping layer 40, SOT layer 26, and bottom electrode 24 are formed, a second capping layer 44 can be formed to cover the inclined sidewalls 26SW of the first capping layer 40, SOT layer 26, bottom electrode 24, and dielectric layer 20. In some embodiments, a masking material 44M can be formed first to cover the first capping layer 40, SOT layer 26, bottom electrode 24, and dielectric layer 20, and an etching-back fabrication process can be performed on the masking material 44M. The masking material 44M can be patterned by this etching-back fabrication process to become the second capping layer 44, but this is not a limitation. In some embodiments, the uppermost part of the upper surface TS4 of the first capping layer 40 may not be covered by the second capping layer 44, but this is not a limitation. Figure 10 and Figure 1 As shown, after the second capping layer 44 is formed, the aforementioned interlayer dielectric layer 46 can be formed, thereby forming... Figure 1 The memory device 100 shown.

[0106] In summary, in the memory device and its manufacturing method of the present invention, the upper electrode having an arcuate upper surface and inclined sidewalls can improve the manufacturing process tolerance and / or electrical connection of the corresponding contact structure. The first capping layer, corresponding to the upper electrode and the inclined sidewalls of the MTJ structure, can have different thickness distributions to improve the protection and / or isolation effect on the MTJ structure. Furthermore, a wet etching process with high etching selectivity can be used to define the oxide mask layer, thereby reducing etching damage to the masking material and improving the process control of subsequent etching processes used to define the first capping layer, the SOT layer, and the lower electrode, thereby increasing manufacturing yield and / or reducing production costs.

[0107] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A memory device, comprising: a magnetic tunneling junction (MTJ) structure disposed over a substrate, and the MTJ structure comprising a first sloped sidewall; an upper electrode disposed in a vertical direction over the MTJ structure, and the upper electrode comprising a second sloped sidewall; and a first cap layer covering the upper electrode and the MTJ structure, wherein the first cap layer comprises: a first portion covering the first sloped sidewall in a horizontal direction, wherein the first portion is partially below the first sloped sidewall in the vertical direction; and a second portion covering the second sloped sidewall in the horizontal direction, wherein the second portion is partially below the second sloped sidewall in the vertical direction, and a thickness of the first portion in the horizontal direction is greater than a thickness of the second portion in the horizontal direction.

2. The memory device of claim 1, wherein the first portion of the first cap layer comprises a third sloped sidewall and an upper surface, the second portion of the first cap layer comprises a fourth sloped sidewall, and the upper surface is connected to the third sloped sidewall and the fourth sloped sidewall, respectively.

3. The memory device of claim 2, wherein the third sloped sidewall is directly below the upper surface in the vertical direction, and the fourth sloped sidewall is directly above the upper surface in the vertical direction.

4. The memory device of claim 1, wherein the upper electrode further comprises an arc-shaped upper surface connected to the second sloped sidewall, and a width of the arc-shaped upper surface is greater than a bottom width of the upper electrode.

5. The memory device of claim 1, wherein an upper width of the MTJ structure is greater than a bottom width of the MTJ structure.

6. The memory device of claim 1, further comprising: a spin-orbit torque (SOT) layer disposed over the substrate, wherein the MTJ structure is disposed in the vertical direction over the SOT layer, the SOT layer comprises a fifth sloped sidewall, and the fifth sloped sidewall is below the first portion of the first cap layer in the vertical direction.

7. The memory device of claim 6, wherein an upper width of the SOT layer is greater than a bottom width of the SOT layer.

8. The memory device of claim 6, wherein the first portion of the first cap layer is partially sandwiched between the first sloped sidewall and the SOT layer and partially sandwiched between the second sloped sidewall and the SOT layer in the vertical direction.

9. The memory device of claim 6, further comprising: a bottom electrode disposed in the vertical direction below the SOT layer, wherein the bottom electrode comprises a sixth sloped sidewall, and the sixth sloped sidewall is below the SOT layer in the vertical direction; and a second cap layer covering the bottom electrode and the SOT layer, wherein the second cap layer comprises: a third portion covering the sixth sloped sidewall in the horizontal direction, wherein the third portion is partially below the sixth sloped sidewall in the vertical direction; and a fourth portion covering the fifth sloped sidewall in the horizontal direction, wherein the fourth portion is partially below the fifth sloped sidewall in the vertical direction, and a thickness of the third portion in the horizontal direction is greater than a thickness of the fourth portion in the horizontal direction. A second cap layer covers the first cap layer, the fifth inclined sidewall, and the sixth inclined sidewall, wherein the second cap layer is partially disposed under the fifth inclined sidewall and partially disposed under the sixth inclined sidewall in the vertical direction.

10. The memory device of claim 9, wherein an upper portion width of the bottom electrode is greater than a bottom portion width of the bottom electrode.

11. A method for fabricating a memory device, comprising: forming a magnetic tunneling junction (MTJ) structure and an upper electrode over a substrate, wherein the MTJ structure includes a first inclined sidewall, the upper electrode is located on the MTJ structure in a vertical direction, and the upper electrode includes a second inclined sidewall; and forming a first cap layer to cover the upper electrode and the MTJ structure, wherein the first cap layer includes: a first portion covering the first inclined sidewall in a horizontal direction, wherein the first portion is partially disposed under the first inclined sidewall in the vertical direction; and a second portion covering the second inclined sidewall in the horizontal direction, wherein the second portion is partially disposed under the second inclined sidewall in the vertical direction, and a thickness of the first portion in the horizontal direction is greater than a thickness of the second portion in the horizontal direction.

12. The method for fabricating a memory device of claim 11, wherein the first portion of the first cap layer includes a third inclined sidewall and an upper surface, the second portion of the first cap layer includes a fourth inclined sidewall, and the upper surface is connected to the third inclined sidewall and the fourth inclined sidewall, respectively.

13. The method for fabricating a memory device of claim 12, wherein the third inclined sidewall is directly below the upper surface in the vertical direction, and the fourth inclined sidewall is directly above the upper surface in the vertical direction.

14. The method for fabricating a memory device of claim 11, further comprising: forming a spin-orbit torque (SOT) material over the substrate before the MTJ structure is formed, wherein the MTJ structure and the upper electrode are formed on the SOT material, and the method of forming the first cap layer includes: forming a masking material to cover the SOT material, the MTJ structure, and the upper electrode; forming an oxide mask layer on the masking material; and performing an etching fabrication process on the masking material and the SOT material with the oxide mask layer as a mask, wherein the masking material is patterned into the first cap layer by the etching fabrication process, and the SOT material is patterned into a SOT layer by the etching fabrication process.

15. The method for fabricating a memory device of claim 14, wherein the etching fabrication process includes an ion beam etching (IBE) fabrication process. ​ 16. The method of claim 14, wherein the oxide mask layer comprises a recessed sidewall and an arcuate upper surface connected to the recessed sidewall, and a width of the arcuate upper surface is greater than a bottom width of the oxide mask layer.

17. The method of claim 14, wherein forming the oxide mask layer comprises: forming an oxide material on the cover material; forming a patterned mask layer on the oxide material; and performing a wet etch fabrication process on the oxide material masked by the patterned mask layer, wherein the oxide material is patterned by the wet etch fabrication process to form the oxide mask layer.

18. The method of claim 17, wherein the wet etch fabrication process comprises a buffer oxide etchant (BOE) etch fabrication process.

19. The method of claim 14, further comprising: forming a conductive material on the substrate prior to forming the spin orbit torque material, wherein the spin orbit torque material is formed on the conductive material, and the conductive material is patterned by the etch fabrication process to form a bottom electrode; and forming a second cap layer covering the first cap layer, a fifth sloped sidewall of the spin orbit torque layer, and a sixth sloped sidewall of the bottom electrode, wherein the second cap layer is partially under the fifth sloped sidewall and partially under the sixth sloped sidewall in the vertical direction.

20. The method of claim 19, wherein an upper width of the spin orbit torque layer is greater than a bottom width of the spin orbit torque layer, and an upper width of the bottom electrode is greater than a bottom width of the bottom electrode. ​ ​

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