Magnetic memory device

Abstract

Embodiments provide a magnetic memory device that shortens write time. According to an embodiment, a magnetic memory device includes: a conductive layer; a magnetoresistive effect element disposed on the conductive layer and including a first end portion contacting the conductive layer and a second end portion opposite the first end portion; and a control circuit configured to perform a write operation to write data into the magnetoresistive effect element. The write operation includes: causing a current to flow in the conductive layer in a first cycle; and stopping the current in a second period after the first period and applying a negative voltage to the second end portion with respect to the first end portion.

Description

[0001] Cross-reference of related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2024-141996, filed August 23, 2024, and U.S. Patent Application No. 19 / 075664, filed March 10, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to a magnetic memory device. Background Technology

[0004] Magnetic memory devices that use magnetoresistive elements as storage elements are known. Various methods have been proposed for writing data into magnetoresistive elements. Summary of the Invention

[0005] An embodiment provides a magnetic memory device that reduces write time.

[0006] According to one embodiment, a magnetic memory device includes: a conductive layer; a magnetoresistive element disposed on the conductive layer and including a first end portion contacting the conductive layer and a second end portion opposite to the first end portion; and control circuitry configured to perform a write operation to write data into the magnetoresistive element. The write operation includes: causing current to flow in the conductive layer during a first cycle; and stopping the current and applying a negative voltage to the second end portion relative to the first end portion during a second cycle following the first cycle. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of a magnetic storage device according to an embodiment.

[0008] Figure 2 It is a circuit diagram illustrating the circuit configuration of a memory cell array in a magnetic memory device.

[0009] Figure 3 It is a diagrammatic explanation. Figure 2 The diagram shows a cross-sectional view of the magnetoresistive element and its surrounding wiring.

[0010] Figure 4 It is a waveform diagram illustrating the magnetization reversal of the storage layer during a write operation performed by a magnetic memory device.

[0011] Figure 5 It is a circuit diagram illustrating the voltage applied during a write operation performed by a magnetic memory device.

[0012] Figure 6 It is a circuit diagram illustrating the voltage applied during a write operation performed by a magnetic memory device.

[0013] Figure 7 It is a flowchart illustrating the sequence of write operations performed by a magnetic memory device.

[0014] Figure 8 It is a diagram illustrating the VCMA effect that occurs in the storage layer during a write operation performed by a magnetic memory device.

[0015] Figure 9 The diagram illustrates a cross-sectional view of a write operation performed by a magnetic memory device.

[0016] Figure 10 The diagram illustrates a cross-sectional view of a write operation performed by a magnetic memory device.

[0017] Figure 11 This is a waveform diagram illustrating a first example of a write operation performed by a magnetic memory device.

[0018] Figure 12 This is a waveform diagram illustrating a second example of a write operation performed by a magnetic memory device.

[0019] Figure 13 This is a waveform diagram illustrating a third example of a write operation performed by a magnetic memory device.

[0020] Figure 14 This is a waveform diagram illustrating a fourth example of a write operation performed by a magnetic memory device according to a modified scheme.

[0021] Figure 15 This is a waveform diagram illustrating a fifth example of a write operation performed by a magnetic memory device according to a modified scheme. Detailed Implementation

[0022] In the following description, several embodiments will be described with reference to the accompanying drawings. Components having the same function and configuration will be represented by common reference symbols. Furthermore, when distinguishing between multiple components sharing a common reference symbol, an additional symbol is added after the common reference symbol. When it is not particularly necessary to distinguish between multiple components, only the common reference symbol is assigned to the multiple components, and no additional symbol is added. The additional symbols are not limited to subscripts and superscripts, and include, for example, lowercase letter characters added to the end of the reference symbol, symbols, and indices indicating arrays.

[0023] 1. Configuration

[0024] First, the configuration of the magnetic memory device 1 according to an embodiment will be described. For example, the magnetic memory device 1 is a magnetoresistive random access memory (MRAM). The magnetic memory device 1 includes a magnetoresistive effect element as a storage element. The magnetoresistive effect element is a variable resistance element having a magnetoresistive effect generated by a magnetic tunnel junction (MTJ). The magnetoresistive effect element is also referred to as an "MTJ element".

[0025] 1.1 Magnetic storage device

[0026] Figure 1 This is a block diagram illustrating the configuration of the magnetic memory device 1. The magnetic memory device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a writing circuit 14, a reading circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0027] The memory cell array 10 is a storage unit for data in the magnetic memory device 1. The memory cell array 10 includes a plurality of memory cells MC. Each of the plurality of memory cells MC is associated with a set of rows and columns. Memory cells MC located in the same row are connected to the same word line WL, and memory cells MC located in the same column are connected to the same set of first bit lines BL1 and second bit lines BL2.

[0028] Row selection circuit 11 is a circuit used to select rows of memory cell array 10. Row selection circuit 11 is connected to memory cell array 10 via word line WL. The decoding result (i.e., row address) obtained by decoding address ADD is supplied from decoding circuit 13 to row selection circuit 11. Row selection circuit 11 selects the word line WL corresponding to the row based on the decoding result obtained by decoding address ADD. In the following text, word lines WL other than the selected word line WL are referred to as "non-selected word lines WL".

[0029] Column selection circuit 12 is a circuit used to select columns of memory cell array 10. Column selection circuit 12 is connected to memory cell array 10 via first bit line BL1 and second bit line BL2. The decoding result (i.e., column address) obtained by decoding address ADD is supplied from decoding circuit 13 to column selection circuit 12. Column selection circuit 12 selects the first bit line BL1 and second bit line BL2 corresponding to the column based on the decoding result obtained by decoding address ADD. In the following text, the first bit line BL1 other than the selected bit line BL1 and the second bit line BL2 other than the selected bit line BL2 are referred to as "non-selection bit line BL1" and "non-selection bit line BL2", respectively.

[0030] Decoding circuit 13 is a decoder used to decode the address ADD from input / output circuit 17. Decoding circuit 13 supplies a signal indicating the decoding result obtained by decoding the address ADD to row selection circuit 11 and column selection circuit 12. The address ADD includes a column address and a row address.

[0031] The write circuit 14 includes, for example, a write driver (not illustrated). The write circuit 14 writes data into the memory cell MC.

[0032] The read circuit 15 includes, for example, a sense amplifier (not illustrated). The read circuit 15 reads data from the memory cell MC.

[0033] The voltage generation circuit 16 uses a power supply voltage provided from an external source (not shown) to the magnetic storage device 1 to generate voltages for various operations of the memory cell array 10. For example, the voltage generation circuit 16 generates various voltages required when performing a write operation and outputs these voltages to the write circuit 14. Furthermore, for example, the voltage generation circuit 16 generates various voltages required when performing a read operation and outputs these voltages to the read circuit 15.

[0034] Input / output circuit 17 controls communication with the external environment of magnetic memory device 1. Input / output circuit 17 transmits address ADD received from the external environment of magnetic memory device 1 to decoding circuit 13. Input / output circuit 17 transmits command CMD received from the external environment of magnetic memory device 1 to control circuit 18. Input / output circuit 17 performs operations to send and receive various control signals CNT, and control circuit 18 sends the control signals CNT to the external environment of magnetic memory device 1 and receives the control signals CNT from the external environment. Input / output circuit 17 transmits data DAT from the external environment of magnetic memory device 1 to write circuit 14, and outputs data DAT transmitted from read circuit 15 to the external environment of magnetic memory device 1.

[0035] The control circuit 18 includes, for example, a processor, such as a central processing unit (CPU), a read-only memory (ROM), and a random access memory (RAM). The control circuit 18 controls the operation of the row selection circuit 11, column selection circuit 12, decoding circuit 13, writing circuit 14, reading circuit 15, voltage generation circuit 16, and input / output circuit 17 in the magnetic memory device 1 based on the control signal CNT and the command CMD.

[0036] 1.2 Memory Cell Array

[0037] Next, the configuration of the memory cell array of the magnetic memory device 1 will be described.

[0038] Figure 2 This is a circuit diagram illustrating the circuit configuration of a memory cell array. Figure 2 The diagrams illustrate the word line WL, the first bit line BL1, and the second bit line BL2, distinguished by additional symbols containing index numbers (“<>”).

[0039] The memory cell array 10 includes multiple memory cells MC, multiple word lines WL, multiple first bit lines BL1, and multiple second bit lines BL2. Figure 2 In the example illustrated in the diagram, the multiple memory cells MC include (M+1)×(N+1) memory cells MC<0,0>, MC<0,1>, ..., MC<0,N>, MC<1,0>, ... and MC<0,N>.<M,N> , where each of M and N is an integer equal to or greater than 2. Although Figure 2 The example illustration shows the case where each of M and N is an integer equal to or greater than 2, but the embodiment is not limited to this example. M and N can also be 0 or 1. Multiple word lines WL contain (M+1) word lines WL. <0> WL <1> ...and WL <m>Multiple first-bit lines BL1 contain (N+1) first-bit lines BL1. <0> WBL <1> ...and WBL <n>Multiple second bit lines BL2 contain (N+1) second bit lines BL2. <0> RBL <1> ...and RBL <n>.

[0040] Multiple memory cells MC are arranged in a matrix pattern within the memory cell array 10. Each memory cell MC is associated with a group consisting of one of multiple word lines WL and a set of first bit lines BL1 and second bit lines BL2 from a set of multiple first bit lines BL1 and multiple second bit lines BL2. In other words, the memory cell MC<i,j> (0≤i≤M,0≤j≤N) connects to word line WL The first line BL1 <j>and the second line BL2 <j>.

[0041] Memory unit MC<i,j> It is a three-terminal type memory cell that has a connection to the word line WL. The first end is connected to the first line BL1. <j>The second end and connected to the second bit line BL2 <j>The third end. Memory unit MC<i,j> Includes switching element SEL1<i,j> and SEL2<i,j> MTJ magnetoresistive element<i,j> and wiring SOTL<i,j> .

[0042] SOTL cabling<i,j> It includes a first part, a second part, and a third part located between the first and second parts. (SOTL wiring)<i,j> The first part connects to the word line WL SOTL cabling<i,j> The second part connects to the first line BL1 <j>SOTL cabling<i,j> The third part is connected to the second bit line BL2. <j>Switching element SEL1<i,j> Connect to the SOTL cabling<i,j> Part Two and the First Line BL1 <j>Between. Magnetoresistive element MTJ<i,j> Connect to the SOTL cabling<i,j> The third part and the second bit line BL2 <j>Between. Switching component SEL2<i,j> Connected to the magnetoresistive element MTJ<i,j> With the second bit line BL2 <j>between.

[0043] Switching elements SEL1 and SEL2 are two-terminal switching elements. The difference between a two-terminal switching element and a three-terminal switching element, such as a transistor, is that the two-terminal switching element does not include a third terminal. When the voltage applied between the two terminals is less than the threshold voltages Vth1 and Vth2, respectively, switching elements SEL1 and SEL2 are in a "high resistance" state or an "off" state, for example, in a non-conductive state. When the voltage applied between the two terminals is equal to or higher than the threshold voltages Vth1 and Vth2, respectively, switching elements SEL1 and SEL2 switch to a "low resistance" state or an "on" state, for example, switch to a conductive state. More specifically, for example, if the voltage applied to the corresponding memory cell MC is lower than the threshold voltages Vth1 and Vth2, each of the switching elements SEL1 and SEL2 interrupts the current (i.e., becomes "off"), thereby acting as an insulator with a high resistance value. If the voltage applied to the corresponding memory cell MC exceeds the threshold voltages Vth1 and Vth2, each of the switching elements SEL1 and SEL2 allows current to flow (i.e., becomes "on"), thus acting as an insulator with a small resistance value. Regardless of the polarity of the voltage applied between the two terminals (i.e., regardless of the direction of current flow between the two terminals), the switching elements SEL1 and SEL2 switch between allowing current flow or interrupting current flow according to the magnitude of the voltage applied to the corresponding memory cell MC.

[0044] The SOTL (Site Path Transmission) is a current path within a memory cell (MC). For example, when switching element SEL1 is in the "on" state and switching element SEL2 is in the "off" state, the SOTL serves as a current path between word line WL and the first bit line BL1. Furthermore, for example, when switching element SEL1 is in the "off" state and switching element SEL2 is in the "on" state, a portion of the SOTL serves as a current path between word line WL and the second bit line BL2.

[0045] The magnetoresistive element (MTJ) is a variable resistance element. Based on the current whose path is controlled by switching elements SEL1 and SEL2, the magnetoresistive element (MTJ) can switch its resistance value between a low resistance state and a high resistance state. The magnetoresistive element (MTJ) is used as a storage element to store data in a non-volatile manner by changing its resistance state.

[0046] 1.3 Magnetoresistive element and its surrounding wiring

[0047] Next, the configuration of the magnetoresistive element and its surrounding wiring in the magnetic memory device 1 will be described.

[0048] Figure 3 This is a cross-sectional view illustrating the cross-sectional structure of the magnetoresistive element and its surrounding wiring according to an embodiment. (e.g.) Figure 3 The diagram illustrates that the SOTL wiring includes a conductive layer 20. The magnetoresistive element MTJ includes a stacked structure 30. The stacked structure 30 includes a ferromagnetic layer 31, a non-magnetic layer 32, a ferromagnetic layer 33, a non-magnetic layer 34, and a ferromagnetic layer 35.

[0049] In the following text, the stacking direction of the stacked structure 30 is defined as the "Z direction". The plane orthogonal to the Z direction is defined as the "XY plane". The direction in which the conductive layer 20 extends in the XY plane is defined as the "X direction". The direction in the XY plane that intersects with the X direction is defined as the "Y direction".

[0050] First, the configuration of the conductive layer 20 will be described.

[0051] The conductive layer 20 is a conductive film containing a non-magnetic heavy metal. The conductive layer 20 contains at least one element selected from, for example, tantalum (Ta), tungsten (W), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), and manganese (Mn) as the heavy metal. The element contained in the conductive layer 20 may be an oxide. Furthermore, in the case of containing tantalum (Ta) or tungsten (W), the structure of the element is preferably a β structure. In the conductive layer 20, the spin orbital moment (SOT), mainly due to the bulk spin Hall effect, is generated by the current flowing inside the conductive layer 20. In addition, in some cases, a spin effect may occur due to the spin splitter effect. The spin orbital moment acts on the ferromagnetic layer 31.

[0052] Next, the configuration of the stacked structure 30 will be described.

[0053] A ferromagnetic layer 31 is disposed at the center of the upper surface of the conductive layer 20. The ferromagnetic layer 31 is a conductive film with ferromagnetic properties. The ferromagnetic layer 31 is used as a storage layer. The ferromagnetic layer 31 has an easy magnetization axis in a direction perpendicular to the film surface (i.e., the Z direction). The spin-orbit moment generated in the conductive layer 20 acts on the ferromagnetic layer 31. The ferromagnetic layer 31 is configured such that when a predetermined value of spin-orbit moment is applied to it, the magnetization direction of the ferromagnetic layer 31 is reversed.

[0054] Ferromagnetic layer 31 is generally a ferromagnetic layer using at least one element selected from cobalt (Co), iron (Fe), and nickel (Ni). Cobalt-iron (CoFe) alloys, iron (Fe), cobalt-iron-boron (CoFeB), iron-boron (FeB), cobalt-boron (CoB), and cobalt-iron-nickel-boron (CoFeNiB), etc., are typical ferromagnetic layers with perpendicular magnetization. These have a body-centered cubic (bcc) structure. Phosphorus (P) and carbon (C), etc., are mentioned as elements that can replace boron (B). For example, the magnetic material of CoFeB mentioned above generates perpendicular magnetic anisotropy at the interface by contacting with an oxide having a NaCl (001) structure. A typical example is the MgO (001) / CoFeB stacked structure, etc.

[0055] The ferromagnetic layer 31 further contains a noble metal. The ferromagnetic layer 31 contains at least one element selected from, for example, gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os) as the noble metal. Among these elements, platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os) are preferred. From the viewpoint of improving the VCMA effect, which will be described later, iridium (Ir) is most preferred. Preferably, the ferromagnetic layer 31 contains 50 at% or less of the aforementioned noble metal. This is because if the ferromagnetic layer 31 contains more than 50 at% of the aforementioned noble metal, the magnetism of the ferromagnetic layer 31 may be degraded. In other words, in the case where the ferromagnetic layer 31 contains more than 50 at% of the aforementioned noble metal, the saturation magnetization Ms and the magnetic anisotropy energy Ku of the ferromagnetic layer 31 may be greatly reduced. Furthermore, more preferably, the concentration gradient relative to the concentration of the noble metal in the ferromagnetic layer 31 is a concentration gradient with a higher concentration closer to the non-magnetic layer 32. The concentration gradient can be detected by nano-EDX (energy-dispersive X-ray spectroscopy) analysis or nano-EELS (electron energy loss spectroscopy), etc.

[0056] The ferromagnetic layer 31 has the function of generating the VCMA (Voltage-Controlled Magnetic Anisotropy) effect at the interface with the non-magnetic layer 32 described above. The VCMA effect is a phenomenon in which the energy barrier Eb required to magnetize a reversible magnetic material is changed by applying a voltage. Note that although the VCMA effect physically changes the energy barrier Eb, the change in the coercivity Hc of the ferromagnetic layer 31 is measured as a parameter when measuring the VCMA effect. A decrease in coercivity Hc means that the energy barrier Eb has decreased. Noble metals contained in the ferromagnetic layer 31 can increase the VCMA effect.

[0057] A nonmagnetic layer 32 is disposed on the upper surface of the ferromagnetic layer 31. The nonmagnetic layer 32 is an insulating film with nonmagnetic properties. The nonmagnetic layer 32 is used as a tunnel barrier layer. The nonmagnetic layer 32 is disposed between the ferromagnetic layer 31 and the ferromagnetic layer 33, and together with these two ferromagnetic layers, forms a magnetic tunnel junction. Furthermore, when an initial amorphous layer, such as cobalt iron boron (CoFeB), is used as the interface layer of the ferromagnetic layer 31, the nonmagnetic layer 32 serves as a seed material, which becomes a nucleus for growing a crystalline film from the interface with the ferromagnetic layer 31 during the crystallization process of the ferromagnetic layer 31. Similarly, in the case where cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic layer 33, the nonmagnetic layer 32 also serves as a seed material for the ferromagnetic layer 33. Here, the initial amorphous layer is a layer that is in an amorphous state immediately after film formation and is crystallized after annealing. The nonmagnetic layer 32 has a tetragonal or cubic structure, wherein the film surface is oriented in the (001) plane. Magnesium oxide (MgO) can be mentioned as an example of an oxide used for the nonmagnetic layer 32. MgO has a NaCl structure. When MgO is used for the nonmagnetic layer 32, the (001) interface of MgO matches the (001) interface of CoFeB, and crystals are grown by annealing. For this reason, CoFeB becomes a (001) oriented body-centered cubic structure. The nonmagnetic layer 32 can be an oxide other than MgO. In this case, a nonmagnetic layer with a large VCMA coefficient β is ideal, as described below. When the VCMA coefficient β is large, the VCMA effect increases.

[0058] A ferromagnetic layer 33 is disposed on the upper surface of the non-magnetic layer 32. The ferromagnetic layer 33 is a conductive film with ferromagnetic properties. The ferromagnetic layer 33 is used as a reference layer. The ferromagnetic layer 33 has an easy magnetization axis in a direction perpendicular to the film surface (i.e., the Z direction). The magnetization direction of the ferromagnetic layer 33 is fixed. Figure 3 In the example shown, the magnetization direction of the ferromagnetic layer 33 is in the direction from the conductive layer 20 toward the stacked structure 30. Note that the phrase "the magnetization direction is fixed" means that the magnetization direction cannot be changed by a moment large enough to reverse the magnetization direction of the ferromagnetic layer 33. Typically, an interface layer is used for the ferromagnetic layer 33. As the interface layer for the ferromagnetic layer 33, an initial amorphous layer, such as cobalt iron boron (CoFeB), is used. In addition, an auxiliary ferromagnetic layer is disposed in contact with the surface of the cobalt iron boron (CoFeB) layer, which is the surface on the side opposite to the surface of the cobalt iron boron (CoFeB) layer in contact with the magnesium oxide (MgO) layer. The auxiliary ferromagnetic layer comprises at least one alloy film selected, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). The auxiliary ferromagnetic layer is a stacked structure, such as a Co / Pt stacked structure or a Co / Pd stacked structure. The cobalt-iron-boron (CoFeB) layer used as the initial amorphous layer is used by stacking it with the aforementioned CoPt, CoPd, Co / Pt stacked structures, Co / Pd stacked structures, etc. In this case, in the interface layer of the ferromagnetic layer 33, for example, in the aforementioned CoFeB layer, the (001) oriented MgO layer is formed closer to the nonmagnetic layer 32 side than the other layers.

[0059] A non-magnetic layer 34 is disposed on the upper surface of the ferromagnetic layer 33. The non-magnetic layer 34 is a conductive film with non-magnetic properties. The non-magnetic layer 34 serves as a spacer layer. The non-magnetic layer 34 is composed of elements selected, for example, from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), vanadium (V), and chromium (Cr), or alloys thereof. For example, the film thickness of the non-magnetic layer 34 is equal to or less than 2 nm.

[0060] A ferromagnetic layer 35 is disposed on the upper surface of the non-magnetic layer 34. The ferromagnetic layer 35 is a conductive film with ferromagnetic properties. The ferromagnetic layer 35 serves as a displacement-eliminating layer. The ferromagnetic layer 35 has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). The ferromagnetic layer 35 comprises at least one alloy layer selected from, for example, cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). The ferromagnetic layer 35 can be a stacked structure, such as a Co / Pt stacked structure or a Co / Pd stacked structure.

[0061] Ferromagnetic layer 33 and ferromagnetic layer 35 are antiferromagnetically coupled through nonmagnetic layer 34. That is, ferromagnetic layer 33 and ferromagnetic layer 35 are coupled with magnetization directions that are antiparallel to each other. This type of coupling structure between ferromagnetic layer 33, nonmagnetic layer 34, and ferromagnetic layer 35 is called a "synthetic antiferromagnetic (SAF) structure." By having an SAF structure, ferromagnetic layer 35 can counteract the effect of the leakage magnetic field of ferromagnetic layer 33 on the change in the magnetization direction of ferromagnetic layer 31, thereby reducing the substantial leakage magnetic field of ferromagnetic layer 33.

[0062] Depending on whether the magnetization directions of the storage layer and the reference layer are parallel or antiparallel, the magnetoresistive element (MTJ) can operate in either a low-resistance or high-resistance state. Here, the magnetization direction of the storage layer relative to the reference layer is controlled so that write current does not flow through the MTJ. Specifically, a write method utilizing the spin-orbit torque generated by causing current to flow through the SOTL wiring is employed.

[0063] When a certain amount of write current Ic0 flows through the SOTL wiring in the X direction, the relative magnetization directions of the storage layer and the reference layer become parallel. In this parallel state, the resistance of the magnetoresistive element MTJ becomes the lowest value, and the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "P (parallel) state" and is defined, for example, as the state of data "0".

[0064] Furthermore, when the write current Ic1 flows through the SOTL wiring in the opposite direction to the write current Ic0, the relative magnetization directions of the storage layer and the reference layer become antiparallel. In this antiparallel state, the resistance of the magnetoresistive element MTJ becomes its highest value, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (antiparallel) state" and is defined, for example, as the state of data "1".

[0065] Note that the way data "1" and data "0" are defined is not limited to the examples described above. For example, the P state can be defined as data "1" and the AP state can be defined as data "0".

[0066] Viewed in the Z-direction, the magnetoresistive element (MTJ) is elliptical or circular. From the perspective of high-density integration of memory cells (MCs), a circular shape is the preferred shape for the MTJ when viewed in the Z-direction. From the perspective of reducing area and power consumption, the shorter side length of the MTJ in the elliptical shape and the radius of the MTJ in the circular shape are preferably 100 nm or less.

[0067] 1.2 Write Operation

[0068] Next, the write operation performed by the magnetic memory device 1 will be described.

[0069] 1.2.1 SOT cycle and relaxation cycle

[0070] Figure 4 This is a waveform diagram illustrating the magnetization reversal of the storage layer during a write operation performed by the magnetic memory device 1. Figure 4 In the example illustrated in the diagram, where the vertical axis represents the magnetization of the storage layer expressed as a unit vector and the horizontal axis represents time, the time variation of the Z-direction component mz is illustrated by representing the Z-direction component mz.

[0071] In the following text, for ease of description, it is assumed that the state of the Z-direction component mz = 1 indicates that the magnetization direction of the storage layer is the direction towards the reference layer in the Z-direction. Furthermore, it is assumed that the state of the Z-direction component mz = -1 indicates that the magnetization direction of the storage layer is the direction towards the SOTL wiring in the Z-direction. In other words, Figure 4 The diagram illustrates a situation where the magnetization direction of the reference layer is... Figure 3 In the same case, the magnetization direction of the storage layer is reversed, causing the state of the magnetoresistive element MTJ to change from the P state to the AP state through a write operation.

[0072] like Figure 4 The diagram illustrates that write operations primarily consist of a SOT cycle and a relaxation cycle that follows the SOT cycle. Figure 4 In the example, it is assumed that the Z-direction component mz of the magnetization direction of the storage layer is "1" until time T10 is reached. The SOT period starts from time T10.

[0073] The SOT period is the period during which the spin orbital moment is applied to the memory layer. By applying the spin orbital moment to the memory layer, the magnetization direction of the memory layer can be oriented approximately horizontally. Furthermore, when the spin orbital moment is applied to the memory layer, a bias magnetic field Hx in the X direction is also applied to the wiring SOTL. In this way, the Z-direction component mz of the memory layer's magnetization direction can be given a polarity opposite to that of the Z-direction component prior to the SOT period (in...). Figure 4 In the example, the negative Z-direction component). In other words, during the SOT cycle, the magnetization direction of the storage layer, which had a component parallel to the magnetization direction of the reference layer before the write operation, tilts to have a component antiparallel to the magnetization direction of the reference layer.

[0074] Here, during the SOT cycle, a positive VCMA effect is generated relative to the storage layer. In this way, the time D1 required to tilt the Z-direction component mz of the storage layer's magnetization direction from "1" to a negative value close to "0" can be shortened. The positive VCMA effect will be described later.

[0075] Next, the relaxation period begins at time T20. The relaxation period is the period during which the effect of the spin orbital moment on the storage layer ceases and the magnetization direction of the storage layer stabilizes in the Z direction (i.e., the direction parallel or antiparallel to the magnetization direction of the reference layer). As described above, the direction of the easy magnetization axis of the storage layer is the Z direction. Therefore, by ceasing the effect of the spin orbital moment on the storage layer, the magnetization direction of the storage layer, which has been forced to be approximately horizontal by the spin orbital moment, is oriented in the Z direction.

[0076] Here, as described above, as a result of the SOT cycle, the magnetization direction of the storage layer tilts to have a component antiparallel to the magnetization direction of the reference layer. Therefore, during the relaxation cycle, the magnetization direction of the storage layer tends to tilt in a direction antiparallel to the magnetization direction of the reference layer. The relaxation cycle ends when the reversal of the magnetization direction of the storage layer is complete.

[0077] Here, a negative VCMA effect is generated relative to the storage layer during the relaxation period. In this way, the time D2 required to tilt the Z-direction component mz of the storage layer's magnetization direction from a negative value close to "0" to "-1" can be shortened. The negative VCMA effect will be described later.

[0078] Data is written to the magnetoresistive element MTJ through the write operation described above.

[0079] 1.2.2 Applied voltage

[0080] (SOT cycle)

[0081] Figure 5 This is a circuit diagram illustrating the voltage applied during a write operation performed by the magnetic memory device 1. Figure 5 The diagram illustrates how data is written to memory cell MC across multiple memory cells MC.<m,n> In the case of (0 < m < M, 0 < n < N), voltages are applied to various types of wiring during the SOT cycle.

[0082] When data is written to the memory unit MC<m,n> During the SOT cycle, voltage VDD or VSS is applied to word line WL. <m>and the first line BL1 <n>Each of them. If voltage VDD is applied to word line WL <m>Then voltage VSS is applied to the first line BL1 <n>If voltage VSS is applied to word line WL <m>Then the voltage VDD is applied to the first bit line BL1 <n>Voltage V1 (=VDD / 2+Vg1) is applied to the second bit line BL2. <n>Here, Vg1 is a positive real number. A voltage VDD / 2 is applied to the line excluding word line WL. <m>All other word lines WL, except for the first word line BL1 <n>All other first-line BL1 lines and all other lines except the second-line BL2 lines <n>All other second-order lines BL2.

[0083] As a result, in the word line WL <m>With the first line BL1 <n>A potential difference VDD exists between them. In this case, the wiring SOTL...<m,n> With magnetoresistive element MTJ<m,n> The potential in the connection section is VDD / 2. Therefore, in the second bit line BL2 <n>In, relative to SOTL routing<m,n> A positive potential difference Vg1 (>0) appears.

[0084] In addition, in the word line WL <m>Except for the first line BL1 <n>A potential difference VDD / 2 exists between any first line BL1 other than the word line WL. <m>Any word line WL other than the first word line BL1 <n>A potential difference of VDD / 2 exists between them. This applies except for the word line WL. <m>Any word line other than WL and any word line other than the first word line BL1 <n>No potential difference will occur between any of the first bit lines BL1 except for one set of wiring SOTL.<m,n> With the second bit line BL2 <n>In addition, the potential difference between any set of wiring SOTL and the second bit line BL2 is less than |Vg1|.

[0085] Here, voltage VSS is the reference potential. For example, voltage VSS is 0V. A voltage VDD (or potential difference VDD) relative to voltage VSS puts switching elements SEL1 and SEL2 in the "ON" state. A potential difference VDD / 2 puts switching element SEL1 in the "OFF" state. A voltage V1 (or potential difference Vg1) relative to voltage VDD / 2 puts switching element SEL2 in the "ON" state. (Except for a set of wiring SOTL)<m,n> With the second bit line BL2 <n>In addition, the potential difference that occurs between any set of wiring SOTL and the second bit line BL2 will put the switching element SEL2 into the "off" state.

[0086] Therefore, switching element SEL1<m,n> and SEL2<m,n> Enter "On" state. Except for switching component SEL1.<m,n> All switching elements SEL1 except SEL2 are in the "off" state.<m,n> All other switching elements SEL2 are put into the "off" state.

[0087] Therefore, a potential difference Vg1 can be applied to the magnetoresistive element MTJ.<m,n> At the same time, the potential difference VDD is also applied to the wiring SOTL.<m,n> By applying a potential difference VDD to the wiring SOTL, current can be induced to flow in the magnetoresistive element MTJ to change its resistive state. By applying a positive potential difference Vg1 to the magnetoresistive element MTJ, a positive VCMA effect can be induced in the memory layer. Note that current also flows to the magnetoresistive element MTJ as a result of the switching element SEL2 entering the "on" state.<m,n> However, the amount of current is so small as to be negligible.

[0088] In the aforementioned SOT cycle, the memory cell MC<m,n> The state can also be called the "selected state". Memory cell MC<0,n> to MCn<m-1,n> MC<m+1,n> To MC<M,n> MC<m,0> To MC<m,n-1> and MC<m,n+1> To MC<m,N> The state can also be called a "half-selected state". The state of all memory cells (MCs) that are not in the selected state or half-selected state can also be called a "non-selected state".

[0089] (Relaxation cycle)

[0090] Figure 6 This is a circuit diagram illustrating the voltage applied during a write operation performed by the magnetic memory device 1. Figure 6 The diagram illustrates how data is written to memory cell MC across multiple memory cells MC.<m,n> In the case of voltage applied to various types of wiring during the relaxation period.

[0091] When data is written to the memory unit MC<m,n> During the relaxation period, voltage VDD / 2 is applied to all word lines WL, all first bit lines BL1, and all bit lines except the second bit line BL. <n>All other second bit lines BL2 except for VDD / 2 + Vg2. A voltage V2 (=VDD / 2+Vg2) is applied to the second bit lines BL2. Here, Vg2 is a negative real number.

[0092] As a result, all word lines WL and all first line BL1 <n>There will be no potential difference between them. Therefore, except for the second bit line BL2 <n>No potential difference relative to the corresponding SOTL will appear in any of the second bit lines BL2 except for those in the second bit line BL2. <n>In this context, relative to the corresponding routing SOTL<0,n>, ..., SOTL<m,n> and SOTL<M,n> A negative potential difference Vg2 (<0) appears.

[0093] Here, the voltage V2 (or potential difference Vg2) relative to the voltage VDD / 2 puts the switching element SEL2 into the "on" state.

[0094] Therefore, all switching elements SEL1 enter the "off" state. Switching elements SEL2<0,n>, ..., SEL2<m,n> ...and SEL2<M,n> Enter the "On" state. This excludes switching components SEL2<0,n>, ..., SEL2.<m,n> ...and SEL2<M,n> All other switching elements SEL2 are put into the "off" state.

[0095] Therefore, a potential difference Vg2 can be applied to the magnetoresistive element MTJ.<m,n> And without causing SOTL in the wiring<m,n> A potential difference appears in the storage layer. By applying a negative potential difference Vg2 to the magnetoresistive element MTJ, a negative VCMA effect can be induced in the storage layer.

[0096] In the relaxation cycle described above, memory cells MC<0,n>, ...,MC<m,n> ...and MC<M,n> The state of the memory cells (MCs) that are not in a relaxed state is also called the "relaxed state". The state of all memory cells (MCs) that are not in a relaxed state is also called the "non-selected state".

[0097] 1.2.3 Write Operation Sequence

[0098] Figure 7 This is a flowchart illustrating the sequence of write operations performed by magnetic memory device 1.

[0099] The control circuit 18 of the magnetic memory device 1 begins. Figure 7 A series of processes (starting) are involved, for example, after receiving a signal to begin the write operation and the address information of the memory cell MC to be written from an external memory controller (not shown). The following description of the series of processes corresponds to the processes on the memory cell MC to be written.

[0100] First, during the SOT cycle, control circuit 18 causes write current (Ic0 or Ic1) to flow in the wiring SOTL and applies voltage V1 to the selected bit line BL2 (S11). Note that voltage V1 is applied to the selected bit line BL2, resulting in a positive potential difference Vg1 at one end of the magnetoresistive element MTJ relative to the other end connected to the wiring SOTL.

[0101] Next, during the relaxation cycle, control circuit 18 stops the write current and applies voltage V2 to the selected bit line BL2 (S12). Note that voltage V2 is applied to the selected bit line BL2, causing a negative potential difference Vg2 at one end of the magnetoresistive element MTJ relative to the other end connected to the wiring SOTL. Then, control circuit 18 terminates. Figure 7 The series of processes (end).

[0102] 1.2.4 VCMA effect

[0103] Figure 8 This is a diagram illustrating the VCMA effect that occurs in the storage layer during a write operation performed by magnetic memory device 1. Figure 8 In this diagram, the relative angle of the magnetization direction vector between the storage layer and the reference layer (i.e., the magnetization direction of the storage layer relative to the magnetization direction of the reference layer) is represented on the horizontal axis, and the free energy curve of the storage layer is represented on the vertical axis. This illustrates how the free energy curve of the storage layer changes depending on whether the VCMA effect occurs. Specifically, the solid line L0 corresponds to the case where the VCMA effect is absent. The dashed line L1 corresponds to the case where the positive VCMA effect occurs. The alternating long and short dashed lines L2 correspond to the case where the negative VCMA effect occurs.

[0104] like Figure 8 The diagram illustrates that when the magnetization direction of the storage layer is parallel or antiparallel to the magnetization direction of the reference layer, the free energy curve of the storage layer becomes lower. This corresponds to the fact that the magnetoresistive element MTJ is stable in the P-state or AP-state. On the other hand, when the magnetization direction of the storage layer is oriented horizontally, the free energy curve of the storage layer reaches its maximum value. This corresponds to the fact that there is an energy barrier Eb when the state of the magnetoresistive element MTJ changes from the P-state to the AP-state or from the AP-state to the P-state. The energy barrier Eb is also called the perpendicular magnetic anisotropy energy.

[0105] Using the potential difference Vg applied to the magnetoresistive element MTJ, the energy barrier Eb is represented as follows.

[0106] Eb(Vg)=Eb(0)-βVg / t

[0107] In the expression, β represents the VCMA coefficient and is a real number. Furthermore, t represents the thickness of the tunnel barrier layer.

[0108] As illustrated by solid line L0 and dashed line L1, when a positive potential difference Vg1 is applied to the magnetoresistive element MTJ (i.e., the connection portion of the wiring SOTL to the magnetoresistive element MTJ is applied to the second bit line BL2), the energy barrier Eb(Vg1) becomes lower than the energy barrier Eb(0). In this way, the energy required to reverse the magnetization of the memory layer can be reduced, and the reversal of the memory layer's magnetization can be facilitated. In this embodiment, modulating the energy barrier Eb to facilitate the reversal of the memory layer's magnetization is referred to as the "positive VCMA effect".

[0109] On the other hand, as illustrated by the solid line L0 and the alternating long and short dashed lines L2, when a negative potential difference Vg2 is applied to the magnetoresistive element MTJ (i.e., the connection portion of the wiring SOTL to the magnetoresistive element MTJ is applied to the second bit line BL2), the energy barrier Eb(Vg2) becomes higher than the energy barrier Eb(0). In this way, the energy required to reverse the magnetization of the memory layer can be increased, and the reversal of the magnetization of the memory layer can be suppressed. In this embodiment, modulating the energy barrier Eb to suppress the reversal of the magnetization of the memory layer is called the "negative VCMA effect".

[0110] 1.2.5 Magnetization Reversal

[0111] Figure 9 and 10 This is a cross-sectional view illustrating a write operation performed by magnetic memory device 1. Figure 9 and 10 In section (A), a schematic diagram illustrates the change in the current flowing in the memory cell MC in the selected state during the SOT cycle and the magnetization direction of the magnetoresistive element MTJ. Figure 9 and 10 In part (B), a schematic diagram illustrates the change in magnetization direction of the magnetoresistive element MTJ in a relaxed state during the relaxation period. Figure 9 This corresponds to the write operation when the data "1" is written. Figure 10 This corresponds to the write operation when the data "0" is written.

[0112] First, refer to Figure 9 Describes the write operation used to write the data "1". Figure 9 In the example, the diagram illustrates the flow of write current Ic1 from word line WL (i.e., the right side of the diagram) toward first bit line BL1 (i.e., the left side of the diagram).

[0113] like Figure 9 As illustrated in section (A), during the SOT cycle, the potential difference VDD that puts the switching element SEL1 in the "on" state appears between the two ends of the wiring SOTL. By controlling the potential difference VDD, the write current Ic1 flows in the wiring SOTL. As a result of the write current Ic1 flowing in the wiring SOTL, a spin orbital moment is generated that attempts to tilt the magnetization direction of the memory layer to the horizontal direction. The spin orbital moment acts on the memory layer closest to the wiring SOTL. Furthermore, although Figure 9 Although not illustrated, a bias magnetic field Hx in the X direction is applied to the storage layer.

[0114] Therefore, through the action of the spin orbital moment and the application of the bias magnetic field Hx, the magnetization direction of the storage layer is tilted in a direction that is approximately horizontal, and has a component that is antiparallel to the magnetization direction of the reference layer.

[0115] Furthermore, a potential difference Vg1 appears between the two ends of the magnetoresistive element MTJ, causing the reference layer side to become higher than the storage layer side. As a result, a positive VCMA effect occurs, and the energy barrier Eb of the storage layer decreases. Therefore, with the help of the positive VCMA effect, the magnetization direction of the storage layer tilts rapidly.

[0116] Next, as Figure 9 As illustrated in section (B), no potential difference exists between the two ends of the SOTL wiring during the relaxation period. As a result, the write current Ic1 stops, and the spin-orbit moment also ceases. During SOT, the state of the storage layer transitions from the P state to the AP state by exceeding the energy barrier Eb. Therefore, during the relaxation period, the magnetization direction of the storage layer tilts to a more stable state in the AP state (i.e., a state that is completely antiparallel to the magnetization direction relative to the reference layer).

[0117] Furthermore, a potential difference Vg2 appears between the two ends of the magnetoresistive element MTJ, causing the reference layer side to become lower than the storage layer side. As a result, a negative VCMA effect occurs, and the energy barrier Eb of the storage layer increases. Therefore, with the help of the negative VCMA effect, the magnetization direction of the storage layer tilts more rapidly.

[0118] Through the operations described above, the magnetization direction of the storage layer is reversed to an antiparallel direction to the magnetization direction of the reference layer, and the operation to write the data "1" is completed.

[0119] Next, we will refer to Figure 10 The write operation described in [the context of writing data "0"] Figure 10 In the example, the diagram illustrates the flow of write current Ic0 from the first bit line BL1 (i.e., the left side of the diagram) toward the word line WL (i.e., the right side of the diagram).

[0120] like Figure 10 As illustrated in section (A), during the SOT cycle, the potential difference VDD that puts the switching element SEL1 in the "on" state appears between the two ends of the wiring SOTL. By controlling the potential difference VDD, the write current Ic0 flows in the wiring SOTL. As a result of the write current Ic0 flowing in the wiring SOTL, a spin orbital moment is generated that attempts to tilt the magnetization direction of the memory layer to the horizontal direction. The spin orbital moment acts on the memory layer closest to the wiring SOTL. Furthermore, although Figure 10 The diagram is not provided, but a bias magnetic field Hx in the X direction is applied to the storage layer.

[0121] Therefore, through the action of the spin orbital moment and the application of the bias magnetic field Hx, the magnetization direction of the storage layer is tilted in a direction that is approximately horizontal, and has a component parallel to the magnetization direction of the reference layer.

[0122] Furthermore, a potential difference Vg1 appears between the two ends of the magnetoresistive element MTJ, causing the reference layer side to become higher than the storage layer side. As a result, a positive VCMA effect occurs, and the energy barrier Eb of the storage layer decreases. Therefore, with the help of the positive VCMA effect, the magnetization direction of the storage layer tilts rapidly.

[0123] Next, as Figure 10 As illustrated in section (B), no potential difference exists between the two ends of the SOTL wiring during the relaxation period. Consequently, the write current Ic0 stops, and the spin-orbit moment also ceases to act. During the SOT period, the storage layer transitions to the P state by exceeding the energy barrier Eb from the AP state. Therefore, during the relaxation period, the magnetization direction of the storage layer tilts to the more stable state in the P state (i.e., a state that is perfectly parallel to the magnetization direction relative to the reference layer).

[0124] Furthermore, a potential difference Vg2 appears between the two ends of the magnetoresistive element MTJ, causing the reference layer side to become lower than the storage layer side. As a result, a negative VCMA effect occurs, and the energy barrier Eb of the storage layer increases. Therefore, with the help of the negative VCMA effect, the magnetization direction of the storage layer tilts more rapidly.

[0125] Through the operations described above, the magnetization direction of the storage layer is reversed to be parallel to the magnetization direction of the reference layer, and the operation of writing the data "0" is completed.

[0126] 1.2.6 Potential Difference and Application Mode

[0127] Figure 11 This is a waveform diagram illustrating a first example of the potential difference or voltage applied to a magnetoresistive element during a write operation performed by the magnetic memory device 1. Figure 12 This is a waveform diagram illustrating a second example of the potential difference or voltage applied to the magnetoresistive element during a write operation performed by the magnetic memory device 1. Figure 13 This is a waveform diagram illustrating a third example of the potential difference or voltage applied to a magnetoresistive element during a write operation performed by the magnetic memory device 1.

[0128] like Figure 11 The diagram illustrates that, for potential difference Vg1, the application can begin at the start of the SOT cycle and end at the end of the SOT cycle. For potential difference Vg2, the application can begin at the start of the relaxation cycle and end at the end of the relaxation cycle. The absolute values ​​of potential differences Vg1 and Vg2 can be equal or different.

[0129] like Figure 12 The diagram illustrates that, for potential difference Vg1, the application can begin simultaneously with the start of the SOT cycle and end at time T15 (T10 < T15 < T20) during the SOT cycle. For potential difference Vg2, the application can begin simultaneously with the end of the application of potential difference Vg1 (at time T15) and end simultaneously with the end of the relaxation cycle.

[0130] like Figure 13 The diagram illustrates that the application of potential difference Vg1 can begin simultaneously with the start of the SOT cycle. The application of potential difference Vg2 can end simultaneously with the end of the relaxation cycle. Furthermore, the potential difference can continuously change from the start of the application of potential difference Vg1 until the application of potential difference Vg2 ends.

[0131] 1.3 Effect

[0132] In the magnetic memory device 1 described above, a writing method utilizing spin-orbit moments is employed. In this case, after the magnetization direction of the storage layer tilts horizontally during the SOT cycle, the magnetization direction is completely reversed during the relaxation cycle. Specifically, because the change in magnetization direction during the relaxation cycle does not depend on the spin-orbit moments, a long period may be required until the magnetization direction reverses.

[0133] During the write operation, the write circuit 14 causes the write current to flow through the wiring SOTL during the SOT cycle. Furthermore, during the relaxation cycle, the write circuit 14 stops the write current and applies a negative potential difference Vg2 to one end of the wiring SOTL relative to the other end connected to the magnetoresistive element MTJ. In this way, the energy barrier Eb of the memory layer can be significantly increased during the relaxation cycle. Therefore, the magnetization direction of the horizontally tilted memory layer can be rapidly reversed during the SOT cycle. This reduces the write time.

[0134] Furthermore, the magnetization direction fluctuates under the influence of thermal perturbations. In some cases, such thermal perturbations can cause the magnetization direction of a horizontally tilted memory layer during the SOT cycle to return to its original direction. According to an embodiment, the energy barrier Eb of the memory layer can increase significantly during the relaxation cycle. Therefore, it is difficult for the horizontally tilted magnetization direction of the memory layer to return to its original direction. Thus, write errors can be reduced.

[0135] 2. Revised Plan

[0136] The foregoing embodiments are merely examples and can be modified in various ways.

[0137] Although in the foregoing embodiment, a potential difference Vg1 is applied to the magnetoresistive element MTJ during the SOT cycle, the embodiment is not limited to this example.

[0138] Figure 14 This is a waveform diagram illustrating a fourth example of the potential difference or voltage applied to a magnetoresistive element during a write operation performed by a magnetic memory device according to a modified scheme. Figure 15 This is a waveform diagram illustrating a fifth example of the potential difference or voltage applied to a magnetoresistive element during a write operation performed by a magnetic memory device according to a modified scheme. Figure 14 and Figure 15 Corresponding to Figure 11 and Figure 12 .

[0139] like Figure 14 and Figure 15 As illustrated in the diagram, the potential difference Vg1 can be approximately equal to "0". Making the potential difference Vg1 equal to "0" includes situations where unexpected noise, such as voltage disturbances or fluctuations occurring during device operation, is applied as voltage. Even in such cases, a shorter relaxation period and suppression of write errors during the relaxation period can be achieved.

[0140] While specific embodiments have been described, those embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel apparatus and methods described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes may be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the invention.

[0141] [Symbol Explanation]

[0142] 1: Magnetic storage device

[0143] 10: Memory cell array

[0144] 11: Row selection circuit

[0145] 12: Column Selection Circuit

[0146] 13: Decoding circuit

[0147] 14: Writing Circuit

[0148] 15: Reading circuit

[0149] 16: Voltage generation circuit

[0150] 17: Input / Output Circuit

[0151] 18: Control Circuit

[0152] 20: Conductive layer

[0153] 30: Stacked structure

[0154] 31, 33, 35: Ferromagnetic layers

[0155] 32, 34: Non-magnetic layers.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / n> < / n> < / m>

Claims

1. A magnetic memory device comprising: a conductive layer; a magnetoresistive element disposed on the conductive layer and including a first end portion contacting the conductive layer and a second end portion opposite the first end portion; and a control circuit configured to perform a write operation to write data into the magnetoresistive element, the write operation including: causing a current to flow in the conductive layer in a first period; and stopping the current and applying a negative voltage to the second end portion relative to the first end portion in a second period after the first period.

2. The magnetic memory device of claim 1, wherein the write operation includes applying a positive voltage to the second end portion relative to the first end portion in the first period.

3. The magnetic memory device of claim 2, wherein the first period includes a first sub-period and a second sub-period after the first sub-period, and the write operation includes applying the negative voltage to the second end portion relative to the first end portion in the second sub-period and the second period. the positive voltage applied to the second end portion continuously changes to the negative voltage within the first period and the second period.

4. The magnetic memory device of claim 2, wherein, 5. The magnetic memory device of claim 1, wherein the write operation includes applying a voltage approximately equal to 0 to the second end portion in the first period.

6. The magnetic memory device of claim 1, wherein the first period has a first sub-period and a second sub-period after the first sub-period, and the write operation includes: applying a voltage approximately equal to 0 to the second end portion in the first sub-period; and applying the negative voltage to the second end portion in the second sub-period and the second period.

7. The magnetic memory device of claim 1, wherein the write operation includes: causing the current to flow in a first direction when writing first data; and causing the current to flow in a second direction anti-parallel to the first direction when writing second data different from the first data.

8. The magnetic memory device of claim 1, wherein the conductive layer includes at least one element selected from the group consisting of tantalum, tungsten, ruthenium, rhodium, palladium, silver, copper, osmium, iridium, platinum, gold, and manganese.

9. The magnetic memory device of claim 1, wherein the magnetoresistive element includes: a first ferromagnetic layer in contact with the conductive layer; a first non-magnetic layer over the first ferromagnetic layer; and a second ferromagnetic layer over the first non-magnetic layer, and the first non-magnetic layer includes magnesium and oxygen.

10. The magnetic memory device of claim 9, wherein the first ferromagnetic layer includes at least one element selected from the group consisting of cobalt, iron, and nickel.

11. The magnetic memory device of claim 10, wherein the first ferromagnetic layer further includes at least one element selected from the group consisting of gold, silver, platinum, palladium, rhodium, iridium, ruthenium, and osmium.

12. The magnetic memory device of claim 9, wherein the magnetoresistive element further includes: ​ a second non-magnetic layer over the second ferromagnetic layer; and a third ferromagnetic layer over the second non-magnetic layer.

13. The magnetic memory device of claim 12, wherein the second non-magnetic layer contains at least one element selected from ruthenium, osmium, rhodium, iridium, vanadium, and chromium.

14. A method for performing a write operation to write data into a magnetic memory device, the magnetic memory device including a conductive layer and a magnetoresistive element disposed over the conductive layer and including a first end portion contacting the conductive layer and a second end portion opposite the first end portion, the method comprising: causing a current to flow in the conductive layer in a first period; and stopping the current and applying a negative voltage to the second end portion relative to the first end portion in a second period after the first period.

15. The method of claim 14, further comprising: applying a positive voltage to the second end portion relative to the first end portion in the first period.

16. The method of claim 15, wherein the first period includes a first sub-period and a second sub-period after the first sub-period, and the method further comprises: applying the negative voltage to the second end portion relative to the first end portion in the second sub-period and the second period.

17. The method of claim 15, wherein the positive voltage applied to the second end portion continuously changes to the negative voltage in the first period and the second period.

18. The method of claim 14, further comprising: applying a voltage approximately equal to 0 to the second end portion in the first period.

19. The method of claim 18, wherein the first period has a first sub-period and a second sub-period after the first sub-period, and the method further comprises: applying a voltage approximately equal to 0 to the second end portion relative to the first end portion in the first sub-period; and applying the negative voltage to the second end portion relative to the first end portion in the second sub-period and the second period.

20. The method of claim 14, further comprising: causing the current to flow in a first direction when writing first data; and causing the current to flow in a second direction anti-parallel to the first direction when writing second data different from the first data.

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