Phase change memory device and method of fabricating same

Abstract

The phase change memory device includes a substrate, a first electrode, a second electrode, a first carbon layer, a second carbon layer, and a phase change memory layer. The first electrode and the second electrode are arranged on the substrate and are separated from each other. The first carbon layer and the second carbon layer are disposed on the substrate and spaced apart from each other. The first carbon layer and the second carbon layer are respectively electrically connected with the first electrode and the second electrode, and are respectively a doped carbon nanotube layer or a doped graphene layer. The phase change storage layer is arranged between the first carbon layer and the second carbon layer. Since the doped carbon layer has high conductivity and high carrier mobility, the phase change memory device can be operated by a lower programming current, and has fast signal response and transmission speed.

Description

Technical Field

[0001] This disclosure relates to a phase change memory device and a method for manufacturing the same. Background Technology

[0002] Recently, phase-change memory (PCM) devices have gained increasing attention due to their advantages, such as low power consumption, fast read / write speeds, high capacity, robustness, ease of embedding in integrated circuits (ICs), and low cost. PCM devices can be used to fabricate non-volatile memories because they store data by switching phase-change memory materials between amorphous and crystalline states. However, PCM devices typically require high programming currents, which limits their applicability. Summary of the Invention

[0003] This disclosure provides a phase-change memory (PCM) device, comprising a substrate, a first electrode, a second electrode, a first carbon layer, a second carbon layer, and a phase-change storage layer. The first and second electrodes are disposed on the substrate and spaced apart from each other. The first and second carbon layers are disposed on the substrate and spaced apart from each other. The first and second carbon layers are electrically connected to the first and second electrodes, respectively, and are respectively doped carbon nanotube layers or doped graphene layers. The phase-change storage layer is disposed between the first and second carbon layers.

[0004] In some embodiments, the phase change storage layer includes GeTe, SbTe, BiTe, SnTe, AsTe, GeSe, SbSe, BiSe, SnSe, AsSe, InSe, InSb, InSbTe, GeSbTe, AgInSbTe, SiGeSb, TeGeSbS, AgSbSe, GeSbMnSn, AgSbTe, AuSbTe, AlSb, CrGeTe, CuGeTe, ScSbTe, VO2, MoO2, V2O3, NbO2, Fe3O4, FeS, Ta2O5, Ti3O5, Ti2O3, LaCoO3, SmNiO3, or combinations thereof.

[0005] In some embodiments, the first carbon layer and the second carbon layer each include a plurality of carbon nanotubes having a length of 10 nm to 90 nm.

[0006] In some embodiments, the thicknesses of the first carbon layer and the second carbon layer are 100 nm to 500 nm, respectively.

[0007] In some embodiments, the first carbon layer includes a plurality of carbon nanotubes extending substantially from the first electrode along a first axial direction, and the second carbon layer includes a plurality of carbon nanotubes extending substantially from the second electrode along a second axial direction.

[0008] In some embodiments, the first carbon layer is in contact with the first electrode, and the second carbon layer is in contact with the second electrode.

[0009] In some implementations, the closest distance between the first carbon layer and the second carbon layer is less than or equal to 100 nm.

[0010] In some embodiments, the dopant concentrations of the first carbon layer and the second carbon layer are 3 at% to 10 at%, respectively.

[0011] In some embodiments, the first carbon layer and the second carbon layer are nitrogen-doped or phosphorus-doped, respectively.

[0012] In some embodiments, the first electrode and the second electrode each include a titanium layer and a metal layer on the titanium layer, wherein the metal layer is a palladium layer, a silver layer or a gold layer.

[0013] This disclosure provides a method for manufacturing a phase change memory device, comprising the following operations: forming a first electrode and a second electrode on a substrate, wherein the first electrode and the second electrode are spaced apart from each other; forming a first carbon layer and a second carbon layer on the substrate, wherein the first carbon layer and the second carbon layer are spaced apart from each other, electrically connected to the first electrode and the second electrode respectively, and respectively being a carbon nanotube layer or a graphene-doped layer; and forming a phase change memory layer between the first carbon layer and the second carbon layer.

[0014] In some embodiments, the formation of the first carbon layer and the second carbon layer is performed by plasma-enhanced chemical vapor deposition (PECVD).

[0015] In some embodiments, forming the first carbon layer and the second carbon layer includes the following operations: forming a first electrode including a first titanium layer and a second electrode including a second titanium layer on a substrate; growing a plurality of carbon nanotubes extending from the first titanium layer to form the first carbon layer; and growing a plurality of carbon nanotubes extending from the second titanium layer to form the second carbon layer.

[0016] In some embodiments, the first carbon layer and the second carbon layer are nitrogen-doped or phosphorus-doped, respectively.

[0017] In some embodiments, forming a phase change storage layer between the first carbon layer and the second carbon layer includes forming a phase change storage layer to cover multiple upper surfaces and multiple side surfaces of the first carbon layer and the second carbon layer.

[0018] In some implementations, the closest distance between the first carbon layer and the second carbon layer is less than or equal to 100 nm. Attached Figure Description

[0019] This disclosure can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings.

[0020] Figure 1 This is a flowchart of a method for manufacturing a phase change memory device according to various embodiments of the present disclosure.

[0021] Figure 2A , Figure 3A and Figure 4A This is a perspective view showing an intermediate stage in the manufacture of a phase change memory device according to various embodiments of this disclosure.

[0022] Figure 2B , Figure 3B and Figure 4B Each phase change memory device is manufactured along the following path during the manufacturing process. Figure 2A , Figure 3A and Figure 4A The cross-sectional view of section line A-A' in the figure.

[0023] Figure 3C yes Figure 3A A top view of a phase change memory device. Detailed Implementation

[0024] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0025] Several embodiments will be disclosed in detail below with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the scope of this disclosure. That is, these practical details are not essential in some embodiments of this disclosure. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simplified schematic manner.

[0026] Phase change memory (PCM) devices typically require large currents to melt the PCM material into an amorphous phase for reset operations, which reduces energy efficiency. This disclosure provides a PCM device and a method for manufacturing the same to overcome this problem. The PCM device uses a doped carbon layer as part of the electrode. Due to the high conductivity and high carrier mobility of the doped carbon layer, the PCM device can operate with a lower programming current and has fast signal response and transmission speed.

[0027] Please see Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C , Figure 4A and Figure 4B . Figure 1 This is a flowchart of a method 100 for manufacturing a phase change memory device according to various embodiments of the present disclosure. Method 100 includes operations 110, 120, and 130. Figure 2A , Figure 3A and Figure 4A This is a perspective view showing an intermediate stage in the manufacture of a phase change memory device according to various embodiments of this disclosure.

[0028] Figure 2B , Figure 3B and Figure 4B Each phase change memory device is manufactured along the following path during the manufacturing process. Figure 2A , Figure 3A and Figure 4A The cross-sectional view of section line A-A' in the figure. Figure 3C yes Figure 3A A top view of the phase change memory device. Operations 110-130 described above will be discussed later. Figures 2A to 4B illustrate.

[0029] Although the methods disclosed herein are illustrated using a series of operations or steps, the order in which these operations or steps are shown should not be construed as a limitation of this disclosure. For example, some operations or steps may be performed in a different order and / or simultaneously with other steps. Furthermore, it is not necessary to perform all illustrated operations, steps, and / or features to achieve the implementation of this disclosure. In addition, each operation or step described herein may comprise several sub-steps or actions.

[0030] In operation 110, such as Figure 2A and Figure 2BAs shown, a first electrode 220 and a second electrode 230 are formed on a substrate 210, wherein the first electrode 220 and the second electrode 230 are spaced apart from each other. In some embodiments, the substrate 210 includes a semiconductor substrate 212 and an insulating layer 214 disposed on the semiconductor substrate 212. In some embodiments, the substrate 210 is a semiconductor-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 212 is formed of commonly used semiconductor materials, such as silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), or similar materials. The semiconductor substrate 212 can be amorphous, polycrystalline, or single-crystal. For example, the semiconductor substrate 212 is a highly doped p-type (p+) silicon substrate. In some embodiments, the insulating layer 214 includes SiO2, Si3N4, or combinations thereof. In some embodiments, the first electrode 220 and the second electrode 230 respectively include W, TiN, Pt, Ti, Ru, Mo, Al, Cu, Ag, Au, or combinations thereof. For example, the first electrode 220 and the second electrode 230 are pure metal blocks. For example, the first electrode 220 and the second electrode 230 each include metal stacks containing different metals. In some embodiments, the first electrode 220 includes a first titanium layer 222 and a metal layer 224 disposed on the first titanium layer 222, wherein the metal layer 224 is a palladium layer, a silver layer, or a gold layer. In some embodiments, the second electrode 230 includes a second titanium layer 232 and a metal layer 234 disposed on the second titanium layer 232, wherein the metal layer 234 is a palladium layer, a silver layer, or a gold layer.

[0031] In operation 120, such as Figure 3A , Figure 3B and Figure 3C As shown, a first carbon layer 310 and a second carbon layer 320 are formed on a substrate 210, wherein the first carbon layer 310 and the second carbon layer 320 are spaced apart from each other and electrically connected to the first electrode 220 and the second electrode 230, respectively, and are respectively doped carbon nanotube layers or doped graphene layers. The first carbon layer 310 and the second carbon layer 320 are separated by a gap G, so they do not contact each other. The first carbon layer 310 and the second carbon layer 320 can be regarded as extensions of the first electrode 220 and the second electrode 230. Therefore, the first electrode 220 and the first carbon layer 310 can be regarded as one electrode, and the second electrode 230 and the second carbon layer 320 can also be regarded as one electrode. In some embodiments, the first carbon layer 310 and the second carbon layer 320 are doped carbon nanotube layers, and each includes a plurality of carbon nanotubes with a length of 10 nm to 90 nm, such as 10, 20, 30, 40, 50, 60, 70, 80 or 90 nm. Therefore, this is beneficial for miniaturization. Figures 3A to 3C The dimensions of the structure shown.

[0032] Please refer to [the original text]. Figure 3A , Figure 3B and Figure 3C In some embodiments, the formation of the first carbon layer 310 and the second carbon layer 320 is performed by plasma-enhanced chemical vapor deposition (PECVD). If the insulating layer 214 is a SiO2 layer, the doped carbon nanotube layer can be easily grown. In some embodiments, the formation of the first carbon layer 310 and the second carbon layer 320 includes the following operations: forming a first electrode 220 including a first titanium layer 222 and a second electrode 230 including a second titanium layer 232 on a substrate 210. Growing a plurality of carbon nanotubes extending from the first titanium layer 222 to form the first carbon layer 310. Growing a plurality of carbon nanotubes extending from the second titanium layer 232 to form the second carbon layer 320. In some embodiments, the first carbon layer 310 includes a plurality of carbon nanotubes extending substantially from the first electrode 220 along a first axial direction A1 toward the second electrode 230, and the second carbon layer 320 includes a plurality of carbon nanotubes extending substantially from the second electrode 230 along a second axial direction A2 toward the first electrode 220. The first axial direction A1 is the long axis direction of the carbon nanotubes in the first carbon layer 310, and the second axial direction A2 is the long axis direction of the carbon nanotubes in the second carbon layer 320. The first axial direction A1 and the second axial direction A2 are substantially parallel. In some embodiments, the first carbon layer 310 is in contact with the first electrode 220, and the second carbon layer 320 is in contact with the second electrode 230. In some embodiments, the first carbon layer 310 is in contact with the first titanium layer 222, and the second carbon layer 320 is in contact with the second titanium layer 232.

[0033] The first carbon layer 310 and the second carbon layer 320 may be doped with N-type or P-type dopants, respectively. Due to the increased carrier concentration, the dopant can effectively accelerate the transport speed of the first carbon layer 310 and the second carbon layer 320. N-type dopants are more effective because electrons move faster than holes. When the first carbon layer 310 and the second carbon layer 320 are doped carbon nanotube layers, the dopant can increase the dispersion of the carbon nanotubes, thereby reducing their aggregation, which can increase the conductivity of the first carbon layer 310 and the second carbon layer 320. It is worth noting that the conductivity of the first carbon layer 310 and the second carbon layer 320 is greater than that of the first electrode 220 and the second electrode 230. The first electrode 220 and the second electrode 230 serve as elements for transmitting electrical signals to other circuits. In some embodiments, the first carbon layer 310 and the second carbon layer 320 are either nitrogen-doped or phosphorus-doped, respectively. In some embodiments, the first carbon layer 310 and the second carbon layer 320 are boron-doped. In some embodiments, the dopant concentrations of the first carbon layer 310 and the second carbon layer 320 are 3 at% to 10 at%, for example, 3, 4, 5, 6, 7, 8, 9, or 10 at%. If the dopant concentrations of the first carbon layer 310 and the second carbon layer 320 are within the above ranges, the first carbon layer 310 and the second carbon layer 320 may have high conductivity to improve the transfer speed of the phase change memory device. If the dopant concentration is higher than 10 at%, the resistance of the first carbon layer 310 and the second carbon layer 320 may increase.

[0034] Please note now. Figure 3B It is worth noting that the first titanium layer 222 helps reduce the contact resistance between the first titanium layer 222 and the first carbon layer 310, while the second titanium layer 232 helps reduce the contact resistance between the second titanium layer 232 and the second carbon layer 320. In some embodiments, the thickness t1 of the first carbon layer 310 and the thickness t2 of the second carbon layer 320 are 100 nm to 500 nm, for example, 100, 150, 200, 250, 300, 350, 400, 450, or 500 nm. If the thicknesses t1 and t2 are within the above ranges, the first carbon layer 310 and the second carbon layer 320 can have high electrical conductivity to improve the transfer speed of the phase change memory device. In some embodiments, the thicknesses t1 and t2 are less than or equal to the thicknesses of the first titanium layer 222 and the second titanium layer 232. Therefore, the first carbon layer 310 does not contact the metal layer 224, and the second carbon layer 320 does not contact the metal layer 234.

[0035] Please see Figure 3CIn some embodiments, the closest distance d1 between the first carbon layer 310 and the second carbon layer 320 is less than or equal to 100 nm, for example, 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100 nm. If the closest distance d1 is within the above range, the phase change memory material (formed in subsequent operations) between the first carbon layer 310 and the second carbon layer 320 can be switched at a small programming current (e.g., 0.5 mA), which is either a set current or a reset current. If the closest distance d1 is sufficiently small, the set current and / or reset current can be reduced to, for example, 0.01 mA. The closest distance d1 can be considered as the length of the gap G. In some embodiments, the length of the first carbon layer 310 along the first axial direction A1 is 10 nm to 90 nm, and the length of the second carbon layer 320 along the second axial direction A2 is 10 nm to 90 nm. For example, these lengths are 10, 20, 30, 40, 50, 60, 70, 80, or 90 nm. Therefore, they are advantageous for miniaturization. Figure 3C The dimensions of the structure shown.

[0036] In operation 130, such as Figure 4A and Figure 4B As shown, a phase change storage layer 410 is formed between the first carbon layer 310 and the second carbon layer 320. More specifically, the phase change storage layer 410 fills the gap G between the first carbon layer 310 and the second carbon layer 320. It is worth noting that the first carbon layer 310 and the second carbon layer 320 are separated by the phase change storage layer 410, and a phase change can be initiated by applying an electrical signal to melt the phase change storage layer 410. In some embodiments, forming the phase change storage layer 410 between the first carbon layer 310 and the second carbon layer 320 includes forming the phase change storage layer 410 to cover multiple upper surfaces and multiple side surfaces of the first carbon layer 310 and the second carbon layer 320, as well as multiple upper surfaces and multiple side surfaces of the first electrode 220 and the second electrode 230. In some embodiments, the phase change storage layer 410 includes GeTe, SbTe (e.g., Sb2Te3), BiTe, SnTe, AsTe, GeSe, SbSe, BiSe, SnSe, AsSe, InSe, InSb, InSbTe, GeSbTe (e.g., Ge2Sb2Te5, GST), AgInSbTe, SiGeSb, TeGeSbS, AgSbSe, GeSbMnSn, AgSbTe, AuSbTe, AlSb, CrGeTe (e.g., Cr2Ge2Te6), CuGeTe, ScSbTe, VO2, MoO2, V2O3, NbO2, Fe3O4, FeS, Ta2O5, Ti3O5, Ti2O3, LaCoO3, SmNiO3, or combinations thereof, wherein the elemental proportions of these materials can be arbitrarily adjusted.

[0037] Please refer to [the original text]. Figure 4A and Figure 4B The phase change memory device 400 includes a substrate 210, a first electrode 220, a second electrode 230, a first carbon layer 310, a second carbon layer 320, and a phase change memory layer 410. The first electrode 220 and the second electrode 230 are disposed on the substrate 210 and spaced apart from each other. The first carbon layer 310 and the second carbon layer 320 are disposed on the substrate 210 and spaced apart from each other. The first carbon layer 310 and the second carbon layer 320 are electrically connected to the first electrode 220 and the second electrode 230, respectively, and are respectively doped carbon nanotube layers or doped graphene layers. The phase change memory layer 410 is disposed between the first carbon layer 310 and the second carbon layer 320.

[0038] The phase change memory device 400 can be switched to an on-state or an off-state. When the phase change memory device 400 is in the off-state, the phase change storage layer 410 between the first carbon layer 310 and the second carbon layer 320 is in an amorphous state, corresponding to logic state "0". When the phase change memory device 400 is in the on-state, the phase change storage layer 410 between the first carbon layer 310 and the second carbon layer 320 is in a crystalline state, corresponding to logic state "1", thus allowing current to flow. More specifically, the phase change storage layer 410 can be heated and / or melted by current, thus transforming into a crystalline state with low resistance. If the first carbon layer 310 and the second carbon layer 320 are doped carbon nanotube layers, when a voltage is applied to the phase change memory device 400 to switch it to the on-state, broken carbon nanotubes can be reformed or reconnected. The amorphous state can be switched to the crystalline state by a setting operation (setting pulse), and the crystalline state can be switched back to the amorphous state by a reset operation (reset pulse). In some embodiments, the phase change memory layer 410 is a GST layer, and the first carbon layer 310 and the second carbon layer 320 can be triggered by applying an electrical signal to initiate a GST transition. Since the first carbon layer 310 and the second carbon layer 320 are doped, the set current and / or reset current (programming current) used to switch behavior between crystallization and amorphization can be reduced to, for example, equal to or less than 0.05 mA, which is significantly lower than the programming current required by conventional phase change memory devices (e.g., 0.5 mA). See also... Figure 3C and Figure 4B If the closest distance d1 between the first electrode 220 and the second electrode 230 is small enough, the setting current and / or reset current can be reduced to, for example, 0.01 mA.

[0039] In summary, this disclosure provides a phase change memory device and a method for manufacturing the same. The phase change memory device uses a doped carbon layer as part of the electrode to control the switching between an amorphous and crystalline state. Because the doped carbon layer has high electrical conductivity and high carrier mobility, the phase change memory device can be programmed with a very small current and achieve fast transfer speeds.

[0040] Although this disclosure has been described in considerable detail with reference to some embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0041] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover any modifications and variations falling within the scope of the appended claims.

[0042] [Symbol Explanation]

[0043] 100: Method

[0044] 110, 120, 130: Operation

[0045] 210:Substrate

[0046] 212: Semiconductor substrate

[0047] 214: Insulation layer

[0048] 220: First electrode

[0049] 222: First titanium layer

[0050] 224, 234: Metal layer

[0051] 230: Second electrode

[0052] 232: Second titanium layer

[0053] 310: First carbon layer

[0054] 320: Second carbon layer

[0055] 400: Phase Change Memory Device

[0056] 410: Phase Change Storage Layer

[0057] A-A': Section line

[0058] A1: First axial direction

[0059] A2: Second axial direction

[0060] d1: Closest distance

[0061] G: Gap

[0062] t1, t2: thickness.

Claims

1. A phase change memory device, characterized by, comprising: a substrate; a first electrode and a second electrode disposed on the substrate and spaced apart from each other; a first carbon layer and a second carbon layer disposed on the substrate and spaced apart from each other, wherein the first carbon layer and the second carbon layer are electrically connected to the first electrode and the second electrode, respectively, and are doped nanocarbon tube layer or doped graphene layer, respectively; and a phase change storage layer disposed between the first carbon layer and the second carbon layer.

2. The phase change memory device of claim 1, wherein the phase change storage layer comprises GeTe, SbTe, BiTe, SnTe, AsTe, GeSe, SbSe, BiSe, SnSe, AsSe, InSe, InSb, InSbTe, GeSbTe, AgInSbTe, SiGeSb, TeGeSbS, AgSbSe, GeSbMnSn, AgSbTe, AuSbTe, AlSb, CrGeTe, CuGeTe, ScSbTe, VO2, MoO2, V2O3, NbO2, Fe3O4, FeS, Ta2O5, Ti3O5, Ti2O3, LaCoO3, SmNiO3, or a combination thereof.

3. The phase change memory device of claim 1, wherein the first carbon layer and the second carbon layer each comprise a plurality of nanocarbon tubes having a length of 10 nm to 90 nm.

4. The phase change memory device of claim 1, wherein the first carbon layer and the second carbon layer each have a thickness of 100 nm to 500 nm.

5. The phase change memory device of claim 1, wherein the first carbon layer comprises a plurality of nanocarbon tubes extending substantially along a first axial direction from the first electrode, and the second carbon layer comprises a plurality of nanocarbon tubes extending substantially along a second axial direction from the second electrode.

6. The phase change memory device of claim 1, wherein the first carbon layer is in contact with the first electrode, and the second carbon layer is in contact with the second electrode.

7. The phase change memory device of claim 1, wherein a closest distance between the first carbon layer and the second carbon layer is less than or equal to 100 nm.

8. The phase change memory device of claim 1, wherein a dopant concentration of the first carbon layer and the second carbon layer is 3 at% to 10 at%, respectively.

9. The phase change memory device of claim 1, wherein the first carbon layer and the second carbon layer are each nitrogen-doped or phosphorus-doped.

10. The phase change memory device of claim 1, wherein the first electrode and the second electrode each comprise a titanium layer and a metal layer on the titanium layer, the metal layer being a palladium layer, a silver layer, or a gold layer.

11. A method of fabricating a phase change memory device, characterized by, comprising: forming a first electrode and a second electrode on a substrate, wherein the first electrode and the second electrode are spaced apart from each other; forming first and second carbon layers on the substrate, wherein the first and second carbon layers are spaced apart from each other, are electrically connected to the first and second electrodes, respectively, and are doped nanocarbon tube layers or doped graphene layers, respectively; and forming a phase change storage layer between the first and second carbon layers.

12. The method of claim 11, wherein forming the first and second carbon layers is performed by plasma enhanced chemical vapor deposition.

13. The method of claim 11, wherein forming the first and second carbon layers comprises: forming the first and second electrodes comprising first and second titanium layers on the substrate; growing a plurality of nanocarbon tubes extending from the first titanium layer to form the first carbon layer; and growing a plurality of nanocarbon tubes extending from the second titanium layer to form the second carbon layer.

14. The method of claim 11, wherein the first and second carbon layers are nitrogen-doped or phosphorus-doped, respectively.

15. The method of claim 11, wherein forming the phase change storage layer between the first and second carbon layers comprises forming the phase change storage layer to cover a plurality of upper surfaces and a plurality of side surfaces of the first and second carbon layers.

16. The method of claim 11, wherein a closest distance between the first and second carbon layers is less than or equal to 100 nm.

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