Trench structure for low-noise device isolation and manufacturing method thereof

Abstract

The invention discloses a trench structure for isolating a low-noise device and a manufacturing method of the trench structure. The manufacturing method comprises the following steps of providing a substrate and forming a first shallow trench and a second shallow trench on the substrate; depositing in the first shallow trench and the second shallow trench to form a second oxide layer; etching the middle part of the first shallow trench to form a deep trench which passes through the second oxide layer and extends into the substrate; performing ion implantation at the bottom of the deep trench to form a junction separation region; forming a third oxide layer in the deep trench and filling the deep trench with polycrystalline silicon; and depositing a fourth oxide layer and carrying out polishing and grinding to realize global leveling above the substrate, and then forming a groove structure. By combining a manufacturing process with a standard shallow trench manufacturing process, the formed trench structure not only retains the advantage of high integration density of shallow trench isolation, but also realizes deep noise blocking through deep trench isolation, and has an excellent low-noise isolation characteristic.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a trench structure for isolation of low-noise devices and a method for manufacturing the same. Background Technology

[0002] In the modern semiconductor field, especially in analog / mixed-signal and radio frequency circuits, effective isolation between devices is one of the key factors in ensuring circuit performance. Parasitic effects and substrate noise coupling are the main causes of device performance degradation and decreased signal-to-noise ratio. Therefore, developing efficient and reliable isolation technologies has always been one of the core research topics in semiconductor processes.

[0003] Shallow trench isolation (STI) technology has become the standard isolation technology for deep submicron process nodes, offering advantages such as high integration density and good planarization. However, STI has limited depth, and its main function is to block leakage paths from surface attachments. For substrates and deeply buried layers, further isolation technologies are needed, leading to the development of deep trench isolation (DTI) technology. However, existing deep trench technologies face challenges in etching, filling, planarization, and integration with mainstream STI processes. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a trench structure for the isolation of low-noise devices and a method thereof that can combine the beneficial isolation performance of deep trenches with the standard process of shallow trenches.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a method for manufacturing a trench structure for isolating low-noise devices, comprising the following steps: S100, Provide a substrate and form a first shallow trench and a second shallow trench on the substrate; S200, A second oxide layer is deposited in the first shallow trench and the second shallow trench to form a second oxide layer; S300, A deep trench is etched in the middle of the first shallow trench to form a trench that penetrates the second oxide layer and extends into the substrate; S400, Ion implantation is performed at the bottom of the deep trench to form a junction-separated region; S500: A third oxide layer is formed in the deep trench and filled with polycrystalline silicon; S600 is used to deposit the fourth oxide layer and then polish it to achieve global planarization above the substrate, thus completing the trench structure.

[0006] Furthermore, step S100 includes the following sub-steps: A substrate is provided, on which a first oxide layer is formed, and a silicon nitride layer is deposited on the first oxide layer, wherein the first oxide layer and the silicon nitride layer form a first hard mask; The silicon nitride layer and the first oxide layer are etched using a first type of photomask to obtain a shallow trench window on the first hard mask; The substrate is etched at the shallow trench window to form a shallow trench, the shallow trench including a first shallow trench in the middle of the substrate and a second shallow trench at the edge of the substrate.

[0007] Furthermore, step S300 includes the following sub-steps: Using the bottom of the first shallow trench as a stop layer, the second oxide layer in the first shallow trench is etched using a second type of photomask to form a deep trench window; Using the second oxide layer as a second hard mask, deep silicon etching is performed on the substrate through the deep trench window to form a deep trench. Etch inward along each edge of the second oxide layer to remove a portion of the second oxide layer.

[0008] Furthermore, step S400 includes the following sub-steps: A sacrificial oxide layer is formed on the sidewalls and bottom of the deep trench through a thermal oxidation process; A junction-isolated region is formed at the bottom of the deep trench using an ion implantation process; The sacrificial oxide layer is removed using an etching process.

[0009] Furthermore, step S500 includes the following sub-steps: A third oxide layer is formed on the bottom and sidewalls of the deep trench; A layer of polysilicon is deposited, the polysilicon filling the deep trench; Using the second oxide layer as a stop layer, an etching process is used to etch away the polysilicon outside the deep trench and to etch away the polysilicon above the deep trench.

[0010] Furthermore, the shallow trench has a depth of 3000-5000 angstroms, the second oxide layer has a thickness of 5000-10000 angstroms, the deep trench has a depth of 20000-60000 angstroms, and the third oxide layer has a thickness of 100-300 angstroms.

[0011] Furthermore, step S600 includes the following sub-steps: A fourth oxide layer is deposited on the polycrystalline silicon and the second oxide layer; Using the silicon nitride layer as a stop layer, the second oxide layer and the fourth oxide layer are removed by polishing and grinding; By wet etching to remove the silicon nitride layer, a trench structure including shallow trenches and deep trenches is obtained.

[0012] Furthermore, the unpatterned area of ​​the first type of photomask is used to form shallow trench patterns, and the patterned area of ​​the second type of photomask is used to form deep trench patterns.

[0013] Furthermore, the thickness of the sacrificial oxide layer gradually decreases from top to bottom; The deep trench bottom is implanted with P-type impurities, including B ions and / or BF2 ions, by ion implantation. The implantation dose is 5E13-5E14 / cm2, the B ion implantation energy is 5-40 keV, and the BF2 ion implantation energy is 30-80 keV.

[0014] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a trench structure for isolating low-noise devices, which is manufactured by the aforementioned method for manufacturing trench structures for isolating low-noise devices.

[0015] The trench structure and its manufacturing method for low-noise device isolation of the present invention have at least the following beneficial effects: By combining the manufacturing process with the standard shallow trench manufacturing process, the trench structure formed by the present invention retains the advantages of high integration density of shallow trench isolation, and achieves deep noise blocking through deep trench isolation, thus possessing excellent low-noise isolation characteristics. It is suitable for the isolation requirements of devices such as high-speed SiGe HBT and high-voltage LDMOS, and has a wide range of applications. The process flow is fully compatible with standard shallow trench isolation, which not only reduces process complexity, but also solves the problems of low compatibility between deep trench isolation and shallow trench and void filling in deep trenches, significantly improving process reliability. The deep trench profile, which is wider at the top and narrower at the bottom, reduces filling stress, thereby improving device stability. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0017] Figure 2 The cross-sectional view of the structure is obtained in step S101 of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0018] Figure 3 This is a schematic diagram of the first type photomask and the second type photomask used in one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0019] Figure 4This is a cross-sectional view of the structure obtained in step S103 of one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0020] Figure 5 The cross-sectional view of the structure is obtained in step S200 of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0021] Figure 6 The cross-sectional view of the structure is obtained in step S301 of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0022] Figure 7 The cross-sectional view of the structure obtained in step S302-S303 is shown in one embodiment of the manufacturing method of the trench structure for isolation of low noise devices of the present invention.

[0023] Figure 8 The cross-sectional view of the structure is obtained in step S401 of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0024] Figure 9 The cross-sectional view of the structure obtained in step S402 is shown in one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices of the present invention.

[0025] Figure 10 The cross-sectional view of the structure obtained in step S403 is shown in one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices of the present invention.

[0026] Figure 11 The cross-sectional view of the structure is obtained in step S501 of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0027] Figure 12 The cross-sectional view of the structure obtained in step S502 is shown in one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices of the present invention.

[0028] Figure 13 The cross-sectional view of the structure obtained in step S503 is shown in one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices of the present invention.

[0029] Figure 14 The cross-sectional view of the structure is obtained in step S601 of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0030] Figure 15 This is a cross-sectional view of the structure obtained in step S602 of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention.

[0031] Figure 16This is a cross-sectional view of the structure obtained in step S603 of one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention. The meanings of the labels in the attached diagram are as follows: Active Zone Version Figure 11 1. Deep trench layout 22. Substrate 101. First shallow trench 102. Second shallow trench 103. Deep trench window 104. Deep trench 105. First oxide layer 201. Silicon nitride layer 202. Second oxide layer 301. Sacrificial oxide layer 401. Junction separation region 402. Third oxide layer 501. Polysilicon 502. Fourth oxide layer 601. Detailed Implementation

[0032] The invention will now be further described with reference to the accompanying drawings.

[0033] Please see Figure 1 This is a flowchart of one embodiment of the manufacturing method of the trench structure for isolation of low-noise devices according to the present invention. This embodiment includes the following steps: S100: Provide a substrate 101, and form a first shallow trench 102 and a second shallow trench 103 on the substrate 101. Specifically, this step may include the following sub-steps: S101, please refer to Figure 2 A substrate 101 is provided, on which a first oxide layer 201 is formed, and a silicon nitride layer 202 is deposited on the first oxide layer 201. The first oxide layer 201 and the silicon nitride layer 202 form a first hard mask. Specifically, the first oxide layer 201 is a silicon oxide layer obtained by a thermal oxidation process, and its thickness is preferably 100-200 angstroms. The thickness of the silicon nitride layer 202 is preferably 1000-2500 angstroms. The substrate 101 may be a silicon substrate. As a preferred embodiment, the substrate 101 may be a silicon-on-insulator substrate to form all-dielectric isolation, further reducing the noise of the substrate 101.

[0034] S102. The silicon nitride layer 202 and the first oxide layer 201 are etched using a first type of photomask to obtain a shallow trench window on the first hard mask. (See also...) Figure 3 Active version Figure 11 The marked area is the patterned area of ​​the first type of photomask, i.e., the non-groove isolation area. The non-patterned area of ​​the first type of photomask is used to form shallow groove windows, defining the patterned area of ​​the shallow groove windows.

[0035] S103, please refer to Figure 4The substrate 101 is etched at the shallow trench window to form a shallow trench. Specifically, the depth of the shallow trench is preferably 3000-5000 angstroms, and the shallow trench includes two first shallow trenches 102 in the middle of the substrate 101 and two second shallow trenches 103 at the edge of the substrate 101. The first shallow trenches 102 are used to form a deep trench 105 later.

[0036] S200, please refer to Figure 5 A second oxide layer 301 is deposited in the first shallow trench 102 and the second shallow trench 103. The second oxide layer 301 is preferably formed by high-density plasma deposition equipment, and its thickness is preferably 5000-10000 angstroms. To repair silicon surface damage caused by shallow trench etching, as a preferred embodiment, before depositing the second oxide layer 301, thermal oxidation is performed on the surfaces of the first shallow trench 102 and the second shallow trench 103 to form a thin thermal oxide layer, the thickness of which is preferably 100-200 angstroms.

[0037] S300, a deep trench 105 is formed by etching in the middle of the first shallow trench 102, penetrating the second oxide layer 301 and extending into the substrate 101. Specifically, this step may include the following sub-steps: S301, please refer to Figure 6 Using the bottom of the first shallow trench 102 as a stop layer, a second type of photomask is used to etch the second oxide layer 301 in the first shallow trench 102 to form the deep trench window 104. For details, please refer to... Figure 3 The deep trench pattern 22 marks the patterned area of ​​the second type of photomask, which has a deep trench pattern and can precisely define the position of the deep trench 105. If a thermal oxide layer is formed in step S200, then in this step, when etching the second oxide layer 301 in the first shallow trench 102, the thermal oxide layer will also be etched. The etching width is preferably 0.6-2 μm, and the silicon loss thickness at the bottom of the first shallow trench 102 is 50-200 angstroms. In this embodiment, the silicon at the bottom of the first shallow trench 102 is used as the etching stop layer, which can precisely control the opening position and size of the deep trench window 104, ensuring that the deep trench 105 is located in the exact center of the first shallow trench 102.

[0038] S302, please refer to Figure 7 Using the second oxide layer 301 as a second hard mask, deep silicon etching is performed on the substrate 101 through the deep trench window 104 to form a deep trench 105. Specifically, the depth of the deep trench 105 is preferably 20,000-60,000 angstroms.

[0039] S303, please continue reading Figure 7The second oxide layer 301 is etched inwards along each edge to remove a portion of it. Specifically, this step uses a wet etching process with an HF solution to remove the second oxide layer 301, with the removed layer having a thickness of 500-1500 angstroms. This wet etching process reduces the thickness of the second oxide layer 301, reserving space for the subsequent sealing formation of the top fourth oxide layer 601 after the polysilicon 502 is filled.

[0040] S400, Ion implantation is performed at the bottom of the deep trench 105 to form a junction-separated region 402. Specifically, this step may include the following sub-steps: S401, please refer to Figure 8 A sacrificial oxide layer 401 is formed on the sidewalls and bottom of the deep trench 105 through a thermal oxidation process. Specifically, a low-temperature, low-pressure thermal oxidation method can be used to form a sacrificial oxide layer 401 on the sidewalls and bottom of the deep trench 105. The thickness of the sacrificial oxide layer 401 is preferably 100-1500 angstroms, and the thickness gradually decreases from top to bottom, with the smallest thickness at the bottom. The deep silicon etching in step S302 can cause damage; growing a sacrificial oxide layer 401 can eliminate surface defects.

[0041] S402, please refer to Figure 9 A junction isolation region 402 is formed at the bottom of the deep trench 105 using an ion implantation process. Specifically, the impurity implanted in the ion implantation process is a P-type impurity, which can be either B ions or BF2 ions. The implantation dose is 5E13-5E14 / cm2. When using B ion implantation, the implantation energy is 5-40 keV, and when using BF2 ion implantation, the energy is 30-80 keV. Implanting a P-type impurity at the bottom of the deep trench 105 forms a P+ region under the N-type substrate 101. This P+ region and the N-type region form a reverse-biased PN junction, creating PN junction isolation, which can effectively block noise.

[0042] S403, please refer to Figure 10 The sacrificial oxide layer 401 is removed using an etching process. Specifically, the sacrificial oxide layer 401 is removed using a wet etching process with an HF solution. Defects and impurities are introduced into the sacrificial oxide layer 401 during growth and ion implantation. Removing these defects facilitates the growth of a high-quality isolation oxide layer on a clean silicon surface in the subsequent step S501.

[0043] S500, A third oxide layer 501 is formed within the deep trench 105 and filled with polysilicon 502. Specifically, this step may include the following sub-steps: S501, please refer to Figure 11A third oxide layer 501 is formed on the bottom and sidewalls of the deep trench 105. By growing a third oxide layer 501 on the repaired clean silicon surface, it can serve as the primary insulating medium for the deep trench 105. Specifically, the third oxide layer 501 is formed by thermal oxidation, and its thickness is preferably 100-300 angstroms.

[0044] S502, please refer to Figure 12 A layer of polycrystalline silicon 502 is deposited, which fills the deep trench 105. Specifically, a layer of polycrystalline silicon 502 is deposited using a polycrystalline silicon deposition equipment, and its thickness is preferably 3500-15000 angstroms. Polycrystalline silicon has excellent filling ability, which can effectively avoid the generation of gaps or voids when filling deep trenches.

[0045] S503, please refer to Figure 13 Using the second oxide layer 301 as a stop layer, an etching process is employed to remove the polysilicon 502 outside the deep trench 105, and to remove the polysilicon 502 above the deep trench 105. In a preferred embodiment, when a stop layer signal is detected during the etching of the polysilicon 502, the polysilicon 502 is further etched to a preset thickness, preferably 3000-5000 angstroms. This embodiment etches back the polysilicon 502 in the shallow trench region and above the deep trench 105, intentionally making its top lower than the shallow trench oxide layer to form a groove, creating the necessary conditions for subsequent deposition of the fourth oxide layer 601 to achieve global planarization.

[0046] In step S600, a fourth oxide layer 601 is deposited and polished to achieve global planarization above the substrate 101, completing the trench structure. This global planarization of the chip surface lays the foundation for subsequent device fabrication. This is the final step in transforming the non-planar composite trench structure into a planar surface suitable for subsequent photolithography and thin film deposition. Specifically, this step may include the following sub-steps: S601, please refer to Figure 14 A fourth oxide layer 601 is deposited on the polysilicon 502 and the second oxide layer 301. Specifically, silicon oxide can be deposited using a high-density plasma deposition apparatus to form the fourth oxide layer 601, followed by annealing for densification. The thickness of the fourth oxide layer 601 is preferably 5000-10000 angstroms, the annealing temperature is 1000-1050℃, and the annealing time is 5-20s. By depositing silicon oxide, the groove formed in step S503 can be filled, and the formed fourth oxide layer 601 completely encapsulates the polysilicon 502, providing protection and insulation.

[0047] S602, please refer to Figure 15Using the silicon nitride layer 202 as a stop layer, the second oxide layer 301 and the fourth oxide layer 601 are removed by polishing and grinding. This step uses chemical mechanical polishing to smooth out the uneven areas on the silicon oxide surface. In a preferred embodiment, after the stop layer signal is detected, the silicon nitride layer 202 is further ground to a preset thickness, preferably 100-400 angstroms.

[0048] S603, please refer to Figure 16 The silicon nitride layer 202 is removed by wet etching to obtain a trench structure including shallow trenches and deep trenches 105. Specifically, the silicon nitride layer 202 can be removed by thermal phosphoric acid stripping. Removing the silicon nitride layer 202 exposes the silicon active region, thereby obtaining the trench structure.

[0049] The present invention also discloses a trench structure for isolating low-noise devices. The trench structure for isolating low-noise devices can be manufactured by the manufacturing method of the trench structure for isolating low-noise devices according to any of the above embodiments, including a combination structure of shallow trenches and deep trenches, wherein the deep trenches are located in the shallow trenches.

[0050] This invention combines a manufacturing process with a standard shallow trench manufacturing process, resulting in a trench structure that retains the high integration density advantages of shallow trench isolation while achieving deep noise blocking through deep trench isolation. It possesses excellent low-noise isolation characteristics, making it suitable for the isolation requirements of high-speed SiGe HBTs and high-voltage LDMOS devices, with a wide range of applications. Employing a process flow fully compatible with standard shallow trench isolation not only reduces process complexity but also solves problems such as low compatibility between deep trench isolation and shallow trench isolation, and voids in deep trench filling, significantly improving process reliability. Furthermore, the wide-at-the-top, narrow-at-the-bottom deep trench profile reduces filling stress, enhancing device stability.

[0051] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A method for manufacturing a trench structure for low noise device isolation, characterized by, The method comprises the following steps: S100, providing a substrate and forming a first shallow trench and a second shallow trench on the substrate; S200, depositing a second oxide layer in the first shallow trench and the second shallow trench; S300, etching a middle part of the first shallow trench to form a deep trench penetrating the second oxide layer and extending into the substrate; S400, performing ion implantation on a bottom of the deep trench to form a junction isolation region; S500, forming a third oxide layer in the deep trench and filling the deep trench with polysilicon; S600, depositing a fourth oxide layer and performing polishing and grinding to realize global planarization above the substrate and complete the trench structure.

2. The method of manufacturing a trench structure for low noise device isolation as recited in claim 1, wherein, The step S100 comprises the following sub-steps: providing a substrate, forming a first oxide layer on the substrate, and depositing a silicon nitride layer on the first oxide layer, wherein the first oxide layer and the silicon nitride layer form a first hard mask; etching the silicon nitride layer and the first oxide layer by using a first photomask to obtain a shallow trench window on the first hard mask; etching the substrate at the shallow trench window to form a shallow trench, wherein the shallow trench comprises a first shallow trench in a middle part of the substrate and a second shallow trench at an edge of the substrate.

3. The method of manufacturing a trench structure for low noise device isolation as recited in claim 1, wherein, The step S300 comprises the following sub-steps: taking the bottom of the first shallow trench as a stop layer, etching the second oxide layer in the first shallow trench by using a second photomask to form a deep trench window; taking the second oxide layer as a second hard mask, and performing deep silicon etching on the substrate through the deep trench window to form a deep trench; etching inward along each edge of the second oxide layer to remove part of the second oxide layer.

4. The method of manufacturing a trench structure for low noise device isolation as recited in claim 1, wherein, The step S400 comprises the following sub-steps: forming a sacrificial oxide layer on the sidewall and the bottom of the deep trench by a thermal oxidation process; forming a junction isolation region on the bottom of the deep trench by an ion implantation process; stripping the sacrificial oxide layer by an etching process.

5. The method of manufacturing a trench structure for low noise device isolation as defined in claim 1, wherein, The step S500 comprises the following sub-steps: forming a third oxide layer on the bottom and the sidewall of the deep trench; depositing a layer of polysilicon, wherein the polysilicon fills the deep trench; taking the second oxide layer as a stop layer, and etching and removing the polysilicon outside the deep trench and the polysilicon on the upper part of the deep trench by an etching process.

6. The method of manufacturing a trench structure for low noise device isolation as defined in Claim 5, wherein: The depth of the shallow trench is 3000-5000 angstroms, the thickness of the second oxide layer is 5000-10000 angstroms, the depth of the deep trench is 20000-60000 angstroms, and the thickness of the third oxide layer is 100-300 angstroms.

7. The method of manufacturing a trench structure for low noise device isolation as defined in claim 1, wherein, The step S600 comprises the following sub-steps: depositing a fourth oxide layer on the polysilicon and the second oxide layer; taking the silicon nitride layer as a stop layer, and removing the second oxide layer and the fourth oxide layer by polishing and grinding; stripping the silicon nitride layer by wet etching to obtain a trench structure comprising the shallow trench and the deep trench.

8. The method of manufacturing a trench structure for low noise device isolation as recited in claim 3, wherein, The non-patterned area of the first photomask is used to form a shallow trench pattern, and the patterned area of the second photomask is used to form a deep trench pattern.

9. The method of manufacturing a trench structure for low noise device isolation as defined in Claim 4, wherein: The thickness of the sacrificial oxide layer gradually decreases from top to bottom. The P-type impurities injected at the bottom of the deep trench by the ion implantation process include B ions and / or BF2 ions, with an injection dose of 5E13-5E14 / cm 2 , and a B ion implantation energy of 5-40 KeV and a BF2 ion implantation energy of 30-80 KeV.

10. A trench structure for low noise device isolation, characterized by: The trench structure for low-noise device isolation is manufactured by using the manufacturing method according to any one of claims 1-9.

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