Method of manufacturing semiconductor device and semiconductor device
By introducing an air gap structure into semiconductor devices, the short-circuit and leakage current problems in the semiconductor device manufacturing process are solved using directional self-assembly technology, thereby reducing parasitic capacitance and improving signal transmission speed, making it suitable for high-frequency and high-performance applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-11
- Publication Date
- 2026-03-10
AI Technical Summary
Short circuits and leakage currents between adjacent conductive features are prone to occur during the manufacturing and integration of semiconductor devices, and existing technologies are unable to effectively solve these problems.
An air gap is formed by using directional self-assembly technology. By introducing an air gap structure into a semiconductor device, block copolymer materials are phase-separated after heat treatment to form first and second polymer layers. The second polymer layer is selectively removed to form an air gap, thereby reducing the dielectric constant and parasitic capacitance.
It effectively reduces parasitic capacitance in semiconductor devices, improves signal transmission speed, reduces power consumption, and improves signal integrity, making it particularly suitable for high-frequency, high-performance applications.
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Figure CN121646347A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to semiconductor devices having air gaps and methods of manufacturing the same. BACKGROUND
[0002] Semiconductor devices are essential for many modern applications. As electronic technology advances, semiconductor devices are becoming smaller in size while having more functions and larger amounts of integrated circuits. Due to the miniaturization of semiconductor elements, various types and sizes of semiconductor devices performing different functions are integrated and packaged into a single module. In addition, in order to integrate various types of semiconductor devices together, a large number of manufacturing operations are performed.
[0003] However, the manufacturing and integration of semiconductor devices involve many complex steps and operations. The integration in semiconductor devices is becoming more and more complex. The increase in complexity of semiconductor devices in manufacturing and integration can cause defects, such as short circuits between adjacent conductive features and leakage current. Accordingly, there is a need to continuously improve the manufacturing process of semiconductor devices to address these issues. SUMMARY
[0004] Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, the method comprising: disposing a bit line over a substrate; disposing a first insulating layer over and aside the bit line; disposing a directed self-assembly (DSA) material layer over and aside the first insulating layer; disposing a second insulating layer over the bit line, the first insulating layer, and the DSA material layer and aside the DSA material layer; performing a phase separation operation to layer the DSA material layer into a first polymer layer and a second polymer layer, wherein the first polymer layer contacts the first insulating layer and the second insulating layer and surrounds the second polymer layer; and removing the second polymer layer to form an air gap.
[0005] In some embodiments, each of the first insulating layer and the second insulating layer is a nitride layer.
[0006] In some embodiments, a first affinity between the first polymer layer and the first insulating layer is greater than a second affinity between the second polymer layer and the first insulating layer.
[0007] In some embodiments, the DSA material layer comprises: polystyrene-polydimethylsiloxane (PS-PDMS), polystyrene-polyvinylpyrrolidone (PS-PVP), polystyrene-poly(methyl methacrylate) (PS-PMMA), polystyrene-poly(4-vinylpyridine) (PS-P4VP), or polystyrene-polyethylene glycol (PS-PEG).
[0008] In some embodiments, the phase separation operation includes a heat treatment.
[0009] In some implementations, the first insulating layer includes: polydimethylsiloxane (PDMS), polyvinylpyrrolidone (PVP), polymethyl methacrylate (PMMA), poly(4-vinylpyridine) (P4VP), or polyethylene glycol (PEG).
[0010] In some implementations, the second insulating layer includes: polystyrene (PS).
[0011] In some implementations, removing the second polymer layer to form the air gap includes selective etching.
[0012] In some implementations, removing the second polymer layer to form the air gap includes using a solvent, and the solvent selectively dissolves the second polymer layer.
[0013] In some implementations, the size of the air gap is adjusted via a ratio of a content of a constituent of the first polymer layer to a content of a constituent of the second polymer layer in the layer of directed self-assembly material.
[0014] In some implementations, the first insulating layer and the second insulating layer are the same.
[0015] In some implementations, the method of fabricating a semiconductor device further includes: after disposing the layer of directed self-assembly material and before disposing the second insulating layer, removing a top portion of the first insulating layer and a top portion of the layer of directed self-assembly material.
[0016] In some implementations, after removing the top portion of the first insulating layer and the top portion of the layer of directed self-assembly material, a top surface of the first insulating layer and a top surface of the layer of directed self-assembly material are flush.
[0017] In some implementations, a first etch resistance of the first polymer layer is higher than a second etch resistance of the second polymer layer.
[0018] Some implementations of the disclosure provide a semiconductor device, comprising: a substrate, a bit line, a first insulating layer, a first polymer layer, a second insulating layer, and an air gap. The bit line is disposed above the substrate. The first insulating layer is disposed laterally from the bit line. The first polymer layer is disposed on a side of the first insulating layer, wherein the first polymer layer includes a first side and a second side opposite the first side, and the first side of the first polymer layer is separated from the bit line via the first insulating layer. The second insulating layer is disposed above the first polymer layer, the first insulating layer, and the bit line and on the second side of the first polymer layer. The air gap is surrounded by the first polymer layer.
[0019] In some implementations, in the semiconductor device, each of the first insulating layer and the second insulating layer is a nitride layer.
[0020] In some embodiments, the first polymer comprises a siloxane chain.
[0021] In some embodiments, the first polymer layer comprises: polydimethylsiloxane (PDMS), polyvinylpyrrolidone (PVP), polymethyl methacrylate (PMMA), poly(4-vinylpyridine) (P4VP), or polyethylene glycol (PEG).
[0022] In some implementations, the topmost interface between the air gap and the first insulating layer is below the top surface of the bit line.
[0023] In some embodiments, the top surface of the first insulating layer and the top surface of the first polymer layer are flush. Attached Figure Description
[0024] Several aspects of this disclosure can be described in detail below and in conjunction with the appended... Figure One For best understanding, please read carefully. Note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be increased or decreased arbitrarily for clarity of discussion.
[0025] Figures 1 to 7 Partial cross-sectional views of several intermediate stages in the manufacture of a semiconductor device, according to some embodiments, are illustrated.
[0026] Figure 8 This is a flowchart of a method for manufacturing a semiconductor device according to some implementation methods. Detailed Implementation
[0027] The embodiments described herein will now be explained in detail with reference to the accompanying drawings, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.
[0028] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the accompanying drawings, spatially relative terms such as "below," "below," "lower," "higher," "upper," or similar terms may be used herein. In addition to the directions depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.
[0029] In several embodiments of this disclosure, an air gap is formed within an insulating layer adjacent to the bit lines of a semiconductor device (e.g., a memory device) to reduce parasitic capacitance between multiple bit lines. Existing memory devices typically have a nitride-oxide-nitride (NON) structure near the sides of the bit lines. In several embodiments of this disclosure, an "insulator-air gap-insulator" structure is provided near the sides of the bit lines. By introducing an air gap into the semiconductor device, existing dielectric materials (e.g., silicon dioxide or other high-dielectric-constant dielectric materials) are replaced. The dielectric constant (ε) of air is close to 1, which is significantly lower than the dielectric constant of other materials (e.g., silicon dioxide has a dielectric constant of approximately 3.9). Using an air gap significantly reduces the dielectric constant, thereby reducing parasitic capacitance. Furthermore, the air gap also reduces electric field coupling between the metal layer and the substrate, reducing the formation of parasitic capacitance. This effect is particularly pronounced in structures with multiple metal layers, contributing to reduced signal interference and noise.
[0030] By reducing parasitic capacitance in semiconductor devices, signal transmission speeds can be increased. This is because parasitic capacitance causes delays and energy losses, while air gaps effectively mitigate these problems. Lower parasitic capacitance also increases the switching speed of semiconductor components (e.g., transistors). This means current can be driven more quickly, thus improving overall performance. Therefore, air gaps effectively reduce parasitic capacitance in semiconductor devices, thereby enhancing device performance, reducing power consumption, and improving signal integrity. These advantages are particularly important for high-frequency, high-performance semiconductor applications.
[0031] In several embodiments of this disclosure, air gaps are formed using materials that are directionally self-assembled (DSA). The primary material for DSA is a block copolymer, composed of two or more segments with different chemical properties. These segments undergo phase separation under specific conditions and form patterns. For example, when a block copolymer is exposed to heat or a specific solvent, different segments repel each other, while identical segments spontaneously aggregate to form the desired structure at specific locations. Compared to existing photolithography and etching techniques, DSA can produce finer nanostructures. Since forming narrower, deeper air gaps is difficult, using DSA helps to create finer structures. In some embodiments, the size of the air gap can be adjusted by the proportion of different compounds or components in the DSA material layer.
[0032] See Figures 1 to 7 The cross-sectional views of the intermediate stages of the semiconductor device shown, and in Figure 8 The flowchart in the document.
[0033] In method 200 for manufacturing a semiconductor device, firstly, in step 202, bit lines are formed over a substrate. See also... Figure 1 The semiconductor device 100 includes a substrate 110 and a bit line 120 above the substrate.
[0034] In some embodiments, substrate 110 may be, for example, a semiconductor substrate, or a semiconductor substrate with a structural layer on it. In some embodiments, substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 110 may be a wafer, such as a silicon wafer. In some embodiments, the semiconductor material of substrate 110 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.
[0035] Bit lines 120 are wires used for reading and writing data in semiconductor memories. They are mainly made of metallic materials to ensure fast and reliable data transmission. Bit lines 120 mainly include metallic conductive materials, such as copper, aluminum, tungsten, similar materials, or combinations thereof.
[0036] In step 204 of method 200, a first insulating layer is formed above and to the side of the bit line. See also Figure 2 The first insulating layer 130 is located above and to the side of the bit line 120. In some embodiments, the first insulating layer 130 is conformally deposited above the bit line 120. In some embodiments, the first insulating layer 130 is a nitride layer, such as silicon nitride (Si3N4). In some embodiments, the first insulating layer 130 can be formed via a conformal deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or similar methods.
[0037] In step 206 of method 200, an oriented self-assembling material layer is formed above and to the side of the first insulating layer. See also Figure 3 An oriented self-assembly material layer 140 is formed above and to the side of the first insulating layer 130. In some embodiments, the oriented self-assembly material layer 140 is formed conformally on the first insulating layer 130 by means of coating, such as spin coating, sputtering, dip coating, or other suitable methods.
[0038] In some embodiments, the oriented self-assembled material layer 140 is a block copolymer, such as a diblock copolymer, and the components constituting the block copolymer are immiscible with each other. The block copolymer contains different polymer components, each with different properties, such as differences in functionality, polarity, hydrophilicity, etch resistance, and glass transition temperature (Tg), thereby allowing the different components to be subsequently separated or aligned. One component of the block copolymer can then be selectively removed, while the other component remains in the semiconductor device.
[0039] In some embodiments, the oriented self-assembling material layer 140 comprises components of two different polymers: a first polymer component and a second polymer component. The first polymer component has a high affinity for the first insulating layer 130 and the subsequently formed second insulating layer 150, while the second polymer component has a low affinity for both the first insulating layer 130 and the second insulating layer 150. In some embodiments, the first polymer component can form a structural layer with higher hardness and chemical stability.
[0040] In some embodiments, the first insulating layer 130 and the second insulating layer 150 are nitrides, such as silicon nitride, and the composition of the first polymer is a polymer capable of forming a stable self-assembled layer on the nitride surface. In some embodiments, the block copolymer of the oriented self-assembled material layer 140 includes: polystyrene-polydimethylsiloxane (PS-PDMS), polystyrene-polyvinylpyrrolidone (PS-PVP), polystyrene-polymethyl methacrylate (PS-PMMA), polystyrene-poly(4-vinylpyridine) (PS-P4VP), or polystyrene-polyethylene glycol (PS-PEG).
[0041] In some embodiments, the first insulating layer 130 and the second insulating layer 150 are made of silicon nitride, and the oriented self-assembled material layer 140 is PS-PDMS. In PS-PDMS, the PDMS portion is silicon-rich, which provides better surface compatibility with the nitride. Furthermore, the interfacial interaction between the siloxane structure of PDMS and silicon nitride is strong, which facilitates the formation of stable patterns after subsequent phase separation processes.
[0042] In step 208 of method 200, the top portion of the first insulating layer and the top portion of the oriented self-assembly material layer are removed. See also Figure 4 The top of the first insulating layer 130 and the top of the orientation self-assembled material layer 140 are removed. In some embodiments, after the removal operation, the top surfaces 130T of the first insulating layer 130 and 140T of the orientation self-assembled material layer 140 are flush with each other. In some embodiments, the top surfaces 130T of the first insulating layer 130 and 140T of the orientation self-assembled material layer 140 are flush with the top surface 120T of the bit line 120. In other embodiments, after the removal operation, the top surfaces 130T of the first insulating layer 130 and 140T of the orientation self-assembled material layer 140 may be higher or lower than the top surface 120T of the bit line 120. In some embodiments, the removal operation may be performed via chemical mechanical planarization (CMP). In some embodiments, the removal operation may be performed using etching, such as dry etching or wet etching.
[0043] In step 210 of method 200, a second insulating layer is formed over the bit line, the first insulating layer, and the oriented self-assembly material layer, and on the side of the oriented self-assembly material layer. See also Figure 5 The second insulating layer 150 is disposed above the bit line 120, the first insulating layer 130, and the oriented self-assembly material layer 140, and on the side of the oriented self-assembly material layer 140. In some embodiments, the second insulating layer 150 is conformally deposited on... Figure 4 Above the structure shown. In some embodiments, the second insulating layer 150 may be, for example, a nitride layer, such as silicon nitride (Si3N4). In some embodiments, the first insulating layer 130 and the second insulating layer 150 are made of the same material. In some embodiments, the second insulating layer 150 may be formed via a conformal deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or similar.
[0044] In step 212 of method 200, a phase separation operation is performed to decompose the oriented self-assembled material layer into a first polymer layer and a second polymer layer. See also Figure 6 A phase separation operation is performed to separate the oriented self-assembled material layer 140 into a first polymer layer 160 and a second polymer layer 162.
[0045] In some embodiments, the phase separation operation of the oriented self-assembled material layer 140 is a heat treatment, such as annealing. In some embodiments, annealing is performed by heating the oriented self-assembled material layer above its glass transition temperature (Tg). In some embodiments, the annealing temperature can range from about 100°C to about 450°C. In some embodiments, the annealing duration can range from about 5 minutes to about 1 hour. The heat treatment does not exceed the thermal degradation limit of the block copolymer or the underlying substrate 110. This phase separation of the block copolymer results in self-assembly to form extremely small (e.g., nanoscale) structures. When the oriented self-assembled material layer 140 undergoes heat treatment, components of the first polymer layer having a strong affinity for the first insulating layer 130 and the second insulating layer 150 are assembled on the surfaces of the first insulating layer 130 and the second insulating layer 150.
[0046] In other words, after the phase separation process, the oriented self-assembled material layer 140 is divided into different domains. The first polymer layer 160 is a first domain with a high affinity for the first insulating layer 130 and the second insulating layer 150, while the second polymer layer 162 is a second domain with a low affinity for the first insulating layer 130 and the second insulating layer 150. In some embodiments, the oriented self-assembled material layer 140 is formed into a columnar structure, with the first polymer layer 160 contacting the first insulating layer 130 and the second insulating layer 150 on the outside, and the second polymer layer 162 being enclosed inside by the first polymer layer 160.
[0047] In some embodiments, the first polymer layer 160 is made of polydimethylsiloxane (PDMS), polyvinylpyrrolidone (PVP), polymethyl methacrylate (PMMA), poly(4-vinylpyridine) (P4VP), or polyethylene glycol (PEG), and the second polymer layer 162 is made of polystyrene (PS).
[0048] In step 214 of method 200, the second polymer layer is removed to form an air gap. See also Figure 7 The second polymer layer 162 is selectively removed to form the air gap 170. In some embodiments, etching (e.g., dry etching or wet etching) can be used to selectively remove the second polymer layer. In some embodiments, selective removal can be achieved using an etchant with different etching selectivity for the first polymer layer 160 and the second polymer layer 162, for example, an etchant that etches the second polymer layer 162 but does not etch (or etches less) the first polymer layer 160.
[0049] In some embodiments, solvents exhibiting different solubilities for the first polymer layer 160 and the second polymer layer 162 are used to selectively remove one of these layers. For example, the solvent may dissolve the second polymer layer 162 without dissolving the first polymer layer 160. In some embodiments, the solvents and related operations are selected to avoid affecting the nitrides in the first insulating layer 130. In some embodiments, the oriented self-assembled material layer 140 is PS-PDMS; after phase separation, the first polymer layer 160 is PDMS and the second polymer layer is PS; the solvent used may be xylene, n-hexane, or chloroform to remove the polyethylene layer (PS layer) of the second polymer layer.
[0050] After selectively removing the second polymer layer 162, an air gap 170 is formed, surrounded by the first polymer layer 160. The air gap 170 can achieve nanoscale dimensions by utilizing the self-assembly properties of the block copolymer material. In some embodiments, the air gap 170 may also have a high aspect ratio.
[0051] As in Figure 7 As shown, the formed air gap 170 is located within the first polymer layer 160; in other words, the air gap 170 is surrounded by the first polymer layer 160. An interface exists between the air gap 170 and the first insulating layer 130, wherein the topmost interface 170T is lower than the top surface 120T of the bit line 120. The side of the first polymer layer 160 closest to the bit line 120 is separated from the bit line 120 via the first insulating layer 130 and directly contacts the first insulating layer 130. The other side and top surface 160T of the first polymer layer 160 directly contact the second insulating layer 150. The top surface 130T of the first insulating layer 130 is flush with the top surface 160T of the first polymer layer 160. In some embodiments, the top surface 130T of the first insulating layer 130, the top surface 160T of the first polymer layer 160, and the top surface 120T of the bit line 120 are flush. In some embodiments, the top surface 120T of the bit line 120 may be higher or lower than the top surface 160T of the first polymer layer 160 and the top surface 130T of the first insulating layer 130. In some embodiments, the topmost interface 170T between the air gap 170 and the first insulating layer 130 may be higher than the top surface 120T of the bit line 120.
[0052] In some embodiments, the size of the formed air gap 170 can be adjusted by changing the content ratio of the first polymer and the second polymer in the oriented self-assembly material layer 140. For example, the higher the proportion of the second polymer in the oriented self-assembly material layer, the larger the size of the air gap 170. Conversely, the lower the proportion of the second polymer in the oriented self-assembly material layer, the smaller the size of the air gap 170.
[0053] The air gap provided in several embodiments of this disclosure can reduce the parasitic capacitance between multiple bit lines. By forming the air gap within an insulating layer near the bit lines using oriented self-assembly materials, manufacturing precision and efficiency can be improved. Furthermore, the resulting semiconductor device exhibits better performance characteristics, such as high programming speed and low power consumption during operation.
[0054] The foregoing outlines several features of various embodiments, enabling those skilled in the art to better understand the multiple variations of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for the design or modification of other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.
[0055] [Symbol Explanation] 100: Semiconductor devices 110: Substrate 120: Bit line 120T: Top surface 130: First insulating layer 130T: Top surface 140: Directional self-assembly material layer 140T: Top surface 150: Second insulation layer 160: First polymer layer 162: Second polymer layer 160T: Top surface 170: Air gap 170T: Topmost interface 200: Method 202, 204, 206, 208, 210, 212, 214: Steps.
Claims
1. A method of manufacturing a semiconductor device, characterized by, Comprising: disposing a bit line over a substrate; disposing a first insulating layer over and alongside the bit line; disposing a layer of a directed self-assembly material over and alongside the bit line, the first insulating layer, and the layer of the directed self-assembly material; performing a phase separation operation to delaminate the layer of the directed self-assembly material into a first polymer layer and a second polymer layer, wherein the first polymer layer contacts the first insulating layer and the second insulating layer and surrounds the second polymer layer; and removing the second polymer layer to form an air gap. Each of the first insulating layer and the second insulating layer is a nitride layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein A first affinity between the first polymer layer and the first insulating layer is greater than a second affinity between the second polymer layer and the first insulating layer.
3. The method of manufacturing a semiconductor device according to claim 1, wherein The layer of the directed self-assembly material comprises: a polystyrene- polydimethylsiloxane, a polystyrene-polyvinylpyrrolidone, a polystyrene- polymethylmethacrylate, a polystyrene-poly(4-vinylpyridine), or a polystyrene- polyethylene glycol.
4. The method of manufacturing a semiconductor device according to claim 1, wherein The phase separation operation comprises a thermal treatment.
5. The method of manufacturing a semiconductor device according to claim 1, wherein The first insulating layer comprises: a polydimethylsiloxane, a polyvinylpyrrolidone, a polymethylmethacrylate, a poly(4-vinylpyridine), or a polyethylene glycol.
6. The method of manufacturing a semiconductor device according to claim 1, wherein The second insulating layer comprises: a polystyrene.
7. The method of manufacturing a semiconductor device according to claim 1, wherein Removing the second polymer layer to form the air gap comprises a selective etching.
8. The method of manufacturing a semiconductor device according to Claim 1, wherein Removing the second polymer layer to form the air gap comprises using a solvent, and the solvent selectively dissolves the second polymer layer.
9. The method of manufacturing a semiconductor device according to Claim 1, wherein A size of the air gap is adjusted via a content ratio of a constituent of the first polymer layer to a constituent of the second polymer layer in the layer of the directed self-assembly material.
10. The method of manufacturing a semiconductor device according to Claim 1, wherein The first insulating layer and the second insulating layer are identical.
11. The method of manufacturing a semiconductor device according to Claim 1, wherein Further comprising:
12. The method of manufacturing a semiconductor device according to Claim 1, wherein after disposing the layer of the directed self-assembly material and before disposing the second insulating layer, removing a top portion of the first insulating layer and a top portion of the layer of the directed self-assembly material. after said removing the top portion of the first insulating layer and the top portion of the layer of the directed self-assembly material, a top surface of the first insulating layer and a top surface of the layer of the directed self-assembly material are flush.
13. The method of manufacturing a semiconductor device according to claim 12, wherein A first etch resistance of the first polymer layer is higher than a second etch resistance of the second polymer layer.
14. The method of manufacturing a semiconductor device according to Claim 1, wherein Comprising:
15. A semiconductor device, characterized by comprising: a substrate; a bit line disposed over the substrate; a first insulating layer disposed alongside the bit line; a first polymer layer disposed on a side of the first insulating layer, wherein the first polymer layer includes a first side and a second side opposite the first side, and the first side of the first polymer layer is separated from the bit line via the first insulating layer; a second insulating layer disposed over the first polymer layer, the first insulating layer, and the bit line, and on the second side of the first polymer layer; and an air gap surrounded by the first polymer layer. Each of the first insulating layer and the second insulating layer is a nitride layer. The first polymer layer comprises a siloxane chain.
16. The semiconductor device according to claim 15, wherein The first polymer layer comprises: a polydimethylsiloxane, a polyvinylpyrrolidone, a polymethylmethacrylate, a poly(4-vinylpyridine), or a polyethylene glycol.
17. The semiconductor device according to claim 15, wherein A topmost interface between the air gap and the first insulating layer is lower than a top surface of the bit line.
18. The semiconductor device according to claim 15, wherein 19. The semiconductor device according to claim 15, wherein 20. The semiconductor device according to claim 15, wherein A top surface of the first insulating layer and a top surface of the first polymer layer are flush. A top surface of the first insulating layer and a top surface of the first polymer layer are flush.