Device for calculating logarithm of complex amplitude, signal processing method, device and circuit

Abstract

The invention discloses a device for calculating logarithm of complex amplitude, a signal processing method, a device, an integrated circuit, an electromagnetic wave device and electronic equipment, which are applied to the field of digital signal processing and are used for calculating and outputting by taking the sum of absolute values of a real part and an imaginary part of a complex as input based on a lookup table. Taking the data as an input, and calculating and outputting the data based on the lookup table; ,...; the embodiment of the invention does not need a multiplier, and the hardware area is small. Compared with the prior art, the method has the advantage of higher cost, and can also achieve higher numerical precision when the lookup table is used for calculating the logarithm.

Description

[0001] Cross-reference to related applications This disclosure claims priority to Chinese Patent Application No. 202411287415.1, filed with the China National Intellectual Property Administration on September 13, 2024, entitled “Signal Processing Apparatus, Integrated Circuit, Electromagnetic Wave Device and Terminal Equipment”, the contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, digital signal processing technology, and more specifically, to an apparatus, signal processing method, device, integrated circuit, electromagnetic wave device, and electronic device for calculating the logarithm of a complex amplitude. Background Technology

[0003] In digital signal processing, when it is necessary to compare or accumulate the amplitude of a signal, it is sometimes necessary to calculate the logarithm of the complex amplitude, i.e.: (1) in, It is a complex number. It is a complex amplitude. That is, the logarithm of the complex magnitude.

[0004] When calculating the complex amplitude according to the above formula (1), a multiplier is required. This requires a lot of hardware resources, resulting in higher chip costs and larger area. Summary of the Invention

[0005] One embodiment of this disclosure provides an apparatus for calculating the logarithm of a complex amplitude, comprising: The first computational unit is configured to use the absolute values ​​of the real and imaginary parts of a complex number. and As input, calculate based on lookup table , And output, yes and One of the numbers, yes and Another number in; The second computing unit is configured to... , As input, calculate based on lookup table And output; The first adder is configured to... and As input, calculate and The sum of these values ​​yields the logarithm of the complex magnitude, which is then output. in, , , .

[0006] An embodiment of this disclosure also provides a signal processing method, including: The system samples and processes the received signals to obtain multiple complex data. Calculate the logarithm of the magnitudes of the plurality of complex data values, including: based on the absolute values ​​of the real and imaginary parts of the complex data. and Calculate , , = , = or = , = ;based on , Calculate ,Will Plus That is, the logarithm of the magnitude of the complex data is obtained; The magnitudes of the multiple complex data amplitudes are compared based on the logarithms of the calculated multiple complex data amplitudes, and a specified digital signal processing task is executed according to the magnitudes of the multiple complex data amplitudes. in, , , , , , All calculations are based on lookup tables.

[0007] An embodiment of this disclosure also provides a signal processing apparatus, including a storage circuit and a processing circuit, wherein the processing circuit is configured to implement the signal processing method described in any embodiment of this disclosure.

[0008] One embodiment of this disclosure also provides an integrated circuit, including a radio frequency module, an analog signal processing module, and a digital signal processing module connected in sequence; The radio frequency module is configured to generate and transmit electromagnetic wave signals, and to receive electromagnetic wave signals. The analog signal processing module is configured to down-frequency the received electromagnetic wave signal to obtain an intermediate frequency signal. The digital signal processing module is configured to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal, and to process the digital signal, including the signal processing method described in any embodiment of this disclosure.

[0009] An embodiment of this disclosure also provides an electromagnetic wave device, including: Carrier; The integrated circuit described in any embodiment of this disclosure is disposed on the carrier; The antenna is mounted on the carrier and can be integrated with the integrated circuit as a single device or disposed separately. The integrated circuit is connected to the antenna to transmit and / or receive the electromagnetic wave signal.

[0010] An embodiment of this disclosure also provides an electronic device, including: The equipment itself; and The electromagnetic wave device described in any embodiment of this disclosure is disposed on the device body; The electromagnetic wave device is configured to perform target detection and / or communication to provide reference information for the operation of the device body.

[0011] The above embodiments of this disclosure use two functions l(x) and g(x) The corresponding computational units are cascaded to calculate the logarithm of the complex amplitude. l(x) and g(x) Both methods can be calculated using lookup tables, eliminating the need for multipliers and resulting in a smaller hardware footprint. This offers a significant cost advantage, while using lookup tables to calculate logarithms also achieves high numerical accuracy.

[0012] An embodiment of this disclosure also provides a target detection method applied in an FMCW radar. The method includes: for target complex data, using a sparse lookup table to replace the multiplier to perform logarithmic compression to obtain the amplitude value of the target complex data, so as to perform constant false alarm detection to obtain target information; wherein, the target complex data is the output data of range-dimensional FFT, the output data of Doppler-dimensional FFT, or the output data of beamforming (DBF).

[0013] In one example of this embodiment, the step of using a sparse lookup table to replace the multiplier for logarithmic compression to obtain the amplitude value can be achieved by processing the target complex data using the method described in any embodiment of this disclosure to obtain the amplitude value represented by the logarithm of the complex amplitude.

[0014] This embodiment of the disclosure decomposes the problem of obtaining the amplitude value into the calculation and summation of two functions through mathematical identities, thereby converting the traditional multiplication into addition. At the same time, it adopts a sparse lookup table method for segmented approximation, and performs large-amplitude precision acquisition in steep intervals, thereby achieving sufficient calculation accuracy at the lowest hardware resource cost.

[0015] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the embodiments described in the description, claims, and drawings. Attached Figure Description

[0016] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0017] Figure 1 This is a schematic diagram of an apparatus for calculating the logarithm of a complex amplitude according to an embodiment of the present disclosure; Figures 2 to 5 They are Figure 1 Four exemplary structural diagrams of the device shown; Figure 6 This is a calculation of an embodiment of the present disclosure. A diagram illustrating the selection of indices and interpolations from input data; Figure 7 , Figure 8 and Figure 9 These are calculations based on an embodiment of this disclosure. hour, x A schematic diagram illustrating the selection of index bits and interpolation bits when located in the 1st, 2nd, and 3rd sub-intervals; Figure 10 This is a schematic diagram of an embodiment of a radar sensor measuring environmental targets; Figure 11 This is a schematic diagram of an FMCW signal transmitted by a radar system according to an embodiment; Figure 12 This is a schematic diagram of a transceiver required for radar detection in one embodiment; Figure 13 This is a flowchart of a signal processing method according to an embodiment of the present disclosure; Figure 14 This is a flowchart of a target detection method according to an embodiment of the present disclosure; Figure 15 This is a schematic diagram of an apparatus for calculating the logarithm of a complex amplitude according to an embodiment of the present disclosure; Figure 16 This is a schematic diagram of an integrated circuit according to an embodiment of the present disclosure; Figure 17 This is a schematic diagram of an electromagnetic wave device according to an embodiment of the present disclosure. Detailed Implementation

[0018] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that more embodiments and implementations are possible within the scope of the embodiments described herein.

[0019] In the description of this disclosure, words such as "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments. The word "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this disclosure, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply differences.

[0020] In describing representative exemplary embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Furthermore, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders may be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0021] To calculate the logarithm of a complex amplitude, we usually first calculate the square of the complex amplitude, i.e. Then perform logarithmic calculations: This scheme requires a multiplier, consuming significant hardware resources and resulting in a large chip area. While some approximation algorithms can be used, such as the JPL (alpha max plus min) approximation algorithm, to estimate... , then calculate The JPL approximation algorithm can quickly calculate the square root value through a series of mathematical transformations and approximations, but this method has a relatively large error. For example, when using the CORDIC (Coordinate Rotation Digital Computer) algorithm to calculate the logarithm of a complex number's magnitude, it first calculates... , then calculate This algorithm replaces complex multiplication operations with basic addition, subtraction, and bit shifting, but it suffers from high latency and requires significant hardware resources. Therefore, the industry needs a device for calculating the logarithm of complex number magnitudes that achieves high numerical accuracy while maintaining a small hardware implementation area.

[0022] Therefore, one embodiment of this disclosure provides an apparatus for calculating the logarithm of a complex amplitude through cascaded functions. and To calculate the logarithm of a complex number amplitude, and The formula for calculating the logarithm of a complex number's magnitude is obtained through decomposition, as follows:

[0023] in, and They are defined as follows: ,

[0024] function For logarithmic functions, the function The product of the logarithm and 0.5 can be achieved by shifting the logarithm after it has been calculated. The logarithm calculation in both functions can be implemented using a lookup table.

[0025] like Figure 1 As shown, the apparatus for calculating the logarithm of a complex amplitude according to an embodiment of this disclosure includes: The first calculation unit 10 is configured to use the absolute values ​​of the real and imaginary parts of a complex number. and As input, calculate based on lookup table , And output, yes and One of the numbers, yes and Another number in; The second computing unit 20 is configured to... , As input, calculate based on lookup table And output; The first adder 30 is configured to... and As input, calculate and The sum of these values ​​yields the logarithm of the complex magnitude, which is then output. in, , , .

[0026] The above embodiments of this disclosure use two functions l(x) and g(x) The corresponding computational units are cascaded to calculate the logarithm of the complex amplitude. l(x) and g(x) Both methods can be calculated using lookup tables, eliminating the need for multipliers and resulting in a smaller hardware footprint. This offers a significant cost advantage, while using lookup tables to calculate logarithms also achieves high numerical accuracy.

[0027] In an exemplary embodiment of this disclosure, the first computing unit includes: an execution function. The two first computing circuits of the operation, one of which is... Input, Output ; another with Input, Output ,in, ; The second computing unit includes: The subtractor is configured to... and As input, calculate or And output, , ; The second computing circuit is configured to compute functions. The calculation function Including: Input, Output Or, with Input, Output .

[0028] The embodiments of this disclosure are illustrated below through several examples: Figure 2 In the example shown, the first computational unit includes two functions for calculating the function. The first computing circuit, respectively called the first l(x) Operator and Second l(x) Operator, should be first l(x) The input of the operator is In this example for and The one with the larger median value is ,second l(x) The input of the operator is In this example for and The smaller of the median values ​​is The second computing unit includes the components located in the second... l(x) Operators and Subtractor between operators and second calculation circuit (in this example) Operator). One input of the subtractor is the first... l(x) The output of the operator is The other input is the second l(x) Operator output The output is - The output of the subtractor is input to... Operator, The operator performs the following computation: , The operator's output is: Overall, the computation performed by the second computing unit can be represented as follows: Then, the first adder combines the output of the second computation unit with the first... l(x) The outputs of the operators are summed to obtain the logarithm of the complex magnitude.

[0029] Figure 3 The example shown is the same as Figure 2 The examples are basically the same, except for the first one. l(x) Operator input min( , ),second l(x) Operator input max( , ), that is, two l(x) The inputs to the operators can be interchanged, but this does not affect the final result.

[0030] Figure 4 In the example shown, the two first computing circuits of the first computing unit are the first... l(x) Operator and Second l (x) Operator. First l(x) Operator input ,second l(x) Operator input The second calculation unit includes a subtractor and a second calculation circuit (in this example, ...). Operator). The input to the subtractor is the first l(x) The output of the operator is Second l(x) Operator output The output is - The subtractor's output is input to... Operator, Operator is A simple transformation of the operator = , that is Therefore The operator's output is: Overall, the computation performed by the second computing unit can still be represented as: Then, the first adder will... The first output of the operator l(x) The outputs of the operators are summed to obtain the logarithm of the complex magnitude. Although this is used... and They represent and The calculation can be performed, but it can also be used uniformly as in some other embodiments. express and In this case, if the input is - , = If the input is - , = This is just for convenience and there is no essential difference.

[0031] Figure 5 The example shown is the same as Figure 4 The examples are basically the same, except for the first one. l(x) Operator input min( , ),second l(x) Operator input max , That is, the inputs of the two are interchanged, which does not affect the final result.

[0032] Calculation based on a 6-bit lookup table l(x) , In the case of calculating the logarithm of a complex amplitude using the embodiments of this disclosure, the error is less than 0.0082 and the accuracy is less than 0.05 dB, which is higher than the accuracy achieved by using the JPL approximation algorithm. When calculating the logarithm of a complex amplitude using the JPL approximation algorithm, the error exceeds 0.011, equivalent to an accuracy of 0.066 dB. Furthermore, the embodiments of this disclosure maintain consistent accuracy across the entire dynamic range of the input, and the accuracy of non-top-down floating-point numbers does not decrease.

[0033] The above examples illustrate some equivalent implementations of the embodiments of this disclosure, and will not be listed one by one.

[0034] In an exemplary embodiment of this disclosure, It is a floating-point number or pseudo-floating-point number, including a sign bit, an exponent part, and a mantissa part; the first calculation circuit (i.e. l(x) The operator is configured to be based on l(x) Input data The index part is obtained from the index t ,according to The last digit is obtained by searching a pre-stored lookup table. Approximate value, then based on the exponent t And the approximate value obtained And output; where, t It is an integer. , m Greater than or equal to 0 and less than 1.

[0035] The calculation in this embodiment can be expressed as: According to the index t And the approximate value obtained When outputting, you can t The value can be added to the approximate value obtained from the lookup table and then output directly. Alternatively, an interpolation can be added before outputting.

[0036] In one example of an embodiment of this disclosure, the first computing circuit includes: The exponent extraction circuit is configured to extract the input data. The exponent part is decoded to obtain the exponent t; The lookup table circuit is configured to use... The high k bits of the mantissa are used as an index, which is read from the lookup table. Approximate value, k≥1; An interpolation circuit is configured to add the approximate value to the interpolation circuit. Output later; The second adder is configured to add the number output by the interpolation circuit. t ,get logarithm And output; Where k and p are positive integers. express In the mantissa portion, the p bits following the high k bits, k+p is less than or equal to N, where N is a constant. The number of bits in the mantissa.

[0037] When using linear interpolation for calculation:

[0038] like Figure 6 As shown, express The high k bits of the mantissa Indicated by For indexes read from the lookup table Approximate value, express In the mantissa portion, the p bits after the high k bits, k+p is less than N, and N is... The number of bits in the mantissa. Linear interpolation can further improve the computational accuracy of embodiments of this disclosure.

[0039] In an exemplary embodiment of this disclosure, For fixed-point numbers, including a sign bit and a value field; the second calculation circuit is configured to calculate based on Input data x The index bits in the numerical field are used to search a pre-stored lookup table to obtain... An approximate value is obtained, and then based on the approximate value, an approximate value is obtained. And output; x equal or .

[0040] The output of the subtractor in this embodiment It can be converted to fixed-point format to reduce hardware resource consumption and improve computation speed. In the text, Input data x = This means... ; In input data x = When, it means .

[0041] Based on the approximate value, we obtain When outputting, you can either directly output the approximate value obtained from the table lookup, or add an interpolation value to the approximate value before outputting.

[0042] In an exemplary embodiment of this disclosure, the second computing circuit includes: Segmented circuit, configured according to x Numerical range determination x The index i of the sub-interval; where, x The value range is divided into M sub-intervals from smallest to largest. The i-th sub-interval corresponds to the i-th pre-stored lookup table, i=1,2,…,M; The lookup table circuit is configured to determine the index i at least when i is less than M. x n in the numerical field i Using the index bits as addresses, read from the i-th lookup table. Approximate value; The interpolation circuit is configured to determine the index i at least when i is less than M. x q in the numerical field iInterpolated bits and interpolation coefficients , add the approximation to the product of the interpolated bits and to obtain and output it; where n i , q i are positive integers, M is greater than or equal to 2, the interpolated bits are located after the index bits and adjacent to the index bits.

[0043] In this embodiment, after performing linear interpolation when calculating , the calculation accuracy of the embodiments of the present disclosure can be further improved. In addition, this embodiment uses a sparse lookup table to calculate . By dividing the value range of x from small to large into M sub-intervals, according to x numerical range to determine x the index i of the sub-interval where it is located and look up the corresponding lookup table of the sub-interval. Compared with using one lookup table to calculate , it can reduce resource occupancy, speed up the calculation speed, and the accuracy is controllable.

[0044] In an example of this embodiment, M>2, and the segmentation circuit is further configured to directly output =0 when i = M; the breakpoints of the M sub-intervals are powers of 2, and when i < M, the larger i is, the smaller the number of bits of n i , and the larger the number of bits of q i , and is a negative power of 2. When i = M, the input data x of the second calculation circuit is relatively large, making approach 0. Therefore, the approximation =0 can be directly output without using the lookup table to speed up the operation. When i < M, the larger i is, the larger the input data x , along with x the smaller the gradient of change, and a smaller number of bits can be used as the index to access the lookup table, which can reduce resource occupancy without causing a large loss of accuracy. And the larger i is, the larger the number of bits of q i , and the interpolation is more accurate, thereby improving the calculation accuracy.

[0045] In an example of this embodiment, the input data x of includes an integer part and a decimal part. The value range of x is divided into 4 sub-intervals from small to large. The first sub-interval is [0,1), the second sub-interval is [1,2), the third sub-interval is [2,4), and the fourth sub-interval is (4, ); When i=1, the index bit is x The high n1 bits of the fractional part, the interpolation bits are: x The remaining bits of the fractional part =2 -2 When i=2, the index bits are x The high n2 bits of the fractional part, the interpolation bits are: x The remaining bits of the fractional part =2 -3 When i=2, the index bits are x The high n3 bits of the fractional part, the index bits are x The last bit of the integer part and the high n3 bits of the fractional part are interpolated by the following bits: x The remaining bits of the fractional part =2 -5 Where n1 > n2 > n3 ≥ 1; The segmented circuit is configured according to x Determine the last two digits of the integer part x The index i of the sub-interval.

[0046] Figure 7 The input data is shown below. x In the case of being in the first subinterval [0,1), i=1, the index bit is x The high 5 bits of the fractional part, interpolation bits are: x The remaining bits of the fractional part are the last 5 bits. The calculation can be expressed as:

[0047] in, It is a 5-bit index bit. Therefore The address is read from the first lookup table Approximate value, For interpolation bits, This means shifting right by 2 bits. =2 -2 .

[0048] Figure 8 The input data is shown below. x In the case of being in the second subinterval [1,2), i=2, and the index bit is... x The high 4 bits of the fractional part, interpolation bits are: x The remaining bits of the fractional part are the last 6 bits. The calculation can be expressed as:

[0049] in, It is a 4-bit index bit. Therefore The address is read from the second lookup table. Approximate value, For interpolation bits, This means shifting right by 3 bits. =2 -3 .

[0050] Figure 9 The input data is shown below. x In the case of the 3rd subinterval [2,4), i=3, and the index bit is... x The last digit of the integer part x The high 2 bits of the fractional part, interpolation bits are: x The remaining bits of the fractional part are the last 8 bits. The calculation can be expressed as:

[0051] in, It is a 5-bit index bit. Therefore The address is read from the 3rd lookup table Approximate value, For interpolation bits, This means shifting right by 5 bits. =2 -5 .

[0052] This example only requires constructing three lookup tables with indexes of 5 bits, 4 bits, and 3 bits respectively, and can be implemented based on these lookup tables. The calculation. Because the input data... x When changing within the first subinterval [0,1), The range of variation is the largest, and using a 5-bit index can improve the precision of the lookup table. (Input data...) x When the variation is located within the second subinterval [1,2), As the change slows down, the number of index bits can be reduced to 4 without a significant decrease in precision. However, in the input data... x When the variation is located within the third subinterval [2,4), As the rate of change slows further (approaching 0), a 3-bit index can be used, resulting in a minimal lookup table. Therefore, this example achieves a good balance between resource consumption, processing speed, and precision.

[0053] The embodiments described above are based on lookup table calculations. , When performing interpolation, the accuracy can be more than twice that of the JPL approximation algorithm.

[0054] The apparatus for calculating the logarithm of a complex amplitude according to the above embodiments of this disclosure can be widely used in the field of digital signal processing, such as radar. Figure 10 As shown, radar sensor 10 is a sensor that uses the Doppler effect of electromagnetic waves to measure physical quantities of an environmental target 20. Within its detection range, the radar sensor emits electromagnetic waves at a defined frequency, and the echoes formed by the reflection from the target are received by the radar sensor. Based on the distance between the radar and the object, a certain frequency difference exists between the electromagnetic waves emitted by the radar sensor and the received echoes. By performing frequency domain analysis on the intermediate frequency signal of this frequency difference, the physical quantities between the object and the radar chip can be obtained. For example, by utilizing the coherence characteristics between the electromagnetic waves emitted by the radar sensor and the received echoes, spectral analysis of the coherent signal (also known as the intermediate frequency signal) can be performed to obtain the relative physical quantities with respect to the target, such as at least one of distance, angle, and velocity. Radar sensors typically emit a series of chirps for detection. Examples of chirps include continuous frequency modulation (FMCW) signals or continuous phase modulation (PMCW) signals, not shown in the figure. Figure 11 Taking the FMCW signal as an example, multiple chirp signals can form a frame (or a group). Each chirp signal includes an up-modulation band, an down-modulation band, and a frequency holding band. The period of the chirp signal is Tc.

[0055] A radar sensor includes a radar chip and a radar circuit board. The radar circuit board houses the radar chip and provides external circuitry connected to it. This external circuitry includes non-integrated circuitry that powers the radar chip, such as power supply circuits and crystal oscillator circuits. The radar circuit board also includes circuitry for controlling the radar chip's operation and / or processing the data reported by the radar chip, such as a host computer or processor (CPU).

[0056] Radar chips integrate the transceivers required for radar detection in the form of semiconductor integrated circuits. For example... Figure 12 As shown, the transceiver 20 includes a signal generator 210, a transmit link 220, and a receive link 230. The signal generator 210 generates a local oscillator signal LO with a specific waveform. The transmit link 220 converts the local oscillator signal into a probe signal and transmits it to the transmit antenna; it includes a power amplifier 221, etc. The receive link 230 uses the local oscillator signal to amplify and down-frequency the echo signal from the receive antenna to output a received signal. The receive link 230 includes a low-noise amplifier 231 and a mixer 232, etc.

[0057] Taking the FMCW signal as an example, the signal generator 210 can be a millimeter-wave generator implemented with an oscillator. The local oscillator signal generated by the signal generator 210 is amplified by the power amplifier 221 to form the detection signal, and then converted into electromagnetic waves and radiated into free space by one or more transmitting antennas (TX_Antenna). The electromagnetic waves are reflected and / or refracted by objects to form an echo. The echo is converted into an electrical signal (i.e., the echo signal) by the receiving antenna (RX_Antenna). The echo signal is amplified by the low-noise amplifier 231 and then mixed with the local oscillator signal in the mixer 232 to obtain an intermediate frequency signal.

[0058] In some chip examples, the radar chip also includes an analog-to-digital converter (ADC) coupled to a mixer to convert the intermediate frequency (IF) signal into a digital signal. This digital signal is used for digital signal processing by dedicated digital circuits such as FPGAs or hardware accelerators to improve the efficiency of radar signal processing. One or more digital signal processing modules supported by the dedicated digital circuits may include: a 1D-FFT module, a 2D-FFT module, a Constant False Alarm Rate (CFAR) module, and a Direction of Arrival (DOA) module. The 1D-FFT module performs range-dimensional FFT calculations on the digital signals within the chirp within the detection range. The 2D-FFT module performs Doppler-dimensional FFT calculations on the digital signals between chirps based on the 1D-FFT results to obtain a range-Doppler spectrum (RD spectrum). The amplitude of the complex data in this spectrum represents energy information and can be viewed as a range-velocity-energy matrix. The DOA module calculates the angle of arrival using the phase difference to obtain a matrix containing the target angle and energy. The CFAR module is used to filter out false targets from any type of received matrix data for the purpose of target extraction.

[0059] After obtaining the range-Doppler spectrum using 2D-FFT, in the constant false alarm rate (CFAR) stage of target detection, a threshold needs to be set using the CFAR algorithm. Peak values ​​exceeding the threshold are considered "suspected targets." At this point, the peak value is located by comparing the amplitudes of complex data within the target area. Furthermore, the horizontal axis of the peak value in the range-Doppler spectrum corresponds to the target distance, and the vertical axis corresponds to the target velocity. The peak value is also used to calculate the target's range-velocity information. For the detected target point, DOA processing is performed on its multi-antenna received signals to obtain the target's angular response. The calculated angular domain peak value directly corresponds to the target's azimuth / elevation angle, thus completing the extraction of the target's three-dimensional "range-velocity-angle" information. The method for calculating the logarithm of complex amplitudes in the above embodiments of this disclosure can be used for radar digital signal processing to compare the magnitudes of complex data amplitudes and locate peak values. However, this disclosure is not limited to this.

[0060] This disclosure also provides a signal processing method, such as... Figure 13 As shown, it includes: Step 110: Sample and process the signal received by the system to obtain multiple complex data; Step 120: Calculate the logarithm of the magnitudes of the plurality of complex data, including: based on the absolute values ​​of the real and imaginary parts of the complex data. and Calculate , , = , = or = , = ;based on , Calculate ,Will Plus That is, the logarithm of the magnitude of the complex data is obtained; Step 130: Compare the magnitudes of the multiple complex data amplitudes based on the calculated logarithms, and complete the specified digital signal processing task according to the magnitudes of the multiple complex data amplitudes.

[0061] in, , , , , , All calculations are based on lookup tables.

[0062] The systems to which the above signal processing methods are applied can be, but are not limited to, radar systems. They can also be used in other communication systems such as mobile communication systems and wireless local area networks. The method of calculating the logarithm of complex amplitudes is not limited to peak location; it can also be used for channel quality assessment (e.g., selecting the channel with the largest signal amplitude), interference detection, etc. It can also be output as information about the detected signal (e.g., information representing energy levels) for subsequent processing.

[0063] This disclosure embodiment uses two functions l(x) and g(x) The corresponding computational units are cascaded to calculate the logarithm of the complex amplitude. l(x) and g(x) Both methods can be calculated using lookup tables, eliminating the need for multipliers and resulting in a smaller hardware footprint. This offers a significant cost advantage, while using lookup tables to calculate logarithms also achieves high numerical accuracy.

[0064] In an exemplary embodiment of this disclosure, the signal processing method is a digital signal processing method for a radar system; the plurality of complex data are complex data in a range-Doppler spectrum; the specified digital signal processing task includes peak localization; after completing peak localization based on the magnitude of the plurality of complex data amplitudes, the method further includes: determining, based on the result of the peak localization, the target to be detected and at least one of the target's distance, velocity, and angle.

[0065] In an exemplary embodiment of this disclosure, It is a floating-point number or a pseudo-floating-point number. Includes the sign bit, exponent part, and mantissa part; the absolute value of the real and imaginary parts of the complex number data. and Calculate , ,include: according to Input data The index part is obtained from the index t , equal ;by The high k bits of the mantissa are used as an index, which is read from a pre-stored lookup table. Approximate values, k≥1; and Add the approximation value In addition t ,get logarithm ; in, x = , t It is an integer. m Greater than or equal to 0 and less than 1; k and p are positive integers. express In the mantissa portion, the p bits following the high k bits, k+p is less than or equal to N, where N is a constant. The number of bits in the mantissa.

[0066] Linear interpolation can further improve the computational accuracy of the embodiments of this disclosure.

[0067] In an exemplary embodiment of this disclosure, the basis , Calculate ,include: according to and Calculate , and then Calculate for input ;at this time It represents ;or according to and Calculate , and then Calculate for input ;at this time It represents .

[0068] In an exemplary embodiment of this disclosure, A fixed-point number including a sign bit and a numerical field; the aforementioned... or Calculate for input ,include: according to Input data x Determining the numerical range x The index i of the sub-interval; x equal or , x The value range is divided into M sub-intervals from smallest to largest. The i-th sub-interval corresponds to the i-th pre-stored lookup table, i=1,2,…,M; At least when i is less than M, the value is determined based on index i. x n in the numerical field i Using the index bits as addresses, read from the i-th lookup table. Approximate value; At least when i is less than M, the value is determined based on index i. x q in the numerical field i Interpolation bits and interpolation coefficients Add the interpolation bits to the approximate value. The product is obtained ; Where, ni , q i is a positive integer, M is greater than or equal to 2, the interpolation bit is after the index bit and adjacent to the index bit.

[0069] In this embodiment, after performing linear interpolation during the calculation of , the calculation accuracy of the embodiments of the present disclosure can be further improved. Moreover, this embodiment uses a sparse lookup table to calculate . By dividing the x value range from small to large into M subintervals, and judging the index i of the subinterval where x is located according to the x numerical domain and looking up the corresponding lookup table of the subinterval, compared with using one lookup table to calculate , the resource occupancy can be reduced, the calculation speed can be accelerated, and the accuracy is controllable.

[0070] In an example of this embodiment, M > 2. When i = M, = 0; The breakpoints of the M subintervals are powers of 2. And when i < M, the larger i is, the smaller the number of bits of n i is, and the larger the number of bits of q i is, and it is a negative power of 2.

[0071] When i = M, approaches 0. Therefore, the approximate value = 0 can be directly output, and the lookup table is no longer used to speed up the operation. When i < M, the larger i is, the larger the input data x is, The gradient of x changing with i [[ID=4**]] is smaller. Fewer bits can be used as the index to access the lookup table, which can reduce resource occupancy without causing a large loss of accuracy. And the larger i is, the larger the number of bits of q i is, and the interpolation is more accurate, thus improving the calculation accuracy.

[0072] In an example of this embodiment, The input data of x includes an integer part and a decimal part. The x value range is divided into 4 subintervals from small to large. The first subinterval is [0, 1), the second subinterval is [1, 2), the third subinterval is [2, 4), and the fourth subinterval is (4, ); When i = 1, the index bit is x The high n1 bits of the decimal part, and the interpolation bit is x The other bit positions of the decimal part, = 2 -2When i=2, the index bits are x The high n2 bits of the fractional part, the interpolation bits are: x The remaining bits of the fractional part =2 -3 When i=2, the index bits are x The high n3 bits of the fractional part, the index bits are x The last bit of the integer part and the high n3 bits of the fractional part are interpolated by the following bits: x The remaining bits of the fractional part =2 -5 Where n1 > n2 > n3 ≥ 1; The segmented circuit is configured according to x Determine the last two digits of the integer part x The index i of the sub-interval.

[0073] This example only requires constructing three lookup tables with indexes of 5 bits, 4 bits, and 3 bits respectively, and can be implemented based on these lookup tables. The calculation. And the input data. x When located in different sub-intervals, the number of bits used in the index is different, which can achieve a good balance between resource consumption, operation speed and precision.

[0074] This disclosure also provides a target detection method in one embodiment, applied to FMCW radar, such as... Figure 14 As shown, the method includes: Step 310: Obtain the target complex number data; Step 320: For the target complex data, logarithmic compression is performed by replacing the multiplier with a sparse lookup table to obtain the amplitude value of the target complex data, so as to perform constant false alarm detection to obtain target information. The target complex data is the output data of range-dimensional FFT, the output data of Doppler-dimensional FFT, or the output data of beamforming (DBF).

[0075] Calculating the logarithm of the complex amplitude can transform a multiplicative large dynamic range signal (x) 2 + y 2 Converted into an additive small dynamic range signal This greatly compresses the dynamic range of the data, making it easier for subsequent CFAR algorithms to set a uniform and stable threshold.

[0076] In one example of an embodiment of this disclosure, the step of using a sparse lookup table to replace the multiplier for logarithmic compression to obtain the amplitude value includes: processing the target complex data using the signal processing method described in any embodiment of this disclosure to obtain the amplitude value represented by the logarithm of the complex amplitude.

[0077] This embodiment of the disclosure uses mathematical identities to decompose the problem of obtaining amplitude values ​​into the calculation and summation of two functions, thereby converting the traditional multiplication into addition. At the same time, a sparse lookup table method is used for segmented approximation, and large-amplitude precision acquisition is performed on steep intervals (such as the [0,1) interval mentioned above), thereby achieving sufficient calculation accuracy at the lowest hardware resource cost.

[0078] One embodiment of this disclosure also provides a signal processing apparatus, such as... Figure 15 As shown, it includes a storage circuit 101 and a processing circuit 102, wherein the processing circuit 102 is configured to implement the signal processing method described in any embodiment of the present disclosure.

[0079] The arithmetic circuit of this embodiment may include a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a microprocessor, etc., or other conventional processors; the arithmetic circuit may also include a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), discrete logic or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components; or a combination of the above devices. That is, the arithmetic circuit of the above embodiments can be any processing device or combination of devices that implements the signal processing method of the embodiments of this disclosure. If the embodiments of this disclosure are implemented in part in software, then instructions for software can be stored in a suitable non-volatile computer-readable storage medium, and one or more processors can be used to execute the instructions in hardware to implement the method of the embodiments of this disclosure.

[0080] One embodiment of this disclosure also provides an integrated circuit, such as... Figure 16 As shown, the integrated circuit includes a radio frequency module 2011, an analog signal processing module 2012, and a digital signal processing module 2013 connected in sequence, wherein: The radio frequency module 2011 is configured to generate and transmit electromagnetic wave signals, and to receive electromagnetic wave signals; The analog signal processing module 2012 is configured to down-frequency the received electromagnetic wave signal to obtain an intermediate frequency signal; and The digital signal processing module 2013 is configured to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal, and to process the digital signal, including the signal processing method described in any embodiment of this disclosure.

[0081] In an exemplary embodiment of this disclosure, the integrated circuit is a radar chip.

[0082] In some optional embodiments of this disclosure, the integrated circuit may be an AiP (Antenna-In-Package) chip structure, an AoP (Antenna-On-Package) chip structure, an AoC (Antenna-On-Chip) chip structure, a RoP (Radiator-on-Package) chip structure, etc. Specifically, a RoP involves setting a radiator structure on the chip package and surrounding this radiator structure with solder balls to form an air waveguide structure. That is, the radio frequency (RF) signal generated by the chip can be transmitted through the aforementioned radiator structure, the air cavity waveguide structure surrounded by the solder balls, and the air waveguide built into the PCB board to an external antenna for radiation towards a target area.

[0083] One embodiment of this disclosure also provides an electromagnetic wave device, such as... Figure 17 As shown, the device includes: a carrier 4; an integrated circuit 5 as described in any embodiment of this disclosure, disposed on the carrier 4; and an antenna 6 disposed on the carrier 4, integrated with the integrated circuit 5 as a single device (i.e., the antenna can be an antenna configured in structures such as AiP, AoP, AoC, or RoP) or disposed separately; wherein the integrated circuit 5 is connected to the antenna 6 (i.e., the antenna can be an antenna configured in structures such as AiP, AoP, AoC, or RoP), and is used to transmit and / or receive the electromagnetic wave signal. The carrier can be a printed circuit board (PCB), and the integrated circuit and the antenna are routed through the PCB.

[0084] Electromagnetic wave devices can achieve functions such as target detection and / or communication by transmitting and receiving electromagnetic wave signals, thereby providing the device body with target detection information and / or communication information, and thus assisting or even controlling the operation of the device body. One embodiment of this disclosure also provides an electronic device, such as... Figure 8 As shown, it includes: a device body; and an electromagnetic wave device disposed on the device body as described in any embodiment of this disclosure; wherein the electromagnetic wave device is configured to perform target detection and / or communication to provide reference information to the operation of the device body.

[0085] An embodiment of this disclosure also provides an electronic device, including: The equipment itself; and The electromagnetic wave device described in any embodiment of this disclosure is disposed on the device body; The electromagnetic wave device is configured to perform target detection and / or communication to provide reference information for the operation of the device body.

[0086] In one optional embodiment of this disclosure, the electromagnetic wave device may be disposed outside the device body or inside the device body. In other optional embodiments of this disclosure, the electromagnetic wave device may be partially disposed inside the device body and partially disposed outside the device body. This disclosure does not limit the specific implementation; it may be determined according to the specific circumstances.

[0087] In an optional embodiment, the aforementioned device body can be a component or product applied in fields such as smart cities, smart homes, transportation, smart homes, consumer electronics, security monitoring, industrial automation, in-cabin detection (such as smart cockpits), medical devices, and healthcare. For example, the device body can be intelligent transportation equipment (such as automobiles, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments for detecting vital signs parameters and various devices equipped with such instruments, such as in-cabin vital sign detection, indoor personnel monitoring, smart medical devices, consumer electronic devices, car digital keys, air mice, etc.

[0088] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. An apparatus for calculating the logarithm of a complex number amplitude, characterized in that, include: The first computational unit is configured to use the absolute values ​​of the real and imaginary parts of a complex number. and As input, calculate based on lookup table , And output, yes and One of the numbers, yes and Another number in; The second computing unit is configured to... , As input, calculate based on lookup table And output; The first adder is configured to... and As input, calculate and The sum of these values ​​yields the logarithm of the complex magnitude, which is then output. in, , , .

2. The apparatus as described in claim 1, characterized in that: The first calculation unit includes: a function for calculating... Two first computing circuits, one of which is Input, Output ; another with Input, Output ,in, ; The second computing unit includes: The subtractor is configured to... and As input, calculate or And output, , ; The second computing circuit is configured to compute functions. The calculation function Including: Input, Output Or, with Input, Output .

3. The apparatus as described in claim 2, characterized in that: It is a floating-point number or pseudo-floating-point number, including the sign bit, exponent part and mantissa part; The first computing circuit is configured to according to Input data The index part is obtained from the index t ,according to The last digit is obtained by searching a pre-stored lookup table. Approximate value, then based on the exponent t And the approximate value obtained And output; where, t It is an integer. , m Greater than or equal to 0 and less than 1.

4. The apparatus as described in claim 3, characterized in that: The first computing circuit includes: The exponent extraction circuit is configured to extract the input data. The exponent part is decoded to obtain the exponent t; The lookup table circuit is configured to use... The high k bits of the mantissa are used as an index, which is read from the lookup table. Approximate value, k≥1; An interpolation circuit is configured to add the approximate value to the interpolation circuit. Output later; The second adder is configured to add t to the number output by the interpolation circuit to obtain... logarithm And output; Where k and p are positive integers. express In the mantissa portion, the p bits following the high k bits, k+p is less than or equal to N, where N is a constant. The number of bits in the mantissa.

5. The apparatus as described in claim 2, characterized in that: For fixed-point numbers, including a sign bit and a value field; the second calculation circuit is configured to calculate based on Input data x The index bits in the numerical field are used to search a pre-stored lookup table to obtain... An approximate value is obtained, and then based on the approximate value, an approximate value is obtained. And output; x equal or .

6. The apparatus as described in claim 5, characterized in that: The second computing circuit includes: Segmented circuit, configured according to x Numerical range determination x The index i of the sub-interval; where, x The value range is divided into M sub-intervals from smallest to largest. The i-th sub-interval corresponds to the i-th pre-stored lookup table, i=1,2,…,M; The lookup table circuit is configured to determine the index i at least when i is less than M. x n in the numerical field i Using the index bits as addresses, read from the i-th lookup table. Approximate value; The interpolation circuit is configured to determine the index i at least when i is less than M. x q in the numerical field i Interpolation bits and interpolation coefficients Add the interpolation bits to the approximate value. The product is obtained And output; Where, n i , q i M is a positive integer, M is greater than or equal to 2, and the interpolation bit is located after the index bit and adjacent to the index bit.

7. The apparatus as claimed in claim 6, characterized in that: M > 2, the segmented circuit is further configured to directly output when i = M = 0; the breakpoints of the M sub-intervals are powers of 2; and when i < M, the larger i is, the smaller the number of bits of n i and the larger the number of bits of q i is, and it is a negative power of 2. ​ 8. The apparatus as claimed in claim 7, characterized in that: Input data x The numerical range of x includes an integer part and a decimal part. The range of x is divided into four sub-intervals, M=4, from smallest to largest. The first sub-interval is [0,1), the second sub-interval is [1,2), the third sub-interval is [2,4), and the fourth sub-interval is (4,1). ); When i=1, the index bit is x The high n1 bits of the fractional part, the interpolation bits are: x The remaining bits of the fractional part =2 -2 When i=2, the index bits are x The high n2 bits of the fractional part, the interpolation bits are: x The remaining bits of the fractional part =2 -3 ; When i=3, the index bits are x The high n3 bits of the fractional part, the index bits are x The last bit of the integer part and the high n3 bits of the fractional part are interpolated by the following bits: x The remaining bits of the fractional part =2 -5 Where n1 > n2 > n3 ≥ 1; The segmented circuit is configured according to x Determine the last two digits of the integer part x The index i of the sub-interval.

9. A signal processing method, comprising: The system samples and processes the received signals to obtain multiple complex data. Calculate the logarithm of the magnitudes of the plurality of complex data values, including: based on the absolute values ​​of the real and imaginary parts of the complex data. and Calculate , , = , = or = , = ;based on , Calculate ,Will Plus That is, the logarithm of the magnitude of the complex data is obtained; The magnitudes of the multiple complex data amplitudes are compared based on the logarithms of the calculated multiple complex data amplitudes, and a specified digital signal processing task is executed according to the magnitudes of the multiple complex data amplitudes. in, , , , , , All calculations are based on lookup tables.

10. The signal processing method as described in claim 9, characterized in that: The signal processing method is a digital signal processing method used in the target detection stage of a radar system; the multiple complex data are complex data in the range-Doppler spectrum. The specified digital signal processing task includes peak localization. After performing peak localization based on the magnitude of the plurality of complex data amplitudes, the method further includes: determining, based on the result of the peak localization, the target to be detected and at least one of the target's distance, velocity, and angle.

11. The signal processing method as described in claim 9, characterized in that: It is a floating-point number or a pseudo-floating-point number. Includes the sign bit, exponent part, and mantissa part; the absolute value of the real and imaginary parts of the complex number data. and Calculate , ,include: according to Input data The index part is obtained from the index t , equal ;by The high k bits of the mantissa are used as an index, which is read from a pre-stored lookup table. Approximate values, k≥1; and Add the approximation value In addition t ,get logarithm ; in, x = , t It is an integer. m Greater than or equal to 0 and less than 1; k and p are positive integers. express In the mantissa portion, the p bits following the high k bits, k+p is less than or equal to N, where N is a constant. The number of bits in the mantissa.

12. The signal processing method as described in claim 9, characterized in that: The basis , Calculate ,include: according to and Calculate , and then Calculate for input ;at this time It represents ;or according to and Calculate , and then Calculate for input ;at this time It represents .

13. The signal processing method as described in claim 12, characterized in that: A fixed-point number including a sign bit and a numerical field; the aforementioned... or Calculate for input ,include: according to Input data x Determining the numerical range x The index i of the sub-interval; x equal or , x The value range is divided into M sub-intervals from smallest to largest. The i-th sub-interval corresponds to the i-th pre-stored lookup table, i=1,2,…,M; At least when i is less than M, the value is determined based on index i. x n in the numerical field i Using the index bits as addresses, read from the i-th lookup table. Approximate value; At least when i is less than M, the value is determined based on index i. x q in the numerical field i Interpolation bits and interpolation coefficients Add the interpolation bits to the approximate value. The product is obtained ; Where, n i , q i M is a positive integer, M is greater than or equal to 2, and the interpolation bit is located after the index bit and adjacent to the index bit.

14. The signal processing method as described in claim 13, characterized in that: When M > 2, and i = M, =0; The breakpoints of the M sub-intervals are powers of 2, and when i < M, the larger the value of i, the smaller the number of bits of n i , and the larger the number of bits of q i , and it is a negative power of 2. ​ 15. The signal processing method as described in claim 14, characterized in that: The input data x has a numerical field that includes an integer part and a fractional part. x equal or The range of x is divided into four sub-intervals from smallest to largest: the first sub-interval is [0, 1), the second sub-interval is [1, 2), the third sub-interval is [2, 4), and the fourth sub-interval is (4, 1). The value of index i is based on... x The last two digits of the integer part are judged; When i=1, the index bit is x The high n1 bits of the fractional part, the interpolation bits are: x The remaining bits of the fractional part =2 -2 When i=2, the index bits are x The high n2 bits of the fractional part, the interpolation bits are: x The remaining bits of the fractional part =2 -3 When i=3, the index bits are x The high n3 bits of the fractional part, the index bits are x The last bit of the integer part and the high n3 bits of the fractional part are interpolated by the following bits: x The remaining bits of the fractional part =2 -5 Where n1> n2> n3≥1.

16. A target detection method, characterized in that, When applied to FMCW radar, the method includes: For target complex data, a sparse lookup table is used to replace the multiplier for logarithmic compression to obtain the amplitude value of the target complex data, so as to perform constant false alarm detection to obtain target information; The target complex data is the output data of range-dimensional FFT, the output data of Doppler-dimensional FFT, or the output data of beamforming (DBF).

17. The method as described in claim 16, characterized in that, The method of using a sparse lookup table to replace the multiplier for logarithmic compression to obtain the amplitude value includes: processing the target complex data using the method described in any one of claims 9-15 to obtain the amplitude value expressed as the logarithm of the complex amplitude value.

18. A signal processing apparatus, comprising a storage circuit and an arithmetic circuit, characterized in that, The arithmetic circuit is configured to implement the signal processing method as described in any one of claims 9 to 15.

19. An integrated circuit, characterized in that, It includes a radio frequency module, an analog signal processing module, and a digital signal processing module connected in sequence; The radio frequency module is configured to generate and transmit electromagnetic wave signals, and to receive electromagnetic wave signals. The analog signal processing module is configured to down-frequency the received electromagnetic wave signal to obtain an intermediate frequency signal. The digital signal processing module is configured to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal, and to process the digital signal, including the signal processing method as described in any one of claims 9 to 15.

20. The integrated circuit according to claim 19, characterized in that, The integrated circuit is a radar chip.

21. An electromagnetic wave device, characterized in that, include: Carrier; The integrated circuit as described in claim 19 or 20 is disposed on the carrier; The antenna is mounted on the carrier and can be integrated with the integrated circuit as a single device or disposed separately. The integrated circuit is connected to the antenna to transmit and / or receive the electromagnetic wave signal.

22. An electronic device, characterized in that, include: Equipment body; as well as The electromagnetic wave device as described in claim 21 is disposed on the device body; The electromagnetic wave device is configured to perform target detection and / or communication to provide reference information for the operation of the device body.

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