A dynamic channel normalization method based on shift operation

Abstract

This invention discloses a dynamic channel normalization method based on shift operations, belonging to the fields of artificial intelligence and integrated circuit design technology. This invention constructs a normalization operator without division or floating-point exponents through piecewise linear fitting and binarized power interpolation mechanisms, achieving hardware-friendly dynamic channel normalization based on shift operations. It transforms traditional high-complexity nonlinear mapping into the most efficient shift and addition operations at the underlying hardware level, significantly reducing circuit area and power consumption while maintaining the model's feature extraction capabilities.

Description

Technical Field

[0001] This invention relates to the fields of artificial intelligence and integrated circuit design technology, and in particular to a dynamic channel normalization method based on shift operations. Background Technology

[0002] With the rapid development of artificial intelligence technology, deep neural networks (DNNs), especially models based on the Transformer architecture and convolutional neural networks (CNNs), have been widely used in computer vision and natural language processing tasks. In these deep models, normalization techniques are key components for accelerating model convergence, preventing overfitting, and maintaining the stability of data distribution. Batch normalization (BN) and layer normalization (LN) are currently the two most common mainstream solutions.

[0003] However, both of these existing mainstream normalization methods face challenges in practical applications. For Layer Normalization (LN), although it has become a standard configuration in Transformer architectures due to its ability to effectively preserve channel specificity, its hardware deployment is extremely difficult. LN must calculate the mean and variance of input features in real time during inference, a process involving complex summations, squares, and costly division operations. In integrated circuit design, dividers and floating-point units occupy large chip areas and consume high power, making it difficult for LN to operate efficiently on resource-constrained edge computing devices or neuromorphic chips. Conversely, for Batch Normalization (BN), although it can avoid real-time statistical calculations during inference through parameter folding, it also has significant drawbacks. BN heavily relies on the batch statistical characteristics of training data, exhibiting poor stability when training with small batches or processing variable-length sequences. More importantly, BN often fails to preserve channel specificity as finely as LN, resulting in suboptimal model accuracy in high-performance architectures like Transformer that are sensitive to feature distribution.

[0004] To resolve the conflict between hardware efficiency and model performance, several alternative solutions have emerged in existing technologies. For example, a method called Dynamic Transformation (DyT) abandons real-time calculation of the mean and variance, instead utilizing the characteristics of nonlinear functions to simulate the normalization effect. Its core calculation formula is typically expressed as:

[0005]

[0006] in, This represents the computation result of the DyT method. As input features, For learnable, dynamically scaling scalars and These are the channel parameter vectors used for the affine transformation. The hyperbolic tangent function is used. DyT utilizes the S-shaped curve property of the hyperbolic tangent function to approximate the truncation and normalization of data, thereby avoiding complex statistical calculations.

[0007] While the DyT approach successfully avoids the calculation of mean and variance, it still suffers from technical limitations in its underlying hardware implementation: it relies on the hyperbolic tangent function. Mathematically, calculating the hyperbolic tangent function inherently involves complex nonlinear exponential operations, such as exponentiation, division, and the hyperbolic tangent itself. In existing digital circuits or neuromorphic computing hardware, achieving high-precision exponential operations typically requires expensive floating-point computing resources or significant storage space to construct high-precision look-up tables (LUTs). This means that although the DyT approach reduces statistical computation, the introduced nonlinear exponential operations still result in high hardware latency and energy consumption. This reliance on complex floating-point operations represents a significant gap between the current integrated circuit design's pursuit of extreme energy efficiency and hardware-friendly principles, and the low-power requirements of resource-constrained edge devices. Summary of the Invention

[0008] The purpose of this invention is to address the problem that existing deep neural network normalization methods rely on complex nonlinear operations, resulting in high hardware computational overhead and low energy efficiency on FPGA (Field-Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), and edge computing devices. This invention proposes a dynamic channel normalization method based on shift operations.

[0009] The technical solution adopted in this invention is as follows:

[0010] A dynamic channel normalization method based on shift operations, comprising the following steps:

[0011] Step 1: Receive the signed fixed-point input signal from the deep neural network for normalization operations, and define... This indicates the bit width of the input signal; the input signal format is as follows: the highest bit is the sign bit, the middle bit... The bits are integer bits, low-order bits. The decimal place is the number of decimal places. ;

[0012] Define the bit width of the output signal as , used to output the quantization result of the normalization operation;

[0013] Step 2, Generate For bit-width amplitude signals: the sign of the input signal is determined by the sign bit. If it is negative, the input signal is bit-inverted and incremented by one to obtain the amplitude signal; if it is positive, the input signal is directly used as the amplitude signal.

[0014] Step 3, according to the preset scaling factor Perform an arithmetic right shift on the input signal Bitwise operations are used to generate linear region candidate results, where... The preset scaling parameters for the linear region;

[0015] Step 4: Extract key parameters for piecewise fitting from the generated amplitude signal, including:

[0016] Extracting the high amplitude signal Bits as integer index ;

[0017] Extracting the low amplitude signal The digit is used as the decimal weight. ;

[0018] Step 5, generate interval boundaries based on shift:

[0019] Load the preset reference constant And perform an arithmetic right shift on it. The lower bound signal is obtained by using the bit position.

[0020] For reference constant Arithmetic right shift The upper bound signal is obtained by using the bit position.

[0021] Step 6, weighted by fractional number The weights of the upper bound signal are used with complementary weights. Assuming the lower bound signal as weights, linear interpolation is performed on the upper and lower bound signals to generate the fitting result. And generate fitting results according to the two's complement rule. The negative form;

[0022] Step 7: Generate candidate results for the nonlinear region based on the sign bit of the input signal.

[0023] If it is negative, then the sign bit 1 will be compared with the fitting result. Combine to generate alternative results in the nonlinear region; or combine the fitted results Negative values ​​are used as candidate results for the nonlinear region.

[0024] If positive, then the sign bit 0 is set to the fitted result. The negative values ​​are combined to generate alternative results for the nonlinear region; or the fitting results are used to generate alternative results for the nonlinear region. The positive form is used as the candidate result for the nonlinear region;

[0025] Step 8: Based on the absolute value of the input signal, use a comparator to determine if it is equal to 1 shifted left. The result of the bit is determined by the size relationship. If it is smaller than the result of the linear region in step 3, the candidate result of the linear region in step 3 is output; otherwise, the candidate result of the nonlinear region in step 7 is output.

[0026] Furthermore, it also includes step 9, gradient backpropagation processing based on shift operations for deep neural network training, specifically including:

[0027] Step 901: Receive the input gradient signal returned from the next layer of the neural network. This gradient signal has the same signal format as the input signal.

[0028] Step 902: Based on the absolute value of the input signal, determine its left shift by 1 using a comparator. The magnitude of the result is determined by the relationship between the bits. If the result is less than the preset linear constant, then the linear constant will be applied. As the number of shifts That is, the linear region shift factor; otherwise, As the number of shifts That is, the linear region shift factor;

[0029] Step 903, based on the number of shift bits Perform an arithmetic right shift operation on the gradient signal;

[0030] Step 904: The shifted gradient signal is passed as the output gradient to the previous layer of the neural network.

[0031] Furthermore, in step 3, the linear region scaling parameter is... Set to 1.

[0032] Furthermore, in step 3, the binary two's complement of the input signal is shifted right by 1 bit using an arithmetic right shifter.

[0033] Furthermore, in step 5, the reference constant Set to 1 and shift left Bit.

[0034] Furthermore, in step 7, the candidate results for the nonlinear region are: ,in, Indicates the input signal. Represents a symbolic function.

[0035] Furthermore, deep neural networks are used to process computer vision tasks (such as semantic segmentation of images), and their input data is image data. That is, the input signal in step 1 is the feature tensor transmitted to the normalization layer in the deep neural network, which is the output feature of the layer preceding the normalization layer.

[0036] Furthermore, the input data for deep neural networks can be text data or audio data.

[0037] The technical solution provided by this invention brings at least the following beneficial effects:

[0038] This invention constructs a normalization operator without division or floating-point exponent by using piecewise linear fitting and binarized power interpolation mechanism to achieve hardware-friendly dynamic channel normalization based on shift operations. It transforms the traditional high-complexity nonlinear mapping into the most efficient shift and addition operations at the underlying hardware level, while maintaining the feature extraction capability of the model, significantly reducing circuit area and power consumption. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A comparative diagram of a dynamic channel normalization method based on shift operation (hereinafter referred to as the Shift-DyT scheme) and the hyperbolic tangent function provided in an embodiment of the present invention;

[0041] Figure 2 A schematic diagram comparing the gradients of the Shift-DyT scheme and the hyperbolic tangent function provided in this embodiment of the invention;

[0042] Figure 3 This is a schematic diagram comparing the performance of the Shift-DyT scheme and BN on the ADE20K dataset provided in this embodiment of the invention;

[0043] Figure 4 This is a cross-channel distribution analysis diagram of the Q (query) and K (key) matrices in the bipolar self-attention mechanism after optimization by the Shift-DyT scheme regularization. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be described in detail and completely below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Generally, the components of the embodiments of the present invention described and shown in the accompanying drawings can be arranged and designed using different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present invention.

[0045] This invention proposes a dynamic channel normalization method based on shift operations (referred to as the Shift-DyT scheme). Its core design idea is to utilize... The power-law decay characteristic is used to approximate the nonlinear saturation curve, and linear interpolation is used to smooth the quantization error. The specific technical solution is detailed below:

[0046] 1. Construction of piecewise nonlinear functions based on shifting

[0047] In this step, a hardware-efficient piecewise function is first constructed. To replace traditional Or the Sigmoid function, the construction process of which is based on specific hardware-optimized derivation logic. Traditional While the function possesses the desirable S-shaped characteristic of being linear near the origin and saturating at the far end, its computation relies on complex floating-point exponent units (Exp Units). To simulate this characteristic at the hardware level and eliminate the high computational cost, this embodiment of the invention employs... Exponential function with base As a basic attenuation model.

[0048] The core basis of this design lies in the operational characteristics of the binary system: that is, operations... (in In digital hardware circuits, (where the input value is an integer) is strictly equivalent to inputting the function value... The binary code is directly shifted to the right. Bits, to obtain the output value of the operation. Therefore, as long as complex nonlinear operations can be transformed into operations based on... By performing integer exponentiation operations, the use of multipliers and exponentiation units can be completely eliminated at the physical level. Based on this principle, embodiments of the present invention, according to the input value... The amplitude is used to divide the processing logic into two physical regions for separate optimization:

[0049] A. Linear region processing logic (when...) hour):

[0050] Within this interval, in order to maintain effective backpropagation of the gradient and prevent feature collapse, the embodiments of the present invention employ linear mapping:

[0051]

[0052] To facilitate hardware optimization, this invention mandates a scaling factor. In a preferred embodiment, take In the hardware circuit, this step is directly configured to right-shift the two's complement of the input data by one bit using an arithmetic right shifter. This operation requires only one clock cycle and no multiplication logic gates are needed.

[0053] B. Logic for handling the exponential decay region (when...) hour):

[0054] Within this interval, to simulate saturation characteristics, a shift-based linear interpolation algorithm is used, and its calculation formula is as follows:

[0055]

[0056] in, Yes The piecewise linear approximation. Because... Usually not an integer, calculate directly. Exponential operations are still required. This invention decomposes it into a pure shift operation using the following logic:

[0057] Step 1: Numerical Decomposition

[0058] Enter absolute value Decompose into integer parts and decimal part :

[0059]

[0060] Step 2: Reference Shift Generation

[0061] Generate two baseline values, corresponding to the left and right endpoints of the interval, respectively. The power of . That is, the lower bound reference. and upper bound benchmark :

[0062]

[0063]

[0064] Step 3: Linear interpolation calculation

[0065] Using the decimal part As weights, perform linear interpolation on the two shift results above:

[0066]

[0067] The physical significance of this formula lies in using the line connecting two adjacent "shift points" to approximate the curve, thereby completely eliminating nonlinear calculations and retaining only fixed-point addition and low-width multiplication.

[0068] like Figure 1 As shown, the Shift-DyT scheme of this invention divides the computational domain into three physical regions: in the central region... Within the origin, the function performs a linear mapping to preserve the numerical characteristics near the origin; while in the saturation intervals on both sides... and Inside, the function switches to shift operation mode. This piecewise design uses simple shift and linear operations to approximate the S-curve characteristics of nonlinear functions across the entire domain, thus avoiding complex nonlinear operations at the hardware level.

[0069] 2. Hardware-friendly Surrogate Gradient Design

[0070] During the training phase of a neural network, calculating the derivative of the original function is often complex and can lead to gradient vanishing. This invention addresses this piecewise function by designing a specialized step-wise gradient replacement to adapt to hardware and stabilize training.

[0071]

[0072] In the linear region, the gradient is clamped to a constant. (like This ensures the stability of the gradient flow near the origin; in the decay region, the gradient decreases in a stepwise manner, with the value of each step strictly set to 0. The advantage of this design is that, during backpropagation, the product of the error term and the gradient can also be transformed into a dynamic shift operation. For example, when the gradient is... At this time, the hardware only needs to right-shift the returned error by 3 bits to complete the gradient weighting, thus realizing low power consumption throughout the training process.

[0073] like Figure 2 As shown, the Shift-DyT scheme in this embodiment employs an exponentially decaying gradient strategy for backpropagation to construct the alternative gradient. In the linear interval... Within the initial gradient, it is clamped to a constant to ensure stable error backpropagation; however, in the saturation regions on both sides, the gradient curve does not change continuously but descends discretely in a step-like manner, with the height of each step strictly corresponding to a power of 2. This discretized gradient shape not only effectively prevents gradient vanishing or exploding but also allows the gradient weighting operation in backpropagation to be transformed into an efficient dynamic shift operation.

[0074] 3. Overall Processing Flow

[0075] The specific implementation steps of the dynamic channel normalization method based on shift operation provided in this embodiment of the invention include:

[0076] Input acquisition steps: Receive the input feature tensor.

[0077] Interval discrimination steps: The absolute value of the input value is determined by a comparator to determine whether it is in the linear region or the decay region.

[0078] Parallel computation steps: If the region is identified as linear, the first shift logic (fixed right shift) is triggered; if the region is identified as decaying, the second shift logic (dynamic right shift) and interpolation logic are triggered.

[0079] Output steps: Recover the sign of the result based on the input sign bit, and output the normalized features.

[0080] The method (Shift-DyT scheme) proposed in this invention not only replaces the complex nonlinear function calculation with binary shift operations in the forward propagation (inference stage), but also introduces a hardware-friendly alternative gradient strategy in the backpropagation (training stage), achieving low-power computation throughout the entire process.

[0081] In one embodiment, the processing flow of a dynamic channel normalization method based on shift operations provided in this embodiment includes:

[0082] Phase 1: Forward Propagation

[0083] At this stage, input values ​​are received. That is, input features, and perform segmented shift logic according to their magnitude:

[0084] Step 1: Interval Determination and Preprocessing

[0085] First, calculate the absolute value of the input value. And extract symbols .Will With threshold The comparisons are made to determine the computation path.

[0086] Step 2: Linear region calculation (when hour)

[0087] If the input is determined to be in the linear region, a linear function is used. .

[0088] Hardware implementation: Setting the scaling factor In this embodiment, (Right now The normalization circuit directly performs an arithmetic right shift of 1 bit on the binary two's complement of the input data. This step completely replaces floating-point multiplication and consumes very little power.

[0089] Step 3: Calculation of the exponential decay region (when...) hour)

[0090] If the input is determined to be in the exponential decay region, perform shift-based interpolation calculation. .

[0091] Benchmark generation: Extracting the integer part Generate two baseline values:

[0092]

[0093] .

[0094] Linear interpolation: using the fractional part Weighting the benchmark values: The hardware implementation involves: Move right Position, will Move right Bit.

[0095] Output composition: calculation .

[0096] Phase Two: Backpropagation

[0097] To address the issue of piecewise functions being non-differentiable during training, this embodiment employs a specialized surrogate gradient during the backpropagation phase, ensuring that error backpropagation can also be accomplished through shift operations.

[0098] Step 4: Gradient Calculation and Error Backpropagation

[0099] When the network needs to update its weights, it should do so based on the input from the forward propagation. Calculate the gradient according to the following logic :

[0100] Case A (corresponding to the linear region) ):

[0101] Set the gradient value to a constant (Right now ).

[0102] Hardware operation: At this point, the returned error signal only needs to be shifted right by 1 bit to complete the gradient weighting.

[0103] Case B (corresponding to the attenuation region) ):

[0104] Set the gradient value to .

[0105] Hardware operation: For example, when the input is located When the interval is reached, the gradient value is... At this point, the hardware simply needs to right-shift the returned error signal by 3 bits.

[0106] By combining the two stages described above, this embodiment eliminates floating-point exponentiation and division operations during inference and replaces floating-point multiplication updates with dynamic shifting during training, thereby achieving efficient deployment and online learning of the neural network model on edge devices.

[0107] The application of this invention significantly reduces computational complexity and achieves extreme energy efficiency at the hardware level: compared with existing technologies that rely on the hyperbolic tangent function or involve mean / variance calculations, this invention constructs a system based on... The power-law decay model theoretically reduces the complexity of the normalization operation from exponential to exponential. Reduced to linear level The proposed solution transforms all multiplication, division, and exponentiation operations into basic shift, addition, and sign bit operations at the underlying hardware level, thereby completely eliminating the reliance on expensive floating-point units (FPUs). This optimization of the underlying operators significantly reduces chip area footprint and dynamic power consumption, making it easier to deploy deep neural network models in resource-constrained edge computing scenarios such as IoT (Internet of Things) devices, mobile terminals, and neuromorphic chips.

[0108] In one embodiment, the hardware processing flow of a digital circuit system based on the Shift-DyT scheme of the present invention specifically includes the following steps:

[0109] Step S1: Signal Reception and Format Definition

[0110] The system receives clock and reset signals, and receives... A signed fixed-point input signal, i.e. This represents the bit width of the input signal.

[0111] The input signal format is configured as follows: the highest bit is the sign bit, and the middle bit is the... The bits are integer bits, low-order bits. The decimal place is the number of decimal places. .

[0112] The output signal is defined as Bit width is used to output the normalized quantization result.

[0113] Step S2: Take the absolute value of the input signal

[0114] Absolute value extraction: Determine the sign of the input based on the sign bit. If negative, then extract the low-order bits of the input signal. The bitwise NOT operation is performed, followed by a increment; if the result is positive, it remains unchanged. This step generates... Amplitude signal with a bit width.

[0115] Step S3: Linear region shift

[0116] Based on the preset scaling factor Perform an arithmetic right shift directly on the input signal Bit operations ( This generates linear region candidate results. This operation corresponds mathematically to multiplying by a scaling factor. (or divided by) ),in, The preset scaling parameters for the linear region.

[0117] Step S4: Extracting interpolation parameters

[0118] The system extracts key parameters from the amplitude signal for piecewise fitting:

[0119] (1) Exponential shift factor extraction: extracting the high-amplitude signal. Bits as integer index That is, the integer part.

[0120] (2) Interpolation weight extraction: Extracting the low-amplitude signal. The digit is used as the decimal weight. That is, the decimal part.

[0121] (3) Calculation of complementary weights: weighting of decimals Perform a bitwise inversion and increment operation to generate complementary weights. .

[0122] Step S5: Generation of interval boundaries based on shift

[0123] Generate the upper and lower bound reference values ​​of the current interval using shift logic:

[0124] (1) Lower bound reference (Floor): Load the preset reference constant. (Corresponding to the base value of 1.0 in the fixed-point format or the preset scaling base), perform an arithmetic right shift. The lower bound signal is obtained by using the bit.

[0125] (2) Upper bound reference (Ceil): The reference constant is... Arithmetic right shift The upper bound signal is obtained by using the bit.

[0126] In this embodiment, this step is implemented entirely by a combinational logic shifter, utilizing shift operations to construct... Its exponential decay characteristic.

[0127] Step S6: Linear interpolation calculation

[0128] Linear fitting within an interval is achieved through shift operations and adders:

[0129] (1) Complementary weights Move right Bit.

[0130] (2) Weighting the decimals Move right Bit.

[0131] (3) Add the two shift results to generate the fitting result. At the same time, its negative form is generated according to the two's complement rule.

[0132] Step S7: Synthesis of results in the nonlinear region

[0133] Assemble the nonlinear region candidate results based on the original input sign bit:

[0134] If the input is negative, then the sign bit 1 will be added to the fitted result. Combine (or select its negative form);

[0135] If the input is positive, the sign bit 0 is combined with the negative form of the fitted result (or its positive form is selected).

[0136] Step S8: Threshold Decision and Output

[0137] Output logic: Based on the absolute value of the input signal, determine its left shift by 1. The result of the bit ( If the value of the result is less than the value of the result of the linear region in step 3, the result of the nonlinear region in step 7 will be output.

[0138] Meanwhile, for the training phase of the neural network, the digital circuit system in this embodiment is further configured with gradient backpropagation logic based on shift operations, specifically including the following steps:

[0139] Step S9: Gradient signal reception and state backtracking

[0140] The system receives the input gradient signal passed back from the next layer of the neural network, which is the same as the input signal:

[0141] The input signal format is configured as follows: the highest bit is the sign bit, and the middle bit is the sign bit. The bits are integer bits, low-order bits. The number of decimal places (where) ).

[0142] The output signal is defined as Bit width is used to output the normalized quantization result.

[0143] At the same time, the high amplitude signal is intercepted. Bits as integer part .

[0144] Step S10: Gradient shift factor decision

[0145] Based on the absolute value of the input signal, determine its relationship to a left shift of 1. The result of the bit ( The size relationship determines the scaling factor of the gradient, which is mapped to the number of bits in the shift operation. :

[0146] (1) Linear region shift factor: If the result is less than, the system selects the preset linear region constant. As the number of shifts ( This setting corresponds to the mathematical derivative. It is used to maintain the numerical stability of the gradient near the origin.

[0147] (2) Saturation region shift factor: If the result is greater than, the system selects the dynamically calculated value. As the number of shifts ( This setting corresponds to the step derivative in mathematics. This is used to simulate the gradient decay characteristics in the saturation region.

[0148] Step S11: Gradient weighting calculation based on shift

[0149] The execution unit receives the input gradient signal and the shift number determined in step S10. Perform an arithmetic right shift operation.

[0150] Step S12: Output gradient generation

[0151] The shifted signal is directly used as the output gradient and passed to the previous layer of the neural network.

[0152] Since the objective function (sigmoid / Tanh-like) fitted by this invention is a monotonically increasing function with a constant positive derivative, this step directly keeps the sign bit of the input gradient unchanged and only shifts and scales its magnitude to complete the backpropagation process.

[0153] This invention demonstrates significantly superior performance compared to traditional normalization methods in visual tasks: it not only boasts advantages in hardware efficiency but also exhibits excellent accuracy in practical regression vision tasks. Based on semantic segmentation ablation experiments conducted on the ADE20K dataset (a widely used dataset in computer vision, particularly in semantic segmentation tasks of images), as shown... Figure 3 As shown, this embodiment of the invention verifies the effectiveness of the proposed Shift-DyT scheme on a Spike-driven V3 architecture with 5 million (5M) parameters. To objectively verify performance, the experiment selected the Spiking Self-Attention (SSA) mechanism as the baseline control group of the prior art, and the Bipolar Self-Attention (BSA) mechanism as the integrated verification architecture of the Shift-DyT operator in this embodiment. The experiment comprehensively analyzes the interaction of three components: normalization method (Shift-DyT and BN), matrix product design including binary matrix product (BMP) and ternary matrix product (TMP), and row-stochasticity constraints (RSC).

[0154] Experimental data show that, compared to the baseline SSA configuration (using BN+BMP+no RSC) with a mean intersection-over-union (mIoU) score of 33.6%, the model using the optimal configuration of this invention (i.e., applying Shift-DyT+TMP+Softmax in the BSA architecture) achieves a score of 39.2% mIoU, representing a 5.6% overall performance leap. Furthermore, under the high-performance configuration of the BSA architecture (using TMP), when the fixed activation policy is Softmax, the model using traditional batch normalization (BN) has an mIoU of 36.8%, while the model with Shift-DyT reaches 39.2%. This means that, even without completely eliminating floating-point statistical calculations, this invention still achieves a significant 2.4% accuracy improvement. These results strongly demonstrate that while significantly simplifying the underlying computational complexity, this scheme enhances the model's feature representation ability in complex visual tasks by preserving channel specificity.

[0155] Meanwhile, the proposed solution effectively maintains channel specificity and solves the problem of channel homogenization. Existing technologies often lead to convergence of feature distributions across different channels, thereby reducing the model's ability to capture complex information. This invention successfully solves this problem through a piecewise shift fitting strategy. Figure 4 As shown in the experiment, the feature distributions (Q and K matrices) after Shift-DyT processing were analyzed. Significant differences in the statistical distributions and means were observed between channels 102 to 47. For example, in channel 56, the mean of the Q matrix was approximately -0.45, while the mean of the K matrix reached -3.27. Simultaneously, a large distribution difference was also observed between channel 102 (mean of Q matrix 2.82) and channel 28 (mean of Q matrix -1.84). These significant inter-channel differences demonstrate that the Shift-DyT scheme effectively preserves rich data feature diversity and avoids information loss due to computational simplification, thus achieving high-precision feature extraction with low hardware overhead.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0157] The above descriptions are merely some embodiments of the present invention. Those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A dynamic channel normalization method based on shift operations, characterized in that, Includes the following steps: Step 1: Receive the signed fixed-point input signal from the deep neural network for normalization operations, and define... This indicates the bit width of the input signal; the input signal format is as follows: the highest bit is the sign bit, the middle bit... The bits are integer bits, low-order bits. The decimal place is the number of decimal places. ; Define the bit width of the output signal as This is used to output the quantization result of the normalization operation; where the input data of the deep neural network is image data, text data, or audio data; Step 2, Generate For bit-width amplitude signals: the sign of the input signal is determined by the sign bit. If it is negative, the input signal is bit-inverted and incremented by one to obtain the amplitude signal; if it is positive, the input signal is directly used as the amplitude signal. Step 3, according to the preset scaling factor Perform an arithmetic right shift on the input signal Bitwise operations are used to generate linear region candidate results, where... The preset scaling parameters for the linear region; Step 4: Extract key parameters for piecewise fitting from the generated amplitude signal, including: Extracting the high amplitude signal Bits as integer index ; Extracting the low amplitude signal The digit is used as the decimal weight. ; Step 5, generate interval boundaries based on shift: Load the preset reference constant And perform an arithmetic right shift on it. The lower bound signal is obtained by using the bit position. For reference constant Arithmetic right shift The upper bound signal is obtained by using the bit position. Step 6, weighted by fractional number The weights of the upper bound signal are used with complementary weights. Assuming the lower bound signal as weights, linear interpolation is performed on the upper and lower bound signals to generate the fitting result. And generate fitting results according to the two's complement rule. The negative form; Step 7: Generate candidate results for the nonlinear region based on the sign bit of the input signal. If it is negative, then the sign bit 1 will be compared with the fitting result. Combine to generate alternative results in the nonlinear region; or combine the fitted results Negative values ​​are used as candidate results for the nonlinear region. If positive, then the sign bit 0 is set to the fitted result. The negative values ​​are combined to generate alternative results for the nonlinear region; or the fitting results are used to generate alternative results for the nonlinear region. The positive form is used as the candidate result for the nonlinear region; Step 8: Based on the absolute value of the input signal, use a comparator to determine if it is equal to 1 shifted left. The result of the bit is determined by the size relationship. If it is smaller than the result of the linear region in step 3, the candidate result of the linear region in step 3 is output; otherwise, the candidate result of the nonlinear region in step 7 is output.

2. The dynamic channel normalization method based on shift operations as described in claim 1, characterized in that, It also includes step 9, gradient backpropagation processing based on shift operations for deep neural network training, specifically including: Step 901: Receive the input gradient signal returned from the next layer of the neural network. This gradient signal has the same signal format as the input signal. Step 902: Based on the absolute value of the input signal, determine its left shift by 1 using a comparator. The magnitude of the result is determined by the relationship between the bits. If the result is less than the preset linear constant, then the linear constant will be applied. As the number of shifts Otherwise, As the number of shifts ; Step 903, based on the number of shift bits Perform an arithmetic right shift operation on the gradient signal; Step 904: The shifted gradient signal is passed as the output gradient to the previous layer of the neural network.

3. The dynamic channel normalization method based on shift operations as described in claim 1, characterized in that, In step 3, the linear region scaling parameter is adjusted. Set to 1.

4. The dynamic channel normalization method based on shift operations as described in claim 3, characterized in that, In step 3, the binary two's complement of the input signal is shifted right by 1 bit using an arithmetic right shifter.

5. The dynamic channel normalization method based on shift operations as described in claim 1, characterized in that, In step 5, the reference constant Set to 1 and shift left Bit.

6. The dynamic channel normalization method based on shift operations as described in claim 1, characterized in that, In step 7, the candidate results for the nonlinear region are: ,in, Indicates the input signal. Represents a symbolic function.

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