Parallel receiving processing device and method for multi-system signals based on dynamic configuration

Abstract

The application relates to the technical field of communication signal processing, and provides a parallel receiving and processing device and method for multi-system signals based on dynamic configuration, wherein through the cooperative design of a data receiving module, a channel scheduling module, a tracking despreading module and a decoding module, a limited number of general signal processing channels are designed into a dynamic channel resource pool, dynamic allocation and recovery according to decoding results are supported, the decoupling of channels and signal systems is realized, and the resource utilization rate is greatly improved. A hardware scheduling module is realized in an FPGA, fast scheduling and parameter configuration are realized. The scheduling strategy is flexibly configured, the priority allocation of channel resources of key signals is guaranteed, each general channel is designed in a parameterized mode, different system signals can be seamlessly switched, FPGA logic does not need to be reconfigured, parallel tracking and despreading are realized, signal receiving and processing with multiple systems, multiple channels, high concurrency and low resource occupation can be realized in a single machine, and the system reliability is improved.

Description

Technical Field

[0001] This invention belongs to the field of communication signal processing technology, and relates to a device and method for parallel reception and processing of multi-mode signals based on dynamic configuration. Background Technology

[0002] With the rapid development of communication technology, various communication systems have emerged, such as terrestrial mobile communication, BeiDou short message service, Tiantong-1 and low-orbit satellite Internet of Things system. These communication systems each adopt different signal systems, including different spreading code sequences / generator polynomials, different modulation methods (BPSK, QPSK / OQPSK, etc.), different channel coding (convolutional codes, Turbo codes, LDPC / RS codes), and different message arrangement and frame structure.

[0003] In scenarios involving concurrent reception of multiple signal systems, a single receiving device only supports one signal system. Multi-system reception requires stacking multiple receiving devices, resulting in higher size, power consumption, and cost, as well as poor integration. Such receiving devices are essentially single-system dedicated devices. Furthermore, the entire receiving device is hard-bound to the signal type, making channel-level dynamic scheduling impossible. When there is a sudden increase in signals of a certain system, its dedicated channel cannot meet the demand, while channels for other systems remain idle. This leads to low resource utilization and difficulty in adapting to sudden concurrent access of multiple systems. In other words, such receiving devices have fixed channel binding.

[0004] While existing technologies include FPGA multi-channel processing and DSP decoding acceleration solutions, none of them have solved the coordination problems of parallel tracking and despreading of heterogeneous signals of multiple systems, dynamic scheduling of channel resources pooling, and time-division multiplexing of decoding modules. They cannot achieve signal reception and processing of multiple systems, multiple channels, high concurrency, and low resource consumption in a single machine. Summary of the Invention

[0005] To address the problems existing in the above-mentioned traditional methods, this invention proposes a multi-system parallel signal reception and processing method and a multi-system parallel signal reception and processing device based on dynamic configuration, which can realize multi-system, multi-channel, high-concurrency and low-resource-consumption signal reception and processing in a single machine.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] On the one hand, a method for parallel reception and processing of multi-mode signals based on dynamic configuration is provided, including the following steps:

[0008] The data receiving module receives baseband sampling data sent by each front-end capture unit through the switch and carrying capture information via a standardized high-speed interface, and buffers the baseband sampling data in different FIFOs according to the sampling data encapsulation protocol.

[0009] After parsing the baseband sampling data packets read from the FIFO, the channel scheduling module selects the optimal channel from the idle channel pool according to the preset scheduling strategy and allocates it to the data packets. It reads the complete channel configuration parameters according to the signal system index of the data packets, configures the optimal channel, issues a start command, and monitors and reclaims the channel status.

[0010] The tracking and despreading module performs carrier tracking, code tracking, despreading, and demodulation on the optimal channel and outputs the symbol coherence accumulation value. The tracking and despreading module consists of P general-purpose signal processing channels inside the FPGA. According to the operating parameters configured by the DSP through the channel configuration bus, the general-purpose signal processing channels are modified into signal processing channels of different signal systems, where P is the total number of signal processing channels.

[0011] The time-division multiplexing internal scheduler of the decoding module executes in a round-robin fashion according to fixed time slots, sequentially reading data from the decoding input buffer of each channel for decoding; the data receiving module, channel scheduling module, and tracking despreading module are deployed in the FPGA, and the decoding module is deployed in the DSP. The DSP completes CRC check and message framing, and sends a channel release command to the channel scheduling module.

[0012] In one embodiment, the format of the sampling data encapsulation protocol includes a frame header, version number, device number, VLAN number, week count, week seconds, signal type, number of synchronization headers, synchronization header k start position, synchronization header k Doppler frequency offset, synchronization header k signal strength, sampling data byte length, sampling data, and CRC32.

[0013] In one embodiment, the channel scheduling module maintains a channel status table containing P entries to record the channel status of each channel;

[0014] Each entry includes the following fields:

[0015] The channel state (state), the current allocation system type (body_type), the allocation start position (start_pos), the allocation time stamp (assign_time), the timeout counter (timeout_cnt), the current task priority, and whether the DSP has finished processing the channel's decoding (dsp_handled) are all included. The channel state (state) is used to describe the state transition of each channel.

[0016] Each signal system includes spreading code correlation parameters, carrier tracking loop parameters, code tracking loop parameters, and signal demodulation parameters.

[0017] In one embodiment, the preset scheduling strategy includes round-robin scheduling and priority scheduling;

[0018] Among them, priority scheduling adopts a priority definition based on the sampled data source. The scheduling engine of the channel scheduling module starts from the highest priority sub-queue. If the highest priority sub-queue is not empty, it takes the request at the head of the queue and tries to allocate the channel. If the allocation is successful, the request at the head of the queue is removed from the highest priority sub-queue. If the allocation fails, the request at the head of the queue remains at the head of the queue and waits for the next scheduling.

[0019] In one embodiment, if a waiting request waits in the queue for more than a set time threshold, the scheduling engine automatically raises the priority of the waiting request by one level.

[0020] On the other hand, a multi-mode signal parallel receiving and processing device based on dynamic configuration is also provided, including:

[0021] The data receiving module is used to receive baseband sampling data sent by each front-end capture unit through the switch and carrying capture information via a standardized high-speed interface, and to buffer the baseband sampling data in different FIFOs according to the sampling data encapsulation protocol.

[0022] The channel scheduling module is used to parse the data packets of baseband sampling data read from the FIFO, select the optimal channel from the idle channel pool according to the preset scheduling strategy and allocate it to the data packets, read the complete channel configuration parameters according to the signal system index of the data packets and configure the optimal channel to issue a start command, and monitor and reclaim the channel status.

[0023] The tracking and despreading module is used to complete carrier tracking, code tracking, despreading and demodulation of the optimal channel and output the symbol coherence accumulation value. The tracking and despreading module consists of P general signal processing channels inside the FPGA. According to the operating parameters configured by the DSP through the channel configuration bus, the general signal processing channels are modified into signal processing channels of different signal systems, where P is the total number of signal processing channels.

[0024] The decoding module is used by the time-division multiplexing internal scheduler to execute in a round-robin fashion according to fixed time slots, sequentially reading data from the decoding input buffer of each channel for decoding; the data receiving module, channel scheduling module, and tracking despreading module are deployed in the FPGA, while the decoding module is deployed in the DSP. The DSP completes CRC verification and message framing, and sends a channel release command to the channel scheduling module.

[0025] One of the above technical solutions has the following advantages and beneficial effects:

[0026] The aforementioned parallel reception and processing device and method for multi-mode signals based on dynamic configuration, through the collaborative design of the data reception module, channel scheduling module, tracking despreading module, and decoding module, designs a limited number of general-purpose signal processing channels as a dynamic channel resource pool. This supports dynamic allocation and recycling based on decoding results, achieving decoupling between channels and signal modes and significantly improving resource utilization. A hardware scheduling module is implemented within the FPGA to handle acquisition result parsing, idle channel selection, full parameter loading, and start command issuance, meeting the real-time requirements of short burst signals and enabling rapid scheduling and parameter configuration. Flexible scheduling strategies ensure priority allocation of channel resources for critical signals. Each general-purpose channel employs a parameterized design, dynamically loading spreading code parameters, loop parameters, and demodulation parameters to seamlessly switch between processing different signal modes without requiring FPGA logic refactoring. This achieves parallel tracking despreading, enabling multi-mode, multi-channel, high-concurrency, and low-resource-consumption signal reception and processing within a single unit, improving system reliability. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a block diagram of the module architecture of a dynamically configured multi-system signal parallel receiving and processing device in one embodiment.

[0029] Figure 2 This is a schematic diagram of the signal processing channel resource pool and scheduling in one embodiment;

[0030] Figure 3 This is a schematic diagram of channel state transitions in one embodiment;

[0031] Figure 4 This is a schematic diagram of the overall signal processing flow of a dynamically configured multi-mode signal parallel receiving and processing device in one embodiment.

[0032] Figure 5 This is a flowchart illustrating a method for parallel reception and processing of multi-mode signals based on dynamic configuration in one embodiment. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0034] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0035] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0036] In one embodiment, such as Figure 1 As shown, a multi-mode signal parallel reception and processing device based on dynamic configuration is provided, which may include a data receiving module 11, a channel scheduling module 13, a tracking despreading module 15, and a decoding module 17. The data receiving module 11 receives baseband sampling data carrying capture information sent by each front-end acquisition unit through a switch via a standardized high-speed interface, and buffers the baseband sampling data in different FIFOs according to the sampling data encapsulation protocol. The channel scheduling module 13 reads the baseband sampling data packets from the FIFOs, parses them, selects the optimal channel from the idle channel pool according to a preset scheduling strategy, allocates the optimal channel to the data packets, reads the complete channel configuration parameters according to the signal mode index of the data packets, configures the optimal channel, issues a start command, and monitors and reclaims the channel status.

[0037] The tracking and despreading module 15 is used to complete carrier tracking, code tracking, despreading, and demodulation for the optimal channel, and outputs the symbol coherence accumulation value. The tracking and despreading module consists of P general-purpose signal processing channels inside the FPGA. According to the operating parameters configured by the DSP through the channel configuration bus, the general-purpose signal processing channels are modified into signal processing channels of different signal systems, where P is the total number of signal processing channels. The decoding module 17 is used by the time-division multiplexing internal scheduler to execute in a round-robin fashion according to fixed time slots, and reads data from the decoding input buffer of each channel for decoding in sequence. The data receiving module 11, the channel scheduling module 13, and the tracking and despreading module 15 are deployed in the FPGA, and the decoding module 17 is deployed in the DSP. The DSP completes CRC check and message framing, and sends a channel release command to the channel scheduling module.

[0038] It is understood that this embodiment adopts a heterogeneous collaborative architecture of DSP+FPGA. The FPGA is responsible for the resource scheduling of multi-channel and multi-system signal channels and parallel tracking and despreading; the DSP is responsible for channel decoding, message parsing, decoding time-division multiplexing scheduling and data post-processing.

[0039] like Figure 1 As shown, the designed device includes the following key modules: a data receiving module, a channel scheduling module, a tracking despreading module, and a decoding module. The data receiving module, channel scheduling module, and tracking despreading module are deployed in an FPGA, while the decoding module is deployed in a DSP.

[0040] Data receiving module: The data receiving module is the signal input of the device. It is used to receive baseband sampling data from M front-end capture units sent through the switch and carrying capture information through a standardized high-speed interface. According to the unit identification of each front-end capture unit, such as the number or VLAN number, the baseband sampling data from different front-end capture units is buffered in different FIFOs (first-in, first-out queues).

[0041] The channel scheduling module is the core hub connecting the data receiving module and the system's signal processing channel resource pool. It is used for dynamic allocation, parameter configuration, status monitoring, and recycling of signal processing channels, achieving millisecond-level fast scheduling, efficient resource utilization, and flexible adaptation to multiple systems. Figure 2 As shown. Specifically, the channel scheduling module reads baseband sampled data packets from each FIFO of the data receiving module and extracts key information (such as signal system, synchronization header start position, Doppler estimation and signal strength, etc.) in a polling or interrupt manner.

[0042] The tracking and despreading module consists of P general-purpose signal processing channels within the FPGA. Since the hardware structure of each signal processing channel within the FPGA (such as mixers, correlators, NCOs, and loop filters) is fixed and general, it can cover the common processing requirements of all target signal systems. What needs to be changed are the operating parameters of these modules, including: the frequency control word of the carrier NCO, the code rate control word of the code NCO, the generator polynomial or code table address of the local code generator, the coefficients of the loop filter, the integration length for clearing the integral, and the modulation scheme configuration of the demodulation module (such as BPSK / QPSK / OQPSK switching). These operating parameters are all stored in the channel's configuration register group and can be modified at any time by the DSP through the channel configuration bus. After modifying the operating parameters, the channel will operate according to the new operating parameters upon the next startup, without needing to refactor the FPGA hardware logic. This allows the signal processing channels to seamlessly switch between processing different signal systems in real time.

[0043] It is important to note that when implementing FPGA, resources need to be reserved according to the maximum requirements, including: the code table RAM capacity is set according to the longest spreading code, and only a portion of the storage space is needed for short codes; the number of taps of the matched filter is instantiated according to the maximum code length, and the actual number of taps used is controlled by the enable signal; the phase accumulator bit width of the carrier NCO is sufficient to cover the frequency resolution requirements of all systems; the loop filter uses parameterized coefficient settings to support dynamic bandwidth adjustment.

[0044] This design philosophy of reserving resources and dynamic configuration enables a single hardware channel to cover multiple systems. When switching, only the register values ​​of the configuration register group need to be updated, without the need for rewiring or loading a new bit stream.

[0045] To conserve processing resources, the decoding module employs a time-division multiplexing mechanism. This mechanism works as follows: the decoding module allocates an independent buffer for each channel to store the demodulated bitstream; the decoder's scheduler operates in a round-robin fashion, using fixed time slots (e.g., 1ms / slot): it reads the buffer data for the current channel, loads the corresponding decoding algorithm and parameters, executes the decoding and verification, outputs the message, and marks the channel as decoded; higher-priority channels can preempt decoding time slots; after decoding is complete, the decoding module sends a reclaim instruction to the scheduler to release decoding resources.

[0046] The aforementioned parallel reception and processing device for multi-mode signals based on dynamic configuration, through the collaborative design of the data receiving module 11, channel scheduling module 13, tracking and despreading module 15, and decoding module 17, designs a limited number of general-purpose signal processing channels as a dynamic channel resource pool. This supports dynamic allocation and recycling based on decoding results, achieving decoupling between channels and signal modes and significantly improving resource utilization. A hardware scheduling module is implemented within the FPGA to complete acquisition result parsing, idle channel selection, loading of all parameters, and issuance of start commands, meeting the real-time requirements of short burst signals and enabling rapid scheduling and parameter configuration. Flexible configuration using scheduling strategies ensures priority allocation of channel resources for critical signals. Each general-purpose channel adopts a parameterized design, and by dynamically loading spreading code parameters, loop parameters, and demodulation parameters, it can seamlessly switch between processing different signal modes without refactoring the FPGA logic, achieving parallel tracking and despreading. This enables multi-mode, multi-channel, high-concurrency, and low-resource-occupancy signal reception and processing within a single unit, improving system reliability.

[0047] In one embodiment, for baseband sampling data packets, this embodiment also proposes a sampling data encapsulation protocol with capture information based on UDP (User Datagram Protocol). The format of the sampling data encapsulation protocol is shown in Table 1:

[0048] Table 1

[0049]

[0050] Frame header: Fixed pattern, used by the receiver to identify the start position of the packet.

[0051] Version number: Identifies the protocol version.

[0052] Device Number: The device number that identifies the front-end capture unit.

[0053] VLAN ID: Identifies which front-end capture unit the packet originated from.

[0054] Week count: Indicates the week number of the data packet.

[0055] Weekly seconds: The number of seconds accumulated starting from midnight on Sunday of this week, indicating the specific time within this week.

[0056] Signal type: Identifies the signal type of the data sampled in this data packet.

[0057] Synchronization header count: Identifies the number of synchronization headers detected within this data packet (only counting the number of synchronization headers whose starting positions are within the sampling point of this data packet). Based on the chip rate R... chip Sampling rate R sampling Given the number of sampling points n in each data packet, the maximum number of synchronization headers m can be calculated:

[0058] .

[0059] Synchronization header k starting position: Identifies the starting sampling point number of the kth synchronization header. If the number of synchronization headers in this data packet is less than m, fill in "FF".

[0060] Synchronization Header k Doppler Frequency Offset: Indicates the Doppler frequency offset of the kth synchronization header. If the number of synchronization headers in this data packet is less than m, fill in "FF".

[0061] Synchronization header k signal strength: Indicates the signal strength of the kth synchronization header. If the number of synchronization headers in this data packet is less than m, fill in "FF".

[0062] Sample data byte length: The total number of bytes in the "sample data" section of this packet.

[0063] Sampling data: I / Q samples arranged continuously in order of channel number, including alternating sampling point I branch and sampling point Q branch, with sampling point I branch being continuous or sampling point Q branch being continuous.

[0064] CRC32: Performs CRC check on the entire packet to ensure correct transmission.

[0065] The channel scheduling module maintains a channel status table with P entries (P being the total number of signal processing channels) to record the channel status of each channel. Furthermore, each entry contains the following fields as shown in Table 2:

[0066] Table 2

[0067]

[0068] The transition conditions between the states of each channel are as follows: Figure 3 As indicated by the middle arrow, the specific descriptions of the state transitions for each channel are as follows:

[0069] IDLE→ALLOC, trigger condition: The channel scheduling module retrieves a capture request from the pending request queue and selects the current channel (the corresponding idle channel described by IDLE) for allocation. At this time, configuration parameters are written to the current idle channel.

[0070] ALLOC→DEMOD, trigger condition: all channel configuration parameters are written to the current channel, the channel scheduling module issues a start command, transmits the starting position and Doppler estimation, so that the current channel starts tracking the demodulated signal from the specified time.

[0071] DEMOD→WAIT_DSP, trigger condition: The current channel completes the demodulation of the entire signal (or reaches the preset end condition), sends the symbol coherent cumulative value data to the DSP through the high-speed interface, and notifies the channel scheduling module. The current channel enters the waiting state for DSP decoding.

[0072] DEMOD→LOST, trigger condition: During demodulation, when the timeout monitoring unit configured inside the channel scheduling module finds that the current channel occupancy time exceeds the preset threshold (e.g., the burst signal should have ended but has not), or when the current channel reports a lost-lock status (carrier loop lost-lock, correlation value too low), the current channel is marked as abnormal.

[0073] WAIT_DSP→RELEASE, Triggering condition: After the DSP completes the soft bit decoding of the current channel, it sends a channel release command to the channel scheduling module. The channel scheduling module sets the current channel to the released state and begins a hardware reset.

[0074] WAIT_DSP→LOST, trigger condition: During the waiting period for DSP decoding, if the timeout monitoring unit finds that the waiting time exceeds the threshold (e.g., DSP processing congestion or communication failure), the current channel is marked as abnormal.

[0075] RELEASE→IDLE, trigger condition: When the current channel completes hardware reset and FIFO clearing and other cleanup operations, the state machine returns to idle, and the current channel is added back to the idle channel pool in the signal processing channel resource pool, so that the current channel can be reassigned.

[0076] LOST→IDLE, trigger condition: Force recycling (such as reset) is performed on the channel in the LOST state, and the channel is set to idle after completion.

[0077] The channel scheduling module selects the optimal channel from the idle channel pool according to a preset scheduling strategy; the scheduling strategy includes round-robin scheduling and priority scheduling. Optionally, the scheduling strategy can adopt the following methods:

[0078] Round-robin scheduling is a simple and fair channel allocation strategy. All captured signal requests are treated equally. The channel scheduling module iterates through the idle channel pool in a fixed order, assigning the next detected idle channel to the currently pending data packet. This strategy does not distinguish between data sources, signal types, or signal strengths, and is suitable for scenarios where channel load balancing is required and there are no special priority requirements.

[0079] Priority scheduling assigns different priorities to different data packets based on the importance or urgency of the signal. The channel scheduling module allocates idle channels preferentially to high-priority requests. This strategy is suitable for scenarios with Quality of Service (QoS) requirements and where it is necessary to ensure the priority processing of critical signals, such as emergency communications and command and dispatch.

[0080] Priority definitions can be flexibly configured according to actual business needs. Common methods include priority definitions based on signaling systems, as shown in Table 3:

[0081] Table 3

[0082]

[0083] In some implementations, different data sources (such as satellites, beams, or regions) may have different levels of importance, so a priority definition based on the sampled data source can also be used, as shown in Table 4:

[0084] Table 4

[0085]

[0086] To implement priority scheduling, the queue of pending requests, which stores all requests waiting to be processed, is organized into multiple priority sub-queues (each priority corresponds to a FIFO). After the capture result is parsed, it is placed into the corresponding priority sub-queue according to its priority. The scheduling engine of the channel scheduling module starts from the highest priority sub-queue. If the priority sub-queue is not empty, it retrieves the request at the head of the queue and attempts to allocate a channel; if the allocation is successful, the request at the head of the queue is removed from the priority sub-queue; if the allocation fails (no free channel), the request at the head of the queue remains at the head of the queue, waiting for the next scheduling. The next highest priority sub-queue is only processed when the high-priority sub-queue is empty.

[0087] In one embodiment, optionally, to prevent low-priority requests from being unserviced for a long time, an aging mechanism can be introduced: if a waiting request waits in the queue for more than a set time threshold, the scheduling engine automatically raises its priority by one level and then puts it back into the waiting process until the highest priority.

[0088] The channel scheduling module reads the complete channel configuration parameters from the signal system parameter table based on the signal system index in the captured data packet; it then sends the parameters to the configuration register of the corresponding channel via the channel configuration bus. Once the channel configuration parameters are written, the channel is capable of processing signals of that system. After all channel configuration parameters have been written, the signal processing channel resource pool returns a "configuration complete" flag to the scheduling engine. Upon receiving the "configuration complete" flag, the scheduling engine enters the channel startup phase.

[0089] Specifically, each signal system includes spreading code related parameters, carrier tracking loop parameters, code tracking loop parameters, and signal demodulation parameters, as shown in Tables 5 to 8. The signal system parameter tables are stored in the Block RAM (Block Random Access Memory) inside the FPGA and are dynamically updated by the DSP during initialization or operation.

[0090] Table 5

[0091]

[0092] Table 6

[0093]

[0094] Table 7

[0095]

[0096] Table 8

[0097]

[0098] After configuring the parameters, the channel scheduling module sends a start command to the currently selected target channel, simultaneously transmitting the start position of the baseband sampling data packet and the Doppler estimate. The start command can be implemented via a dedicated control line or a specific register bit in the channel configuration bus.

[0099] Specifically, the channel startup process can be as follows:

[0100] Upon receiving the start command, the target channel loads the start position of the data packet into the local sampling point counter comparator. It converts the Doppler estimate of the data packet into the initial value of the carrier NCO (Numerically Controlled Oscillator) frequency control word and loads it into the NCO. The channel continuously receives the baseband sampled data stream. When the local counter matches the start position, it begins reading data from the FIFO (or directly from the broadcast bus), entering the tracking and demodulation state.

[0101] After the DSP completes decoding, it sends a channel release command (including the channel number) to the channel scheduling module. The channel scheduling module sets the channel status of the channel corresponding to the channel release command to IDLE, updates the channel status, and reclaims the channel into the idle channel pool.

[0102] The channel scheduling module collects statistics on channel allocation success rate, allocation failure rate (no available channels), channel anomaly rate, channel utilization rate (cumulative occupied time), and average scheduling delay, providing channel monitoring information for system monitoring and dynamic optimization.

[0103] In some implementations, such as Figure 4As shown, this example also illustrates the complete signal processing flow that the above-mentioned device can be used for corresponding implementations:

[0104] (1) System initialization phase: The DSP reads the system configuration from the non-volatile memory. The system configuration includes the spreading code related parameters, carrier tracking loop parameters, code tracking loop parameters, and signal demodulation parameters for each signal system, and writes them into the signal system parameter table in the FPGA. The scheduling policy register used to store the scheduling strategy is set to the default value (such as round-robin scheduling). All channel status tables are set to IDLE.

[0105] (2) The data receiving module receives multiple baseband sampling data carrying capture information in parallel through the network port or optical port.

[0106] (3) The channel scheduling module receives the baseband sampling data packets (i.e., sampling results), parses them, and places them into the corresponding pending request queue according to priority. Then, according to the current scheduling policy, the channel scheduling module retrieves the request from the highest priority pending request queue and queries the idle channel pool. If an idle channel is found as the target channel, the corresponding parameters are read from the signal system parameter table, written to the register of the target channel through the channel configuration bus, and a start command is issued to the target channel. At the same time, the channel status of the target channel is set to DEMOD. If no idle channel can be allocated, the request remains in the queue to wait or is discarded according to the scheduling policy.

[0107] (4) The tracking and despreading module quickly starts the tracking channel, completes carrier tracking, code tracking, despreading and demodulation, and outputs symbol coherence accumulation value.

[0108] (5) The FPGA sends the symbolic coherent cumulative value to the DSP through the SRIO / PCIe interface, along with information such as signal type and channel number.

[0109] (6) After receiving the symbol coherent cumulative value, the DSP puts it into the decoding input buffer of the corresponding target channel. The time-division multiplexing internal scheduler of the decoding module executes in a round-robin fashion according to fixed time slots, reads data from the decoding input buffer of each channel in sequence, and calls the corresponding decoding algorithm to perform decoding.

[0110] (7) After decoding, the DSP completes CRC check and message framing, and sends a channel release command (including channel number) to the channel scheduling module, setting the channel status of the corresponding channel to IDLE.

[0111] (8) The channel scheduling module continuously updates the timeout counter, which can be read by the DSP at any time for status monitoring.

[0112] It should be noted that the specific signal processing implementations in the above embodiments, such as carrier tracking, code tracking, despreading, demodulation, outputting symbol coherent cumulative value, CRC check and message framing, can be understood by referring to the corresponding signal processing processes already existing in the field, and will not be elaborated in detail in this specification.

[0113] By dynamically pooling channel resources, a limited number of general-purpose signal processing channels are pooled together. These channels are dynamically allocated and reclaimed based on decoding results, decoupling them from the signal processing architecture and significantly improving resource utilization. A hardware scheduling module is implemented within the FPGA to handle acquisition result parsing, idle channel selection, loading of all parameters, and issuance of start commands. This meets the real-time requirements of short burst signals, enabling rapid scheduling and parameter configuration. A multi-priority scheduling strategy is employed, supporting polling, signal processing architecture-based priority, data source-based priority, and hybrid scheduling strategies. This allows for flexible configuration and ensures priority allocation of channel resources for critical signals. Each general-purpose channel is parametrically designed. By dynamically loading spreading code parameters, loop parameters, and demodulation parameters, it can seamlessly switch between processing different signal processing architectures without refactoring the FPGA logic, achieving parallel tracking and despreading.

[0114] A sampling data caching mechanism was designed, with an independent input FIFO for each channel to buffer the sampling data sent from the baseband data allocation module, and supporting precise start-up from the starting position. Multiple channels share a single decoding core (such as Turbo, Polar, and LDPC decoders), processing the soft bit data of each channel sequentially through time-division multiplexing, achieving time-division multiplexing of decoding and significantly reducing decoding resource consumption. Furthermore, status monitoring and anomaly handling were improved, with real-time monitoring of channel status and mechanisms for timeout recovery and lockout handling, enhancing system reliability.

[0115] Through the above design, a single receiving device can be compatible with multiple signal systems, replacing multiple dedicated units and achieving multi-system single-unit integration, which significantly reduces the size, power consumption and cost of the device; it supports dynamic channel scheduling, and can be allocated when idle, realizing efficient resource pooling and greatly improving resource utilization; when adding a new signal system, only the corresponding parameter table and decoding library need to be updated, without changing the hardware architecture, which has strong scalability.

[0116] Each module in the aforementioned multi-mode signal parallel receiving and processing device based on dynamic configuration can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of a device with data processing capabilities, or stored in software within the memory of the aforementioned device, so that the processor can call and execute the operations corresponding to each module. The aforementioned device can be, but is not limited to, various types of computer devices already existing in the art.

[0117] In one embodiment, such as Figure 5As shown, a method for parallel reception and processing of multi-mode signals based on dynamic configuration is provided, which may include the following processing steps S10 to S16:

[0118] S10, the data receiving module receives baseband sampling data sent by each front-end capture unit through the switch and carrying capture information through a standardized high-speed interface, and caches the baseband sampling data in different FIFOs according to the sampling data encapsulation protocol;

[0119] S12, after parsing the data packets of baseband sampling data read from the FIFO, the channel scheduling module selects the optimal channel from the idle channel pool according to the preset scheduling strategy and allocates it to the data packets. It reads the complete channel configuration parameters according to the signal system index of the data packets and configures the optimal channel to issue a start command. It also monitors and reclaims the channel status.

[0120] S14, the tracking and despreading module completes carrier tracking, code tracking, despreading and demodulation for the optimal channel and outputs symbol coherence accumulation value; the tracking and despreading module consists of P general signal processing channels inside the FPGA, and modifies the general signal processing channels into signal processing channels of different signal systems according to the operating parameters configured by the DSP through the channel configuration bus, where P is the total number of signal processing channels;

[0121] S16, the time-division multiplexing internal scheduler of the decoding module executes in a round-robin fashion according to fixed time slots, sequentially reading data from the decoding input buffer of each channel for decoding; the data receiving module, channel scheduling module and tracking despreading module are deployed in the FPGA, the decoding module is deployed in the DSP, the DSP completes CRC check and message framing, and sends a channel release command to the channel scheduling module.

[0122] The aforementioned parallel reception and processing method for multi-mode signals based on dynamic configuration, through the collaborative design of the data reception module, channel scheduling module, tracking despreading module, and decoding module, designs a limited number of general-purpose signal processing channels as a dynamic channel resource pool. This supports dynamic allocation and recycling based on decoding results, achieving decoupling between channels and signal modes and significantly improving resource utilization. A hardware scheduling module is implemented within the FPGA to handle acquisition result parsing, idle channel selection, full parameter loading, and start command issuance, meeting the real-time requirements of short burst signals and enabling rapid scheduling and parameter configuration. Flexible scheduling strategies ensure priority allocation of channel resources for critical signals. Each general-purpose channel employs a parameterized design, dynamically loading spreading code parameters, loop parameters, and demodulation parameters to seamlessly switch between processing different signal modes without requiring FPGA logic refactoring. This achieves parallel tracking despreading, enabling multi-mode, multi-channel, high-concurrency, and low-resource-consumption signal reception and processing within a single machine, improving system reliability.

[0123] In one embodiment, the format of the sampling data encapsulation protocol includes a frame header, version number, device number, VLAN number, week count, week seconds, signal type, number of synchronization headers, synchronization header k start position, synchronization header k Doppler frequency offset, synchronization header k signal strength, sampling data byte length, sampling data, and CRC32.

[0124] In one embodiment, the channel scheduling module maintains a channel status table containing P entries to record the channel status of each channel;

[0125] Each entry includes the following fields:

[0126] The channel state (state), the current allocation system type (body_type), the allocation start position (start_pos), the allocation time stamp (assign_time), the timeout counter (timeout_cnt), the current task priority, and whether the DSP has finished processing the channel's decoding (dsp_handled) are all included. The channel state (state) is used to describe the state transition of each channel.

[0127] Each signal system includes spreading code correlation parameters, carrier tracking loop parameters, code tracking loop parameters, and signal demodulation parameters.

[0128] In one embodiment, the preset scheduling strategy includes round-robin scheduling and priority scheduling;

[0129] Among them, priority scheduling adopts a priority definition based on the sampled data source. The scheduling engine of the channel scheduling module starts from the highest priority sub-queue. If the highest priority sub-queue is not empty, it takes the request at the head of the queue and tries to allocate the channel. If the allocation is successful, the request at the head of the queue is removed from the highest priority sub-queue. If the allocation fails, the request at the head of the queue remains at the head of the queue and waits for the next scheduling.

[0130] In one embodiment, if a waiting request waits in the queue for more than a set time threshold, the scheduling engine automatically raises the priority of the waiting request by one level.

[0131] It is understood that the specific limitations of the above-mentioned multi-system signal parallel reception and processing device based on dynamic configuration can be found in the corresponding limitations of the multi-system signal parallel reception and processing method based on dynamic configuration mentioned above, and will not be repeated here.

[0132] It should be understood that, although Figure 5 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 5At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0133] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus DRAM (RDRAM), and interface DRAM (DRDRAM), etc.

[0134] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A method for parallel reception and processing of multi-mode signals based on dynamic configuration, characterized in that, Including the following steps: The data receiving module receives baseband sampling data sent by each front-end capture unit through the switch and carrying capture information via a standardized high-speed interface, and buffers the baseband sampling data in different FIFOs according to the sampling data encapsulation protocol. After parsing the baseband sampling data packets read from the FIFO, the channel scheduling module selects the optimal channel from the idle channel pool according to the preset scheduling strategy and allocates it to the data packets. It reads the complete channel configuration parameters according to the signal system index of the data packets, configures the optimal channel, issues a start command, and monitors and reclaims the channel status. The tracking and despreading module performs carrier tracking, code tracking, despreading, and demodulation on the optimal channel and outputs the symbol coherence accumulation value. The tracking and despreading module consists of P general-purpose signal processing channels inside the FPGA. According to the operating parameters configured by the DSP through the channel configuration bus, the general-purpose signal processing channels are modified into signal processing channels of different signal systems, where P is the total number of signal processing channels. The time-division multiplexing internal scheduler of the decoding module executes in a round-robin fashion according to fixed time slots, sequentially reading data from the decoding input buffer of each channel for decoding; the data receiving module, channel scheduling module, and tracking despreading module are deployed in the FPGA, and the decoding module is deployed in the DSP. The DSP completes CRC check and message framing, and sends a channel release command to the channel scheduling module.

2. The method for parallel reception and processing of multi-mode signals based on dynamic configuration according to claim 1, characterized in that, The format of the sampling data encapsulation protocol includes frame header, version number, device number, VLAN number, week count, seconds within the week, signal type, number of synchronization headers, start position of synchronization header k, Doppler frequency offset of synchronization header k, signal strength of synchronization header k, byte length of sampling data, sampling data, and CRC32.

3. The method for parallel reception and processing of multi-mode signals based on dynamic configuration according to claim 1 or 2, characterized in that, The channel scheduling module maintains a channel status table with P entries to record the channel status of each channel; Each entry includes the following fields: The channel state (state), the current allocation system type (body_type), the allocation start position (start_pos), the allocation time stamp (assign_time), the timeout counter (timeout_cnt), the current task priority, and whether the DSP has finished processing the channel's decoding (dsp_handled) are all included. The channel state (state) is used to describe the state transition of each channel. Each signal system includes spreading code correlation parameters, carrier tracking loop parameters, code tracking loop parameters, and signal demodulation parameters.

4. The method for parallel reception and processing of multi-mode signals based on dynamic configuration according to claim 3, characterized in that, The preset scheduling strategies include round-robin scheduling and priority scheduling; Among them, priority scheduling adopts a priority definition based on the sampled data source. The scheduling engine of the channel scheduling module starts from the highest priority sub-queue. If the highest priority sub-queue is not empty, it takes the request at the head of the queue and tries to allocate the channel. If the allocation is successful, the request at the head of the queue is removed from the highest priority sub-queue. If the allocation fails, the request at the head of the queue remains at the head of the queue and waits for the next scheduling.

5. The method for parallel reception and processing of multi-mode signals based on dynamic configuration according to claim 4, characterized in that, If a waiting request waits in the queue for more than a set time threshold, the scheduling engine will automatically raise the priority of the waiting request by one level.

6. A multi-mode signal parallel receiving and processing device based on dynamic configuration, characterized in that, include: The data receiving module is used to receive baseband sampling data sent by each front-end capture unit through the switch and carrying capture information via a standardized high-speed interface, and to buffer the baseband sampling data in different FIFOs according to the sampling data encapsulation protocol. The channel scheduling module is used to parse the data packets of baseband sampling data read from the FIFO, select the optimal channel from the idle channel pool according to the preset scheduling strategy and allocate it to the data packets, read the complete channel configuration parameters according to the signal system index of the data packets and configure the optimal channel to issue a start command, and monitor and reclaim the channel status. The tracking and despreading module is used to complete carrier tracking, code tracking, despreading and demodulation of the optimal channel and output the symbol coherence accumulation value. The tracking and despreading module consists of P general signal processing channels inside the FPGA. According to the operating parameters configured by the DSP through the channel configuration bus, the general signal processing channels are modified into signal processing channels of different signal systems, where P is the total number of signal processing channels. The decoding module is used by the time-division multiplexing internal scheduler to execute in a round-robin fashion according to fixed time slots, sequentially reading data from the decoding input buffer of each channel for decoding; the data receiving module, channel scheduling module, and tracking despreading module are deployed in the FPGA, while the decoding module is deployed in the DSP. The DSP completes CRC verification and message framing, and sends a channel release command to the channel scheduling module.

7. The multi-mode signal parallel receiving and processing device based on dynamic configuration according to claim 6, characterized in that, The format of the sampling data encapsulation protocol includes frame header, version number, device number, VLAN number, week count, seconds within the week, signal type, number of synchronization headers, start position of synchronization header k, Doppler frequency offset of synchronization header k, signal strength of synchronization header k, byte length of sampling data, sampling data, and CRC32.

8. The multi-mode signal parallel receiving and processing apparatus based on dynamic configuration according to claim 6 or 7, characterized in that, The channel scheduling module maintains a channel status table with P entries to record the channel status of each channel; Each entry includes the following fields: The channel state (state), the current allocation system type (body_type), the allocation start position (start_pos), the allocation time stamp (assign_time), the timeout counter (timeout_cnt), the current task priority, and whether the DSP has finished processing the channel's decoding (dsp_handled) are all included. The channel state (state) is used to describe the state transition of each channel. Each signal system includes spreading code correlation parameters, carrier tracking loop parameters, code tracking loop parameters, and signal demodulation parameters.

9. The multi-mode signal parallel receiving and processing device based on dynamic configuration according to claim 8, characterized in that, The preset scheduling strategies include round-robin scheduling and priority scheduling; Among them, priority scheduling adopts a priority definition based on the sampled data source. The scheduling engine of the channel scheduling module starts from the highest priority sub-queue. If the highest priority sub-queue is not empty, it takes the request at the head of the queue and tries to allocate the channel. If the allocation is successful, the request at the head of the queue is removed from the highest priority sub-queue. If the allocation fails, the request at the head of the queue remains at the head of the queue and waits for the next scheduling.

10. The multi-mode signal parallel receiving and processing device based on dynamic configuration according to claim 9, characterized in that, If a waiting request waits in the queue for more than a set time threshold, the scheduling engine will automatically raise the priority of the waiting request by one level.

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