Shift register, gate drive circuit and display panel

Abstract

The invention provides a shift register, a gate drive circuit and a display panel, relates to the technical field of display, and is used for solving the problems of secondary steps and miscellaneous peaks existing in gate drive signals output by an existing shift register. In the shift register, a first node control circuit is respectively coupled with a first node, a first initial signal input end, a first clock signal input end, a first level signal input end and a second level signal input end; the second node control circuit is respectively coupled with the second node, the third node, the first gate driving signal output end, the first level signal input end and the second level signal input end; the first output control circuit is respectively coupled with a first gate driving signal output end, a first node, a second node, a first level signal input end and a second level signal input end; the third node control circuit is coupled with the third node, the fourth node, the first clock signal input end, the first level signal input end and the second level signal input end.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a shift register, a gate driving circuit, and a display panel. Background Technology

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly wide, and people's requirements for the display quality of display products are getting higher and higher. In order to better realize narrow bezel display products, GOA (Gate On Array) technology is adopted in display products. This technology directly fabricates the gate driving circuit on the array substrate, and drives the sub-pixel rows of the display area through the shift registers included in the gate driving circuit, thereby realizing the display function of the display product. However, the gate driving signal output by the existing shift registers has the problems of two-stage steps and noise. Summary of the Invention

[0003] The purpose of this invention is to provide a shift register, a gate drive circuit, and a display panel to solve the problems of secondary steps and noise in the gate drive signal output by existing shift registers.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A first aspect of the present invention provides a shift register, comprising:

[0006] The first node control circuit is coupled to the first node, the first start signal input terminal, the first clock signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the first node and the first level signal input terminal to be turned on or off under the control of the first start signal input at the first start signal input terminal and the first clock signal input at the first clock signal input terminal, and to control the electrical connection between the first node and the second level signal input terminal to be turned on or off.

[0007] The second node control circuit is coupled to the second node, the third node, the first gate drive signal output terminal, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the second node and the first level signal input terminal to be turned on or off under the control of the potential of the third node and the first gate drive signal output from the first gate drive signal output terminal, and to control the electrical connection between the second node and the second level signal input terminal to be turned on or off.

[0008] A first output control circuit is coupled to the first gate drive signal output terminal, the first node, the second node, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the first gate drive signal output terminal and the first level signal input terminal to be turned on or off under the control of the potential of the first node and the potential of the second node, and to control the electrical connection between the first gate drive signal output terminal and the second level signal input terminal to be turned on or off.

[0009] The third node control circuit is coupled to the third node, the fourth node, the first clock signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the third node and the first level signal input terminal to be turned on or off under the control of the potential of the fourth node and the first clock signal input terminal, and to control the electrical connection between the third node and the second level signal input terminal to be turned on or off.

[0010] The fourth node control circuit is coupled to the fourth node, the first start signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the fourth node and the first level signal input terminal to be turned on or off under the control of the first start signal input at the first start signal input terminal, and to control the electrical connection between the fourth node and the second level signal input terminal to be turned on or off.

[0011] Optionally, the first node control circuit includes a first control sub-circuit and a second control sub-circuit.

[0012] The first control sub-circuit is coupled to the first start signal input terminal, the second level signal input terminal, the fifth node, and the first node respectively; it is used to control the electrical connection between the first node and the second level signal input terminal to be turned on or off under the control of the first start signal input at the first start signal input terminal, and to control the electrical connection between the first node and the fifth node to be turned on or off.

[0013] The second control sub-circuit is coupled to the first clock signal input terminal, the second level signal input terminal, the first node, the fifth node, and the first level signal input terminal respectively; it is used to control the electrical connection between the second level signal input terminal and the first node to be turned on or off under the control of the first clock signal input at the first clock signal input terminal, and to control the electrical connection between the first level signal input terminal and the fifth node to be turned on or off.

[0014] The second node control circuit includes a third control sub-circuit and a fourth control sub-circuit;

[0015] The third control sub-circuit is coupled to the third node, the second level signal input terminal, the sixth node, and the second node respectively; it is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the second node under the control of the potential of the third node, and to control the conduction or disconnection of the electrical connection between the sixth node and the second node.

[0016] The fourth control sub-circuit is coupled to the first gate drive signal output terminal, the second level signal input terminal, the second node, the sixth node, and the first level signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the second node to be turned on or off under the control of the first gate drive signal output from the first gate drive signal output terminal, and to control the electrical connection between the sixth node and the first level signal input terminal to be turned on or off.

[0017] The first output control circuit includes a fifth control sub-circuit and a sixth control sub-circuit;

[0018] The fifth control sub-circuit is coupled to the first node, the second level signal input terminal, the first gate drive signal output terminal, and the seventh node, respectively; it is used to control the electrical connection between the second level signal input terminal and the first gate drive signal output terminal to be turned on or off under the control of the potential of the first node, and to control the electrical connection between the seventh node and the first gate drive signal output terminal to be turned on or off.

[0019] The sixth control sub-circuit is coupled to the second node, the second level signal input terminal, the first gate drive signal output terminal, the seventh node, and the first level signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the first gate drive signal output terminal to be turned on or off under the control of the potential of the second node, and to control the electrical connection between the seventh node and the first level signal input terminal to be turned on or off.

[0020] The third node control circuit includes a seventh control sub-circuit and an eighth control sub-circuit;

[0021] The seventh control sub-circuit is coupled to the fourth node, the second level signal input terminal, the third node, and the eighth node respectively; it is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the third node under the control of the potential of the fourth node, and to control the conduction or disconnection of the electrical connection between the third node and the eighth node.

[0022] The eighth control sub-circuit is coupled to the first clock signal input terminal, the second level signal input terminal, the third node, the eighth node, and the first level signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the third node to be turned on or off under the control of the first clock signal input to the first clock signal input terminal, and to control the electrical connection between the eighth node and the first level signal input terminal to be turned on or off.

[0023] Optionally, the first control sub-circuit includes a first transistor and a third transistor; the gate of the first transistor is coupled to the first start signal input terminal, the first electrode of the first transistor is coupled to the second level signal input terminal, and the second electrode of the first transistor is coupled to the first node; the gate of the third transistor is coupled to the first start signal input terminal, the first electrode of the third transistor is coupled to the fifth node, and the second electrode of the third transistor is coupled to the first node.

[0024] The second control sub-circuit includes a second transistor and a fourth transistor; the gate of the second transistor is coupled to the first clock signal input terminal, the first terminal of the second transistor is coupled to the second level signal input terminal, and the second terminal of the second transistor is coupled to the first node; the gate of the fourth transistor is coupled to the first clock signal input terminal, the first terminal of the fourth transistor is coupled to the first level signal input terminal, and the second terminal of the fourth transistor is coupled to the fifth node.

[0025] The third control sub-circuit includes a thirteenth transistor and a fifteenth transistor; the gate of the thirteenth transistor is coupled to the third node, the first terminal of the thirteenth transistor is coupled to the second level signal line, and the second terminal of the thirteenth transistor is coupled to the second node; the gate of the fifteenth transistor is coupled to the third node, the first terminal of the fifteenth transistor is coupled to the sixth node, and the second terminal of the fifteenth transistor is coupled to the second node.

[0026] The fourth control sub-circuit includes a fourteenth transistor and a sixteenth transistor; the gate of the fourteenth transistor is coupled to the first gate drive signal output terminal, the first terminal of the fourteenth transistor is coupled to the second level signal input terminal, and the second terminal of the fourteenth transistor is coupled to the second node; the gate of the sixteenth transistor is coupled to the first gate drive signal output terminal, the first terminal of the sixteenth transistor is coupled to the first level signal input terminal, and the second terminal of the sixteenth transistor is coupled to the sixth node;

[0027] The fifth control sub-circuit includes a fifth transistor and a seventh transistor. The gate of the fifth transistor is coupled to the first node, the first terminal of the fifth transistor is coupled to the second level signal input terminal, and the second terminal of the fifth transistor is coupled to the first gate drive signal output terminal. The gate of the seventh transistor is coupled to the first node, the first terminal of the seventh transistor is coupled to the seventh node, and the second terminal of the seventh transistor is coupled to the first gate drive signal output terminal.

[0028] The sixth control sub-circuit includes a sixth transistor and an eighth transistor. The gate of the sixth transistor is coupled to the second node, the first terminal of the sixth transistor is coupled to the second level signal input terminal, and the second terminal of the sixth transistor is coupled to the first gate drive signal output terminal. The gate of the eighth transistor is coupled to the second node, the first terminal of the eighth transistor is coupled to the first level signal input terminal, and the second terminal of the eighth transistor is coupled to the seventh node.

[0029] The seventh control sub-circuit includes a ninth transistor and an eleventh transistor. The gate of the ninth transistor is coupled to the fourth node, the first terminal of the ninth transistor is coupled to the second level signal input terminal, and the second terminal of the ninth transistor is coupled to the third node. The gate of the eleventh transistor is coupled to the fourth node, the first terminal of the eleventh transistor is coupled to the eighth node, and the second terminal of the eleventh transistor is coupled to the third node.

[0030] The eighth control sub-circuit includes a tenth transistor and a twelfth transistor. The gate of the tenth transistor is coupled to the first clock signal input terminal, the first terminal of the tenth transistor is coupled to the second level signal input terminal, and the second terminal of the tenth transistor is coupled to the third node. The gate of the twelfth transistor is coupled to the first clock signal input terminal, the first terminal of the twelfth transistor is coupled to the first level signal input terminal, and the second terminal of the twelfth transistor is coupled to the eighth node.

[0031] The fourth node control circuit includes a seventeenth transistor and an eighteenth transistor. The gate of the seventeenth transistor is coupled to the first start signal input terminal, the first terminal of the seventeenth transistor is coupled to the second level signal input terminal, and the second terminal of the seventeenth transistor is coupled to the fourth node. The gate of the eighteenth transistor is coupled to the first start signal input terminal, the first terminal of the eighteenth transistor is coupled to the first level signal input terminal, and the second terminal of the eighteenth transistor is coupled to the fourth node.

[0032] The first transistor, the second transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, and the fourteenth transistor are P-type transistors; the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, and the sixteenth transistor are N-type transistors.

[0033] Based on the above-mentioned shift register technical solution, a second aspect of the present invention provides a gate driving circuit, including a plurality of cascaded shift registers; a first start signal input terminal coupled to a first-stage shift register is coupled to a first frame start signal line; a first start signal input terminal coupled to an (n+1)th-stage shift register is coupled to a first gate driving signal output terminal of an nth-stage shift register, where n is an integer greater than or equal to 1.

[0034] Based on the above-described gate driving circuit technical solution, a third aspect of the present invention provides a display panel including the above-described gate driving circuit. The display panel further includes a first clock signal line, wherein at least a portion of the shift registers in the gate driving circuit have their orthogonal projections on the substrate of the display panel at least partially overlapping with the orthogonal projections of the first clock signal line on the substrate.

[0035] Optionally, the display panel further includes a second shift register, which includes:

[0036] The second output control circuit is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the first level signal input terminal, and the second gate drive signal output terminal, respectively; it is used to control the electrical connection between the first level signal input terminal and the second gate drive signal output terminal to be turned on or off under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0037] The third output control circuit is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the second level signal input terminal, and the second gate drive signal output terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the second gate drive signal output terminal to be turned on or off under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0038] The voltage regulator circuit is coupled to the ground signal input terminal and the second gate drive signal output terminal, respectively.

[0039] Optionally, the second output control circuit includes:

[0040] The ninth control sub-circuit is coupled to the third clock signal input terminal, the ninth node and the second gate drive signal output terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the ninth node and the second gate drive signal output terminal under the control of the third clock signal input at the third clock signal input terminal.

[0041] The tenth control sub-circuit is coupled to the second clock signal input terminal, the ninth node, and the tenth node respectively, and is used to control the conduction or disconnection of the electrical connection between the ninth node and the tenth node under the control of the second clock signal input to the second clock signal input terminal;

[0042] The eleventh control sub-circuit is coupled to the second start signal input terminal, the tenth node and the first level signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the tenth node and the first level signal input terminal under the control of the second start signal input to the second start signal input terminal;

[0043] The twelfth control sub-circuit is coupled to the third clock signal input terminal, the eleventh node and the second gate drive signal output terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the eleventh node and the second gate drive signal output terminal under the control of the third clock signal input at the third clock signal input terminal.

[0044] The thirteenth control sub-circuit is coupled to the second clock signal input terminal, the eleventh node and the twelfth node respectively, and is used to control the conduction or disconnection of the electrical connection between the eleventh node and the twelfth node under the control of the second clock signal input to the second clock signal input terminal;

[0045] The fourteenth control sub-circuit is coupled to the second start signal input terminal, the twelfth node and the second level signal input terminal respectively, and is used to control the electrical connection between the twelfth node and the second level signal input terminal to be turned on or off under the control of the second start signal input at the second start signal input terminal.

[0046] Optionally, the ninth control sub-circuit includes a nineteenth transistor, the gate of the nineteenth transistor is coupled to the third clock signal input terminal, the first terminal of the nineteenth transistor is coupled to the ninth node, and the second terminal of the nineteenth transistor is coupled to the second gate drive signal output terminal.

[0047] The tenth control sub-circuit includes a twentieth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the tenth node, and the second terminal of which is coupled to the ninth node.

[0048] The eleventh control sub-circuit includes a twenty-first transistor, the gate of which is coupled to the second start signal input terminal, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the tenth node.

[0049] The twelfth control sub-circuit includes a twenty-second transistor, the gate of which is coupled to the third clock signal input terminal, the first terminal of which is coupled to the eleventh node, and the second terminal of which is coupled to the second gate drive signal output terminal.

[0050] The thirteenth control sub-circuit includes a twenty-third transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the twelfth node, and the second terminal of which is coupled to the eleventh node.

[0051] The fourteenth control sub-circuit includes a twenty-fourth transistor, the gate of which is coupled to the second start signal input terminal, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the twelfth node.

[0052] The voltage regulator circuit includes a capacitor structure, with a first end of the capacitor structure coupled to the ground signal input terminal and a second end of the capacitor structure coupled to the second gate drive signal output terminal.

[0053] The nineteenth, twenty-first, and twenty-second transistors include P-type transistors, and the twentieth, twenty-third, and twenty-fourth transistors include N-type transistors.

[0054] Optionally, the display panel further includes a second clock signal line, a third clock signal line, a fourth clock signal line, and a fifth clock signal line;

[0055] The display panel includes a plurality of cascaded second type shift registers. The second start signal input terminal of the first-stage second type shift register is coupled to the second frame start signal line in the display panel; the second start signal input terminal of the (n+1)th-stage second type shift register is coupled to the second gate drive signal output terminal of the nth-stage second type shift register, where n is an integer greater than or equal to 1.

[0056] The cascaded multiple second-type shift registers are divided into multiple shift register groups. Each shift register group includes two adjacent shift registers. In each shift register group, the second clock signal input terminal of the preceding shift register is coupled to the second clock signal line, the third clock signal input terminal of the preceding shift register is coupled to the third clock signal line, the second clock signal input terminal of the following shift register is coupled to the fourth clock signal line, and the third clock signal input terminal of the following shift register is coupled to the fifth clock signal line.

[0057] Optionally, the orthographic projection of the second type of shift register on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the second clock signal line, the third clock signal line, the fourth clock signal line, and the fifth clock signal line on the substrate.

[0058] In the technical solution provided by this invention, the gate drive signal output by the shift register does not have secondary steps or noise issues. When this shift register is applied to display products, the display products will not exhibit bright lines caused by premature pixel row activation after undergoing reliability tests such as high temperature and high humidity tests. Attached Figure Description

[0059] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0060] Figure 1 This is a schematic diagram of the first module of the shift register provided in an embodiment of the present invention;

[0061] Figure 2 This is a schematic diagram of the second module of the shift register provided in an embodiment of the present invention;

[0062] Figure 3 A first circuit diagram of a shift register provided in an embodiment of the present invention;

[0063] Figure 4 To and Figure 3 The corresponding timing diagram;

[0064] Figure 5 This is a schematic diagram of a first layout of a display panel provided in an embodiment of the present invention;

[0065] Figure 6 This is a schematic diagram of the layout of the shift register and signal lines of the display panel provided in an embodiment of the present invention.

[0066] Figure 7A schematic diagram of the third module of the shift register provided in an embodiment of the present invention;

[0067] Figure 8 This is a schematic diagram of the fourth module of the shift register provided in an embodiment of the present invention;

[0068] Figure 9 A schematic diagram of the fifth module of the shift register provided in an embodiment of the present invention;

[0069] Figure 10 A schematic diagram of the sixth module of the shift register provided in an embodiment of the present invention;

[0070] Figure 11 A second circuit diagram of a shift register provided in an embodiment of the present invention;

[0071] Figure 12 A third circuit diagram of a shift register provided in an embodiment of the present invention;

[0072] Figure 13 To and Figure 11 and Figure 12 The corresponding timing diagram. Detailed Implementation

[0073] To further illustrate the shift register, gate driving circuit, and display panel provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0074] Please see Figure 1 This invention provides a shift register, comprising:

[0075] The first node control circuit 10 is coupled to the first node n1, the first start signal input terminal STV1, the first clock signal input terminal CLK, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively. It is used to control the electrical connection between the first node n1 and the first level signal input terminal VGL, and to control the electrical connection between the first node n1 and the second level signal input terminal VGH, under the control of the first start signal input terminal STV1 and the first clock signal input terminal CLK.

[0076] The second node control circuit 20 is coupled to the second node n2, the third node n3, the first gate drive signal output terminal OUT1, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively. It is used to control the electrical connection between the second node n2 and the first level signal input terminal VGL, and to control the electrical connection between the second node n2 and the second level signal input terminal VGH, under the control of the potential of the third node n3 and the first gate drive signal output terminal OUT1.

[0077] The first output control circuit 50 is coupled to the first gate drive signal output terminal OUT1, the first node n1, the second node n2, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively; it is used to control the electrical connection between the first gate drive signal output terminal OUT1 and the first level signal input terminal VGL to be turned on or off under the control of the potential of the first node n1 and the potential of the second node n2, and to control the electrical connection between the first gate drive signal output terminal OUT1 and the second level signal input terminal VGH to be turned on or off.

[0078] The third node control circuit 30 is coupled to the third node n3, the fourth node n4, the first clock signal input terminal CLK, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively. It is used to control the electrical connection between the third node n3 and the first level signal input terminal VGL, and to control the electrical connection between the third node n3 and the second level signal input terminal VGH, under the control of the potential of the fourth node n4 and the first clock signal input terminal CLK.

[0079] The fourth node control circuit 40 is coupled to the fourth node n4, the first start signal input terminal STV1, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively. It is used to control the electrical connection between the fourth node n4 and the first level signal input terminal VGL, and to control the electrical connection between the fourth node n4 and the second level signal input terminal VGH, under the control of the first start signal input to the first start signal input terminal STV1.

[0080] like Figure 4 As shown, for example, the period of the first clock signal input at the first clock signal input terminal CLK is 4H, and the pulse width of the first clock signal is 2H, but it is not limited to this.

[0081] For example, the first level signal input at the first level signal input terminal VGL is a low level signal, and the second level signal input at the second level signal input terminal VGH is a high level signal, but it is not limited to this.

[0082] As can be seen from the specific structure of the shift register described above, in the shift register provided by this embodiment of the invention, the first start signal input through the first start signal input terminal STV1 and the first clock signal input through the first clock signal input terminal CLK can control the first node control circuit 10, thereby controlling the potential of the first node n1; the first clock signal and the fourth node n4 can control the third node control circuit, thereby controlling the potential of the third node n3; the third node n3 and the first gate drive signal output through the first gate drive signal output terminal OUT1 can control the second node control circuit, thereby controlling the potential of the second node n2; the first node n1 and the second node n2 can control the first output control circuit, thereby controlling the first gate drive signal output terminal OUT1 to output a stable first gate drive signal. The circuit structures included in the shift register can be implemented using transistors, eliminating the need for capacitor structures and thus avoiding the secondary step and noise problems caused by capacitor structures. When the shift register provided in this embodiment of the invention is applied to a display product, since the first gate drive signal does not have secondary steps or noise peaks, even if the transistors in the pixel circuit experience threshold voltage drift after the display product has undergone reliability tests such as high temperature and high humidity, the first gate drive signal will not cause the pixel row to turn on prematurely, thereby avoiding the problem of bright lines on the display.

[0083] Moreover, the shift register provided in the above embodiment only needs to be connected to one clock signal input terminal (first clock signal input terminal CLK), that is, only one clock signal line connected to the clock signal input terminal is needed to provide the clock signal. This not only helps to simplify the layout complexity and bezel width of the display product in which the shift register is applied, but also reduces signal interference and product power consumption.

[0084] like Figure 2 As shown, in some embodiments, the first node control circuit 10 includes a first control sub-circuit 101 and a second control sub-circuit 102.

[0085] The first control sub-circuit 101 is coupled to the first start signal input terminal STV1, the second level signal input terminal VGH, the fifth node n5, and the first node n1, respectively; it is used to control the electrical connection between the first node n1 and the second level signal input terminal VGH, and to control the electrical connection between the first node n1 and the fifth node n5, under the control of the first start signal input to the first start signal input terminal STV1.

[0086] The second control sub-circuit 102 is coupled to the first clock signal input terminal CLK, the second level signal input terminal VGH, the first node n1, the fifth node n5, and the first level signal input terminal VGL, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the first node n1, and to control the electrical connection between the first level signal input terminal VGL and the fifth node n5, under the control of the first clock signal input to the first clock signal input terminal CLK.

[0087] The second node control circuit 20 controls a third control sub-circuit 201 and a fourth control sub-circuit 202;

[0088] The third control sub-circuit 201 is coupled to the third node n3, the second level signal input terminal VGH, the sixth node n6, and the second node n2 respectively; it is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal VGH and the second node n2 under the control of the potential of the third node n3, and to control the conduction or disconnection of the electrical connection between the sixth node n6 and the second node n2.

[0089] The fourth control sub-circuit 202 is coupled to the first gate drive signal output terminal OUT1, the second level signal input terminal VGH, the second node n2, the sixth node n6, and the first level signal input terminal VGL, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the second node n2, and to control the electrical connection between the sixth node n6 and the first level signal input terminal VGL, under the control of the first gate drive signal output from the first gate drive signal output terminal OUT1.

[0090] The first output control circuit 50 includes a fifth control sub-circuit 501 and a sixth control sub-circuit 502;

[0091] The fifth control sub-circuit 501 is coupled to the first node n1, the second level signal input terminal VGH, the first gate drive signal output terminal OUT1, and the seventh node n7, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the first gate drive signal output terminal OUT1 to be turned on or off under the control of the potential of the first node n1, and to control the electrical connection between the seventh node n7 and the first gate drive signal output terminal OUT1 to be turned on or off.

[0092] The sixth control sub-circuit 502 is coupled to the second node n2, the second level signal input terminal VGH, the first gate drive signal output terminal OUT1, the seventh node n7, and the first level signal input terminal VGL, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the first gate drive signal output terminal OUT1 to be turned on or off under the control of the potential of the second node n2, and to control the electrical connection between the seventh node n7 and the first level signal input terminal VGL to be turned on or off.

[0093] The third node control circuit 30 includes a seventh control sub-circuit 301 and an eighth control sub-circuit 302;

[0094] The seventh control sub-circuit 301 is coupled to the fourth node n4, the second level signal input terminal VGH, the third node n3, and the eighth node n8, respectively; it is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal VGH and the third node n3 under the control of the potential of the fourth node n4, and to control the conduction or disconnection of the electrical connection between the third node n3 and the eighth node n8.

[0095] The eighth control sub-circuit 302 is coupled to the first clock signal input terminal CLK, the second level signal input terminal VGH, the third node n3, the eighth node n8, and the first level signal input terminal VGL, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the third node n3, and to control the electrical connection between the eighth node n8 and the first level signal input terminal VGL, under the control of the first clock signal input to the first clock signal input terminal CLK.

[0096] like Figure 2 and Figure 3 As shown, exemplarily, the first control sub-circuit 101 includes a first transistor T1 and a third transistor T3; the gate of the first transistor T1 is coupled to the first start signal input terminal STV1, the first terminal of the first transistor T1 is coupled to the second level signal input terminal VGH, and the second terminal of the first transistor T1 is coupled to the first node n1; the gate of the third transistor T3 is coupled to the first start signal input terminal STV1, the first terminal of the third transistor T3 is coupled to the fifth node n5, and the second terminal of the third transistor T3 is coupled to the first node n1;

[0097] The second control sub-circuit 102 includes a second transistor T2 and a fourth transistor T4; the gate of the second transistor T2 is coupled to the first clock signal input terminal CLK, the first terminal of the second transistor T2 is coupled to the second level signal input terminal VGH, and the second terminal of the second transistor T2 is coupled to the first node n1; the gate of the fourth transistor T4 is coupled to the first clock signal input terminal CLK, the first terminal of the fourth transistor T4 is coupled to the first level signal input terminal VGL, and the second terminal of the fourth transistor T4 is coupled to the fifth node n5;

[0098] The third control sub-circuit 201 includes a thirteenth transistor T13 and a fifteenth transistor T15; the gate of the thirteenth transistor T13 is coupled to the third node n3, the first terminal of the thirteenth transistor T13 is coupled to the second level signal line, and the second terminal of the thirteenth transistor T13 is coupled to the second node n2; the gate of the fifteenth transistor T15 is coupled to the third node n3, the first terminal of the fifteenth transistor T15 is coupled to the sixth node n6, and the second terminal of the fifteenth transistor T15 is coupled to the second node n2;

[0099] The fourth control sub-circuit 202 includes a fourteenth transistor T14 and a sixteenth transistor T16; the gate of the fourteenth transistor T14 is coupled to the first gate drive signal output terminal OUT1, the first terminal of the fourteenth transistor T14 is coupled to the second level signal input terminal VGH, and the second terminal of the fourteenth transistor T14 is coupled to the second node n2; the gate of the sixteenth transistor T16 is coupled to the first gate drive signal output terminal OUT1, the first terminal of the sixteenth transistor T16 is coupled to the first level signal input terminal VGL, and the second terminal of the sixteenth transistor T16 is coupled to the sixth node n6;

[0100] The fifth control sub-circuit 501 includes a fifth transistor T5 and a seventh transistor T7. The gate of the fifth transistor T5 is coupled to the first node n1, the first terminal of the fifth transistor T5 is coupled to the second level signal input terminal VGH, and the second terminal of the fifth transistor T5 is coupled to the first gate drive signal output terminal OUT1. The gate of the seventh transistor T7 is coupled to the first node n1, the first terminal of the seventh transistor T7 is coupled to the seventh node n7, and the second terminal of the seventh transistor T7 is coupled to the first gate drive signal output terminal OUT1.

[0101] The sixth control sub-circuit 502 includes a sixth transistor T6 and an eighth transistor T8. The gate of the sixth transistor T6 is coupled to the second node n2, the first terminal of the sixth transistor T6 is coupled to the second level signal input terminal VGH, and the second terminal of the sixth transistor T6 is coupled to the first gate drive signal output terminal OUT1. The gate of the eighth transistor T8 is coupled to the second node n2, the first terminal of the eighth transistor T8 is coupled to the first level signal input terminal VGL, and the second terminal of the eighth transistor T8 is coupled to the seventh node n7.

[0102] The seventh control sub-circuit 301 includes a ninth transistor T9 and an eleventh transistor T11. The gate of the ninth transistor T9 is coupled to the fourth node n4, the first terminal of the ninth transistor T9 is coupled to the second level signal input terminal VGH, and the second terminal of the ninth transistor T9 is coupled to the third node n3. The gate of the eleventh transistor T11 is coupled to the fourth node n4, the first terminal of the eleventh transistor T11 is coupled to the eighth node n8, and the second terminal of the eleventh transistor T11 is coupled to the third node n3.

[0103] The eighth control sub-circuit 302 includes a tenth transistor T10 and a twelfth transistor T12. The gate of the tenth transistor T10 is coupled to the first clock signal input terminal CLK, the first terminal of the tenth transistor T10 is coupled to the second level signal input terminal VGH, and the second terminal of the tenth transistor T10 is coupled to the third node n3. The gate of the twelfth transistor T12 is coupled to the first clock signal input terminal CLK, the first terminal of the twelfth transistor T12 is coupled to the first level signal input terminal VGL, and the second terminal of the twelfth transistor T12 is coupled to the eighth node n8.

[0104] The fourth node control circuit 40 includes a seventeenth transistor T17 and an eighteenth transistor T18. The gate of the seventeenth transistor T17 is coupled to the first start signal input terminal STV1, the first terminal of the seventeenth transistor T17 is coupled to the second level signal input terminal VGH, and the second terminal of the seventeenth transistor T17 is coupled to the fourth node n4. The gate of the eighteenth transistor T18 is coupled to the first start signal input terminal STV1, the first terminal of the eighteenth transistor T18 is coupled to the first level signal input terminal VGL, and the second terminal of the eighteenth transistor is coupled to the fourth node n4.

[0105] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors; the third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, the twelfth transistor T12, the fifteenth transistor T15, and the sixteenth transistor T16 are N-type transistors.

[0106] The shift register is configured with the above structure so that it can be formed into a CMOS circuit structure, thereby achieving strong output capability, good stability, and low power consumption. Moreover, the CMOS circuit structure can usually achieve stronger output capability with transistors with smaller aspect ratios. While improving the driving effect, it is also beneficial to further reduce the layout space occupied by the shift register and further narrow the bezel width of the display products in which it is applied.

[0107] like Figure 5 As shown, when the shift register is applied in a display panel, the display area AA of the display panel includes arrayed sub-pixels. The shift register may specifically include: EM GOA, N-gate GOA, Rest-P GOA, and Rest-H GOA. EM GOA is used to provide a gate drive signal for light emission control to the corresponding sub-pixel row; N-gate GOA is used to provide a high-level active gate drive signal to the corresponding sub-pixel row; Rest-P GOA and Rest-H GOA are used to provide a gate drive signal for reset to the corresponding sub-pixel row. Rest-P GOA can provide a gate drive signal to the reset transistor used to reset the electrode of the reset drive transistor in the sub-pixel drive circuit, and Rest-H GOA can provide a gate drive signal to the reset transistor used to reset the anode in the sub-pixel drive circuit, but is not limited to these.

[0108] like Figure 3 and Figure 4 As shown, the operation of the shift register provided in the above embodiment is as follows:

[0109] During period P1, the first transistor T1 is turned on, the third transistor T3 is turned off, the second transistor T2 is turned off, and the fourth transistor T4 is turned on. The potential of the first node n1 is the same as the second level signal input at the second level signal input terminal VGH, that is, the potential of the first node n1 is high. At this time, the seventh transistor T7 is turned on, and the fifth transistor T5 is turned off. Since the first gate drive signal output at the first gate drive signal output terminal OUT1 in the previous period was low, the fourteenth transistor T14 is turned on, and the sixteenth transistor T16 is turned off, thereby controlling the potential of the second node n2 to be high. The eighth transistor T8 is turned on, controlling the potential of the first gate drive signal output at the first gate drive signal output terminal OUT1 in the current period to be the same as the first level signal input at the first level signal input terminal VGL, that is, the first gate drive signal output at the first gate drive signal output terminal OUT1 in the current period is low.

[0110] It is worth noting that during the P1 period, since the first start signal input at the first start signal input terminal STV1 is at a low level, the seventeenth transistor T17 is turned on and the eighteenth transistor T18 is turned off. This controls the potential of the fourth node n4 to be the same as the second level signal input at the second level signal input terminal VGH, that is, the potential of the fourth node n4 is at a high level. This controls the eleventh transistor T11 to be turned on and the ninth transistor T9 to be turned off. Since the first clock signal input at the first clock signal input terminal CLK is at a high level, this controls the twelfth transistor T12 to be turned on and the tenth transistor T10 to be turned off. This makes the potential of the third node n3 the same as the first level signal, that is, the potential of the third node n3 is at a low level. This controls the thirteenth transistor T13 to be turned on and the fifteenth transistor T15 to be turned off, thereby stabilizing the potential of the second node n2 at a high level.

[0111] During period P2, the first transistor T1 is off, the third transistor T3 is on, the second transistor T2 is on, and the fourth transistor T4 is off. The potential of the first node n1 is the same as the second level signal input at the second level signal input terminal VGH, that is, the potential of the first node n1 is high. At this time, the seventh transistor T7 is on, and the fifth transistor T5 is off. Since the first gate drive signal output at the first gate drive signal output terminal OUT1 in the previous period was low, the fourteenth transistor T14 is turned on, and the sixteenth transistor T16 is turned off, thereby controlling the potential of the second node n2 to be high. The eighth transistor T8 is on, controlling the potential of the first gate drive signal output at the first gate drive signal output terminal OUT1 in the current period to be the same as the first level signal input at the first level signal input terminal VGL, that is, the first gate drive signal output at the first gate drive signal output terminal OUT1 in the current period is low.

[0112] It is worth noting that during period P2, because the first start signal input at the first start signal input terminal STV1 is at a high level, the seventeenth transistor T17 is turned off and the eighteenth transistor T18 is turned on, controlling the potential of the fourth node n4 to be the same as the first level signal input at the first level signal input terminal VGL, that is, the potential of the fourth node n4 is at a low level, thereby controlling the eleventh transistor T11 to be turned off and the ninth transistor T9 to be turned on. Because the first clock signal input at the first clock signal input terminal CLK is at a low level, the twelfth transistor T12 is turned off and the tenth transistor T10 is turned on, making the potential of the third node n3 the same as the second level signal, that is, the potential of the third node n3 is at a high level, thereby controlling the thirteenth transistor T13 to be turned off and the fifteenth transistor T15 to be turned on, thereby controlling the potential of the second node n2 to remain the same as during period P1.

[0113] During the P3 period, the first transistor T1 is off, the third transistor T3 is on, and the potential of the first node n1 is opposite to the first clock signal input at the first clock signal input terminal CLK, that is, the potential of the first node n1 is low, which controls the fifth transistor T5 to turn on and the seventh transistor T7 to turn off. At this time, the first gate drive signal output at the first gate drive signal output terminal OUT1 is high.

[0114] It is worth noting that during the P3 period, because the first start signal input at the first start signal input terminal STV1 is at a high level, the seventeenth transistor T17 is turned off and the eighteenth transistor T18 is turned on, controlling the potential of the fourth node n4 to be the same as the first level signal input at the first level signal input terminal VGL, that is, the potential of the fourth node n4 is at a low level, thereby controlling the eleventh transistor T11 to be turned off and the ninth transistor T9 to be turned on. Because the first clock signal input at the first clock signal input terminal CLK is at a high level, the twelfth transistor T12 is turned on and the tenth transistor T10 is turned off, making the potential of the third node n3 the same as the second level signal, that is, the potential of the third node n3 is at a high level, thereby controlling the thirteenth transistor T13 to be turned off and the fifteenth transistor T15 to be turned on. Because the first gate drive signal output at the first gate drive signal output terminal OUT1 in the previous period was at a low level, the fourteenth transistor T14 is turned on and the sixteenth transistor T16 is turned off, thereby controlling the potential of the second node n2 to be at a high level and the eighth transistor T8 to be turned on.

[0115] During the P4 period, the first transistor T1 is off, the third transistor T3 is on, and the potential of the first node n1 is opposite to the first clock signal input CLK. That is, the potential of the first node n1 will alternate between high and low levels, which controls the fifth transistor T5 to alternately turn on and off, and the seventh transistor T7 to alternately turn off and on.

[0116] It is worth noting that during period P4, because the first start signal input at the first start signal input terminal STV1 is at a high level, the seventeenth transistor T17 is turned off and the eighteenth transistor T18 is turned on, controlling the potential of the fourth node n4 to be the same as the first level signal input at the first level signal input terminal VGL, that is, the potential of the fourth node n4 is at a low level, thereby controlling the eleventh transistor T11 to be turned off and the ninth transistor T9 to be turned on. Thus, even if the first clock signal input at the first clock signal input terminal CLK alternates between high and low levels, the potential of the third node n3 can only be the same as the second level signal, that is, the potential of the third node n3 is at a high level, thereby controlling the thirteenth transistor T13 to be turned off and the fifteenth transistor T15 to be turned on. Since the first gate drive signal output at the first gate drive signal output terminal OUT1 was at a high level in the previous period, the fourteenth transistor T14 was turned off and the sixteenth transistor T16 was turned on, thereby controlling the potential of the second node n2 to be at a low level and the eighth transistor T8 to be turned off. At this time, the first gate drive signal output at the first gate drive signal output terminal OUT1 remains at a high level.

[0117] During the P5 phase, at least one of the working processes of P3 and P4 is repeated, and the first gate drive signal output by the first gate drive signal output terminal OUT1 remains at a high level.

[0118] In stage P6, the first transistor T1 is turned on, the third transistor T3 is turned off, the second transistor T2 is turned on, and the fourth transistor T4 is turned off. The potential of the first node n1 is the same as the second level signal input at the second level signal input terminal VGH, that is, the potential of the first node n1 is high. At this time, the seventh transistor T7 is turned on, and the fifth transistor T5 is turned off. Since the first gate drive signal output at the first gate drive signal output terminal OUT1 was high in the previous period, it controls the fourteenth transistor T14 to turn off and the sixteenth transistor T16 to turn on. Since the first start signal input at the first start signal input terminal STV1 is low, it causes the seventeenth transistor T17 to turn on and the eighteenth transistor T18 to turn off, controlling the fourth node n4. The potential of node n4 is the same as the second level signal input at the second level signal input terminal VGH, that is, the potential of node n4 is high, thereby controlling the eleventh transistor T11 to turn on and the ninth transistor T9 to turn off. Since the first clock signal input at the first clock signal input terminal CLK is low, the twelfth transistor T12 is turned off and the tenth transistor T10 is turned on, making the potential of node n3 the same as the second level signal, that is, the potential of node n3 is high, thereby controlling the thirteenth transistor T13 to turn off and the fifteenth transistor T15 to turn on, thereby stabilizing the potential of node n2 at a low level, the eighth transistor T8 is turned off, and the first gate drive signal output at the first gate drive signal output terminal OUT1 remains high.

[0119] During period P7, the first transistor T1 is turned on, the third transistor T3 is turned off, the second transistor T2 is turned off, and the fourth transistor T4 is turned on. The potential of the first node n1 is the same as the second level signal input at the second level signal input terminal VGH, that is, the potential of the first node n1 is high. At this time, the seventh transistor T7 is turned on, and the fifth transistor T5 is turned off. Since the first gate drive signal output at the first gate drive signal output terminal OUT1 was high in the previous period, the fourteenth transistor T14 is turned off, and the sixteenth transistor T16 is turned on. Since the first start signal input at the first start signal input terminal STV1 is low, the seventeenth transistor T17 is turned on, and the eighteenth transistor T18 is turned off, which controls the potential of the fourth node n4 to be the same as the second level signal input at the second level signal input terminal VGH, that is, the fourth... The potential of node n4 is high, thus controlling the eleventh transistor T11 to turn on and the ninth transistor T9 to turn off. Since the first clock signal input at the first clock signal input terminal CLK is high, it controls the twelfth transistor T12 to turn on and the tenth transistor T10 to turn off, making the potential of the third node n3 the same as the first level signal, that is, the potential of the third node n3 is low, thus controlling the thirteenth transistor T13 to turn on and the fifteenth transistor T15 to turn off, controlling the potential of the second node n2 to be high, and the eighth transistor T8 to turn on, controlling the potential of the first gate drive signal output at the first gate drive signal output terminal OUT1 in the current period to be the same as the first level signal input at the first level signal input terminal VGL, that is, the first gate drive signal output at the first gate drive signal output terminal OUT1 in the current period is low.

[0120] This invention also provides a gate driving circuit, including a plurality of cascaded shift registers provided in the above embodiments; the first start signal input terminal STV1 of the first-stage shift register is coupled to the first frame start signal line; the first start signal input terminal STV1 of the (n+1)th-stage shift register is coupled to the first gate driving signal output terminal OUT1 of the nth-stage shift register, where n is an integer greater than or equal to 1.

[0121] For example, in a cascaded array of multiple shift registers, the first clock signal input terminal CLK of each shift register is connected to the same first clock signal line CLK'.

[0122] For example, in different gate drive circuits formed by cascading different shift registers (such as EM GOA, N-gate GOA, Rest-P GOA, and Rest-HGOA), the start signal input terminal of the first-stage shift register in each type of gate drive circuit is coupled to the corresponding first frame start signal line; or the start signal input terminal of the first-stage shift register in each type of gate drive circuit is coupled to the same first frame start signal line.

[0123] In the gate drive circuit provided in the above embodiment, the shift time width of the first gate drive signal output by the adjacent stage shift register is the low-level time width of the first clock signal. If the low-level time width of the first clock signal is set to 2H, then the shift time width of the first gate drive signal output by the adjacent stage shift register can be 2H.

[0124] like Figure 5 and Figure 6 As shown, this embodiment of the invention also provides a display panel, including the gate driving circuit provided in the above embodiment. The display panel further includes a first clock signal line. At least a portion of the shift registers in the gate driving circuit have their orthogonal projections on the substrate of the display panel at least partially overlapping with the orthogonal projections of the first clock signal line on the substrate.

[0125] For example, the display panel includes an active matrix organic light-emitting diode display panel, but is not limited to this.

[0126] For example, the display panel includes a display area AA and a peripheral area surrounding the display area AA. The peripheral area includes a left border area and a right border area that are set opposite to each other. For example, EM GOA and N-gate GOA are located in the left border area, and Rest-P GOA and Rest-H GOA are located in the right border area, but it is not limited to this.

[0127] For example, the orthographic projection of the first clock signal line CLK' on the substrate at least partially overlaps with the orthographic projection of the EM GOA on the substrate, the orthographic projection of the first clock signal line CLK' on the substrate at least partially overlaps with the orthographic projection of the N-gate GOA on the substrate, the orthographic projection of the first clock signal line CLK' on the substrate at least partially overlaps with the orthographic projection of the Rest-P GOA on the substrate, and the orthographic projection of the first clock signal line CLK' on the substrate at least partially overlaps with the orthographic projection of the Rest-H GOA on the substrate.

[0128] For example, along the extension direction of the first clock signal line CLK', EM GOA and N-gate GOA are arranged alternately. Along the extension direction of the first clock signal line CLK', Rest-P GOA and Rest-H GOA are arranged alternately.

[0129] The display panel can be applied to a display device, which can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0130] The above-mentioned arrangement, in which at least a portion of the shift register in the gate driving circuit is projected onto the substrate of the display panel, overlaps at least partially with the projected image of the first clock signal line onto the substrate. This arrangement helps to reduce the overall layout space occupied by the gate driving circuit and the signal line, and also helps to reduce the difficulty of connecting the gate driving circuit and the signal line.

[0131] like Figure 7 and Figure 8 As shown, in some embodiments, the display panel further includes a second shift register, which includes:

[0132] The second output control circuit 60 is coupled to the second start signal input terminal, the second clock signal input terminal (e.g., CK1, CK3), the third clock signal input terminal (e.g., CK2, CK4), the first level signal input terminal VGL, and the second gate drive signal output terminal, respectively; it is used to control the electrical connection between the first level signal input terminal VGL and the second gate drive signal output terminal under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0133] The third output control circuit 70 is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the second level signal input terminal VGH, and the second gate drive signal output terminal, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the second gate drive signal output terminal under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0134] The voltage regulator circuit 80 is coupled to the ground signal input terminal and the second gate drive signal output terminal, respectively.

[0135] It should be noted that, Figure 7 The diagram shows the nth stage shift register, whose second start signal input terminal is connected to the second gate drive signal output terminal gatep-(n-1) of the (n-1)th stage shift register, and the second gate drive signal output terminal of the nth stage shift register is gatep-(n).

[0136] Figure 8The diagram shows the (n+1)th stage shift register, whose second start signal input is connected to the second gate drive signal output of the nth stage shift register, gatep-(n), and the second gate drive signal output of the (n+1)th stage shift register is gatep-(n+1).

[0137] For example, the second type of shift register includes, but is not limited to, P-gate GOAs. P-gate GOAs are used to provide a low-level active gate drive signal to the corresponding sub-pixel row. P-gate GOAs are arranged sequentially along the extension direction of the first clock signal line. In the left and right frame regions, P-gate GOAs are located closer to the display area than the other GOAs.

[0138] For example, the second clock signal input to the second clock signal input terminal and the third clock signal input to the third clock signal input terminal have the same pulse width and different phases.

[0139] For example, the period of the second clock signal and the third clock signal is 1H, but it is not limited to this.

[0140] For example, the first level signal input at the first level signal input terminal VGL is a low level signal, and the second level signal input at the second level signal input terminal VGH is a high level signal, but it is not limited to this.

[0141] In the second type of shift register provided in the above embodiments, the second start signal input at the second start signal input terminal, the second clock signal input at the second clock signal input terminal, and the third clock signal input at the third clock signal input terminal can control the output of the second gate drive signal from the second gate drive signal output terminal. The second type of shift register provided in the above embodiments connects two clock signal input terminals (the second clock signal input terminal and the third clock signal input terminal). When the second type of shift register is cascaded to form a gate drive circuit, the gate drive circuit can connect a total of four clock signal lines, which helps to reduce the loading of the clock signal lines and improve the stability of the output gate drive signal.

[0142] In the second type of shift register provided in the above embodiment, the voltage regulator circuit 80 is set to further improve the stability of the output gate drive signal.

[0143] like Figures 7 to 10 As shown, in some embodiments, the second output control circuit 60 includes:

[0144] The ninth control sub-circuit 66 is coupled to the third clock signal input terminal, the ninth node n9 and the second gate drive signal output terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the ninth node n9 and the second gate drive signal output terminal under the control of the third clock signal input at the third clock signal input terminal.

[0145] The tenth control sub-circuit 61 is coupled to the second clock signal input terminal, the ninth node n9 and the tenth node n10 respectively, and is used to control the conduction or disconnection of the electrical connection between the ninth node n9 and the tenth node n10 under the control of the second clock signal input to the second clock signal input terminal;

[0146] The eleventh control sub-circuit 62 is coupled to the second start signal input terminal, the tenth node n10 and the first level signal input terminal VGL respectively, and is used to control the electrical connection between the tenth node n10 and the first level signal input terminal VGL to be turned on or off under the control of the second start signal input at the second start signal input terminal.

[0147] The twelfth control sub-circuit 63 is coupled to the third clock signal input terminal, the eleventh node n11 and the second gate drive signal output terminal respectively, and is used to control the electrical connection between the eleventh node n11 and the second gate drive signal output terminal to be turned on or off under the control of the third clock signal input at the third clock signal input terminal.

[0148] The thirteenth control sub-circuit 64 is coupled to the second clock signal input terminal, the eleventh node n11 and the twelfth node n12 respectively, and is used to control the conduction or disconnection of the electrical connection between the eleventh node n11 and the twelfth node n12 under the control of the second clock signal input terminal.

[0149] The fourteenth control sub-circuit 65 is coupled to the second start signal input terminal, the twelfth node n12 and the second level signal input terminal VGH respectively, and is used to control the electrical connection between the twelfth node n12 and the second level signal input terminal VGH to be turned on or off under the control of the second start signal input at the second start signal input terminal.

[0150] For example, the ninth control sub-circuit 66 includes a nineteenth transistor T19, the gate of the nineteenth transistor T19 is coupled to the third clock signal input terminal, the first terminal of the nineteenth transistor T19 is coupled to the ninth node n9, and the second terminal of the nineteenth transistor T19 is coupled to the second gate drive signal output terminal.

[0151] The tenth control sub-circuit 61 includes a twentieth transistor T20, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the tenth node n10, and the second terminal of which is coupled to the ninth node n9.

[0152] The eleventh control sub-circuit 62 includes a twenty-first transistor T21, the gate of which is coupled to the second start signal input terminal, the first terminal of which is coupled to the first level signal input terminal VGL, and the second terminal of which is coupled to the tenth node n10.

[0153] The twelfth control sub-circuit 63 includes a twenty-second transistor T22, the gate of which is coupled to the third clock signal input terminal, the first terminal of which is coupled to the eleventh node n11, and the second terminal of which is coupled to the second gate drive signal output terminal.

[0154] The thirteenth control sub-circuit 64 includes a twenty-third transistor T23, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the twelfth node n12, and the second terminal of which is coupled to the eleventh node n11.

[0155] The fourteenth control sub-circuit 65 includes a twenty-fourth transistor T24, the gate of which is coupled to the second start signal input terminal, the first terminal of which is coupled to the second level signal input terminal VGH, and the second terminal of which is coupled to the twelfth node n12.

[0156] The voltage regulator circuit 80 includes a capacitor structure C, the first end of which is coupled to the ground signal input terminal, and the second end of which is coupled to the second gate drive signal output terminal.

[0157] The nineteenth transistor T19, the twenty-first transistor T21, and the twenty-second transistor T22 are P-type transistors, and the twentieth transistor T20, the twenty-third transistor T23, and the twenty-fourth transistor T24 are N-type transistors.

[0158] For example, the capacitor structure C may use a 10pC capacitor, but is not limited to this.

[0159] The second type of shift register is configured with the above structure so that it can be formed into a CMOS circuit structure, thereby achieving the effects of strong output capability, good stability, and low power consumption. Moreover, the CMOS circuit structure can usually achieve stronger output capability with transistors with smaller aspect ratios. While improving the driving effect, it is also beneficial to further reduce the layout space occupied by the shift register and further narrow the bezel width of the display products in which it is applied.

[0160] like Figures 11 to 13 As shown, the operation of the shift register provided in the above embodiment is as follows:

[0161] In stage m1, transistors T19, T20, T21, T22, and T23 are all turned on, while transistor T24 is turned off. The second gate drive signal output from the second gate drive signal output terminal (e.g., gatep-(n+1)) is the same as the first level signal input from the first level signal input terminal VGL, i.e., the second gate drive signal is low.

[0162] During the m2 stage, the nineteenth transistor T19 and the twenty-second transistor T22 are both turned on, while the twentieth transistor T20 and the twenty-third transistor T23 are both turned off, and the second gate drive signal remains at a low level.

[0163] In stage m3, transistors T19, T20, T24, T22, and T23 are all turned on, while transistor T21 is turned off. The second gate drive signal output from the second gate drive signal output terminal (e.g., gatep-(n+1)) is the same as the second level signal input from the second level signal input terminal VGH, i.e., the second gate drive signal is high.

[0164] like Figure 6 As shown, in some embodiments, the display panel further includes a second clock signal line CK1', a third clock signal line CK2', a fourth clock signal line CK3', and a fifth clock signal line CK4';

[0165] The display panel includes a plurality of cascaded second type shift registers. The second start signal input terminal of the first-stage second type shift register is coupled to the second frame start signal line in the display panel; the second start signal input terminal of the (n+1)th-stage second type shift register is coupled to the second gate drive signal output terminal of the nth-stage second type shift register, where n is an integer greater than or equal to 1.

[0166] The cascaded multiple second-type shift registers are divided into multiple shift register groups. Each shift register group includes two adjacent shift registers. In each shift register group, the second clock signal input terminal of the previous shift register is coupled to the second clock signal line CK1', the third clock signal input terminal of the previous shift register is coupled to the third clock signal line CK2', the second clock signal input terminal of the next shift register is coupled to the fourth clock signal line CK3', and the third clock signal input terminal of the next shift register is coupled to the fifth clock signal line CK4'.

[0167] For example, the second clock signal input to the second clock signal line CK1', the third clock signal input to the third clock signal line CK2', the fourth clock signal input to the fourth clock signal line CK3', and the fifth clock signal input to the fifth clock signal line CK4' have the same pulse width and different phases.

[0168] In the gate drive circuit provided in the above embodiment, the shift time width of the second gate drive signal output by the adjacent stage shift register is the period width of the clock signal. If the period width of the clock signal is set to 1H, the shift time width of the second gate drive signal output by the adjacent stage shift register can be 1H.

[0169] The second type of shift register provided in the above embodiment is connected to two clock signal input terminals (a second clock signal input terminal and a third clock signal input terminal). When the second type of shift register is cascaded to form a gate drive circuit, the gate drive circuit can be connected to a total of four clock signal lines, which helps to reduce the loading of clock signal lines and improve the stability of the output gate drive signal.

[0170] In some embodiments, the orthographic projection of the second type of shift register on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the second clock signal line CK1', the third clock signal line CK2', the fourth clock signal line CK3', and the fifth clock signal line CK4' on the substrate.

[0171] The above configuration not only helps to reduce the overall layout space occupied by the gate drive circuit and signal lines formed by the second type of shift register, but also helps to reduce the difficulty of connecting the gate drive circuit and signal lines.

[0172] like Figures 6 to 13 As shown, this embodiment of the invention also provides a shift register, the shift register comprising:

[0173] The second output control circuit 60 is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the first level signal input terminal VGL, and the second gate drive signal output terminal, respectively; it is used to control the electrical connection between the first level signal input terminal VGL and the second gate drive signal output terminal under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0174] The third output control circuit 70 is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the second level signal input terminal VGH, and the second gate drive signal output terminal, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the second gate drive signal output terminal under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0175] The voltage regulator circuit 80 is coupled to the ground signal input terminal and the second gate drive signal output terminal, respectively.

[0176] In some embodiments, the second output control circuit 60 includes:

[0177] The ninth control sub-circuit 66 is coupled to the third clock signal input terminal, the ninth node n9 and the second gate drive signal output terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the ninth node n9 and the second gate drive signal output terminal under the control of the third clock signal input at the third clock signal input terminal.

[0178] The tenth control sub-circuit 61 is coupled to the second clock signal input terminal, the ninth node n9 and the tenth node n10 respectively, and is used to control the conduction or disconnection of the electrical connection between the ninth node n9 and the tenth node n10 under the control of the second clock signal input to the second clock signal input terminal;

[0179] The eleventh control sub-circuit 62 is coupled to the second start signal input terminal, the tenth node n10 and the first level signal input terminal VGL respectively, and is used to control the electrical connection between the tenth node n10 and the first level signal input terminal VGL to be turned on or off under the control of the second start signal input at the second start signal input terminal.

[0180] The twelfth control sub-circuit 63 is coupled to the third clock signal input terminal, the eleventh node n11 and the second gate drive signal output terminal respectively, and is used to control the electrical connection between the eleventh node n11 and the second gate drive signal output terminal to be turned on or off under the control of the third clock signal input at the third clock signal input terminal.

[0181] The thirteenth control sub-circuit 64 is coupled to the second clock signal input terminal, the eleventh node n11 and the twelfth node n12 respectively, and is used to control the conduction or disconnection of the electrical connection between the eleventh node n11 and the twelfth node n12 under the control of the second clock signal input terminal.

[0182] The fourteenth control sub-circuit 65 is coupled to the second start signal input terminal, the twelfth node n12 and the second level signal input terminal VGH respectively, and is used to control the electrical connection between the twelfth node n12 and the second level signal input terminal VGH to be turned on or off under the control of the second start signal input at the second start signal input terminal.

[0183] In some embodiments, the ninth control sub-circuit 66 includes a nineteenth transistor T19, the gate of the nineteenth transistor T19 being coupled to the third clock signal input terminal, the first terminal of the nineteenth transistor T19 being coupled to the ninth node n9, and the second terminal of the nineteenth transistor T19 being coupled to the second gate drive signal output terminal.

[0184] The tenth control sub-circuit 61 includes a twentieth transistor T20, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the tenth node n10, and the second terminal of which is coupled to the ninth node n9.

[0185] The eleventh control sub-circuit 62 includes a twenty-first transistor T21, the gate of which is coupled to the second start signal input terminal, the first terminal of which is coupled to the first level signal input terminal VGL, and the second terminal of which is coupled to the tenth node n10.

[0186] The twelfth control sub-circuit 63 includes a twenty-second transistor T22, the gate of which is coupled to the third clock signal input terminal, the first terminal of which is coupled to the eleventh node n11, and the second terminal of which is coupled to the second gate drive signal output terminal.

[0187] The thirteenth control sub-circuit 64 includes a twenty-third transistor T23, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the twelfth node n12, and the second terminal of which is coupled to the eleventh node n11.

[0188] The fourteenth control sub-circuit 65 includes a twenty-fourth transistor T24, the gate of which is coupled to the second start signal input terminal, the first terminal of which is coupled to the second level signal input terminal VGH, and the second terminal of which is coupled to the twelfth node n12.

[0189] The voltage regulator circuit 80 includes a capacitor structure, the first end of which is coupled to the ground signal input terminal, and the second end of which is coupled to the second gate drive signal output terminal.

[0190] The nineteenth transistor T19, the twenty-first transistor T21, and the twenty-second transistor T22 are P-type transistors, and the twentieth transistor T20, the twenty-third transistor T23, and the twenty-fourth transistor T24 are N-type transistors.

[0191] In some embodiments, the display panel further includes a second clock signal line, a third clock signal line, a fourth clock signal line, and a fifth clock signal line;

[0192] The display panel includes a plurality of cascaded second type shift registers. The second start signal input terminal of the first-stage second type shift register is coupled to the second frame start signal line in the display panel; the second start signal input terminal of the (n+1)th-stage second type shift register is coupled to the second gate drive signal output terminal of the nth-stage second type shift register, where n is an integer greater than or equal to 1.

[0193] The cascaded multiple second-type shift registers are divided into multiple shift register groups. Each shift register group includes two adjacent shift registers. In each shift register group, the second clock signal input terminal of the preceding shift register is coupled to the second clock signal line, the third clock signal input terminal of the preceding shift register is coupled to the third clock signal line, the second clock signal input terminal of the following shift register is coupled to the fourth clock signal line, and the third clock signal input terminal of the following shift register is coupled to the fifth clock signal line.

[0194] In some embodiments, the orthographic projection of the second type of shift register on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the second clock signal line, the third clock signal line, the fourth clock signal line, and the fifth clock signal line on the substrate.

[0195] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0196] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0197] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0198] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0199] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0200] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0201] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A shift register, characterized in that, include: The first node control circuit is coupled to the first node, the first start signal input terminal, the first clock signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively. Under the control of the first start signal input at the first start signal input terminal and the first clock signal input at the first clock signal input terminal, the electrical connection between the first node and the first level signal input terminal is controlled to be turned on or off, and the electrical connection between the first node and the second level signal input terminal is controlled to be turned on or off. The second node control circuit is coupled to the second node, the third node, the first gate drive signal output terminal, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the second node and the first level signal input terminal to be turned on or off under the control of the potential of the third node and the first gate drive signal output from the first gate drive signal output terminal, and to control the electrical connection between the second node and the second level signal input terminal to be turned on or off. A first output control circuit is coupled to the first gate drive signal output terminal, the first node, the second node, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the first gate drive signal output terminal and the first level signal input terminal to be turned on or off under the control of the potential of the first node and the potential of the second node, and to control the electrical connection between the first gate drive signal output terminal and the second level signal input terminal to be turned on or off. The third node control circuit is coupled to the third node, the fourth node, the first clock signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively. Under the control of the potential of the fourth node and the first clock signal input to the first clock signal input terminal, the electrical connection between the third node and the first level signal input terminal is controlled to be turned on or off, and the electrical connection between the third node and the second level signal input terminal is controlled to be turned on or off. The fourth node control circuit is coupled to the fourth node, the first start signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the fourth node and the first level signal input terminal to be turned on or off under the control of the first start signal input at the first start signal input terminal, and to control the electrical connection between the fourth node and the second level signal input terminal to be turned on or off.

2. The shift register according to claim 1, characterized in that, The first node control circuit includes a first control sub-circuit and a second control sub-circuit; The first control sub-circuit is coupled to the first start signal input terminal, the second level signal input terminal, the fifth node, and the first node respectively; it is used to control the electrical connection between the first node and the second level signal input terminal to be turned on or off under the control of the first start signal input at the first start signal input terminal, and to control the electrical connection between the first node and the fifth node to be turned on or off. The second control sub-circuit is coupled to the first clock signal input terminal, the second level signal input terminal, the first node, the fifth node, and the first level signal input terminal respectively; it is used to control the electrical connection between the second level signal input terminal and the first node to be turned on or off under the control of the first clock signal input at the first clock signal input terminal, and to control the electrical connection between the first level signal input terminal and the fifth node to be turned on or off. The second node control circuit includes a third control sub-circuit and a fourth control sub-circuit; The third control sub-circuit is coupled to the third node, the second level signal input terminal, the sixth node, and the second node respectively; it is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the second node under the control of the potential of the third node, and to control the conduction or disconnection of the electrical connection between the sixth node and the second node. The fourth control sub-circuit is coupled to the first gate drive signal output terminal, the second level signal input terminal, the second node, the sixth node, and the first level signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the second node to be turned on or off under the control of the first gate drive signal output from the first gate drive signal output terminal, and to control the electrical connection between the sixth node and the first level signal input terminal to be turned on or off. The first output control circuit includes a fifth control sub-circuit and a sixth control sub-circuit; The fifth control sub-circuit is coupled to the first node, the second level signal input terminal, the first gate drive signal output terminal, and the seventh node, respectively; it is used to control the electrical connection between the second level signal input terminal and the first gate drive signal output terminal to be turned on or off under the control of the potential of the first node, and to control the electrical connection between the seventh node and the first gate drive signal output terminal to be turned on or off. The sixth control sub-circuit is coupled to the second node, the second level signal input terminal, the first gate drive signal output terminal, the seventh node, and the first level signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the first gate drive signal output terminal to be turned on or off under the control of the potential of the second node, and to control the electrical connection between the seventh node and the first level signal input terminal to be turned on or off. The third node control circuit includes a seventh control sub-circuit and an eighth control sub-circuit; The seventh control sub-circuit is coupled to the fourth node, the second level signal input terminal, the third node, and the eighth node respectively; it is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the third node under the control of the potential of the fourth node, and to control the conduction or disconnection of the electrical connection between the third node and the eighth node. The eighth control sub-circuit is coupled to the first clock signal input terminal, the second level signal input terminal, the third node, the eighth node, and the first level signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the third node to be turned on or off under the control of the first clock signal input to the first clock signal input terminal, and to control the electrical connection between the eighth node and the first level signal input terminal to be turned on or off.

3. The shift register according to claim 2, characterized in that, The first control sub-circuit includes a first transistor and a third transistor; the gate of the first transistor is coupled to the first start signal input terminal, the first electrode of the first transistor is coupled to the second level signal input terminal, and the second electrode of the first transistor is coupled to the first node; the gate of the third transistor is coupled to the first start signal input terminal, the first electrode of the third transistor is coupled to the fifth node, and the second electrode of the third transistor is coupled to the first node. The second control sub-circuit includes a second transistor and a fourth transistor; The gate of the second transistor is coupled to the first clock signal input terminal, the first terminal of the second transistor is coupled to the second level signal input terminal, and the second terminal of the second transistor is coupled to the first node; the gate of the fourth transistor is coupled to the first clock signal input terminal, the first terminal of the fourth transistor is coupled to the first level signal input terminal, and the second terminal of the fourth transistor is coupled to the fifth node; The third control sub-circuit includes a thirteenth transistor and a fifteenth transistor; The gate of the thirteenth transistor is coupled to the third node, the first terminal of the thirteenth transistor is coupled to the second level signal line, and the second terminal of the thirteenth transistor is coupled to the second node; the gate of the fifteenth transistor is coupled to the third node, the first terminal of the fifteenth transistor is coupled to the sixth node, and the second terminal of the fifteenth transistor is coupled to the second node. The fourth control sub-circuit includes a fourteenth transistor and a sixteenth transistor; The gate of the fourteenth transistor is coupled to the first gate drive signal output terminal, the first terminal of the fourteenth transistor is coupled to the second level signal input terminal, and the second terminal of the fourteenth transistor is coupled to the second node; the gate of the sixteenth transistor is coupled to the first gate drive signal output terminal, the first terminal of the sixteenth transistor is coupled to the first level signal input terminal, and the second terminal of the sixteenth transistor is coupled to the sixth node. The fifth control sub-circuit includes a fifth transistor and a seventh transistor. The gate of the fifth transistor is coupled to the first node, the first terminal of the fifth transistor is coupled to the second level signal input terminal, and the second terminal of the fifth transistor is coupled to the first gate drive signal output terminal. The gate of the seventh transistor is coupled to the first node, the first terminal of the seventh transistor is coupled to the seventh node, and the second terminal of the seventh transistor is coupled to the first gate drive signal output terminal. The sixth control sub-circuit includes a sixth transistor and an eighth transistor. The gate of the sixth transistor is coupled to the second node, the first terminal of the sixth transistor is coupled to the second level signal input terminal, and the second terminal of the sixth transistor is coupled to the first gate drive signal output terminal. The gate of the eighth transistor is coupled to the second node, the first terminal of the eighth transistor is coupled to the first level signal input terminal, and the second terminal of the eighth transistor is coupled to the seventh node. The seventh control sub-circuit includes a ninth transistor and an eleventh transistor. The gate of the ninth transistor is coupled to the fourth node, the first terminal of the ninth transistor is coupled to the second level signal input terminal, and the second terminal of the ninth transistor is coupled to the third node. The gate of the eleventh transistor is coupled to the fourth node, the first terminal of the eleventh transistor is coupled to the eighth node, and the second terminal of the eleventh transistor is coupled to the third node. The eighth control sub-circuit includes a tenth transistor and a twelfth transistor. The gate of the tenth transistor is coupled to the first clock signal input terminal, the first terminal of the tenth transistor is coupled to the second level signal input terminal, and the second terminal of the tenth transistor is coupled to the third node. The gate of the twelfth transistor is coupled to the first clock signal input terminal, the first terminal of the twelfth transistor is coupled to the first level signal input terminal, and the second terminal of the twelfth transistor is coupled to the eighth node. The fourth node control circuit includes a seventeenth transistor and an eighteenth transistor. The gate of the seventeenth transistor is coupled to the first start signal input terminal, the first terminal of the seventeenth transistor is coupled to the second level signal input terminal, and the second terminal of the seventeenth transistor is coupled to the fourth node. The gate of the eighteenth transistor is coupled to the first start signal input terminal, the first terminal of the eighteenth transistor is coupled to the first level signal input terminal, and the second terminal of the eighteenth transistor is coupled to the fourth node. The first transistor, the second transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor, and the fourteenth transistor are P-type transistors; the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor, and the sixteenth transistor are N-type transistors.

4. A gate driving circuit, characterized in that, It includes multiple cascaded shift registers as described in any one of claims 1 to 3; the first start signal input terminal of the first-stage shift register is coupled to the first frame start signal line; the first start signal input terminal of the (n+1)th-stage shift register is coupled to the first gate drive signal output terminal of the nth-stage shift register, where n is an integer greater than or equal to 1.

5. A display panel, characterized in that, Including the gate driving circuit as described in claim 4, the display panel further includes a first clock signal line, wherein at least a portion of the shift register in the gate driving circuit has its orthogonal projection on the substrate of the display panel at least partially overlaps with the orthogonal projection of the first clock signal line on the substrate.

6. The display panel according to claim 5, characterized in that, The display panel further includes a second type of shift register, which includes: The second output control circuit is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the first level signal input terminal, and the second gate drive signal output terminal, respectively; it is used to control the electrical connection between the first level signal input terminal and the second gate drive signal output terminal to be turned on or off under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal. The third output control circuit is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the second level signal input terminal, and the second gate drive signal output terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the second gate drive signal output terminal to be turned on or off under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal. The voltage regulator circuit is coupled to the ground signal input terminal and the second gate drive signal output terminal, respectively.

7. The display panel according to claim 6, characterized in that, The second output control circuit includes: The ninth control sub-circuit is coupled to the third clock signal input terminal, the ninth node and the second gate drive signal output terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the ninth node and the second gate drive signal output terminal under the control of the third clock signal input at the third clock signal input terminal. The tenth control sub-circuit is coupled to the second clock signal input terminal, the ninth node, and the tenth node respectively, and is used to control the conduction or disconnection of the electrical connection between the ninth node and the tenth node under the control of the second clock signal input to the second clock signal input terminal; The eleventh control sub-circuit is coupled to the second start signal input terminal, the tenth node and the first level signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the tenth node and the first level signal input terminal under the control of the second start signal input to the second start signal input terminal; The twelfth control sub-circuit is coupled to the third clock signal input terminal, the eleventh node and the second gate drive signal output terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the eleventh node and the second gate drive signal output terminal under the control of the third clock signal input at the third clock signal input terminal. The thirteenth control sub-circuit is coupled to the second clock signal input terminal, the eleventh node and the twelfth node respectively, and is used to control the conduction or disconnection of the electrical connection between the eleventh node and the twelfth node under the control of the second clock signal input to the second clock signal input terminal; The fourteenth control sub-circuit is coupled to the second start signal input terminal, the twelfth node and the second level signal input terminal respectively, and is used to control the electrical connection between the twelfth node and the second level signal input terminal to be turned on or off under the control of the second start signal input at the second start signal input terminal.

8. The display panel according to claim 7, characterized in that, The ninth control sub-circuit includes a nineteenth transistor, the gate of which is coupled to the third clock signal input terminal, the first terminal of which is coupled to the ninth node, and the second terminal of which is coupled to the second gate drive signal output terminal. The tenth control sub-circuit includes a twentieth transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the tenth node, and the second terminal of which is coupled to the ninth node. The eleventh control sub-circuit includes a twenty-first transistor, the gate of which is coupled to the second start signal input terminal, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the tenth node. The twelfth control sub-circuit includes a twenty-second transistor, the gate of which is coupled to the third clock signal input terminal, the first terminal of which is coupled to the eleventh node, and the second terminal of which is coupled to the second gate drive signal output terminal. The thirteenth control sub-circuit includes a twenty-third transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the twelfth node, and the second terminal of which is coupled to the eleventh node. The fourteenth control sub-circuit includes a twenty-fourth transistor, the gate of which is coupled to the second start signal input terminal, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the twelfth node. The voltage regulator circuit includes a capacitor structure, with a first end of the capacitor structure coupled to the ground signal input terminal and a second end of the capacitor structure coupled to the second gate drive signal output terminal. The nineteenth, twenty-first, and twenty-second transistors include P-type transistors, and the twentieth, twenty-third, and twenty-fourth transistors include N-type transistors.

9. The display panel according to claim 7, characterized in that, The display panel also includes a second clock signal line, a third clock signal line, a fourth clock signal line, and a fifth clock signal line; The display panel includes a plurality of cascaded second type shift registers. The second start signal input terminal of the first-stage second type shift register is coupled to the second frame start signal line in the display panel; the second start signal input terminal of the (n+1)th-stage second type shift register is coupled to the second gate drive signal output terminal of the nth-stage second type shift register, where n is an integer greater than or equal to 1. The cascaded multiple second-type shift registers are divided into multiple shift register groups. Each shift register group includes two adjacent shift registers. In each shift register group, the second clock signal input terminal of the preceding shift register is coupled to the second clock signal line, the third clock signal input terminal of the preceding shift register is coupled to the third clock signal line, the second clock signal input terminal of the following shift register is coupled to the fourth clock signal line, and the third clock signal input terminal of the following shift register is coupled to the fifth clock signal line.

10. The display panel according to claim 9, characterized in that, The orthographic projection of the second type of shift register on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the second clock signal line, the third clock signal line, the fourth clock signal line, and the fifth clock signal line on the substrate.

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