Display device

Abstract

Disclosed in the present specification is a display device. A display device according to an embodiment of the present specification includes: a display panel including a plurality of gate drivers and a plurality of pixels arranged in a matrix form; a plurality of level shifters connected to the plurality of gate drivers; and a timing controller connected to the plurality of level shifters, in which the plurality of gate drivers may be disposed between the plurality of pixels. According to an embodiment of the present specification, a display device that adjusts a frame frequency according to each divided driving region may be provided.

Description

Technical Field

[0001] This specification relates to a device, and more particularly to, for example, but not limited to, a display device. Background Technology

[0002] The driving circuit of a flat panel display (FPD) device writes pixel data of an input image to the pixels of the display panel to reproduce the input image on the pixel array. The driving circuit of the display device includes a data driving circuit that provides data signals to data lines, a gating driving circuit that provides gating pulses to gating lines, and a timing controller for controlling the operating timing of the data driving circuit and the gating driving circuit.

[0003] The timing controller controls the outputs of the data drive circuit and the gating drive circuit. The timing controller generates a clock signal to control the gating drive circuit. A level shifter generates a clock in response to the clock input from the timing controller. The gating drive circuit uses a shift register with a clock input to sequentially output gating pulses.

[0004] The descriptions provided in the Background section should not be assumed to be prior art simply because they are mentioned in or associated with that section. The Background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0005] Since the screen size of information devices can be enlarged by using a display, multitasking can be achieved by running two or more applications or content, and a large amount of information can be displayed on the screen simultaneously. It may be necessary to display different images on the screen or control the frame rate of the images differently. In this case, the output of the gating drive circuit is typically controlled independently for each area of ​​the screen. In this situation, the inventors of this disclosure have recognized the limitation that the gating drive circuit becomes larger and its control circuitry becomes more complex.

[0006] This specification is intended to address the aforementioned needs and / or limitations based on relevant technologies.

[0007] The purposes of the embodiments described herein are not limited to those described above, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] A display device according to an embodiment of this specification includes: a display panel including a plurality of gating drivers and a plurality of pixels arranged in a matrix; a plurality of level shifters connected to the plurality of gating drivers; and a timing controller connected to the plurality of level shifters, wherein the plurality of gating drivers are disposed between the plurality of pixels.

[0009] According to various embodiments of this specification, the display panel may include a display area, which includes a first display area and a second display area, and a plurality of gating drivers may include a first gating driver disposed in the first display area and a second gating driver disposed in the second display area.

[0010] According to various embodiments of this specification, the pulse width of the start signal input to the first gating driver may be different from the pulse width of the start signal input to the second gating driver.

[0011] According to various embodiments of this specification, the first frame frequency driving the first display area may be different from the second frame frequency driving the second display area.

[0012] According to various embodiments of this specification, a plurality of level shifters may include a first level shifter connected to a first gating driver and a second level shifter connected to a second gating driver.

[0013] According to various embodiments of this specification, the first level shifter can be connected to the second gating driver, and the second level shifter can be connected to the first gating driver.

[0014] According to various embodiments of this specification, the display device may further include a plurality of source driver integrated circuits (ICs) disposed between a plurality of level shifters and a plurality of gating drivers, wherein the plurality of source driver ICs may be respectively connected to the plurality of level shifters and the plurality of gating drivers.

[0015] According to various embodiments of this specification, a plurality of source driver ICs may include a first source driver IC disposed between a first level shifter and a first gating driver, and a second source driver IC disposed between a second level shifter and a second gating driver.

[0016] According to various embodiments of this specification, a first source driver IC can be connected to a first level shifter and a first gating driver, and a second source driver IC can be connected to a second level shifter and a second gating driver.

[0017] According to various embodiments of this specification, the first source driver IC can be connected to the second level shifter, and the second source driver IC can be connected to the first level shifter.

[0018] According to various embodiments of this specification, the display device may further include a first multiplexer connected to the first level shifter, the second level shifter, and the first source driver IC, and a second multiplexer connected to the second level shifter, the first level shifter, and the second source driver IC.

[0019] According to various embodiments of this specification, the display area may further include a third display area, and the plurality of gating drivers may further include a third gating driver disposed in the third display area.

[0020] According to various embodiments of this specification, the first frame frequency driving the first display area, the second frame frequency driving the second display area, and the third frame frequency driving the third display area can all be different from each other.

[0021] According to various embodiments of this specification, a plurality of level shifters may include a first level shifter connected to a first gating driver, a second level shifter connected to a second gating driver, and a third level shifter connected to a third gating driver.

[0022] According to various embodiments of this specification, a first level shifter can be connected to a second gating driver and a third gating driver, a second level shifter can be connected to a first gating driver and a third gating driver, and a third level shifter can be connected to both the first and second gating drivers.

[0023] According to various embodiments of this specification, the display device may further include a plurality of source driver ICs disposed between a plurality of level shifters and a plurality of gating drivers, wherein the plurality of source driver ICs may be respectively connected to the plurality of level shifters and the plurality of gating drivers.

[0024] According to various embodiments of this specification, a plurality of source driver ICs may include a first source driver IC disposed between a first level shifter and a first gating driver, a second source driver IC disposed between a second level shifter and a second gating driver, and a third source driver IC disposed between a third level shifter and a third gating driver.

[0025] According to various embodiments of this specification, a first source driver IC can be connected to a first level shifter and a first gating driver, a second source driver IC can be connected to a second level shifter and a second gating driver, and a third source driver IC can be connected to a third level shifter and a third gating driver.

[0026] According to various embodiments of this specification, the first source driver IC can be connected to the second level shifter and the third level shifter, the second source driver IC can be connected to the first level shifter and the third level shifter, and the third source driver IC can be connected to the first level shifter and the second level shifter.

[0027] According to various embodiments of this specification, the display device may further include: a first multiplexer connected to the first level shifter, the second level shifter, the third level shifter and the first source driver IC; a second multiplexer connected to the second level shifter, the first level shifter, the third level shifter and the second source driver IC; and a third multiplexer connected to the third level shifter, the first level shifter, the second level shifter and the third source driver IC.

[0028] Other systems, methods, features, and advantages will be apparent or become apparent to those skilled in the art upon reading the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages are included in this specification, fall within the scope of this disclosure, and are protected by the appended claims. Nothing in this section should be construed as limiting these claims. Further aspects and advantages will be discussed below in conjunction with embodiments of this disclosure. Attached Figure Description

[0029] The following figures illustrate some embodiments of this disclosure and, together with the detailed description of this disclosure to follow, are used to further understand the technical concept of this disclosure. Therefore, this disclosure should not be construed as limited to the matters described in these figures, wherein:

[0030] Figure 1 This is a block diagram illustrating a display device according to an embodiment of this specification;

[0031] Figure 2 This is a block diagram illustrating a display device according to another embodiment of this specification;

[0032] Figure 3 It is a waveform diagram showing the timing signal synchronized with the image signal;

[0033] Figure 4 This is a circuit diagram illustrating a pixel circuit according to an embodiment of this specification;

[0034] Figure 5 This is a circuit diagram illustrating a pixel circuit according to another embodiment of this specification;

[0035] Figures 6 to 8 This is a view illustrating various embodiments of a level shifter in a display device according to embodiments of this specification;

[0036] Figure 9 This is a schematic view of the gating driver that outputs the gating signal;

[0037] Figure 10 This is a view showing the gating driver that outputs the gating signal applied to the pixel circuit;

[0038] Figure 11 This is a schematic diagram illustrating the circuit of a shift register with a gating driver;

[0039] Figure 12 This is a circuit diagram showing the circuitry of a stage according to an embodiment of this specification;

[0040] Figure 13 This is a waveform diagram showing the input / output waveforms of a stage circuit according to an embodiment of this specification;

[0041] Figure 14 This is a circuit diagram showing one channel of a level shifter;

[0042] Figure 15 This is a circuit diagram showing the channels of a level shifter;

[0043] Figure 16 This is a waveform diagram showing the input / output signals of the level shifter;

[0044] Figure 17 This is a block diagram showing a display device including a level shifter;

[0045] Figure 18 This is a block diagram illustrating a display device according to a first embodiment of this specification;

[0046] Figure 19 This is a block diagram illustrating a display device according to a second embodiment of this specification;

[0047] Figure 20 This is a waveform diagram illustrating an exemplary input / output signal of a level shifter included in a display device according to the second embodiment;

[0048] Figure 21 This is a waveform diagram showing an exemplary output signal of a level shifter included in a display device according to the second embodiment;

[0049] Figure 22 This is a block diagram illustrating a display device according to a third embodiment of this specification;

[0050] Figure 23 This is a block diagram illustrating the signal transmission path in a display device according to a third embodiment of this specification;

[0051] Figure 24 This is a block diagram illustrating a display device according to a fourth embodiment of this specification;

[0052] Figure 25 This is a waveform diagram illustrating the exemplary multiplexer control and output signals of this specification;

[0053] Figure 26This is a view illustrating an example of a display device according to an embodiment of this specification applied to a vehicle's infotainment system; and

[0054] Figure 27 This is a waveform diagram showing the frame rate used for each display area.

[0055] Throughout the accompanying drawings and detailed embodiments, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0056] The advantages and features of this specification, as well as methods of implementing them, will become clear from the following detailed description of embodiments taken in conjunction with the accompanying drawings. This specification is not limited to the embodiments described below, and may be implemented in various forms. The embodiments are provided only to fully disclose this specification and to fully convey its scope to those skilled in the art, and this specification is defined by the disclosed claims.

[0057] The foregoing objects, features, and advantages of this disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the technical concepts of this disclosure. In describing this specification, detailed descriptions of relevant known technologies will be omitted where it is determined that such descriptions might unnecessarily obscure the essential points of this specification.

[0058] The same reference numerals refer to the same components. Furthermore, some portions of the figures may be exaggerated to effectively describe the thickness, proportions, and dimensions of the components. For ease of description, the scale of the components depicted in the figures differs from the actual scale and is not limited to the scale depicted in the figures.

[0059] When using terms such as "provides," "may include," "has," or "consist of" in this specification, additional parts may be added unless "only" is used. Unless otherwise expressly stated, a component described in the singular may also be interpreted as plural.

[0060] When describing positional and interconnection relationships between two components, such as “on top of,” “on the upper part,” “on the lower part,” “next to,” “connected or linked,” “crossing or intersecting,” one or more other components may be inserted between these components unless mentioned as “immediately adjacent” or “directly.”

[0061] When describing temporal relationships such as “after,” “following,” “next,” or “before,” the temporal relationship may not be continuous on the timeline unless “immediately following” or “directly” is used.

[0062] The terms "first," "second," etc., can be used to distinguish components, but the function or structure of these components is not restricted by the ordinal number preceding the component or component name.

[0063] "And / or" includes all of one or more combinations that can be defined by the associated components. Throughout the specification, unless otherwise stated, the term "A and / or B" means A, B, or both A and B, and unless otherwise stated, the term "C to D" means C or more and D or fewer.

[0064] Unless the context clearly indicates otherwise, singular expressions used in this specification include plural expressions. In this application, terms such as “comprising” or “including” should not be construed as including all components or steps listed in the specification; some components or steps may be excluded, or additional components or steps may be included.

[0065] Furthermore, when referring to any size, relative size, etc., it should be assumed that numerical values ​​or corresponding information (e.g., level, range, etc.) for a component or feature include tolerances or error ranges that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "can".

[0066] Furthermore, when an element or layer is “connected,” “joined,” or “adhered” to another element or layer, unless otherwise specified, this means that the element or layer can not only be directly connected or adhered to the other element or layer, but also indirectly connected or adhered to the other element or layer by means of one or more intermediate elements or layers “set” or “inserted” between these elements or layers. It should be understood that this means the elements can be configured to be in direct contact with each other, or they can be configured not to be in direct contact with each other.

[0067] When describing quantitative or numerical relationships, terms such as "equal" and "identical" generally mean "substantially equal" and "substantially identical," or "similar or equal" and "similar or identical." That is, based on the premise that two elements are equal or identical, a certain margin of error is allowed, such as one percent, five percent, ten percent, etc.

[0068] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of this disclosure without departing from the technical spirit or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0069] The following implementations can be combined with each other in part or in whole, and technically, various types of interconnections and drives are possible. Implementations can be implemented independently of each other or together in an associated relationship.

[0070] The terms (including technical and scientific terms) used in the embodiments of this specification are to be interpreted as having a meaning that is generally understood by a person skilled in the art, unless explicitly defined and described, and the meaning of commonly used terms (such as terms defined in a dictionary) may be interpreted in light of the contextual meaning of the relevant art.

[0071] In the display device according to this specification, the pixel circuit and the gating drive circuit may include a plurality of transistors. The transistors may be oxide thin-film transistors (TFTs) including oxide semiconductors or low-temperature polycrystalline silicon (LTPS) TFTs including LTPS.

[0072] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow out of the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain.

[0073] In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0074] The gating signal can swing between a gating on voltage and a gating off voltage. The transistor turns on in response to the gating on voltage but turns off in response to the gating off voltage. In the case of an n-channel transistor, the gating on voltage can be the high gating voltage VGH, and the gating off voltage can be the low gating voltage VGL. In the case of a p-channel transistor, the gating on voltage can be the low gating voltage VGL, and the gating off voltage can be the high gating voltage VGH.

[0075] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0076] Figure 1 This is a block diagram illustrating a display device according to an embodiment of this specification. Figure 2 This is a block diagram illustrating a display device according to another embodiment of this specification.

[0077] Reference Figure 1 and Figure 2 The display device according to the embodiments of the present disclosure may include a display panel 100 and a display panel driving circuit.

[0078] The screen of the display panel 100 may include a pixel array AA that displays pixel data of an input image. The pixel data of the input image may be displayed in the pixels of the pixel array AA. The pixel array AA may include multiple data lines DL, multiple gate lines GL intersecting the data lines DL, and pixels arranged in a matrix. In addition to the matrix arrangement, the pixels may also be arranged in various forms such as: pixels sharing the same or substantially the same color of light, stripe arrangement, diamond arrangement, etc.

[0079] When the resolution of the pixel array AA is n*m, the pixel array AA can include n pixel columns and m pixel rows L1 to Lm intersecting the pixel columns. Pixel rows can include pixels positioned in a first direction (e.g., the X-axis direction). Pixel columns can include pixels positioned in the first direction (e.g., the X-axis direction). A horizontal period 1H is the time obtained by dividing one frame period by the number of m pixel rows L1 to Lm. Pixel data can be written to the pixels of a pixel row within one horizontal period 1H.

[0080] Each pixel may include two or more subpixels 101 to achieve color. For example, each pixel may be divided into red subpixels, green subpixels, and blue subpixels. Each pixel may also include a white subpixel. Each subpixel 101 may include pixel circuitry. Pixel circuitry may include pixel electrodes, one or more thin-film transistors (TFTs), and capacitors. Pixel circuitry may be connected to a data line DL and a gate line GL.

[0081] Due to process variations and component characteristic variations caused by the manufacturing process of the display panel, the electrical characteristics of the driving elements between pixels may differ. As the driving time of the pixels increases, these differences in electrical characteristics may become more pronounced. To compensate for these electrical characteristic variations between the driving elements of the pixels, internal compensation techniques or external compensation techniques can be applied.

[0082] A touch sensor can be disposed on the display panel 100 to realize a touch screen. Touch input can be sensed using a separate touch sensor or by pixels. The touch sensor can be implemented as an on-cell type or add-on type sensor disposed on the screen of the display panel, or as an in-cell type touch sensor built into a pixel array.

[0083] The display panel driving circuit can write the input image data into the pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit may include a data driver 110, a gating driver 120, a timing controller 130 for controlling the operating timing of the drivers 110 and 120, and a level shifter 140 connected between the timing controller 130 and the gating driver 120. The display panel driving circuit may also include a power supply unit 300.

[0084] The data driver 110 can convert pixel data of the input image received as a digital signal from the timing controller 130 into analog gamma-compensated voltages for each frame and output data signals Vdata1 to Vdata3. For example... Figure 1 As shown in the circles, the first data signal Vdata1 to the third data signal Vdata3 output from the data driver 110 can be provided to the corresponding first data line DL1 to the third data line DL3. The data driver 110 can use a digital-to-analog converter (hereinafter referred to as "DAC") that converts digital signals into analog gamma-compensated voltages to output data signals Vdata1 to Vdata3. The data driver 110 can be integrated into a source driver integrated circuit (IC). The source driver IC can be mounted on a flexible film and connected between the source printed circuit board (PCB) and the display panel 100 in a chip-on-film (COF) bonding process. A touch sensor driver for driving a touch sensor can be built into each source driver IC.

[0085] The display panel driving circuit may also include a demultiplexer array 112 disposed between the data driver 110 and the data line DL.

[0086] Since the demultiplexer array 112 sequentially connects one channel of the data driver 110 to multiple data lines DL, and distributes the data signal output from one channel of the data driver 110 to the data lines DL in a time-division manner, the number of channels of the data driver 110 can be reduced.

[0087] The gating driver 120 may be formed in the border area BZ on the display panel 100 where no image is displayed, or at least a portion of the gating driver 120 may be disposed in the pixel array AA (see [link]). Figure 2When at least a portion of the gate driver 120 is disposed in the pixel array AA, the gate driver 120 can be disposed in the pixel array AA together with the pixel circuit. The gate driver 120 can sequentially output gate signals to the gate line GL under the control of the timing controller 130. The gate driver 120 can sequentially provide gate signals to the gate line GL by shifting the gate signals using a shift register. Since the gate driver 120 is built into the pixel array AA that reproduces the input image, the left and right border areas, which are non-display areas, in the display panel 100 can be reduced or minimized.

[0088] The strobe driver 120 can receive a clock signal from the level shifter 140 and output a strobe pulse GATE. The strobe pulse GATE can be provided to the strobe line GL.

[0089] The gating pulses GATE1 to GATE3 applied to the first gating line GL1 to the third gating line GL3 can turn on the switching elements of sub-pixel 101 to select the pixel to which the voltage of the charged data signals Vdata1 to Vdata3 is applied. The switching elements of sub-pixel 101 can be turned on in response to the gating on voltage VGH of the corresponding gating pulses GATE1 to GATE3, and can be turned off in response to the gating off voltage VGL. The gating pulses GATE1 to GATE3 can oscillate between the gating on voltage VGH and the gating off voltage VGL. The gating driver 120 can use a shift register to shift the gating pulses.

[0090] The timing controller 130 can control the operation timing of the display panel drivers 110 and 120 at a frame frequency of input frame frequency Xi (where i is a positive integer greater than 0) Hz by multiplying the input frame frequency by i. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase-Alternating Line (PAL) method. In one embodiment, the timing controller 130 can be implemented as a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), etc.

[0091] The timing controller 130 can receive pixel data of the input image and timing signals synchronized with the pixel data from the host system 200. The pixel data of the input image received in the timing controller 130 is a digital signal. The timing controller 130 can transmit the pixel data to the data driver 110. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, a data enable signal DE, etc. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE may have a horizontal period of 1H.

[0092] The timing controller 130 can generate data timing control signals for controlling the data driver 110, gating timing control signals for controlling the gating driver 120, and control signals for controlling the switching elements of the demultiplexer array 112, etc., based on timing signals received from the host system 200. The gating timing control signals can be generated as clocks at digital signal voltage levels.

[0093] The host system 200 can be any of a television (TV), set-top box, navigation system, personal computer (PC), home theater, mobile system, and wearable system. In mobile and wearable devices, the data driver 110, timing controller 130, level shifter 140, etc., can be integrated into a single driver IC (not shown). In mobile systems, the host system 200 can be implemented as an application processor (AP). The host system 200 can transmit pixel data of the input image to the driver IC via a Mobile Industrial Processor Interface (MIPI). The host system 200 can be connected to the driver IC via flexible printed circuitry (e.g., a flexible printed circuit board (FPCB)).

[0094] The clock output from level shifter 140 can oscillate between a gating on voltage VGH and a gating off voltage VGL, and can be supplied to gating driver 120 via clock lines CL1 to CLn. The clock output from level shifter 140 can be applied to at least one of demultiplexer array 112, gating driver 120, data driver 110, and touch sensor driver.

[0095] The power supply unit 300 can use a DC-DC converter to generate the voltages required to drive the pixel array and display panel driving circuitry of the display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, buck-boost converter, etc. The power supply unit 300 can adjust the DC input voltage from the host system 200 to generate DC voltages such as the gamma reference voltage VGMA, the gating on voltage VGH, the gating off voltage VGL, half-VDD (HVDD), and the common voltage of the pixels. The half-VDD voltage is half the voltage compared to VDD and can be used as the output buffer drive voltage for the source driver IC. The gamma reference voltage VGMA can be provided to the data driver 110. The gamma reference voltage VGMA can be divided by grayscale using a voltage divider circuit in the data driver 110 and provided to the DAC of the data driver 110. The power supply unit 300 can generate constant voltages commonly applied to the pixels, such as the pixel drive voltage EVDD and the pixel base voltage EVSS. The power supply unit 300 can change the voltage level of the output voltage in response to the control signal VC generated from the timing controller 130.

[0096] Figure 3 This is a waveform diagram showing the timing signal synchronized with the image signal.

[0097] Reference Figure 3 The vertical synchronization signal Vsync defines a frame period. A frame period is the sum of the active segment AT and the vertical blank segment VB. The horizontal synchronization signal Hsync defines a horizontal period (horizontal time). The data enable signal DE synchronizes with the pixel data to be displayed on a pixel row in the input image to define the valid data segment.

[0098] One pulse period of the data enable signal DE and the horizontal sync signal Hsync is a horizontal period 1H, and the high logic segment of the data enable signal DE can represent the data input timing for one pixel row. One horizontal period 1H can be the time required to write pixel data to the pixels of one pixel row on the display panel.

[0099] The timing controller can receive pixel data of the input image synchronized with the data enable signal DE during the active segment AT and transfer the pixel data to the data driver. During the vertical blank segment VB, the timing controller may not receive the data enable signal DE and there may be no pixel data of the input image, and no pixel data may be transferred to the data driver. During the active segment AT, the timing controller can receive data for one frame for which all pixels (PIX) are to be written.

[0100] As can be seen from the data enable signal DE, the display device can not receive any input data during the vertical blank segment VB. The vertical blank segment VB can include the vertical synchronization time VS, the vertical leading edge FP, and the vertical trailing edge BP. The vertical synchronization time VS can be the time from the falling edge to the rising edge of Vsync. The vertical synchronization time VS can represent the start and end of the screen.

[0101] Figure 4 This is a circuit diagram illustrating a pixel circuit according to an embodiment of this specification. Figure 5 This is a circuit diagram illustrating a pixel circuit according to another embodiment of this specification.

[0102] Reference Figure 4 The pixel circuit may include a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a switching element SWT that supplies a data voltage Vdata to the gate electrode of the driving element DT in response to a gating pulse GATE, and a capacitor Cst connected between the gate electrode and the source electrode of the driving element DT. The driving element DT and the switching element SWT may be implemented as n-channel transistors.

[0103] The pixel drive voltage EVDD can be applied to the drain electrode of the driving element DT. The driving element DT can supply current to the light-emitting element EL to drive the EL based on the gate-to-source voltage Vgs. The driving element DT can be turned on in response to the gate voltage VGH of the gating pulse GATE. The light-emitting element EL can be turned on and emit light when the forward voltage between the anode and cathode is at or above the threshold voltage. A pixel base voltage EVSS lower than the pixel drive voltage EVDD can be applied to the cathode electrode of the light-emitting element EL. A capacitor Cst can be connected between the gate and source electrodes of the driving element DT to maintain the gate-to-source voltage Vgs of the driving element DT.

[0104] The light-emitting element (EL) can be implemented as an organic light-emitting diode (OLED) comprising an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but this specification is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, visible light can be emitted from the emissive layer (EML) because holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML) to form excitons. The OLED used as a light-emitting element can have a stacked structure in which multiple emissive layers are stacked. OLEDs with stacked structures can enhance pixel brightness and lifetime.

[0105] Reference Figure 5According to another embodiment, the pixel circuit may include a light-emitting element EL, a plurality of thin-film transistors SWT1 to SWT5 and DT, a capacitor Cst, etc. Transistors SWT1 to SWT5 and DT may be implemented as p-channel transistors (PMOS), but this specification is not limited thereto.

[0106] Switching transistors SWT1 to SWT5 can be turned on / off according to the gating signals from gating lines GL1 to GL3 to initialize the pixel circuit, connect the source and drain of the driving transistor DT, and then provide a data voltage to the capacitor Cst. Furthermore, switching transistors SWT1 to SWT5 can switch the current path between the driving transistor DT and the light-emitting element EL. When the gate and drain of the driving transistor DT are connected, since the driving transistor DT operates as a diode, the source-to-gate voltage of the driving transistor DT rises to the threshold voltage of the driving transistor DT and can be sampled by the capacitor Cst.

[0107] The light-emitting element (EL) can be implemented as an OLED. The OLED may include an organic compound layer formed between the anode and cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc., but this specification is not limited to these. The anode of the OLED can be connected to the fourth switching transistor (SWT4) and the fifth switching transistor (SWT5) via a fourth node (n4). The cathode of the OLED can be connected to a third power line (PL3) to which EVSS is applied. The driving transistor (DT) can supply current to the OLED to drive it. The OLED can emit light with a current amount controlled by the driving transistor (DT) according to the data voltage (Vdata). The current path of the OLED can be switched by the fourth switching transistor (SWT4).

[0108] A capacitor Cst can be connected between a first node n1 and a second node n2. The first node n1 can be connected to the second electrode of the first switching transistor SWT1, the first electrode of the third switching transistor SWT3, and the first electrode of the capacitor Cst. The second node n2 can be connected to the second electrode of the capacitor Cst, the gate of the driving transistor DT, and the first electrode of the second switching transistor SWT2. A data voltage Vdata, compensated by the threshold voltage Vth of the sampled driving transistor DT, can be charged into the capacitor Cst. Therefore, since the data voltage Vdata in each sub-pixel is compensated by the threshold voltage Vth of the driving transistor DT, the characteristic deviation of the driving transistors in the sub-pixel can be compensated, resulting in uniform driving characteristics.

[0109] The first switching transistor SWT1 is a switching element that provides a data voltage Vdata to the first node n1 in response to the gating voltage of the first scan signal SCAN1. The first switching transistor SWT1 may include a gate connected to the first gating line GL1, a first electrode connected to the data line DL, and a second electrode connected to the first node n1. The first scan signal SCAN1 can be simultaneously applied to pixels in two rows of the pixel array via the first gating line GL1. The first scan signal SCAN1 can define a compensation period for sampling the threshold voltage of the driving transistor DT in the pixels in the two rows and charging the pixels with the data voltage. The first scan signal SCAN1 can be generated as a pulse of the gating voltage.

[0110] The second switching transistor SWT2 can be connected to the gate and the second electrode of the driving transistor DT in response to the gating voltage of the second scan signal SCAN2. The second switching transistor SWT2 may include a gate connected to the second gating line GL2, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0111] The third switching transistor SWT3 can initialize the first node n1 to Vref by providing Vref to the first node n1 in response to the EM signal EM's gating voltage. The third switching transistor SWT3 may include a gate connected to the third gating line GL3, a first electrode connected to the first node n1, and a second electrode connected to the second power supply line PL2. The EM signal EM can define the emission time of the light-emitting element EL.

[0112] The fourth switching transistor SWT4 can switch the current path of the light-emitting element EL in response to the EM signal EM. The gate of the fourth switching transistor SWT4 can be connected to the third gate line GL3. The first electrode of the fourth switching transistor SWT4 can be connected to the third node n3, and the second electrode of the fourth switching transistor SWT4 can be connected to the fourth node n4.

[0113] The fifth switching transistor SWT5 can initialize the voltage at the fourth node n4, which is connected to the anode of the light-emitting element EL, to Vref in response to the second scan signal SCAN2. The fifth switching transistor SWT5 may include a gate connected to the second gate line GL2, a first electrode connected to the second power supply line PL2, and a second electrode connected to the fourth node n4.

[0114] The driving transistor DT is a driving element that controls the current flowing through the light-emitting element EL based on the gate-to-source voltage Vgs. The driving transistor DT may include a gate connected to the second node n2, a first electrode connected to the first power line PL1, and a second electrode connected to the third node n3. ELVDD can be supplied to the pixel through the first power line PL1.

[0115] Figures 6 to 8 This is a view illustrating various embodiments of a level shifter in a display device according to embodiments of this specification.

[0116] Reference Figures 6 to 8 The control board 150 can be connected to the first source PCB 152 and the second source PCB 153 via a flexible circuit board (e.g., a flexible circuit board 151 such as a flexible flat cable (FFC) or an FPCB) and connectors 151a and 151b. The source driver IC 110a can be connected between the source PCBs 152 and 153 and the display panel 100.

[0117] Reference Figure 6 The timing controller 130 and the level shifter 140 can be mounted on the control board 150. The input terminals of the level shifter 140 can be connected to the timing controller 130 via lines formed on the control board 150. The output terminals of the level shifter 140 can be connected to the gating driver 120 via lines connecting the flexible circuit board 151, the source PCB 152, the COF 110b, and the gating driver 120 on the display panel 100.

[0118] Reference Figure 7 Level shifters 141 and 142 can be mounted on source PCBs 152 and 153, respectively. Level shifters 141 and 142 may include a first level shifter 141 mounted on the first source PCB 152 and a second level shifter 142 mounted on the second source PCB 153. The input terminals of level shifters 141 and 142 can be connected to the timing controller 130 via lines connecting the control board 150, the flexible circuit board 151, and the source PCBs 152 and 153. The output terminals of level shifters 141 and 142 can be connected to the gating driver 120 via lines connecting the source PCBs 152 and 153, COF 110b, and the gating driver 120 on the display panel 100.

[0119] Reference Figure 8Level shifters 141 and 142 can be connected to source driver IC 110a. Timing controller 130 can send video data packets including pixel data of the input image and control packets including various types of control information to source driver IC 110a. Timing controller 130 can encode gating timing control information into control packets and transmit the gating timing control information to source driver IC 110a, and source driver IC 110a can generate gating timing control signals from the gating timing control information and provide the gating timing control signals to level shifters 141 and 142.

[0120] Figure 9 This is a schematic view of the gating driver that outputs the gating signal. Figure 10 This is a view showing the gating driver that outputs the gating signal applied to the pixel circuit.

[0121] Reference Figure 9 The gating driver may include a first shift register SR1 that sequentially outputs pulses of the first scan signals SC1n-i and SC1n, a second shift register SR2 that sequentially outputs pulses of the second scan signals SC2n-i and SC2n, and a third shift register SR3 that outputs pulses of the EM signals EMn-i and EMn, wherein n is an integer greater than or equal to 2 and i = 1, 2, ..., n-1.

[0122] The first shift register SR1 may include multiple cascaded stages ST1. The first shift register SR1 can receive the start pulse G1VST and the clock G1CLK, and output the pulses of the first scan signal in the order of SC11, SC12, ..., SC1n-i and SC1n.

[0123] The second shift register SR2 may include multiple cascaded stages ST2. The second shift register SR2 can receive the start pulse G2VST and the clock G2CLK, and output the pulses of the second scan signal in the order of SC21, SC22, ..., SC2n-i and SC2n.

[0124] The third shift register SR3 can include multiple cascaded ST3 stages. The third shift register SR3 can receive the start pulse EVST and the clock ECLK, and output the pulses of the EM signal in the order of EM1, EM2, ..., EMn-i and EMn.

[0125] The clock signal CLK input to shift registers SR1, SR2, and SR3 can be two or more clocks with different phases. The start pulse and clock input to shift registers SR1, SR2, and SR3 can differ from each other in one or more aspects of their phase, frequency, and duty cycle.

[0126] Reference Figure 10 The strobe driver may include a first shift register SR1 that sequentially outputs pulses of the first scan signal SC1n, a second shift register SR2 that sequentially outputs pulses of the second scan signal SC2n, and a third shift register SR3 that sequentially outputs pulses of the EM signal EMn.

[0127] The first shift register SR1 may include multiple cascaded stages ST1. The first shift register SR1 can receive a start pulse G1VST and clocks G1CLK1, G1CLK2, G1CLK3, and G1CLK4, and sequentially output pulses of the first scan signal SC1n. Clocks G1CLK1, G1CLK2, G1CLK3, and G1CLK4 may include two or more shift clocks with different phases.

[0128] The second shift register SR2 may include multiple cascaded stages ST2. The second shift register SR2 can receive a start pulse G2VST and clocks G2CLK1, G2CLK2, G2CLK3, G2CLK4, and G2CLK5, and sequentially output pulses of the second scan signal SC2n. Clocks G2CLK1, G2CLK2, G2CLK3, G2CLK4, and G2CLK5 may include two or more shift clocks with different phases.

[0129] The third shift register SR3 may include multiple cascaded stages ST3. The third shift register SR3 can receive the start pulse EVST and clocks ECLK1 and ECLK2, and sequentially output pulses of the EM signal EMn. Clocks ECLK1 and ECLK2 may include two or more shift clocks with different phases. The pulse width of the EM signal EMn can be set to be wider than a horizontal period to be applied simultaneously to pixels located in multiple pixel rows.

[0130] Figure 11 This is a schematic diagram of the shift register of the gating driver.

[0131] Reference Figure 11 The shift register of the strobe driver GIP can include cascaded stages ST. The shift register can receive a start pulse VST or a carry signal CAR and can receive clocks CLK1 to CLKn. The carry signal CAR can be output from the previous stage.

[0132] The driver in each ST stage can charge and discharge the first control node Q and the second control node QB. The output buffer of each ST stage can include a pull-up transistor Tu and a pull-down transistor Td.

[0133] When the first control node Q is charged and clocks CLK1 to CLKn are input, the pull-up transistor Tu can be turned on, and the output voltage at the output node serves as the turn-on voltage. The pull-down transistor Td can be turned on when the second control node QB is charged, and the output voltage at the output node serves as the turn-off voltage.

[0134] The output buffer of the gating driver GIP can be connected to the gating line. The pulses of the gating signals SCAN and EM output through the output buffer of each channel of the gating driver GIP can oscillate between the gating on voltage and the gating off voltage, and the phase can be shifted sequentially.

[0135] Figure 12 This is a circuit diagram illustrating a stage of circuitry according to an embodiment of this specification. Figure 13 This is a waveform diagram showing the input / output waveforms of a stage circuit according to an embodiment of this specification.

[0136] Reference Figure 12 and Figure 13 The nth stage circuit may include multiple transistors T1 to T7, multiple capacitors C3 to C5, and nodes that interconnect the transistors and capacitors.

[0137] Each of the first transistor T1 through the seventh transistor T7 may include a p-channel TFT. The p-channel TFT can respond to... Figure 13 The circuit is turned on by a low gate voltage VGL, but can be turned off in response to a high gate voltage VGH. In the case of a p-channel TFT, the turn-on voltage can be the low gate voltage VGL, and the turn-off voltage can be the high gate voltage VGH.

[0138] The stage circuit may include a CLK node nCLK with a clock signal CLK input, a VST node nVST with a start signal or carry signal VST / CAR input from the previous stage, a first control node nQ, a second control node nQB, an output node nO with an output gating signal GOUT and / or carry signal, a gating voltage node nVGL with a gating voltage VGL applied (hereinafter abbreviated as "VGL node"), and a gating voltage node nVGH with a gating voltage VGH applied (hereinafter abbreviated as "VGH node"), etc.

[0139] The gate voltage VGL applied to the VGL node can be a first constant voltage. The gate voltage VGL applied to the VGL node can be a voltage that swings between a gate high voltage and a gate low voltage. The gate voltage VGH applied to the VGH node can be a second constant voltage.

[0140] In the following text, the fact that a particular node is "activated" means that a gating voltage or a voltage corresponding to the gating voltage can be applied to the node. The fact that a particular node is "deactivated" means that a gating cutoff voltage or a voltage corresponding to the gating cutoff voltage can be applied to that node.

[0141] The stage circuit may include a Q controller, a QB controller, an output unit, and a first stabilizing unit.

[0142] The Q controller may include a first transistor T1. The first transistor T1 can activate the QC node nQC by applying a start signal VST / CAR, which applies a gating voltage to the QC node nQC in response to the clock signal CLK. The gate electrode of the first transistor T1 may be connected to the CLK node nCLK, and the first electrode and the second electrode of the first transistor T1 may be connected to the VST node nVST and the QC node nQC, respectively.

[0143] The QB controller can activate the second control node nQB in response to the clock signal CLK, the start signal VST / CAR, and the potential of the QC node nQC, to be opposite to that of the QC node nQC. The QB controller may include a fifth capacitor C5, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fourth capacitor C4.

[0144] The fifth capacitor C5 can be connected between the CLK node nCLK and the QD node nQD. The third transistor T3 can provide a clock signal CLK to the second control node nQB in response to the potential of the QD node nQD. The gate electrode of the third transistor T3 can be connected to the QD node nQD, and the first electrode and the second electrode of the third transistor T3 can be connected to the CLK node nCLK and the second control node nQB, respectively.

[0145] The second transistor T2 can provide a gating cutoff voltage to the QD node nQD in response to the start signal VST / CAR. The gate electrode of the second transistor T2 can be connected to the VST node nVST, and the first and second electrodes of the second transistor T2 can be connected to the QD node nQD and the VGH node nVGH, respectively. The potential of the QD node nQD can be synchronized with the clock signal CLK, while the start signal VST / CAR is maintained at the gating cutoff voltage. Alternatively, the potential of the QD node nQD can be a gating cutoff voltage, while the start signal VST / CAR is maintained at the gating on voltage.

[0146] The fourth transistor T4 can provide a gate cutoff voltage to the second control node nQB in response to the potential of the QC node nQC. The gate electrode of the fourth transistor T4 can be connected to the QC node nQC, and the first electrode and the second electrode of the fourth transistor T4 can be connected to the second control node nQB and the VGH node nVGH, respectively.

[0147] The fourth capacitor C4 can be connected between the second control node nQB and the VGH node nVGH to stabilize the potential of the second control node nQB.

[0148] The output unit may include a sixth transistor T6 as a pull-down element, a seventh transistor T7 as a pull-up element, and a third capacitor C3.

[0149] The sixth transistor T6 can provide the gating signal GOUT of the turn-on voltage VGL to the output node nO from the timing of the bootstrapping synchronized with the activation of the first control node nQ and the QC node nQC. The gate electrode of the sixth transistor T6 can be connected to the first control node nQ, and the first electrode and the second electrode of the sixth transistor T6 can be connected to the VGL node nVGL and the output node nO, respectively.

[0150] The third capacitor C3 can be connected between the first control node nQ and the output node nO. The third capacitor C3 can be used to bootstrap the first control node nQ by reflecting the change in the potential of the output node nO to the potential of the first control node nQ when the gating signal GOUT changes from the gating cutoff voltage to the gating on voltage.

[0151] When the second control node nQB is activated, the seventh transistor T7 can provide a gating signal GOUT of the gating cutoff voltage VGH to the output node nO. The gate electrode of the seventh transistor T7 can be connected to the second control node nQB, and the first electrode and the second electrode of the seventh transistor T7 can be connected to the output node nO and the VGH node nVGH, respectively.

[0152] The first stabilizing unit may include a fifth transistor T5. The gate electrode of the fifth transistor T5 may be connected to the VGL node nVGL, and the first and second electrodes of the fifth transistor T5 may be connected to the QC node nQC and the first control node nQ, respectively. When the first control node nQ is bootstrapping, the channel current between the first and second electrodes of the fifth transistor T5 can be zero. When the first control node nQ is bootstrapping, the fifth transistor T5 can be turned off, thus blocking the electrical connection between the QC node nQC and the first control node nQ. When the first control node nQ is not bootstrapping, the fifth transistor T5 can remain in the on state.

[0153] The fifth transistor T5 can remain in the on state and can be turned off only when the first control node nQ is bootstrapping, thus blocking the current flow between the QC node nQC and the first control node nQ. When the first control node nQ is bootstrapping, the potential of the QC node nQC can differ from the potential of the first control node nQ. Since the potential of the QC node nQC does not change even if the potential of the first control node nQ changes during bootstrapping, overload can be prevented when the first control node nQ is bootstrapping, connecting the first transistor T1 and the fourth transistor T4 to the QC node nQC.

[0154] When the fifth transistor T5 is absent, the drain-to-source voltage Vds of the first transistor T1 and the gate-to-source voltage Vgs of the fourth transistor T4 may increase to the threshold or greater due to bootstrapping, and if the overload continues, component failure, i.e., breakdown, may occur. The fifth transistor T5 prevents the first transistor T1 and the fourth transistor T4 connected to the QC node nQC from breaking down during the bootstrapping of the first control node nQ.

[0155] Figure 14 This is a circuit diagram showing one channel of a level shifter. Figure 15 This is a circuit diagram showing the channels of a level shifter. Figure 16 This is a waveform diagram showing the input / output signals of the level shifter.

[0156] Reference Figure 14 and Figure 15 One channel of level shifter 140 may include a driver SRL that receives a first input clock GCLK and a second input clock MCLK, a pull-up transistor HS driven by driver SRL, and a pull-down transistor LS driven by driver SRL. “GIP” indicates gating driver 120. Channels of level shifters 140 to 142 may be connected to clock line CL via output terminals, respectively.

[0157] The first input clock GCLK and the second input clock MCLK can be generated from the timing controller 130 and input to the driver SRL. The driver SRL can turn on the pull-up transistor HS in response to the first input clock GCLK and turn on the pull-down transistor LS in response to the second input clock MCLK. The driver SRL can turn on the pull-up transistor HS on the rising edge of the first input clock GCLK and turn on the pull-down transistor LS on the falling edge of the second input clock MCLK, but this specification is not limited thereto. When the pull-up transistor HS is on and the pull-down transistor LS is off, the voltage at the output terminal OUT can be charged to the gate turn-on voltage VGH. When the pull-up transistor HS is off and the pull-down transistor LS is on, the voltage at the output terminal OUT can be discharged to the gate cut-off voltage VGL.

[0158] Reference Figure 15 and Figure 16 The level shifter 140 can output clocks CLK1 to CLKn with sequentially shifted phases through multiple channels. Drivers SRL1 to SRLn can transmit carry signals to the driver of the next channel. The first driver SRL1 to the nth driver SRLn can be enabled and can generate outputs when a carry signal is input.

[0159] At least a portion of the clocks CLK1 to CLKn output from the level shifter 140 may overlap. In this case, the gating driver GIP receiving the clocks CLK1 to CLKn may sequentially provide pulses of at least partially overlapping gating signals to the gating line GL.

[0160] Figure 17 This is a block diagram showing a display device including a level shifter.

[0161] Reference Figure 17 The display area of ​​the display device can be divided and driven to display multiple images. For example, the display area may include a first display area DA1 displaying a first image, a second display area DA2 displaying a second image, etc. Alternatively, the display area can be divided and driven to display a first display area DA1 displaying a first image, a second display area DA2 displaying a second image, and a third display area DA3 displaying a third image.

[0162] In one example, the first display area DA1 can be a high-speed driving area, the second display area DA2 can be a low-speed driving area, and the third display area DA3 can be a medium-speed driving area. For example, the first display area DA1 can be a high-speed driving area that updates the image at a frame rate of 120Hz. The second display area DA2 can be a low-speed driving area that updates the image at a frame rate of 30Hz. The third display area DA3 can be a medium-speed driving area that updates the image at a frame rate of 60Hz. However, the embodiments described in this specification are not limited to these.

[0163] As described above, multiple gating drivers 120 can be arranged in the display area of ​​the display device. The gating driver 120 may include shift registers, etc. The level shifter 140 can receive gating timing control signals for controlling the gating driver 120 from the timing controller 130, and send clock signals to the gating driver 120 through the source driver IC 110a on the COF 110b.

[0164] When display areas DA1, DA2, and DA3 are divided and driven at the same or substantially the same frame rate across all areas, driving display areas DA1, DA2, and DA3 does not reflect the amount of data variation in each divided area. It requires applying the same or substantially the same standard to areas with relatively large data variations (e.g., the first display area DA1) across all areas, and in this case, all areas DA1, DA2, and DA3 can be driven at relatively high speeds, leading to increased power consumption.

[0165] This specification provides a display device that adjusts the frame frequency for each divided driving region by additionally arranging level shifters 140 based on the number of divided and driven regions. Therefore, the power consumption of the display device divided and driven in the horizontal direction can be reduced.

[0166] Figure 18 This is a block diagram illustrating a display device according to a first embodiment of this specification.

[0167] Reference Figure 18 The display device may include a display panel 100, a plurality of level shifters 140, and a timing controller 130. The display panel 100 may include a plurality of gating drivers 120 and arranged in a matrix (see [link to relevant documentation]). Figure 2 Multiple pixels (not shown) are configured. In one embodiment, at least some of the multiple gating drivers 120 may be disposed in the display panel 100. The multiple gating drivers 120 may be disposed between the multiple pixels. The display device may also include multiple source driver ICs 110a disposed between the multiple level shifters 140 and the multiple gating drivers 120.

[0168] Level shifter 140 can be connected to timing controller 130 to receive the aforementioned input clock. Level shifter 140 can generate a clock signal from the input clock and transmit the clock signal to source driver IC 110a, and source driver IC 110a can transmit the clock signal to strobe driver 120.

[0169] According to the embodiment, the source driver IC 110a can be mounted on COF 110b and connected to level shifter 140 and gating driver 120.

[0170] The display panel may include multiple display areas. These multiple display areas may include a first display area DA1, a second display area DA2, and a third display area DA3, but the embodiments described herein are not limited to these. The first display area DA1 may be driven at a first frame rate. The second display area DA2 may be driven at a second frame rate. The third display area DA3 may be driven at a third frame rate. In one embodiment, the first frame rate may be greater than both the second and third frame rates, and the third frame rate may be greater than the second frame rate. For example, the first frame rate may be 120Hz, the second frame rate may be 15Hz to 30Hz, and the third frame rate may be 60Hz, but the embodiments described herein are not limited to these.

[0171] The frame rates driving multiple display areas can all be different from each other. For example, the first frame rate, the second frame rate, and the third frame rate can all be different from each other (see [link to documentation]). Figure 27 ).

[0172] The display area can be divided in the horizontal direction. For example, a second display area DA2 can be set from a first display area DA1 along a first direction (e.g., along the X-axis direction), and a third display area DA3 can be set from the second display area DA2 along the first direction.

[0173] Multiple gating drivers 120 may be configured to extend in a second direction (e.g., in the Y-axis direction). Multiple gating drivers 120 may be configured in a horizontal direction. For example, multiple gating drivers 120 may include a first gating driver 121, a second gating driver 122, and a third gating driver 123, with the second gating driver 122 positioned from the first gating driver 121 along a first direction, and the third gating driver 123 positioned from the second gating driver 122 along the first direction.

[0174] The plurality of gating drivers 120 may include a first gating driver 121 disposed in a first display area DA1, a second gating driver 122 disposed in a second display area DA2, and a third gating driver 123 disposed in a third display area DA3.

[0175] Multiple first gating drivers 121, multiple second gating drivers 122, and multiple third gating drivers 123 can be formed. For example, the first gating driver 121 may include a 1-1 gating driver 1211, a 1-2 gating driver 1212, ..., and a 1-n gating driver 121n. The second gating driver 122 may include a 2-1 gating driver 1221, a 2-2 gating driver 1222, ..., and a 2-n gating driver 122n. The third gating driver 123 may include a 3-1 gating driver 1231, a 3-2 gating driver 1232, ..., and a 3-n gating driver 123n.

[0176] The plurality of level shifters 140 may include a first level shifter 141 connected to a first gating driver 121, a second level shifter 142 connected to a second gating driver 122, and a third level shifter 143 connected to a third gating driver 123.

[0177] Multiple first-level shifters 141, multiple second-level shifters 142, and multiple third-level shifters 143 can be formed. For example, the first-level shifter 141 may include a 1-1 level shifter 1411, a 1-2 level shifter 1412, ..., and a 1-n level shifter 141n. The second-level shifter 142 may include a 2-1 level shifter 1421, a 2-2 level shifter 1422, ..., and a 2-n level shifter 142n. The third-level shifter 143 may include a 3-1 level shifter 1431, a 3-2 level shifter 1432, ..., and a 3-n level shifter 143n.

[0178] The plurality of source driver ICs 110a may include a first source driver IC 111a connected to a first level shifter 141 and a first gating driver 121, a second source driver IC 112a connected to a second level shifter 142 and a second gating driver 122, and a third source driver IC 113a connected to a third level shifter 143 and a third gating driver 123.

[0179] Multiple first source driver ICs 111a, multiple second source driver ICs 112a, and multiple third source driver ICs 113a can be formed. For example, the first source driver IC 111a may include 1-1 source driver IC 111a1, 1-2 source driver IC 111a2, ..., and 1-n source driver ICs 111an. The second source driver IC 112a may include 2-1 source driver IC 112a1, 2-2 source driver IC 112a2, ..., and 2-n source driver ICs 112an. The third source driver IC 113a may include 3-1 source driver IC 113a1, 3-2 source driver IC 113a2, ..., and 3-n source driver ICs 113an.

[0180] In one embodiment, 1-1 gating drivers 1211 to 1-n gating drivers 121n can be connected to 1-1 gating drivers 1211 to 1-n gating drivers 121n, respectively. 1-1 source driver ICs 111a1 to 1-n source driver ICs 111an can be connected to 1-1 level shifters 1411 to 1-n level shifters 141n, respectively. 1-1 source driver ICs 111a1 to 1-n source driver ICs 111an can be connected to 1-1 gating drivers 1211 to 1-n gating drivers 121n, respectively.

[0181] This specification provides a display device that adjusts the frame frequency for each divided display region DA1, DA2, and DA3 by forming a plurality of level shifters 140 based on the number of divided and driven regions. For example, a first level shifter 141 can provide a high-speed driving frequency, a second level shifter 142 can provide a low-speed driving frequency, and a third level shifter 143 can provide a medium-speed driving frequency. Therefore, the horizontally divided regions can be driven only at their respective frequencies, and thus, a display device with reduced power consumption and low-power operation can be provided.

[0182] Figure 19 This is a block diagram illustrating a display device according to a second embodiment of this specification. Figure 20 This is a waveform diagram showing an exemplary input / output signal of a level shifter included in a display device according to the second embodiment.

[0183] Figure 21 This is a waveform diagram showing an exemplary output signal of a level shifter included in a display device according to a second embodiment.

[0184] Reference Figure 19The timing controller 130 can provide different input clocks to each of the first level shifter 141, the second level shifter 142, and the third level shifter 143. The timing controller 130 can transmit multiple input clocks used to provide different drive frame frequencies to the multiple level shifters 141, 142, and 143 respectively.

[0185] For example, multiple input clocks may include input clock 1a GCLKa, input clock 2a MCLKa, input clock 1b GCLKb, input clock 2b MCLKb, input clock 1c GCLKc, and input clock 2c MCLKc. Input clock 1a GCLKa and input clock 2a MCLKa can be transmitted to a first level shifter 141. Input clock 1b GCLKb and input clock 2b MCLKb can be transmitted to a third level shifter 143. Input clock 1c GCLKc and input clock 2c MCLKc can be transmitted to a second level shifter 142.

[0186] Reference Figure 19 and Figure 20 The first level shifter 141 can generate a start signal VSTA input to the first gating driver 121 from the 1a input clock GCLKa and the 2a input clock MCLKa. The driver of the first level shifter 141 can generate the start signal by turning on a pull-up transistor or a pull-down transistor in response to the 1a input clock GCLKa and the 2a input clock MCLKa. For example, the driver can turn on the pull-up transistor in response to the falling edge of the 1a input clock GCLKa and the pull-down transistor in response to the rising edge of the 2a input clock MCLKa, but this specification is not limited thereto. When the pull-up transistor or pull-down transistor is turned on or off, the start signal VSTA can be output as the voltage at the output terminal is charged to the gating on voltage or discharged to the gating off voltage.

[0187] The second level shifter 142 can generate a start signal VSTc input to the second gating driver 122 from the 1c input clock GCLKc and the 2c input clock MCLKc. The driver of the second level shifter 142 can generate the start signal by turning on a pull-up transistor or a pull-down transistor in response to the 1c input clock GCLKc and the 2c input clock MCLKc. For example, the driver can turn on the pull-up transistor in response to the falling edge of the 1c input clock GCLKc and the pull-down transistor in response to the rising edge of the 2c input clock MCLKc, but this specification is not limited thereto. When the pull-up transistor or the pull-down transistor is turned on or off, the start signal VSTc can be output as the voltage at the output terminal is charged to the gating on voltage or discharged to the gating off voltage.

[0188] The third level shifter 143 can generate a start signal VSTb input to the third gating driver 123 from the 1b input clock GCLKb and the 2b input clock MCLKb. The driver of the third level shifter 143 can generate the start signal by turning on a pull-up transistor or a pull-down transistor in response to the 1b input clock GCLKb and the 2b input clock MCLKb. For example, the driver can turn on the pull-up transistor in response to the falling edge of the 1b input clock GCLKb and the pull-down transistor in response to the rising edge of the 2b input clock MCLKb, but this specification is not limited thereto. When the pull-up transistor or the pull-down transistor is turned on or off, the start signal VSTb can be output as the voltage at the output terminal is charged to the gating on voltage or discharged to the gating off voltage.

[0189] In one implementation, the pulse widths PWa, PWb, and PWc of the start signals VSTA, VSTb, and VSTc input to each of the gating drivers 121, 122, and 123 can be different from each other. The pulse width PWa of the start signal VSTA input to the first gating driver 121 can be half the pulse width PWb of the start signal VSTb input to the third gating driver 123. The pulse width PWb of the start signal VSTb input to the third gating driver 123 can be half the pulse width PWc of the start signal VSTc input to the second gating driver 122. By adjusting the pulse widths PWa, PWb, and PWc of the start signals, the sampling period can be ensured and the drive frequency can be freely adjusted.

[0190] Reference Figures 19 to 21 The a-th output signal STa may include the start signal VSTA and clock signals CLK1a, CLK2a, CLK3a, and CLK4a input to the first gating driver 121. The b-th output signal STb may include the start signal VSTb and clock signals CLK1b, CLK2b, CLK3b, and CLK4b input to the third gating driver 123. The c-th output signal STc may include the start signal VSTc and clock signals CLK1c, CLK2c, CLK3c, and CLK4c input to the second gating driver 122.

[0191] The display device according to embodiments of this specification can adjust the driving frame frequency of each display area DA1, DA2, and DA3 by arranging a plurality of level shifters 141, 142, and 143. In one embodiment, the period Pa of the a-th output signal STa can be half of the period Pb of the b-th output signal STb. The period Pb of the b-th output signal STb can be half of the period Pc of the c-th output signal STc. The pulse width of the a-th output signal STa can be half of the pulse width of the b-th output signal STb. The pulse width of the b-th output signal STb can be half of the pulse width of the c-th output signal STc. However, the embodiments of this specification are not limited thereto. By adjusting the pulse width of the output signals, the sampling period can be ensured and the driving frequency can be freely adjusted.

[0192] Figure 22 This is a block diagram illustrating a display device according to a third embodiment of this specification. Figure 23 This is a block diagram illustrating the signal transmission path in a display device according to a third embodiment of this specification.

[0193] Reference Figure 22 The a-th output signal STa may include the start signal VSTA and clock signals CLK1a, CLK2a, CLK3a, and CLK4a input to the first gating driver 121. The b-th output signal STb may include the start signal VSTb and clock signals CLK1b, CLK2b, CLK3b, and CLK4b input to the third gating driver 123. The c-th output signal STc may include the start signal VSTc and clock signals CLK1c, CLK2c, CLK3c, and CLK4c input to the second gating driver 122.

[0194] In a display device according to one embodiment, a first level shifter 141 may be connected to a first gating driver 121, a second gating driver 122, and a third gating driver 123. A second level shifter 142 may be connected to the first gating driver 121, the second gating driver 122, and the third gating driver 123. A third level shifter 143 may be connected to the first gating driver 121, the second gating driver 122, and the third gating driver 123.

[0195] For example, a first level shifter 141 can be connected to a first source driver IC 111a, a second source driver IC 112a, and a third source driver IC 113a. A second level shifter 142 can be connected to the first source driver IC 111a, the second source driver IC 112a, and the third source driver IC 113a. A third level shifter 143 can be connected to the first source driver IC 111a, the second source driver IC 112a, and the third source driver IC 113a. The first source driver IC 111a can be connected to a first gating driver 121. The second source driver IC 112a can be connected to a second gating driver 122. The third source driver IC 113a can be connected to a third gating driver 123.

[0196] Multiple source driver ICs 110a can receive multiple output signals from multiple level shifters 140. A COF (Content Component Assembly) housing each of the multiple source driver ICs 110a can include a multiplexer. The multiplexer, receiving multiple signals, can transmit the desired output signal from each of the multiple gating drivers 120.

[0197] Reference Figure 23 The COF, on which the 1-1 source driver IC 111a1 is mounted, may include a 1-1 multiplexer MUX11. The 1-1 source driver IC 111a1 may include a 1-1 multiplexer MUX11.

[0198] The 1-1 multiplexer MUX11 can receive the a-th output signal STa from the first level shifter 141, the b-th output signal STb from the second level shifter 142, and the c-th output signal STc from the third level shifter 143. The 1-1 multiplexer MUX11, receiving each output signal, can transmit an output signal corresponding to the frame frequency required to drive the first display area DA1, which includes a 1-1 gating driver 1211 connected to the 1-1 source driver IC 111a1. For example, the 1-1 multiplexer MUX11 can transmit the a-th output signal STa to the 1-1 gating driver 1211 in response to the multiplexer control signal CTS.

[0199] Figure 24 This is a block diagram illustrating a display device according to a fourth embodiment of this specification. Figure 25 This is a waveform diagram illustrating the exemplary multiplexer control and output signals of this specification.

[0200] Reference Figure 24 and Figure 25Multiple source driver ICs 110a can each include multiple multiplexers. For example, the first source driver IC 111a, the second source driver IC 112a, and the third source driver IC 113a can each include a first multiplexer, a second multiplexer, and a third multiplexer, respectively. 1-1 source driver ICs 111a1, 1-2 source driver ICs 111a2, ..., and 1-n source driver ICs 111an can each include a 1-1 multiplexer MUX11, a 1-2 multiplexer MUX12, ..., and a 1-n multiplexer MUX1n, respectively. 2-1 source driver ICs 112a1, 2-2 source driver ICs 112a2, ..., and 2-n source driver ICs 112an can each include a 2-1 multiplexer MUX21, a 2-2 multiplexer MUX22, ..., and a 2-n multiplexer MUX2n, respectively. The 3-1 source driver IC 113a1, the 3-2 source driver IC 113a2, ..., and the 3-n source driver IC 113an can respectively include the 3-1 multiplexer MUX31, the 3-2 multiplexer MUX32, ..., and the 3-n multiplexer MUX3n.

[0201] Each of the plurality of multiplexer MUXs can receive a first output signal STa from a first level shifter 141, a second output signal STb from a second level shifter 142, and a third output signal STc from a third level shifter 143. As described above, each of the plurality of multiplexer MUXs can transmit an output signal corresponding to the frame frequency required to drive a display area including a gating driver connected to the multiplexer, in response to a multiplexer control signal CTS. For example, a 1-1 multiplexer MUX 11 can transmit the first output signal STa to a 1-1 gating driver 1211 in response to the multiplexer control signal CTS.

[0202] In this specification, multiple level shifters 140 can be formed based on the number of divided and driven regions. Therefore, a display device that adjusts the frame frequency according to each divided and driven display region can be provided. According to this embodiment, a large display device with reduced power consumption and capable of low-power operation can be provided.

[0203] Figure 26 This is a view illustrating an example of a display device according to an embodiment of this specification applied to a vehicle's infotainment system. Figure 27 This is a waveform diagram showing the frame rate used for each display area.

[0204] Reference Figure 26 In an example of an infotainment system applied to a vehicle, additional service images such as side mirror images, cluster or navigation images, weather information, or multimedia images can be simultaneously displayed on the screen of a display device according to an embodiment of this specification.

[0205] Side-view mirror images can be reproduced at high frame rates to ensure driving stability. Clustered or navigation images can have relatively long update cycles. Therefore, clustered or navigation images can be reproduced at low speeds, and power consumption can be reduced through low-speed driving methods. The update cycle of multimedia images can be shorter than that of clustered or navigation images, but longer than that of side-view mirror images. Therefore, multimedia images can be reproduced at an intermediate speed between high and low speeds.

[0206] According to this embodiment, the display area of ​​the display device can be divided and driven into a first display area DA1 that displays a first image (side mirror image), a second display area DA2 that displays a second image (clustering or navigation image), and a third display area DA3 that displays a third image (weather information or multimedia image).

[0207] In one example, the first display area DA1 could be a high-speed driven area where the image is updated at a frame rate of 120Hz. The second display area DA2 could be a low-speed driven area where the image is updated at a frame rate of 15Hz to 30Hz. The third display area DA3 could be a medium-speed driven area where the image is updated at a frame rate of 60Hz.

[0208] Reference Figure 27 FR1 to FR120 can be frame numbers. FR1 to FR120 can represent frames 1 to 120 of a first display area DA1 driven at a frame rate of 120Hz. FR1 to FR60 can represent frames 1 to 60 of a third display area DA3 driven at a frame rate of 60Hz. FR1 to FR30 can represent frames 1 to 30 of a second display area DA2 driven at a frame rate of 30Hz. Multiple application images or multiple content images can be simultaneously divided and displayed on the screen.

[0209] According to this specification, a display device can be provided that adjusts the frame rate according to each divided driving region.

[0210] According to this specification, the power consumption of a display device that is divided and driven in the horizontal direction can be reduced.

[0211] The embodiments disclosed herein are not intended to limit the technical ideas of this specification, but rather to describe them, and the scope of the technical ideas of this specification is not limited by these embodiments.

[0212] Therefore, the embodiments disclosed in this specification are not intended to limit the technical ideas of this specification, but to illustrate them, and the scope of the technical ideas of this specification is not limited by these embodiments.

[0213] Therefore, the above embodiments should be understood as exemplary rather than limiting in all respects.

[0214] The scope of this disclosure should be interpreted by the claims, and should be construed as including all technical ideas within the equivalent scope within the scope of this disclosure.

[0215] Cross-reference to related applications

[0216] This application claims priority and benefit to Korean Patent Application No. 10-2024-0125339, filed in Korea on September 13, 2024, the entire contents of which are expressly incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel includes a plurality of gating drivers and a plurality of pixels arranged in a matrix. Multiple level shifters, the multiple level shifters being connected to the multiple gating drivers; as well as A timing controller, which is connected to the plurality of level shifters, The plurality of gating drivers are disposed between the plurality of pixels.

2. The display device according to claim 1, wherein, The display panel includes a display area, which includes a first display area and a second display area. The plurality of gating drivers includes a first gating driver disposed in the first display area and a second gating driver disposed in the second display area.

3. The display device according to claim 2, wherein, The pulse width of the start signal input to the first gating driver is different from the pulse width of the start signal input to the second gating driver.

4. The display device according to claim 2, wherein, The first frame frequency driving the first display area is different from the second frame frequency driving the second display area.

5. The display device according to claim 2, wherein, The plurality of level shifters includes a first level shifter connected to the first gating driver and a second level shifter connected to the second gating driver.

6. The display device according to claim 5, wherein, The first level shifter is connected to the second gating driver, and The second level shifter is connected to the first gating driver.

7. The display device according to claim 5, further comprising a plurality of source driver integrated circuits (ICs), the plurality of source driver ICs being disposed between the plurality of level shifters and the plurality of gating drivers. in, The plurality of source driver ICs are respectively connected to the plurality of level shifters and the plurality of gating drivers.

8. The display device according to claim 7, wherein, The plurality of source driver ICs includes a first source driver IC disposed between the first level shifter and the first gating driver, and a second source driver IC disposed between the second level shifter and the second gating driver.

9. The display device according to claim 8, wherein, The first source driver IC is connected to the first level shifter and the first gating driver, and The second source driver IC is connected to the second level shifter and the second gating driver.

10. The display device according to claim 9, wherein, The first source driver IC is connected to the second level shifter, and The second source driver IC is connected to the first level shifter.

11. The display device according to claim 9, further comprising: A first multiplexer is connected to the first level shifter, the second level shifter, and the first source driver IC; as well as The second multiplexer is connected to the second level shifter, the first level shifter, and the second source driver IC.

12. The display device according to claim 2, wherein, The display area also includes a third display area, and The plurality of gating drivers also includes a third gating driver disposed in the third display area.

13. The display device according to claim 12, wherein, The first frame frequency driving the first display area, the second frame frequency driving the second display area, and the third frame frequency driving the third display area are all different from each other.

14. The display device according to claim 12, wherein, The plurality of level shifters includes a first level shifter connected to the first gating driver, a second level shifter connected to the second gating driver, and a third level shifter connected to the third gating driver.

15. The display device according to claim 14, wherein, The first level shifter is connected to the second gating driver and the third gating driver. The second level shifter is connected to the first gating driver and the third gating driver, and The third level shifter is connected to the first gating driver and the second gating driver.

16. The display device according to claim 14, further comprising a plurality of source driver ICs disposed between the plurality of level shifters and the plurality of gating drivers. in, The plurality of source driver ICs are respectively connected to the plurality of level shifters and the plurality of gating drivers.

17. The display device according to claim 16, wherein, The plurality of source driver ICs include a first source driver IC disposed between the first level shifter and the first gating driver, a second source driver IC disposed between the second level shifter and the second gating driver, and a third source driver IC disposed between the third level shifter and the third gating driver.

18. The display device according to claim 17, wherein, The first source driver IC is connected to the first level shifter and the first gating driver. The second source driver IC is connected to the second level shifter and the second gating driver, and The third source driver IC is connected to the third level shifter and the third gating driver.

19. The display device according to claim 18, wherein, The first source driver IC is connected to the second level shifter and the third level shifter. The second source driver IC is connected to the first level shifter and the third level shifter, and The third source driver IC is connected to the first level shifter and the second level shifter.

20. The display device according to claim 18, further comprising: A first multiplexer is connected to the first level shifter, the second level shifter, the third level shifter, and the first source driver IC. A second multiplexer is connected to the second level shifter, the first level shifter, the third level shifter, and the second source driver IC; as well as A third multiplexer is connected to the third level shifter, the first level shifter, the second level shifter, and the third source driver IC.

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