Bidirectional electrostatic protection circuit with high area utilization rate

Abstract

The invention discloses a bidirectional electrostatic protection circuit with a high area utilization rate, and relates to the technical field of electrostatic protection. The circuit comprises a first port connected to an external signal, a power port, a ground port, and an electrostatic protection network connected in parallel among the ports. The network comprises a first electrostatic protection element string arranged in the direction from the power port to the first port, a second electrostatic protection element string arranged in the direction from the first port to the ground port, and two reverse electrostatic protection elements. Wherein the first electrostatic protection element string and the second electrostatic protection element string are respectively composed of two electrostatic protection elements which are connected in series; and one ends of the two reverse electrostatic protection elements are respectively connected to a ground port and a power port, and the other ends of the two reverse electrostatic protection elements are respectively connected to a common node between the two protection element strings in a crossed manner. Discharge path multiplexing is realized through topological optimization, the number of core protection devices is reduced to 6, and interstage metal interconnection is eliminated by combining a compact layout design of a shared active region. According to the scheme, on the premise that the full-mode protection capability is guaranteed, the layout area of a chip and the parasitic capacitance of an I / O port are remarkably reduced, and the electrostatic protection circuit is particularly suitable for electrostatic protection of a low-voltage high-speed circuit under the advanced technology.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection technology, and more specifically to a bidirectional ESD protection circuit with high area utilization. Background Technology

[0002] During the use of electronic devices, static electricity can easily accumulate on the surface of the human body, clothing, or the device itself due to friction, contact separation, and other reasons. When static electricity accumulates to a certain level, electrostatic discharge (ESD) occurs, releasing a high-energy current pulse instantaneously. This ESD can severely damage the integrated circuits (ICs) inside electronic devices, especially the delicate and sensitive semiconductor components, easily leading to irreversible damage such as gate breakdown and thermal failure, thereby causing a decline in device performance or even complete malfunction.

[0003] With the continuous improvement of semiconductor integrated circuit manufacturing processes, the integration density and operating speed of chips have significantly increased, the physical size of internal devices has been greatly reduced, and the gate oxide layer has become extremely thin. In order to reduce power consumption and match device characteristics, the operating voltage of the core circuit has been reduced to about 1V. This low-voltage, thin-gate oxide process characteristic makes the tolerance window of advanced process chips to electrostatic discharge (ESD) extremely narrow, and the difficulty of ESD protection design increases exponentially.

[0004] In the field of electrostatic discharge (ESD) protection for integrated circuits, diode string topologies have become the mainstream choice due to their low parasitic capacitance, high linearity, and compact layout, especially suitable for protecting high-speed input / output (I / O) interfaces. For low-voltage I / O ports operating at around 1V, to prevent normal operating signals from being falsely clamped, an ESD protection circuit with a precise turn-on threshold is required. This means that during normal chip operation, the superposition effect of the forward voltage drop generated by two or more diodes connected in series (e.g., the turn-on voltage of two silicon diodes connected in series is approximately 1.4V) is used to make it higher than the normal signal swing (approximately 1.2V), thus ensuring that signal transmission is not interfered with. Simultaneously, when static electricity occurs, the forward conduction characteristics of the diode string provide a low-impedance discharge path.

[0005] To meet stringent reliability standards in industry, electrostatic discharge (ESD) protection circuits typically need to have "full-mode" protection capabilities, meaning they must simultaneously cover four discharge paths: I / O to power (VDD), I / O to ground (VSS), power to I / O, and both forward and reverse discharge paths between I / O and ground. For example... Figure 1The diagram shown is the equivalent circuit diagram of a typical bidirectional electrostatic discharge (ESD) protection scheme implemented using diode strings in the prior art. In this classic architecture, to achieve the aforementioned full-mode bidirectional protection in low-voltage scenarios, forward and reverse diode strings need to be placed between the I / O port and the power rail, and between the I / O port and the ground rail, respectively. Each diode string consists of 2 diodes, so the entire protection circuit requires a total of 4 diode strings, for a total of 8 diodes.

[0006] While this traditional stacked design functionally meets protection requirements, it suffers from the following major technical drawbacks: First, it incurs significant layout area overhead. The eight diode devices occupy a large portion of the chip's layout area, significantly increasing manufacturing costs in the space-constrained world of advanced processes. Second, it exhibits significant parasitic capacitance effects. The numerous diode devices and their complex metal interconnects introduce substantial superimposed parasitic capacitance at the I / O ports. In applications highly sensitive to signal integrity, such as high-speed interfaces and RF front-ends, excessive parasitic capacitance can impair the normal operation of internal circuits, severely limiting operating bandwidth and data transmission rates.

[0007] Therefore, the industry urgently needs an electrostatic discharge (ESD) protection circuit solution that can achieve high area utilization and low parasitic capacitance by optimizing topology and layout while ensuring effective protection, in order to solve the shortcomings of the existing technologies. Summary of the Invention

[0008] To address the problems of excessively large layout area and high cost in existing technologies, this invention provides an electrostatic discharge protection circuit with high area utilization.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: The electrostatic discharge (ESD) protection circuit of the present invention with high area utilization includes: a first port (I / O) connected to an external signal, a power port (VDD) connected to a power supply voltage, and a ground port (VSS) connected to ground; an ESD protection element network connected between the first port, the power port, and the ground port; the ESD protection element network includes a plurality of bidirectional ESD discharge units connected in parallel between the first port, the power port, and the ground port; each bidirectional ESD discharge unit includes a first string of ESD protection elements arranged along the direction from the power port to the first port, a second string of ESD protection elements arranged along the direction from the first port to the ground port, and two ESD protection elements in opposite directions; wherein the number of ESD protection elements in the first string of ESD protection elements is two, one end of the first ESD protection element is connected to the power port, one end of the second ESD protection element is connected to the second port, and one end of the one in opposite direction ESD protection element is connected to the ground port, and the other end is connected to the common node between the first and second ESD protection elements in the first string of ESD protection elements. The second electrostatic discharge (ESD) protection element string contains two ESD protection elements. One end of the first ESD protection element is connected to the first port, and one end of the second ESD protection element is connected to the ground port. The other ESD protection element, in the opposite direction, has one end connected to the common node between the first and second ESD protection elements in the second ESD protection element string, and the other end connected to the power port.

[0010] Furthermore, the electrostatic discharge protection element includes a diode, a metal-oxide-semiconductor field-effect transistor, a bipolar junction transistor, or a Zener diode.

[0011] Furthermore, the bidirectional electrostatic protection circuit is disposed on a substrate, and the layout shape of the substrate includes a strip layout, a ring layout, or a waffle layout.

[0012] Furthermore, the number of bidirectional electrostatic discharge units is m, where m is an integer greater than 1.

[0013] Compared with the prior art, the beneficial effects of the present invention are: by optimizing the topology connection method and layout, the present invention enables bidirectional electrostatic discharge paths to share a portion of the electrostatic protection components, thereby reducing the number of electrostatic protection components used, significantly saving chip layout area, reducing parasitic capacitance, and ensuring high electrostatic discharge capability. This is conducive to significantly reducing the product layout area and package size, and reducing manufacturing costs. Attached Figure Description

[0014] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 The circuit equivalent diagram is shown for a bidirectional electrostatic discharge (ESD) protection scheme implemented using a single set of bidirectional diode strings in the prior art.

[0016] Figure 2 This is a circuit diagram of the bidirectional electrostatic protection circuit according to the first embodiment of the present invention;

[0017] Figure 3(a) is a schematic cross-sectional view of the device structure of the bidirectional electrostatic protection circuit according to the first embodiment of the present invention;

[0018] Figure 3(b) is a schematic cross-sectional view of the device structure of the bidirectional electrostatic protection circuit according to the first embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the layout structure of the bidirectional electrostatic protection circuit according to the first embodiment of the present invention;

[0020] Figure 5 This is a comparison chart of parasitic capacitance simulation data between the layout structure of the first embodiment of the present invention and the traditional layout structure. Detailed Implementation

[0021] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0022] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment to other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0024] like Figure 2 As shown, the electrostatic discharge (ESD) protection circuit of the present invention with high area utilization includes: a first port (I / O) connected to an external signal, a power port (VDD) connected to the power supply voltage, and a ground port (VSS) connected to ground; an ESD protection element network connected between the first port, the power port, and the ground port; the ESD protection element network includes a plurality of bidirectional ESD discharge units connected in parallel between the first port, the power port, and the ground port; the bidirectional ESD discharge unit includes a first ESD protection element string arranged along the direction from the power port to the first port, a second ESD protection element string arranged along the direction from the first port to the ground port, and two ESD protection elements in opposite directions; wherein the number of ESD protection elements in the first ESD protection element string is two, one end of the first ESD protection element is connected to the power port, one end of the second ESD protection element is connected to the second port, and one end of the opposite ESD protection element is connected to the ground port, and the other end is connected to the common node between the first ESD protection element and the second ESD protection element in the first ESD protection element string. The second electrostatic discharge (ESD) protection element string contains two ESD protection elements. One end of the first ESD protection element is connected to the first port, and one end of the second ESD protection element is connected to the ground port. The other ESD protection element, in the opposite direction, has one end connected to the common node between the first and second ESD protection elements in the second ESD protection element string, and the other end connected to the power port.

[0025] The electrostatic discharge protection element in this example is not only applicable to diodes, but the topology of this invention is also applicable to protection structures composed of other semiconductor elements, such as the series structure of a metal-oxide-semiconductor field-effect transistor (MOSFET), the series structure of a bipolar junction transistor (BJT), the series structure of a Zener diode, and so on.

[0026] The following explanation uses a diode as the electrostatic discharge (ESD) protection element, with the first port as an I / O port, and is further illustrated by a power port and a ground port. The optimization strategy of this patent is as follows: For bidirectional ESD protection, by optimizing the topology and layout, the ESD discharge paths from the first port to the power port and from the first port to the ground port can share a portion of the diode, thereby reducing the number of diodes used and significantly saving chip layout area.

[0027] like Figure 2 As shown, this is the first embodiment of the present invention, which is the basic unit structure of the minimum number of diodes, including six diodes. The specific connection relationship is as follows: The first electrostatic discharge (ESD) protection element string includes a first diode and a second diode connected in series. The anode of the first diode is connected to a power supply port, the cathode of the first diode is connected to the anode of the second diode, and the cathode of the second diode is connected to the first port. The second ESD protection element string includes a third diode and a fourth diode connected in series. The anode of the third diode is connected to the first port, the cathode of the third diode is connected to the anode of the fourth diode, and the cathode of the fourth diode is connected to a ground port. The two ESD protection elements in opposite directions are a fifth diode and a sixth diode. The anode of the fifth diode is connected to a ground port, the cathode of the fifth diode is connected to a common node between the cathodes of the first diode and the anodes of the second diode, the anode of the sixth diode is connected to a common node between the cathodes of the third diode and the anodes of the fourth diode, and the cathode of the sixth diode is connected to a power supply port.

[0028] Through the above topology, this embodiment achieves low-impedance discharge paths under four electrostatic stress modes:

[0029] When a positive electrostatic pulse (PS mode) occurs at the first port to the ground port, the electrostatic current is discharged to ground through the third diode and the fourth diode in sequence;

[0030] When a negative electrostatic pulse (NS mode) occurs at the first port to the ground port, the electrostatic current is discharged to the first port through the fifth diode and the second diode in sequence;

[0031] When a negative electrostatic pulse (ND mode) is generated between the first port and the power port, the electrostatic current is discharged to the first port through the first diode and the second diode in sequence.

[0032] When a positive electrostatic pulse (PD mode) is generated between the first port and the power port, the electrostatic current is discharged to the power port through the third diode and the sixth diode in sequence.

[0033] compared to Figure 1 In the classic scheme, the unit structure for realizing the full-mode electrostatic discharge protection circuit between the power port, ground port and the first port consists of 8 diodes. That is, each of the four discharge paths from the first port to the power port, from the first port to the ground port, from the ground port to the first port and from the power port to the first port consists of 2 diodes connected in series. In this embodiment, the present invention uses only 6 diodes to achieve the same full-mode electrostatic discharge function.

[0034] Referring next to Figure 3(a), a cross-sectional schematic diagram of the device structure of the first diode, second diode, and fifth diode in the first embodiment of the present invention is shown. This part of the circuit is formed on a P-type substrate (Psub). As shown, the P-type substrate is connected to the ground port (VSS) through a heavily doped P+ region and a P-type guard ring (PGR), thereby fixing the substrate potential to ground potential. Each diode is composed of an independent N-well formed on the P-type substrate and its internal heavily doped region. Specifically, the P+ region in the N-well is used as the anode, and the N+ region is used as the cathode. The anodes and cathodes are connected by metal interconnects. Figure 2 The aforementioned logical cascading forms a discharge path.

[0035] Referring further to Figure 3(b), a cross-sectional view of the device structure of the third, fourth, and sixth diodes in the first embodiment of the present invention is shown. Unlike Figure 3(a), to prevent leakage current through the substrate from the nodes in the second electrostatic discharge (ESD) element string, this part of the circuit uses a deep N-well (DNwell) for isolation. As shown, the deep N-well is located deep within the P-type substrate, thereby constructing an isolated P-well region on the P-type substrate. Each diode is formed within the isolated P-well, utilizing the heavily doped N+ region within the well to form a PN junction with P+. The anodes and cathodes are connected by metal interconnects. Figure 2 The aforementioned logical cascading forms a discharge path.

[0036] Based on this cross-sectional diagram, as follows Figure 4 The layout planar structure shown further illustrates the compact layout strategy with shared active area adopted in this embodiment. The layout planar structure of this embodiment shows the planar arrangement of the six diode modules constituting the circuit. The layout includes three vertical metal main buses, from left to right: power bus (VDD), ground bus (VSS), and first port bus (I / O). The first and sixth diodes are arranged near the power bus to facilitate low-impedance connection of their anodes or cathodes to VDD via metal interconnects. The fourth and fifth diodes are arranged near the ground bus to facilitate their connection to VSS. The second and third diodes are arranged near the first port bus to facilitate their connection to I / O. The diode modules are interconnected by horizontal metal interconnects. Figure 2 The topology shown is connected logically to form a complete protection network.

[0037] To verify the effectiveness and universality of the above layout optimization strategy, eight sets of test samples covering different driving capabilities and array sizes were selected for simulation verification. For example... Figure 5The statistical data shows that, under the condition of ensuring the same ESD driving capability, regardless of the device size, the compact layout structure with shared active region described in this invention can significantly reduce input parasitic capacitance. Compared with the traditional layout, the capacitance reduction of the eight samples is stably distributed between 31.3% and 33.3%. This highly consistent optimization ratio confirms that this technical solution is excellently suited for circuit applications such as high-speed interfaces and RF front-ends that are extremely sensitive to insertion loss and parasitic capacitance.

[0038] Of course, the layout of this invention is not only applicable to strip layouts, but also to common layout shapes such as ring layouts and waffle layouts, and has the same significant optimization effect.

[0039] As can be seen from the above embodiments, this invention achieves discharge path reuse by introducing a feedback path in the circuit topology and adopts a compact layout strategy with a shared active area in the physical layout. This not only reduces the number of ESD protection components used, significantly saving chip layout area and reducing manufacturing costs, but also greatly reduces the parasitic capacitance of the circuit. Therefore, this invention achieves high area utilization while also taking into account excellent high-frequency signal transmission performance. It is particularly suitable for the stringent protection requirements of the low-voltage domain of around 1V under advanced processes, and is especially applicable to consumer electronics, wearable devices, and high-speed communication interfaces where layout size is sensitive and signal integrity requirements are extremely high. It provides an economical and high-performance overall ESD protection solution for integrated circuits under low-voltage advanced processes.

[0040] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A bidirectional electrostatic discharge protection circuit, characterized in that, include: The system includes a first port (I / O) connected to an external signal, a power port (VDD) connected to the power supply voltage, and a ground port (VSS) connected to ground. An electrostatic discharge (ESD) protection network is connected between the first port, the power port, and the ground port. This ESD protection network includes several bidirectional ESD discharge units connected in parallel between the first port, the power port, and the ground port. Each bidirectional ESD discharge unit includes a first string of ESD protection elements arranged along the direction from the power port to the first port, a second string of ESD protection elements arranged along the direction from the first port to the ground port, and two ESD protection elements in opposite directions. The first ESD protection element string contains two ESD protection elements. One end of the first ESD protection element is connected to the power port, and one end of the second ESD protection element is connected to the first port. One of the reverse-direction ESD protection elements is connected to the ground port, and its other end is connected to the common node between the first and second ESD protection elements in the first ESD protection element string. The second ESD protection element string also contains two ESD protection elements. One end of the first ESD protection element is connected to the first port, and one end of the second ESD protection element is connected to the ground port. Another reverse-direction ESD protection element is connected to the common node between the first and second ESD protection elements in the second ESD protection element string, and its other end is connected to the power port.

2. The bidirectional electrostatic protection circuit according to claim 1, characterized in that: The electrostatic discharge protection element includes a diode, a metal-oxide-semiconductor field-effect transistor, or a bipolar junction transistor.

3. The bidirectional electrostatic protection circuit according to claim 1, characterized in that: The bidirectional electrostatic protection circuit is disposed on the substrate, and the layout shape of the substrate includes a strip layout, a ring layout, or a waffle layout.

4. The bidirectional electrostatic protection circuit according to claim 1, characterized in that: The number of bidirectional electrostatic discharge units is m, where m is an integer greater than 1.

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