A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a semiconductor layer, a recess extending from the surface of the semiconductor layer to the inside of the semiconductor layer; an epitaxial layer located on the surface of the semiconductor layer, the recess being arranged around the epitaxial layer; a gate dielectric layer surrounding the lower part of the epitaxial layer; a gate conductor surrounding the gate dielectric layer on the side of the gate dielectric layer away from the epitaxial layer; a source region located on the upper part of the epitaxial layer; and a drain region located in the semiconductor layer exposed at the bottom of the recess; wherein the gate dielectric layer and the gate conductor are located above the recess, and the bottom of the gate dielectric layer and the bottom of the gate conductor have a gap between the inner wall of the recess.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Unlike FinFETs, which only surround the channel on three sides, GAAFETs (Gate-All-Around-Field-Effect Transistors) have a 360° gate-all-around channel, which greatly enhances electrostatic control capabilities. The subthreshold swing can be as low as 60mV / decade (close to the theoretical limit), significantly suppressing short-channel effects and reducing leakage current. As a core device for advanced process nodes of 3nm and below, GAAFETs solve the bottleneck problems of short-channel effects in FinFETs as size continues to shrink, and are a key technology for continuing Moore's Law.

[0003] However, due to the short length of the all-around gate channel, the device's breakdown voltage performance is challenged. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a semiconductor device and a method for fabricating the same, wherein the semiconductor device forms a gate conductor that is suspended and surrounded, thereby enhancing the control capability of the semiconductor device without increasing the length of the gate conductor.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor layer having a groove extending from its surface to its interior; an epitaxial layer located on the surface of the semiconductor layer, the groove being disposed around the epitaxial layer; a gate dielectric layer surrounding a lower portion of the epitaxial layer; a gate conductor surrounding the gate dielectric layer on a side of the gate dielectric layer away from the epitaxial layer; a source region located on an upper portion of the epitaxial layer; and a drain region located in the semiconductor layer exposed at the bottom of the groove; wherein the gate dielectric layer and the gate conductor are located above the groove, and a gap is formed between the bottom of the gate dielectric layer and the bottom of the gate conductor and the inner wall of the groove.

[0006] Optionally, the gate conductor includes a first portion located above the groove and a second portion extending into the groove, the width of the second portion gradually decreasing from the top of the groove to the bottom of the groove.

[0007] Optionally, the top opening size of the groove is larger than its bottom opening size, and the sidewall of the groove is inclined; the sidewall of the second portion near the gate dielectric layer is inclined, and the inclination of the sidewall of the second portion is the same as the inclination of the corresponding sidewall of the groove.

[0008] According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: forming a groove extending from the surface of the semiconductor layer into its interior in a semiconductor layer; forming an epitaxial layer on the surface of the semiconductor layer, the groove surrounding the epitaxial layer; forming a gate dielectric layer and a gate conductor, the gate dielectric layer surrounding a lower portion of the epitaxial layer, the gate conductor surrounding the gate dielectric layer on a side of the gate dielectric layer away from the epitaxial layer; forming a drain region in the semiconductor layer exposed at the bottom of the groove, and forming a source region on the upper portion of the epitaxial layer; wherein the gate dielectric layer and the gate conductor are located above the groove, and there is a gap between the bottom of the gate dielectric layer and the bottom of the gate conductor and the inner wall of the groove.

[0009] Optionally, the method of forming a groove in the semiconductor layer includes: forming a pre-groove in the semiconductor layer, wherein the upper part of the pre-groove has a trapezoidal cross-sectional shape and the lower part of the pre-groove has an inverted trapezoidal cross-sectional shape; forming a first filler layer in the pre-groove; removing the first filler layer in the upper part of the pre-groove; removing a portion of the semiconductor layer, while removing the upper part of the pre-groove; and removing the first filler layer in the lower part of the pre-groove, thereby retaining the lower part of the pre-groove to form a groove.

[0010] Optionally, the method of forming an epitaxial layer on the surface of the semiconductor layer includes: forming a second filling layer that fills the groove and covers the surface of the semiconductor layer; removing the second filling layer covering the surface of the semiconductor layer to form a via exposed to the surface of the semiconductor layer; forming an epitaxial layer on the surface of the semiconductor layer exposed by the via; and removing the second filling layer in the groove.

[0011] Optionally, the method of forming a gate dielectric layer and a gate conductor includes: forming a first barrier layer conformally covering the bottom and sidewalls of the groove, wherein after forming the first barrier layer, the remaining space of the groove forms an intermediate state groove, the top opening size of the groove is larger than its bottom opening size, and the sidewalls of the groove are inclined, the intermediate state groove having inclined sidewalls corresponding to the groove; forming a dielectric layer surrounding the sidewalls of the epitaxial layer, and forming a conductor layer surrounding the dielectric layer, wherein the conductor layer covers the bottom and sidewalls of the intermediate state groove, and the portion of the conductor layer covering the sidewalls of the intermediate state groove has inclined sidewalls corresponding to the sidewalls of the intermediate state groove; removing a portion of the conductor layer, at least retaining the conductor layer covering the sidewalls of the intermediate state groove and adjacent to the dielectric layer; removing the first barrier layer, forming a gap between the bottom of the gate dielectric layer and the bottom of the gate conductor and the inner wall of the groove; removing at least a portion of the top of the dielectric layer and the conductor layer, such that the upper part of the epitaxial layer is exposed, the remaining dielectric layer forming the gate dielectric layer, and the remaining conductor layer forming the gate conductor.

[0012] Optionally, the gate conductor includes a first portion located above the groove and a second portion extending into the groove, the width of the second portion gradually decreasing from the top of the groove to the bottom of the groove.

[0013] Optionally, the method of forming a first barrier layer covering the bottom and sidewalls of the groove includes: forming a first barrier layer that conformally covers the bottom and sidewalls of the groove, as well as the top and sidewalls of the epitaxial layer; forming a second barrier layer that conformally covers the surface of the first barrier layer, and by setting the thickness of the second barrier layer, such that the second barrier layer fills the space between adjacent epitaxial layers; removing the second barrier layer and the first barrier layer at the top of the epitaxial layer; removing the first barrier layer at the sidewalls of the epitaxial layer, while retaining the first barrier layer covering the bottom and sidewalls of the groove; and removing the remaining second barrier layer.

[0014] Optionally, the method includes: forming a dielectric layer surrounding the sidewalls of the epitaxial layer, and forming a conductor layer surrounding the dielectric layer, comprising: forming a dielectric layer covering the top and sidewalls of the epitaxial layer; forming a conformal conductor layer covering the surface of the dielectric layer, wherein the thickness of the conductor layer is controlled such that the conductor layer fills the space between adjacent epitaxial layers; and removing the conductor layer and dielectric layer from the top of the epitaxial layer.

[0015] The unexpected technical effect of this application is:

[0016] The semiconductor device provided in this embodiment forms a suspended, surrounding gate conductor, which enhances the control capability of the semiconductor device without increasing the length of the gate conductor.

[0017] The channel length of the semiconductor device provided in this embodiment is the vertical length of the lower part of the epitaxial layer. Furthermore, the semiconductor device provided in this embodiment forms a gate conductor that is wider at the top and narrower at the bottom, resulting in an asymmetry between the source and drain regions relative to the gate conductor, forming a LDMOS-like structure. The drain region is farther from the channel and is separated by a drift region with a lower concentration than the well, which acts as a breakdown voltage layer between the drain and the well, thereby improving the device breakdown voltage.

[0018] This application forms a Sigma groove, and by removing the upper part of the Sigma groove, a groove of the desired shape (a cross-sectional shape of an inverted trapezoid) is finally obtained.

[0019] In a preferred embodiment, during the removal of the upper part of the Sigma groove, a first filler layer with higher hardness is filled in the lower part of the Sigma groove to ensure that the lower part of the Sigma groove is not affected by the grinding process.

[0020] This application forms a second filling layer at the bottom and sidewalls of the trench to form a protective layer at the bottom and sidewalls of the trench, thereby epitaxially growing an epitaxial layer on the surface of a specific semiconductor layer.

[0021] This application first forms a first barrier layer that conformally covers the bottom and sidewalls of the groove, as well as the top and sidewalls of the epitaxial layer. Then, it selectively removes the first barrier layer on the top and sidewalls of the epitaxial layer, and finally retains the first barrier layer that conformally covers the bottom and sidewalls of the groove.

[0022] In this application, the first barrier layer conformally covering the bottom and sidewalls of the groove serves as a shaping layer for forming the gate conductor, thus forming a sacrificial layer for creating the gap between the gate conductor and the interior of the groove. Specifically, this application first forms a groove with inclined sidewalls, then forms a first barrier layer conformally covering the sidewalls of the groove to ensure that the conductor layer covering the first barrier layer has corresponding inclined sidewalls. Finally, the first barrier layer is removed, resulting in a gap between the bottom of the final gate conductor and the inner wall of the groove, while simultaneously forming a gate conductor that is wider at the top and narrower at the bottom. Attached Figure Description

[0023] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 A schematic cross-sectional view of a semiconductor device according to an embodiment of this application is shown;

[0025] Figures 2a to 2s The illustration shows schematic cross-sectional views of various stages in the fabrication process of the semiconductor device provided in the embodiments of this application, wherein:

[0026] Figure 2a A schematic cross-sectional view of a semiconductor layer according to an embodiment of this application is shown;

[0027] Figure 2b A schematic cross-sectional view of a pre-groove formed in a semiconductor layer according to an embodiment of this application is shown;

[0028] Figure 2c A schematic cross-sectional view of an embodiment of this application showing the formation of a first filling layer in a pre-groove is shown;

[0029] Figure 2d A schematic cross-sectional view of the present application embodiment showing the removal of the first filler layer in the upper part of the pre-groove;

[0030] Figure 2e A schematic cross-sectional view of the semiconductor layer removed in an embodiment of this application is shown;

[0031] Figure 2f A schematic cross-sectional view of the formation of the second filling layer according to an embodiment of this application is shown;

[0032] Figure 2g A schematic cross-sectional view of the planarization of the second filler layer according to an embodiment of this application is shown;

[0033] Figure 2h A schematic cross-sectional view is shown of an embodiment of this application, in which a second filler layer covering the surface of a semiconductor layer is removed to form a plurality of vias in the second filler layer;

[0034] Figure 2i A schematic cross-sectional view of an embodiment of this application showing the formation of an epitaxial layer in a via of a second filling layer is shown.

[0035] Figure 2j A schematic cross-sectional view of removing the second filler layer in the groove according to an embodiment of this application is shown;

[0036] Figure 2k A schematic cross-sectional view showing the sequential formation of a first barrier layer and a second barrier layer according to an embodiment of this application is shown;

[0037] Figure 2l A schematic cross-sectional view of the second barrier layer and the first barrier layer removed from the top of the epitaxial layer is shown in an embodiment of this application.

[0038] Figure 2m A schematic cross-sectional view of an embodiment of this application showing the removal of the first barrier layer from the sidewall of the epitaxial layer;

[0039] Figure 2n A schematic cross-sectional view of an embodiment of this application showing the removal of the second barrier layer is shown;

[0040] Figure 2o This illustration shows a schematic cross-sectional view of an embodiment of the present application in which a dielectric layer is formed on the top and sidewalls of the epitaxial layer;

[0041] Figure 2p A schematic cross-sectional view of the conductor layer formed according to an embodiment of this application is shown;

[0042] Figure 2q A schematic cross-sectional view showing the conductor layer and dielectric layer removed from the top of the epitaxial layer is shown;

[0043] Figure 2r A schematic cross-sectional view showing the conductor layer with a portion removed is shown;

[0044] Figure 2s A schematic cross-sectional view showing the formation of a gate dielectric layer, a gate conductor, a source region, and a drain region according to an embodiment of this application is shown;

[0045] Explanation of reference numerals in the attached figures: 101-Semiconductor layer; 101a-Groove; 101aa-Pre-groove; 101b-Intermediate state groove; 1021-First fill layer; 1022-Second fill layer; 1022a-Through hole; 103-Epipolar layer; 1041-First barrier layer; 1042-Second barrier layer; 105-Gate dielectric layer; 105a-Dielectric layer; 106-Gate conductor; 1061-First portion; 1062-Second portion; 106a-Conductor layer; 107-Source region; 108-Drain region; PR1-First resist mask layer; PR2-Second resist mask layer. Detailed Implementation

[0046] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0047] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0048] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on top of and adjacent to".

[0049] Unless otherwise specified below, the various parts of a semiconductor device may be made of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), group IV-IV semiconductors such as silicon carbide (SiC), group II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and group IV semiconductors such as silicon (Si) and germanium (Ge). The gate conductor may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, and PtSi. xThe gate dielectric can be composed of Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric can be made of SiO2 or materials with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0050] This application may be presented in various forms, some of which will be described below.

[0051] Figure 1 A schematic cross-sectional view of a semiconductor device according to an embodiment of this application is shown; as follows: Figure 1 As shown, the semiconductor device includes a semiconductor layer 101 and an epitaxial layer 103. The semiconductor layer 101 has a groove 101a extending from its surface into its interior, wherein the top opening size of the groove 101a is larger than its bottom opening size, and the sidewalls of the groove 101a are inclined. The epitaxial layer 103 is located on the surface of the semiconductor layer 101.

[0052] Semiconductor layer 101 can be selected from any combination of a semiconductor substrate, a doped epitaxial layer (EPI), or a combination thereof. Semiconductor layer 101 serves as the drift region of the device and has a first doping type. Epitaxial layer 103 serves as the well region of the device and has a second doping type opposite to the first doping type. The first doping type is either N-type or P-type, and the second doping type is either N-type or P-type. In this embodiment, the first doping type is, for example, N-type doping, and the second doping type is, for example, P-type doping.

[0053] The semiconductor device further includes a gate dielectric layer 105 and a gate conductor 106. The gate dielectric layer 105 surrounds the lower portion of the epitaxial layer 103, and the gate conductor 106 surrounds the gate dielectric layer 105 on the side of the gate dielectric layer 105 away from the epitaxial layer 103. The gate conductor 106 is isolated from the epitaxial layer 103 via the gate dielectric layer 105. Furthermore, the gate dielectric layer 105 and the gate conductor 106 are located above a recess 101a, and there is a gap between the bottom of the gate dielectric layer 105 and the bottom of the gate conductor 106 and the inner wall of the recess 101a (including the bottom and sidewalls of the recess 101a).

[0054] Furthermore, the bottom surface of the gate dielectric layer 105 is flush with the top surface of the semiconductor layer 101. The gate conductor 106 includes a first portion 1061 located above the recess 101a and a second portion 1062 extending into the recess 101a, and the width of the second portion 1062 gradually decreases from the top to the bottom of the recess 101a. Specifically, the sidewall of the second portion 1062 near the gate dielectric layer 105 is inclined, and the inclination of the sidewall of the second portion 1062 near the gate dielectric layer 105 is the same as the inclination of the corresponding sidewall of the recess 101a, and the sidewall of the second portion 1062 near the gate dielectric layer 105 is parallel to the corresponding sidewall of the recess 101a.

[0055] The semiconductor device also includes a source region 107 located in the epitaxial layer 103 (well region) and a drain region 108 located in the semiconductor layer 101 (drift region), wherein the source region 107 located in the epitaxial layer 103 (well region) and the drain region 108 located in the semiconductor layer 101 (drift region) have a first doping type.

[0056] Furthermore, the semiconductor device also includes a source region 107 and a drain region 108. A first-type dopant is implanted into the upper part of the epitaxial layer 103 to form the source region 107 in the upper part of the epitaxial layer 103, and a channel region is formed in the lower part of the epitaxial layer 103. The length of the channel region is the vertical length of the lower part of the epitaxial layer 103. A first-type dopant is implanted into the semiconductor layer 101 exposed at the bottom of the trench 101a to form the drain region 108 in the semiconductor layer 101 exposed at the bottom of the trench 101a.

[0057] The semiconductor device provided in this embodiment forms a suspended, surrounding gate conductor, which enhances the control capability of the semiconductor device without increasing the length of the gate conductor.

[0058] The channel length of the semiconductor device provided in this embodiment is the vertical length of the lower part of the epitaxial layer 103. Furthermore, the semiconductor device provided in this embodiment forms a gate structure that is wider at the top and narrower at the bottom, resulting in an asymmetry between the source and drain regions relative to the gate conductor, forming a LDMOS-like structure. The drain region is farther from the channel and is separated by a drift region with a lower concentration than the well, thereby acting as a breakdown voltage layer between the drain and the well, improving the device breakdown voltage.

[0059] Corresponding to Figure 1 The semiconductor device shown in this application also provides a method for fabricating the semiconductor device, comprising:

[0060] S10: Forming a groove in the semiconductor layer that extends from the surface of the semiconductor layer into its interior;

[0061] S20: An epitaxial layer is formed on the surface of a semiconductor layer, and the groove is disposed around the epitaxial layer;

[0062] S30: Form a gate dielectric layer and a gate conductor. The gate dielectric layer surrounds the lower part of the epitaxial layer, and the gate conductor surrounds the gate dielectric layer on the side of the gate dielectric layer away from the epitaxial layer. The gate dielectric layer and the gate conductor are located above the groove, and there is a gap between the bottom of the gate dielectric layer and the bottom of the gate conductor and the inner wall of the groove.

[0063] S40: A drain region is formed in the semiconductor layer exposed at the bottom of the groove, and a source region is formed on the upper part of the epitaxial layer.

[0064] Figures 2a to 2s The following are schematic cross-sectional views illustrating various stages in the fabrication process of the semiconductor device provided in the embodiments of this application. Figures 2a to 2s The method for fabricating the semiconductor device provided in the embodiments of this application will be described.

[0065] In step S10, a groove is formed in the semiconductor layer, wherein the top opening size of the groove is larger than its bottom opening size, and the sidewalls of the groove are inclined, such as... Figures 2a to 2e As shown.

[0066] like Figure 2a As shown, a semiconductor layer 101 is provided.

[0067] The semiconductor layer 101 can be selected from any one of a semiconductor substrate, a doped epitaxial layer (EPI), or a combination thereof. The semiconductor layer 101 serves as the drift region of the device and has a first doping type.

[0068] like Figure 2b As shown, a pre-groove 101aa is formed in the semiconductor layer 101.

[0069] In this step, a patterned first resist mask layer PR1 is formed on the semiconductor layer 101, and the semiconductor layer 101 is etched through the patterned first resist mask layer PR1 to form a pre-groove 101aa in the semiconductor layer 101. After the pre-groove 101aa is formed, the first resist mask layer PR1 is removed.

[0070] Furthermore, for example, a wet etching process is used to etch the semiconductor layer 101. The etchant contacts the semiconductor layer 101 exposed by the opening of the first resist mask layer PR1 to form a pre-groove 101aa in the semiconductor layer 101. The upper cross-sectional shape of the pre-groove 101aa is trapezoidal, and the lower cross-sectional shape of the pre-groove 101aa is an inverted trapezoid. The pre-groove 101aa is also called a Sigma groove.

[0071] In this embodiment, the etchant is, for example, a solution comprising tetramethylammonium hydroxide (TMAH). The desired shape of the pre-groove 101aa is obtained by selecting the crystal orientation of the semiconductor layer 101. In this embodiment, the crystal orientation of the semiconductor layer 101 is, for example,

[110] . Typically, the ratio of the etching rate of the crystal plane with crystal orientation

[111] to the etching rate of other crystal planes is close to 1:100; in other words, the etching rate of the crystal plane with crystal orientation

[110] and the crystal plane with crystal orientation

[100] is much greater than the etching rate of the crystal plane with crystal orientation

[111] . Since the crystal plane with crystal orientation

[111] is difficult to etch, a Sigma groove is formed along the crystal plane with crystal orientation

[111] .

[0072] like Figure 2c As shown, a first filling layer 1021 is formed in the pre-groove 101aa.

[0073] In this step, for example, a deposition process is used to form a first filling layer 1021 that fills the pre-groove 101aa and covers the surface of the semiconductor layer 101. Next, for example, a chemical mechanical polishing (CMP) process is used to remove the first filling layer 1021 from the surface of the semiconductor layer 101, leaving the first filling layer 1021 in the pre-groove 101aa. In this embodiment, the first filling layer 1021 is, for example, a silicon nitride layer.

[0074] like Figure 2d As shown, the first filling layer 1021 in the upper part of the pre-groove 101aa is removed.

[0075] In this step, for example, a wet etching process is used to remove the first filler layer 1021 in the upper part of the pre-groove 101aa. Since the semiconductor layer 101 and the first filler layer 1021 have different etching selectivity ratios, the semiconductor layer 101 is retained when the first filler layer 1021 in the pre-groove 101aa is removed.

[0076] like Figure 2e As shown, a portion of the semiconductor layer 101 has been removed.

[0077] In this step, for example, a chemical mechanical polishing (CMP) process is used to remove part of the semiconductor layer 101. It is worth noting that during the chemical mechanical polishing process, the remaining first filler layer 1021 in the groove 101a plays a supporting role to prevent the semiconductor layer 101 from collapsing during the polishing process, and further ensures that the shape of the lower part of the pre-groove 101aa is not affected by the chemical mechanical polishing process.

[0078] As a portion of the semiconductor layer 101 is removed, the cross-sectional shape of the pre-groove 101aa changes accordingly. In this embodiment, due to the support of the first filling layer 1021, the upper part of the pre-groove 101aa is removed, while the lower part of the pre-groove 101aa is completely retained, forming a groove 101a of the desired shape. Figure 2e After the steps shown are completed, the cross-sectional shape of the groove 101a is an inverted trapezoid. In other words, the top opening of the groove 101a is larger than its bottom opening, and the sidewalls of the groove 101a are inclined.

[0079] Next, the remaining first filling layer 1021 in the groove 101a is removed by wet etching.

[0080] In step S20, an epitaxial layer 103 is formed on the surface of the semiconductor layer between adjacent grooves 101a, such as... Figures 2f to 2j As shown.

[0081] like Figure 2f As shown, a second filling layer 1022 is formed.

[0082] In this step, for example, a deposition process is used to form a second filler layer 1022, which fills the groove 101a and covers the surface of the semiconductor layer 101. The second filler layer 1022 is a nitride layer.

[0083] like Figure 2g As shown, the second filling layer 1022 is planarized.

[0084] In this step, for example, a chemical mechanical polishing (CMP) process is used to planarize the second filler layer 1022. It is worth noting that after this step, the second filler layer 1022 includes a portion filling the groove 101a and a portion covering the surface of the semiconductor layer 101.

[0085] like Figure 2h As shown, the second filler layer 1022 covering the surface of the semiconductor layer 101 is removed to form a plurality of vias 1022a in the second filler layer 1022.

[0086] In this step, a patterned second resist mask layer PR2 is formed on the surface of the second filler layer 1022. The second resist mask layer PR2 covers the portion of the second filler layer 1022 that is filled in the groove 101a, and the opening of the second resist mask layer PR2 exposes the portion of the second filler layer 1022 that covers the surface of the semiconductor layer 101. Next, the second filler layer 1022 is etched through the opening of the second resist mask layer PR2 to remove the portion of the second filler layer 1022 that covers the surface of the semiconductor layer 101, forming a plurality of vias 1022a in the second filler layer 1022. The vias 1022a expose the surface of the semiconductor layer 101.

[0087] After forming a via 1022a in the second filler layer 1022, the second resist mask layer PR2 is removed.

[0088] like Figure 2i As shown, an epitaxial layer 103 is formed in the via 1022a of the second filling layer 1022.

[0089] In this step, for example, an epitaxial layer 103 is formed on the surface of the semiconductor layer 101 exposed by the via 1022a using an epitaxial growth process. The epitaxial layer 103 has a second doping type opposite to the first doping type. The epitaxial layer 103 serves as the well region of the device.

[0090] like Figure 2j As shown, the second filling layer 1022 in the groove 101a is removed.

[0091] In this step, for example, a wet etching process is used to remove the second filling layer 1022 in the groove 101a.

[0092] Furthermore, in S30, a gate dielectric layer and a gate conductor are formed. The gate dielectric layer surrounds the lower part of the epitaxial layer, and the gate conductor surrounds the gate dielectric layer on the side of the gate dielectric layer away from the epitaxial layer. The gate conductor is isolated from the epitaxial layer 103 via the gate dielectric layer. The gate dielectric layer and the gate conductor are located above the groove, and there are gaps between the bottom of the gate dielectric layer and the bottom of the gate conductor and the inner wall of the groove. Figures 2k to 2r As shown.

[0093] like Figure 2k As shown, a first barrier layer 1041 and a second barrier layer 1042 are formed sequentially.

[0094] In this step, for example, a deposition process is used to sequentially form a first barrier layer 1041 and a second barrier layer 1042. The first barrier layer 1041 conformally covers the bottom and sidewalls of the groove 101a, and the top and sidewalls of the epitaxial layer 103. The second barrier layer 1042 conformally covers the surface of the first barrier layer 1041. It is worth noting that in this embodiment, by setting the thickness of the second barrier layer 1042, it is possible for the second barrier layer 1042 to fill the space between adjacent epitaxial layers 103.

[0095] The first barrier layer 1041 is, for example, a nitrided layer, and the second barrier layer 1042 is, for example, an oxide layer.

[0096] like Figure 2l As shown, the second barrier layer 1042 and the first barrier layer 1041 on top of the epitaxial layer 103 are removed.

[0097] In this step, for example, a chemical mechanical polishing (CMP) process is used to remove the second barrier layer 1042 and the first barrier layer 1041 on top of the epitaxial layer 103.

[0098] like Figure 2m As shown, the first barrier layer 1041 on the sidewall of the epitaxial layer 103 is removed.

[0099] In this step, for example, wet etching is used to remove the first barrier layer 1041 on the sidewalls of the epitaxial layer 103, while the first barrier layer 1041 on the bottom and sidewalls of the groove 101a is retained due to the protection of the second barrier layer 1042. The epitaxial layer 103 and the first barrier layer 1041 have different etching selectivity ratios; when the first barrier layer 1041 is removed, the epitaxial layer 103 is retained. Similarly, the second barrier layer 1042 and the first barrier layer 1041 have different etching selectivity ratios; when the first barrier layer 1041 is removed, the second barrier layer 1042 is retained.

[0100] like Figure 2n As shown, the second barrier layer 1042 is removed.

[0101] In this step, for example, wet etching is used to remove the second barrier layer 1042, while the first barrier layer 1041 on the bottom and sidewalls of the groove 101a is retained. The first barrier layer 1041 and the second barrier layer 1042 have different etching selectivity ratios. When the second barrier layer 1042 is removed, the first barrier layer 1041 is retained, and the top surface of the first barrier layer 1041 on the sidewalls of the groove 101a is flush with the surface of the semiconductor layer 101. Furthermore, the retained first barrier layer 1041 covers the bottom and sidewalls of the groove 101a, but does not completely fill it. After the first barrier layer 1041 covers the groove 101a, an intermediate-state groove 101b is formed. It is worth noting that, since the remaining first barrier layer 1041 conformally covers the bottom and sidewalls of the groove 101a, the inclination of the sidewall of the intermediate state groove 101b is the same as that of the sidewall of the groove 101a, thereby ensuring the sidewall shape of the second part 1062 of the gate conductor 106 formed subsequently.

[0102] like Figure 2o As shown, a dielectric layer 105a is formed on the top and sidewalls of the epitaxial layer 103.

[0103] In this step, for example, an oxidation growth process is used to form a dielectric layer 105a on the top and sidewalls of the epitaxial layer 103, while the bottom and sidewalls of the groove 101a are not oxidized due to the protection of the first barrier layer 1041.

[0104] like Figure 2p As shown, a conductor layer 106a is formed.

[0105] In this step, for example, a conductor layer 106a is formed by furnace tube growth. The conductor layer 106a conformally covers the surface of the dielectric layer 105a. By controlling the thickness of the conductor layer 106a, the conductor layer 106a fills the space between adjacent epitaxial layers 103, thereby covering the bottom and sidewalls of the intermediate state groove 101b. The portion of the conductor layer 106a covering the sidewalls of the intermediate state groove 101b forms an inclined sidewall corresponding to the sidewalls of the intermediate state groove 101b.

[0106] like Figure 2q As shown, the conductor layer 106a and dielectric layer 105a on top of the epitaxial layer 103 are removed.

[0107] In this step, for example, a chemical mechanical polishing (CMP) process is used to remove the conductor layer 106a and dielectric layer 105a on the top of the epitaxial layer 103, while the dielectric layer 105a on the sidewall of the epitaxial layer 103 is retained. Similarly, the conductor layer 106a between adjacent epitaxial layers 103 is retained.

[0108] like Figure 2r As shown, part of the conductor layer 106a has been removed.

[0109] In this step, a patterned photoresist layer is formed on the aforementioned semiconductor structure. Then, for example, a dry etching process is used to etch the conductor layer 106a through the patterned photoresist layer to remove a portion of the conductor layer 106a. In one embodiment, the conductor layer 106a covering the bottom of the intermediate state recess 101b is removed, while the conductor layer 106a covering the sidewalls of the intermediate state recess 101b and adjacent to the dielectric layer 105a is retained.

[0110] Next, the bottom of the covered groove 101a and the first barrier layer 1041 are removed, and a gap is formed between the bottom of the retained dielectric layer 105a and conductor layer 106a and the bottom and sidewall of the groove 101a.

[0111] In step S40, a gate dielectric layer 105, a gate conductor 106, a source region 107, and a drain region 108 are formed, as follows: Figure 2s As shown.

[0112] In this step, at least a portion of the top of the dielectric layer 105a and the conductor layer 106a is removed, thereby exposing the upper portion of the epitaxial layer 103. The remaining dielectric layer 105a forms the gate dielectric layer 105, and the remaining conductor layer 106a forms the gate conductor 106. Next, for example, a source region 107 is formed on the upper portion of the epitaxial layer 103 by ion implantation, and a drain region 108 is formed at the bottom of the recess 101a.

[0113] The unexpected technical effect of this application is:

[0114] The semiconductor device provided in this embodiment forms a suspended, surrounding gate conductor, which enhances the control capability of the semiconductor device without increasing the length of the gate conductor.

[0115] The channel length of the semiconductor device provided in this embodiment is the vertical length of the lower part of the epitaxial layer 103. Furthermore, the semiconductor device provided in this embodiment forms a gate conductor that is wider at the top and narrower at the bottom, resulting in an asymmetry between the source and drain regions relative to the gate conductor, forming a LDMOS-like structure. The drain region is farther from the channel and is separated by a drift region with a lower concentration than the well, thereby acting as a breakdown voltage layer between the drain and the well, improving the device breakdown voltage.

[0116] This application forms a Sigma groove, and by removing the upper part of the Sigma groove, a groove of the desired shape (a cross-sectional shape of an inverted trapezoid) is finally obtained.

[0117] In a preferred embodiment, during the removal of the upper part of the Sigma groove, a first filler layer with higher hardness is filled in the lower part of the Sigma groove to ensure that the lower part of the Sigma groove is not affected by the grinding process.

[0118] This application forms a second filling layer at the bottom and sidewalls of the groove to form a protective layer at the bottom and sidewalls of the groove, thereby epitaxially growing an epitaxial layer on the surface of a specific semiconductor layer.

[0119] This application first forms a first barrier layer that conformally covers the bottom and sidewalls of the groove, as well as the top and sidewalls of the epitaxial layer. Then, it selectively removes the first barrier layer on the top and sidewalls of the epitaxial layer, and finally retains the first barrier layer that conformally covers the bottom and sidewalls of the groove.

[0120] In this application, the first barrier layer conformally covering the bottom and sidewalls of the groove serves as a shaping layer for forming the gate conductor, thus forming a sacrificial layer for creating the gap between the gate conductor and the interior of the groove. Specifically, this application first forms a groove with inclined sidewalls, then forms a first barrier layer conformally covering the sidewalls of the groove to ensure that the conductor layer covering the first barrier layer has corresponding inclined sidewalls. Finally, the first barrier layer is removed, resulting in a gap between the bottom of the final gate conductor and the inner wall of the groove, while simultaneously forming a gate conductor that is wider at the top and narrower at the bottom.

[0121] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor layer having grooves extending from its surface into its interior; An epitaxial layer is located on the surface of the semiconductor layer, and the groove is disposed around the epitaxial layer; A gate dielectric layer surrounds the lower portion of the epitaxial layer; A gate conductor surrounds the gate dielectric layer on the side of the gate dielectric layer away from the epitaxial layer; The source region is located on the upper part of the epitaxial layer; as well as The drain region is located in the semiconductor layer exposed at the bottom of the groove; The gate dielectric layer and the gate conductor are located above the groove, and there is a gap between the bottom of the gate dielectric layer and the bottom of the gate conductor and the inner wall of the groove; The gate conductor includes a first portion located above the groove and a second portion extending into the groove, the width of which gradually decreases from the top of the groove to the bottom of the groove.

2. The semiconductor device according to claim 1, characterized in that, The top opening of the groove is larger than its bottom opening, and the sidewall of the groove is inclined; the sidewall of the second part near the gate dielectric layer is inclined, and the inclination of the sidewall of the second part is the same as the inclination of the corresponding sidewall of the groove.

3. A method for fabricating a semiconductor device, characterized in that, include: A groove is formed in the semiconductor layer, extending from the surface of the semiconductor layer into its interior; An epitaxial layer is formed on the surface of the semiconductor layer, and the groove is disposed around the epitaxial layer; A gate dielectric layer and a gate conductor are formed, wherein the gate dielectric layer surrounds the lower portion of the epitaxial layer, and the gate conductor surrounds the gate dielectric layer on the side of the gate dielectric layer away from the epitaxial layer; A drain region is formed in the semiconductor layer exposed at the bottom of the groove, and a source region is formed on the upper part of the epitaxial layer; The gate dielectric layer and the gate conductor are located above the groove, and there is a gap between the bottom of the gate dielectric layer and the bottom of the gate conductor and the inner wall of the groove; The gate conductor includes a first portion located above the groove and a second portion extending into the groove, the width of which gradually decreases from the top of the groove to the bottom of the groove.

4. The preparation method according to claim 3, characterized in that, The method of forming a groove in the semiconductor layer includes: A pre-groove is formed in the semiconductor layer, wherein the upper part of the pre-groove has a trapezoidal cross-sectional shape and the lower part of the pre-groove has an inverted trapezoidal cross-sectional shape; A first filling layer is formed in the pre-groove; Remove the first filler layer in the upper part of the pre-groove; Remove part of the semiconductor layer, and at the same time remove the upper part of the pre-groove; The first filler layer in the lower part of the pre-groove is removed, and the lower part of the pre-groove is retained to form a groove.

5. The preparation method according to claim 3, characterized in that, A method for forming an epitaxial layer on the surface of the semiconductor layer includes: A second filler layer is formed to fill the groove and cover the surface of the semiconductor layer; Remove the second filler layer covering the surface of the semiconductor layer to form a via that exposes the surface of the semiconductor layer; An epitaxial layer is formed on the surface of the semiconductor layer exposed by the via; Remove the second filler layer from the groove.

6. The preparation method according to claim 3, characterized in that, Methods for forming the gate dielectric layer and the gate conductor include: A first barrier layer is formed to conformally cover the bottom and sidewalls of the groove. After the first barrier layer is formed, the remaining space of the groove forms an intermediate state groove. The top opening size of the groove is larger than its bottom opening size, and the sidewalls of the groove are inclined. The intermediate state groove has an inclined sidewall corresponding to the groove. A dielectric layer is formed around the sidewalls of the epitaxial layer, and a conductor layer is formed around the dielectric layer, wherein the conductor layer covers the bottom and sidewalls of the intermediate state groove, and the portion of the conductor layer covering the sidewalls of the intermediate state groove has an inclined sidewall corresponding to the sidewalls of the intermediate state groove. Remove part of the conductor layer, leaving at least the conductor layer that covers the sidewalls of the intermediate state groove and is adjacent to the dielectric layer; After removing the first barrier layer, a gap is formed between the bottom of the gate dielectric layer and the bottom of the gate conductor and the inner wall of the groove; At least a portion of the top of the dielectric layer and the conductor layer is removed, such that the upper part of the epitaxial layer is exposed, the remaining dielectric layer forms the gate dielectric layer, and the remaining conductor layer forms the gate conductor.

7. The preparation method according to claim 6, characterized in that, A method for forming a first barrier layer covering the bottom and sidewalls of the groove includes: A first barrier layer is formed, which conformally covers the bottom and sidewalls of the groove, as well as the top and sidewalls of the epitaxial layer; A second barrier layer is formed, which conformally covers the surface of the first barrier layer. By setting the thickness of the second barrier layer, the second barrier layer fills the space between adjacent epitaxial layers. Remove the second barrier layer and the first barrier layer at the top of the epitaxial layer; Remove the first barrier layer from the sidewall of the epitaxial layer, while retaining the first barrier layer covering the bottom and sidewall of the groove; Remove the remaining second barrier layer.

8. The preparation method according to claim 6, characterized in that, include: A method for forming a dielectric layer surrounding the sidewalls of the epitaxial layer, and for forming a conductor layer surrounding the dielectric layer, includes: A dielectric layer is formed covering the top and sidewalls of the epitaxial layer; A conformal conductor layer is formed covering the surface of the dielectric layer, wherein the thickness of the conductor layer is controlled such that the conductor layer fills the space between adjacent epitaxial layers; Remove the conductor layer and dielectric layer on top of the epitaxial layer.

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