Semiconductor device and method of manufacturing the same
By employing specific ion implantation processes in the channel region and source/drain contact region, the problem of high contact resistance between the channel and source/drain electrodes was solved, the on-state current was increased, the process flow was simplified, and the performance of semiconductor devices was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-23
AI Technical Summary
In the prior art, the contact resistance is relatively large when the channel of a metal oxide thin film transistor contacts the source and drain, which affects the improvement of device performance.
By implanting fluorine ions into the channel region to form the gate dielectric layer and the gate, and then implanting hydrogen ions into the source and drain contact regions, the carrier concentration is increased, the contact resistance is reduced, and the additional contact layer preparation step is eliminated by simplifying the process flow.
It effectively reduces the contact resistance between the channel and the source/drain contact area, increases the on-state current, improves the performance of semiconductor devices, and simplifies the process flow.
Smart Images
Figure CN122269729A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Therefore, the requirements for transistor performance in semiconductor devices are becoming increasingly stringent. Transistors with low contact resistance and high on-state current are highly desirable. Summary of the Invention
[0003] Based on this, the present disclosure provides a semiconductor device and its fabrication method, which can effectively reduce the contact resistance between the channel and the source / drain electrodes, increase the on-state current, and thus improve the performance of the semiconductor device.
[0004] According to some embodiments, this disclosure provides a method for fabricating a semiconductor device, comprising:
[0005] A semiconductor layer is formed; the semiconductor layer includes a channel region and a source / drain contact region;
[0006] Fluorine ion implantation is performed on the semiconductor layer in the channel region;
[0007] A gate dielectric layer covering the channel region and a gate electrode covering the gate dielectric layer are formed;
[0008] Perform hydrogen ion implantation on the semiconductor layer of the source / drain contact region;
[0009] Form source / drain electrodes that cover the source / drain contact area.
[0010] According to some embodiments, the fabrication method further includes, prior to forming the semiconductor layer:
[0011] A stacked structure is formed, which includes multiple alternating layers of first dielectric layers and multiple layers of second dielectric layers;
[0012] Etching the stacked structure forms the first hole;
[0013] The first receiving groove is formed by etching the first dielectric layer based on the first hole.
[0014] The semiconductor layer includes:
[0015] Semiconductor material layers are deposited on the inner wall of the first receiving groove and the inner wall of the first hole;
[0016] The stacked structure is etched to form second holes located on opposite sides of the first accommodating trench; the second holes expose the semiconductor material layer located at the bottom of the first accommodating trench;
[0017] Based on the second hole etching of the semiconductor material layer, multiple semiconductor layers are formed at intervals.
[0018] The channel region is located on the surface of the semiconductor layer facing the first via. The source / drain contact region is located on the surface of the semiconductor layer away from the first via.
[0019] According to some embodiments, a fluorine ion implantation process is performed on the semiconductor layer of the channel region, including:
[0020] Fluorine is doped into the semiconductor layer of the channel region using plasma processing, solution processing, or thin film growth processes containing fluorine ions.
[0021] According to some embodiments, a gate dielectric layer covering the channel region and a gate covering the gate dielectric layer are formed, including:
[0022] A gate dielectric layer covering a semiconductor layer is formed in the first accommodating trench and the first hole, and a conductive material covering the gate dielectric layer and filling the first accommodating trench and the first hole is formed.
[0023] The conductive material in the first accommodating groove constitutes the gate, and the conductive material in the first hole constitutes the word line connecting multiple gates.
[0024] According to some embodiments, the step of performing a fluorine ion implantation process on the semiconductor layer of the channel region is performed after the deposition of the semiconductor material layer and before the formation of the gate dielectric layer.
[0025] According to some embodiments, the fabrication method further includes, prior to performing a hydrogen ion implantation process on the semiconductor layer of the source / drain contact region:
[0026] An isolation layer is formed in the etched area of the semiconductor material layer based on the second hole;
[0027] Based on the second hole, the second dielectric layer covering the semiconductor layer is removed to form a second accommodating trench; the second accommodating trench exposes the source / drain contact area.
[0028] The formation of the source / drain electrode covering the source / drain contact area includes: forming a source / drain electrode that fills the second receiving groove.
[0029] According to some embodiments, a hydrogen ion implantation process is performed on the semiconductor layer of the source / drain contact region, including:
[0030] Hydrogen is doped into the semiconductor layer of the source / drain contact region using a plasma processing technology containing hydrogen ions, a solution process containing hydrogen ions, or a thin film growth process containing hydrogen ions.
[0031] According to some embodiments, the material of the semiconductor layer includes: metal oxide semiconductor material.
[0032] According to some embodiments, another aspect of this disclosure provides a semiconductor device, including: a semiconductor layer, a gate dielectric layer, a gate electrode, and source / drain electrodes. The semiconductor layer includes a channel region and a source / drain contact region. The channel region is doped with fluorine, and the source / drain contact region is doped with hydrogen. The gate dielectric layer covers the semiconductor layer of the channel region. The gate electrode covers the gate dielectric layer. The source / drain electrodes are located on the side of the semiconductor layer opposite to the gate dielectric layer and cover the semiconductor layer of the source / drain contact region.
[0033] According to some embodiments, the semiconductor device also includes a stacked structure.
[0034] The stacked structure includes multiple alternating layers of first dielectric layers and multiple layers of second dielectric layers, a first via penetrating each of the first and second dielectric layers, a first receiving trench located within the first dielectric layer and surrounding the first via, and second receiving trenches located within the second dielectric layers and on opposite sides of the first via. The source / drain electrodes are located within the second receiving trenches. Semiconductor layers cover the sidewalls and part of the top and bottom surfaces of the source / drain electrodes. A gate dielectric layer is located within the first receiving trenches and the first via, and covers the surface of the semiconductor layer opposite to the source / drain electrodes. The gate electrode is located on the surface of the gate dielectric layer opposite to the semiconductor layer.
[0035] According to some embodiments, the semiconductor device further includes an isolation layer located within the first dielectric layer and covering the exposed sidewalls of the semiconductor layer and the gate dielectric layer. The isolation layer is also located between adjacent source / drain electrodes in the stacking direction of the first and second dielectric layers.
[0036] According to some embodiments, the semiconductor device further includes word lines located within a first aperture. The word lines are correspondingly connected to gates exposed within the same first aperture.
[0037] According to some embodiments, the material of the semiconductor layer includes: metal oxide semiconductor material.
[0038] According to some embodiments, this disclosure provides another aspect of an electronic device, which includes a semiconductor device manufactured by the method for manufacturing semiconductor devices described in the foregoing embodiments, or the semiconductor device described in the foregoing embodiments.
[0039] The embodiments disclosed herein may have, or at least have, the following advantages:
[0040] In this embodiment, after forming the semiconductor layer, a fluorine ion implantation process is first performed on the semiconductor layer in the channel region to form a gate dielectric layer and a gate covering the channel layer. Then, a hydrogen ion implantation process is performed on the semiconductor layer in the source / drain contact region, which increases the carrier concentration in the semiconductor layer of the source / drain contact region, effectively improving the carrier concentration in the source / drain contact region. This reduces the contact resistance between the channel region and the source / drain contact region, increases the on-state current, and thus improves the performance of the semiconductor device. Moreover, this embodiment achieves a semiconductor device process flow of "semiconductor layer-gate-source / drain electrode" by first growing the semiconductor layer, then growing the gate dielectric layer and the gate, and finally forming the source / drain electrode. That is, this embodiment does not require the additional fabrication of a contact layer between the semiconductor layer and the source / drain electrode, eliminating a series of process steps such as patterning to form the contact layer. Only hydrogen ion doping is needed in the selected area (i.e., the semiconductor layer of the source / drain contact region) to reduce the contact resistance between the channel region and the source / drain contact region, simplifying the semiconductor device process flow.
[0041] Furthermore, by passivating oxygen vacancies in the channel region through the implantation of fluorine ions, the semiconductor layer in the channel region can be made to have good thermal stability, thereby enabling the adjustment of the threshold voltage. Attached Figure Description
[0042] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.
[0043] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in some embodiments;
[0044] Figure 2 This is a schematic diagram of the process of forming a first accommodating trench in a method for fabricating a semiconductor device provided in some embodiments;
[0045] Figure 3 This is a schematic diagram of the process for forming a semiconductor layer in a method for fabricating a semiconductor device provided in some embodiments;
[0046] Figure 4 This is a schematic diagram of the process for forming a second accommodating trench in a method for fabricating a semiconductor device provided in some embodiments;
[0047] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S51 of a method for fabricating a semiconductor device provided in some embodiments;
[0048] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S52 of a method for fabricating a semiconductor device provided in some embodiments;
[0049] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S53 of a method for fabricating a semiconductor device provided in some embodiments;
[0050] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S101 of a method for fabricating a semiconductor device provided in some embodiments;
[0051] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S200 of a method for fabricating a semiconductor device provided in some embodiments;
[0052] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming a gate dielectric layer in a method for fabricating a semiconductor device provided in some embodiments;
[0053] Figure 11 This is a schematic cross-sectional view of the structure obtained after forming a conductive material in a method for fabricating a semiconductor device provided in some embodiments;
[0054] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S102 of a method for fabricating a semiconductor device provided in some embodiments;
[0055] Figure 13 This is a schematic cross-sectional view of the structure obtained in step S103 of a method for fabricating a semiconductor device provided in some embodiments;
[0056] Figure 14 This is a schematic cross-sectional view of the structure obtained in step S351 of a method for fabricating a semiconductor device provided in some embodiments;
[0057] Figure 15 This is a schematic cross-sectional view of the structure obtained in step S352 of a method for fabricating a semiconductor device provided in some embodiments;
[0058] Figure 16 This is a schematic cross-sectional view of the structure obtained in step S400 of a method for fabricating a semiconductor device provided in some embodiments;
[0059] Figure 17 This is a top view schematic diagram of the fluorine ion implantation direction and the hydrogen ion implantation direction in a method for fabricating a semiconductor device provided in some embodiments;
[0060] Figure 18This is a cross-sectional structural diagram of the structure obtained in step S500 of a method for fabricating a semiconductor device provided in some embodiments.
[0061] Explanation of reference numerals in the attached figures:
[0062] 1-Substrate; 11-Semiconductor layer; 110-Semiconductor material layer; 12-Gate dielectric layer; 13-Gate; 14-Isolation layer; 15-Source / drain;
[0063] D - Stacked structure; D1 - First dielectric layer; D2 - Second dielectric layer; C1 - First receiving groove; C2 - Second receiving groove; K1 - First hole; K2 - Second hole. Detailed Implementation
[0064] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0066] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.
[0067] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0068] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0069] When used here, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).
[0070] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.
[0071] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Therefore, the performance requirements for transistors in semiconductor devices are becoming increasingly stringent. Transistors with low contact resistance and high on-state current are highly desirable. However, for thin-film transistors (TFTs) using metal oxides (e.g., indium gallium zinc oxide (IGZO)) as the channel, the IGZO channel exhibits a relatively large current, and there is a certain contact resistance when it contacts the source / drain electrodes. This hinders further improvements in semiconductor device performance.
[0072] For indium-containing metal oxides, such as IGZO, hydrogen doping via hydrogen-containing plasma increases the oxygen vacancy concentration in the shallow donor levels, thereby increasing the number of charge carriers and thus improving carrier mobility. This is further enhanced by using fluoride ions (F... -Fluorine doping can passivate oxygen vacancies, giving IGZO good thermal stability. The concentrations of fluorine and oxygen vacancies remain stable at different annealing temperatures, and fluorine doping reduces the oxygen vacancy concentration, which helps to regulate the threshold voltage of the transistor.
[0073] Based on this, the present disclosure provides a semiconductor device and its fabrication method, which can effectively increase the carrier concentration in the channel and source / drain contact regions, thereby reducing the contact resistance between the channel and the source / drain, increasing the on-state current, and thus improving the performance of the semiconductor device.
[0074] Please see Figure 1 This disclosure provides a method for fabricating a semiconductor device, including steps S100 to S700, through some embodiments.
[0075] S100, forming a semiconductor layer; the semiconductor layer includes a channel region and a source / drain contact region.
[0076] S200 performs a fluorine ion implantation process on the semiconductor layer of the channel region.
[0077] S300, forming a gate dielectric layer covering the channel region, and a gate covering the gate dielectric layer.
[0078] S400 performs a hydrogen ion implantation process on the semiconductor layer of the source / drain contact region.
[0079] S500 forms the source / drain electrodes covering the source / drain contact area.
[0080] In this embodiment, after forming the semiconductor layer, a fluorine ion implantation process is first performed on the semiconductor layer in the channel region to form a gate dielectric layer and a gate covering the channel layer. Then, a hydrogen ion implantation process is performed on the semiconductor layer in the source / drain contact region, which increases the carrier concentration in the semiconductor layer of the source / drain contact region, effectively improving the carrier concentration in the source / drain contact region. This reduces the contact resistance between the channel region and the source / drain contact region, increases the on-state current, and thus improves the performance of the semiconductor device. Moreover, this embodiment achieves a semiconductor device process flow of "semiconductor layer-gate-source / drain electrode" by first growing the semiconductor layer, then growing the gate dielectric layer and the gate, and finally forming the source / drain electrode. That is, this embodiment does not require the additional fabrication of a contact layer between the semiconductor layer and the source / drain electrode, eliminating a series of process steps such as patterning to form the contact layer. Only hydrogen ion doping is needed in the selected area (i.e., the semiconductor layer of the source / drain contact region) to reduce the contact resistance between the channel region and the source / drain contact region, simplifying the semiconductor device process flow.
[0081] Furthermore, by passivating oxygen vacancies in the channel region through the implantation of fluorine ions, the semiconductor layer in the channel region can be made to have good thermal stability, thereby enabling the adjustment of the threshold voltage.
[0082] In some embodiments, please refer to Figure 2 Before forming the semiconductor layer in step S100, the preparation method also includes steps S51 to S53.
[0083] S51, forming a stacked structure, the stacked structure including multiple layers of first dielectric layers and multiple layers of second dielectric layers stacked alternately.
[0084] S52, etch the stacked structure to form the first hole.
[0085] S53, based on the first hole, the first dielectric layer is etched to form the first receiving groove.
[0086] Please refer to Figure 3 Step S100, which forms the semiconductor layer, includes steps S101 to S103.
[0087] S101, deposit a semiconductor material layer on the inner wall of the first receiving groove and the inner wall of the first hole.
[0088] S102, etch the stacked structure to form second holes located on opposite sides of the first accommodating trench; the second holes expose the semiconductor material layer located at the bottom of the first accommodating trench.
[0089] S103, based on the second hole etching of the semiconductor material layer, forms multiple semiconductor layers spaced apart.
[0090] The channel region is located on the surface of the semiconductor layer facing the first via. The source / drain contact region is located on the surface of the semiconductor layer away from the first via.
[0091] In some embodiments, step S200 performs a fluorine ion implantation process on the semiconductor layer of the channel region, including: using a fluorine ion-containing plasma processing process, a fluorine ion-containing solution process, or a fluorine ion-containing thin film growth process to dope fluorine into the semiconductor layer of the channel region.
[0092] In some embodiments, step S300, forming a gate dielectric layer covering the channel region and a gate covering the gate dielectric layer, includes: forming a gate dielectric layer covering a semiconductor layer in the first accommodating trench and the first hole, and a conductive material covering the gate dielectric layer and filling the first accommodating trench and the first hole.
[0093] The conductive material in the first accommodating groove constitutes the gate, and the conductive material in the first hole constitutes the word line connecting multiple gates.
[0094] In some embodiments, step S200 involves performing a fluorine ion implantation process on the semiconductor layer of the channel region, which is performed after depositing the semiconductor material layer and before forming the gate dielectric layer.
[0095] In some embodiments, please refer toFigure 4 Before performing hydrogen ion implantation on the semiconductor layer of the source / drain contact region in step S400, the fabrication method further includes:
[0096] S351, based on the second hole, forms an isolation layer in the etched area of the semiconductor material layer.
[0097] S352, based on the second hole, remove the second dielectric layer covering the semiconductor layer to form a second accommodating trench; the second accommodating trench exposes the source / drain contact area.
[0098] In some examples, a wet etching process can be used to remove the second dielectric layer covering the semiconductor layer, forming a second accommodating trench. Here, the second accommodating trench is an annular trench, which needs to be etched and segmented during subsequent deposition of conductive material to ensure that the source and drain electrodes of each transistor are independent of each other.
[0099] Step S500, which involves forming a source / drain electrode covering the source / drain contact area, includes forming a source / drain electrode that fills the second receiving groove.
[0100] According to some embodiments, step S400 performs a hydrogen ion implantation process on the semiconductor layer of the source / drain contact region, including: using a hydrogen ion-containing plasma processing process, a hydrogen ion-containing solution process, or a hydrogen ion-containing thin film growth process to dope hydrogen into the semiconductor layer of the source / drain contact region.
[0101] According to some embodiments, the material of the semiconductor layer includes a metal oxide semiconductor material. For example, the material of semiconductor layer 11 can be indium gallium zinc oxide.
[0102] It should be noted that in the above embodiments, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, and may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps. The method is limited to enabling the fabrication of the corresponding memory.
[0103] To more clearly illustrate the fabrication method of the semiconductor device provided in the above embodiments, the following is combined with... Figures 5 to 18 The preparation method is described in detail.
[0104] In step S51, please refer to Figure 5 This forms a stacked structure D, which includes multiple alternating layers of first dielectric layer D1 and multiple layers of second dielectric layer D2.
[0105] In some examples, the stacked structure D includes multiple layers of first dielectric layer D1 and multiple layers of second dielectric layer D2 that are alternately stacked along a first direction (e.g., the X direction).
[0106] In some examples, the stacked structure D is disposed on the substrate 1.
[0107] For example, substrate 1 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multilayer structure. For example, substrate 1 can be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0108] For example, the material of the first dielectric layer D1 includes, but is not limited to, nitrides. For instance, the material of the first dielectric layer D1 can be silicon nitride.
[0109] For example, the material of the second dielectric layer D2 includes, but is not limited to, oxides. For instance, the material of the second dielectric layer D2 can be silicon oxide. In this way, by depositing a stack of silicon oxide and silicon nitride layers, the process challenges posed by etching a stack of metal / silicon oxide layers are avoided.
[0110] Here, the first dielectric layer D1 can be located between adjacent second dielectric layers D2, or as the first or top layer, and the number of first dielectric layers D1 can be matched to the number of stacked second dielectric layers D2. Each first dielectric layer D1 and each second dielectric layer D2 can be formed using a separate deposition process.
[0111] For example, the deposition processes mentioned above and below include, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular layer deposition (MLD), and plasma enhanced chemical vapor deposition (PECVD).
[0112] Furthermore, after forming the stacked structure D, a first mask layer (not shown) can be formed on the upper surface of the top first dielectric layer D1.
[0113] For example, the first mask layer includes a photoresist layer and / or a hard mask layer, thereby facilitating subsequent etching of the stacked structure D based on the mask pattern in the first mask layer.
[0114] In step S52, please refer to Figure 6 The stacked structure D is etched to form the first hole K1.
[0115] In some examples, the stacked structure D is etched along a first direction (e.g., the X direction) to form the first hole K1.
[0116] For example, the first dielectric layer D1 and the second dielectric layer D2 in the stacked structure D can be formed by etching based on the pattern of the first mask layer to have the same pattern.
[0117] In some examples, the first hole K1 exposes the surface of the substrate 1.
[0118] In some examples, a dry etching process can be used to form the first hole K1.
[0119] In step S53, please refer to Figure 7 The first dielectric layer D1 is etched based on the first hole K1 to form the first receiving groove C1.
[0120] In some examples, a wet etching process can be used to form the first receiving groove C1.
[0121] In step S101, please refer to Figure 8 A semiconductor material layer 110 is deposited on the inner wall of the first receiving groove C1 and the inner wall of the first hole K1.
[0122] It should be noted here that the inner wall includes the bottom wall and the side walls.
[0123] In some examples, the semiconductor material layer 110 conformally covers the inner wall of the first receiving groove C1 and the inner wall of the first hole K1. That is, the semiconductor material layer 110 is a thin-layer structure, and the surface of the semiconductor material layer 110 conforms to the surface of the inner wall of the first receiving groove C1 and the inner wall of the first hole K1, so that the surface shape of the semiconductor material layer 110 is similar to the surface shape of the inner wall of the first receiving groove C1 and the inner wall of the first hole K1.
[0124] In some examples, the semiconductor material layer 110 can be formed using an atomic layer deposition (ALD) process.
[0125] In some examples, the material of the semiconductor material layer 110 includes indium gallium zinc oxide (IGZO).
[0126] In some embodiments, step S200 is the step of performing a fluorine ion implantation process on the semiconductor layer 11 in the channel region, which is performed after step S101 depositing the semiconductor material layer 110 and before step S300 forming the gate dielectric layer 12.
[0127] In step S200, please refer to Figure 9 Fluorine is doped into the semiconductor layer of the channel region using plasma processing with fluorine ions, solution processing with fluorine ions, or thin film growth processing with fluorine ions.
[0128] Here, Figure 9 The arrow in the image indicates fluoride ion implantation.
[0129] In some examples, performing a fluorine ion implantation process on the semiconductor layer of the channel region includes: doping fluorine into the semiconductor material layer 110 of the channel region using a fluorine-containing plasma treatment (e.g., NF3) process, a fluorine-containing solution process, or a fluorine-containing thin film growth process.
[0130] In step S300, please refer to Figure 10 and Figure 11 A gate dielectric layer 12 covering the semiconductor layer is formed in the first receiving groove C1 and the first hole K1, and a conductive material 13 covering the gate dielectric layer 12 and filling the first receiving groove C1 and the first hole K1 is formed.
[0131] Here, the gate dielectric layer 12 covering the semiconductor layer formed within the first receiving trench C1 and the first hole K1 includes: forming a gate dielectric layer 12 covering the semiconductor material layer 110 within the first receiving trench C1 and the first hole K1. That is, the gate dielectric layer 12 has a thin layer structure, and the surface of the gate dielectric layer 12 is shaped to resemble the surface of the semiconductor material layer 110 near the inner wall surface of the first hole K1, so that the surface shape of the gate dielectric layer 12 is similar to the surface shape of the semiconductor material layer 110 near the inner wall of the first hole K1.
[0132] In some examples, the gate dielectric layer 12 can be formed using an atomic layer deposition (ALD) process.
[0133] In some examples, the gate dielectric layer 12 includes an HK (high-K) dielectric layer or an aluminum oxide (Al2O3) layer. An HK dielectric layer refers to a dielectric layer having a high dielectric constant K, for example, greater than 3.9.
[0134] In some examples, the gate dielectric layer 12 is heat-treated.
[0135] In some examples, the heat treatment temperature range includes 300℃ to 500℃. For example, the heat treatment temperature for the gate dielectric layer 12 can be 300℃, 335℃, 370℃, 405℃, 440℃, 475℃, or 500℃, etc. Thus, by controlling the heat treatment temperature of the gate dielectric layer 12 within 300℃ to 500℃, the quality of the semiconductor material layer 110 in the channel region can be guaranteed not to be affected.
[0136] In some examples, the conductive material 13 can be formed using an atomic layer deposition (ALD) process.
[0137] In some examples, the material of conductive material 13 includes a metal. For example, the material of conductive material 13 is tungsten.
[0138] The conductive material 13 in the first accommodating groove C1 forms a gate, and the conductive material 13 in the first hole K1 forms a word line connecting multiple gates.
[0139] In step S102, please refer to Figure 12 The stacked structure D is etched to form second holes K2 located on opposite sides of the first accommodating trench C1; the second holes K2 expose the semiconductor material layer 110 located at the bottom of the first accommodating trench C1.
[0140] In some examples, a dry etching process can be used to form the second hole K2.
[0141] In step S103, please refer to Figure 13 Based on the second hole K2, the semiconductor material layer 110 is etched to form a plurality of spaced semiconductor layers 11.
[0142] In some examples, a wet etching process can be used to etch the semiconductor material layer 110.
[0143] In step S351, please refer to Figure 14 Based on the second hole K2, an isolation layer 14 is formed in the etched area of the semiconductor material layer 110.
[0144] In some examples, forming an isolation layer 14 in the etched region of the semiconductor material layer 110 based on the second hole K2 includes: forming an isolation material layer that fills the second hole K2 on the surface of the substrate 1 using an ALD process; etching the isolation material layer using a dry etching process, retaining the isolation material layer in the etched region of the semiconductor material layer 110, to form the isolation layer 14.
[0145] In some examples, the material of the isolation layer 14 may include, but is not limited to, nitrides. For example, the material of the isolation layer 14 may be silicon nitride.
[0146] In step S352, please refer to Figure 15 Based on the second hole K2, the second dielectric layer D2 covering the semiconductor layer 11 is removed to form the second accommodating trench C2; the second accommodating trench C2 exposes the source / drain contact area.
[0147] In this embodiment of the disclosure, by removing the second dielectric layer D2 covering the semiconductor layer 11, the exposed semiconductor layer 11 and the contact area between the subsequently formed source / drain electrodes, i.e. the semiconductor layer 11 of the source / drain contact area, facilitate the implementation of the subsequent hydrogen ion implantation process.
[0148] In some examples, a wet etching process can be used to remove the second dielectric layer D2 covering the semiconductor layer 11 to form a second accommodating trench C2. Here, the second accommodating trench C2 is an annular trench, which needs to be etched and divided during the subsequent deposition of conductive material 13 to ensure that the source and drain electrodes of each transistor are independent of each other.
[0149] In step S400, please refer to Figure 16 Hydrogen is doped into the semiconductor layer 11 of the source / drain contact region using a plasma processing technology containing hydrogen ions, a solution process containing hydrogen ions, or a thin film growth process containing hydrogen ions.
[0150] Here, Figure 17 The arrow in the image indicates fluoride ion implantation.
[0151] In some examples, performing a hydrogen ion implantation process on the semiconductor layer 11 of the source / drain contact region includes: doping the semiconductor layer 11 of the source / drain contact region with hydrogen using a hydrogen ion-containing plasma treatment (e.g., N2 and H2) process, a hydrogen ion-containing solution process, or a hydrogen ion-containing thin film growth process.
[0152] In some examples, please refer to Figure 17 , Figure 17 The arrows in the diagram indicate the injection directions of fluoride ions and hydrogen ions, respectively.
[0153] In the embodiments of this disclosure, during the fabrication process of semiconductor devices, especially during the fabrication process of three-dimensional dynamic random access memory with IGZO as the channel layer, the characteristics of the device are controlled by directionally implanting fluorine ions and hydrogen ions in specific steps, thereby reducing the contact resistance between the channel and the source / drain and increasing the on-state current.
[0154] In step S500, please refer to Figure 18 This forms the source / drain electrode 15 that fills the second accommodating groove C2.
[0155] In some examples, forming the source / drain electrode 15 that fills the second accommodating trench C2 includes: forming an electrode material layer that fills the second hole K2 on the surface of the substrate 1 using an ALD process; etching the electrode material layer using a dry etching process, retaining the electrode material layer in the removed area of the second dielectric layer D2, to form the source / drain electrode 15.
[0156] In some examples, the material of the source / drain 15 may include, but is not limited to, metals. For example, the material of the source / drain 15 may be tungsten.
[0157] Please see Figure 17 This disclosure also provides a semiconductor device in some embodiments, including: a semiconductor layer 11, a gate dielectric layer 12, a gate electrode, and a source / drain electrode 15. The semiconductor layer 11 includes a channel region and a source / drain contact region. The channel region is doped with fluorine, and the source / drain contact region is doped with hydrogen. The gate dielectric layer 12 covers the channel region of the semiconductor layer 11. The gate electrode covers the gate dielectric layer 12. The source / drain electrode 15 is located on the side of the semiconductor layer 11 opposite to the gate dielectric layer 12 and covers the source / drain contact region of the semiconductor layer 11.
[0158] In this embodiment, the semiconductor layer 11 of the source / drain contact region is doped with hydrogen, which increases the carrier concentration within the semiconductor layer 11 of the source / drain contact region. This effectively improves the carrier concentration in the source / drain contact region, thereby reducing the contact resistance between the channel region and the source / drain contact region, increasing the on-state current, and thus improving the performance of the semiconductor device. Furthermore, in this embodiment, no additional contact layer is required between the semiconductor layer and the source / drain electrodes, simplifying the structure of the semiconductor device. In addition, the source / drain contact region of the channel layer 11 is doped with fluorine. Thus, fluorine ions can passivate oxygen vacancies in the channel region, giving the semiconductor layer 11 of the channel region good thermal stability, thereby also enabling adjustment of the threshold voltage.
[0159] In some embodiments, the semiconductor device further includes a stacked structure D.
[0160] For example, the stacked structure D includes multiple alternating layers of first dielectric layers D1 and multiple layers of second dielectric layers D2, a first hole K1 penetrating each of the first dielectric layers D1 and the second dielectric layers D2, a first receiving groove C1 located within the first dielectric layer D1 and surrounding the first hole K1, and second receiving grooves C2 located within the second dielectric layer D2 and respectively on opposite sides of the first hole K1. The source / drain electrodes 15 are located within the second receiving grooves C2. A semiconductor layer 11 covers the sidewalls and part of the top and bottom surfaces of the source / drain electrodes 15. A gate dielectric layer 12 is located within the first receiving grooves C1 and the first hole K1 and covers the surface of the semiconductor layer 11 facing away from the source / drain electrodes 15. The gate electrode is located on the surface of the gate dielectric layer 12 facing away from the semiconductor layer 11.
[0161] In some embodiments, the semiconductor device further includes an isolation layer 14 located within the first dielectric layer D1 and covering the exposed sidewalls of the semiconductor layer 11 and the gate dielectric layer 12. The isolation layer 14 is also located between adjacent source / drain electrodes 15 in the stacking direction of the first dielectric layer D1 and the second dielectric layer D2.
[0162] According to some embodiments, the semiconductor device further includes word lines located within a first hole K1. The word lines are correspondingly connected to gates exposed within the same first hole K1.
[0163] In some embodiments, the material of the semiconductor layer 11 includes a metal oxide semiconductor material. For example, the material of the semiconductor layer 11 may be indium gallium zinc oxide.
[0164] In some examples, the gate dielectric layer 12 includes an HK (high-K) dielectric layer or an aluminum oxide (Al2O3) layer. An HK dielectric layer refers to a dielectric layer having a high dielectric constant K, for example, greater than 3.9.
[0165] In some examples, the gate material includes metals. For example, the gate material is tungsten.
[0166] In some examples, the material of the source / drain 15 may include, but is not limited to, metals. For example, the material of the source / drain 15 may be tungsten.
[0167] In some embodiments, this disclosure provides an electronic device, which includes a semiconductor device manufactured by the method described in the foregoing embodiments, or the semiconductor device described in the foregoing embodiments.
[0168] In this embodiment, the electronic device adopts the structure described above. The electronic device includes a semiconductor device fabricated using the method described in the foregoing embodiments, or the semiconductor device described in the foregoing embodiments. This electronic device also possesses all the technical advantages of the semiconductor devices described in the foregoing embodiments, and will not be detailed here.
[0169] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0170] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: Forming a semiconductor layer; The semiconductor layer includes a channel region and a source / drain contact region; Fluorine ion implantation is performed on the semiconductor layer of the channel region; A gate dielectric layer covering the channel region and a gate covering the gate dielectric layer are formed; A hydrogen ion implantation process is performed on the semiconductor layer of the source / drain contact region; Form source / drain electrodes covering the source / drain contact area.
2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Before forming the semiconductor layer, the preparation method further includes: A stacked structure is formed, the stacked structure comprising multiple alternating layers of first dielectric layers and multiple layers of second dielectric layers; The stacked structure is etched to form the first hole; The first dielectric layer is etched based on the first hole to form a first receiving groove; Wherein, the formation of the semiconductor layer includes: A semiconductor material layer is deposited on the inner wall of the first receiving groove and the inner wall of the first hole; The stacked structure is etched to form second holes located on opposite sides of the first accommodating trench; the second holes expose the semiconductor material layer located at the bottom of the first accommodating trench; Based on the second hole, the semiconductor material layer is etched to form a plurality of semiconductor layers spaced apart; wherein, the channel region is located on the surface of the semiconductor layer facing the first hole; and the source / drain contact region is located on the surface of the semiconductor layer away from the first hole.
3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The process of performing fluorine ion implantation on the semiconductor layer of the channel region includes: Fluorine is doped into the semiconductor layer of the channel region using a plasma treatment process containing fluorine ions, a solution process containing fluorine ions, or a thin film growth process containing fluorine ions.
4. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The formation of the gate dielectric layer covering the channel region and the gate covering the gate dielectric layer includes: A gate dielectric layer covering the semiconductor layer is formed in the first receiving groove and the first hole, and a conductive material covering the gate dielectric layer and filling the first receiving groove and the first hole is formed. The conductive material in the first receiving groove constitutes the gate, and the conductive material in the first hole constitutes the word line connecting the plurality of gates.
5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The step of performing fluorine ion implantation on the semiconductor layer of the channel region is performed after the semiconductor material layer is deposited and before the gate dielectric layer is formed.
6. The method for fabricating a semiconductor device as described in claim 2, characterized in that, Before performing hydrogen ion implantation on the semiconductor layer of the source / drain contact region, the fabrication method further includes: An isolation layer is formed in the etched region of the semiconductor material layer based on the second hole; Based on the second hole, the second dielectric layer covering the semiconductor layer is removed to form a second receiving trench; the second receiving trench exposes the source / drain contact area; The process of forming a source / drain electrode covering the source / drain contact area includes: forming the source / drain electrode that fills the second accommodating groove.
7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The hydrogen ion implantation process performed on the semiconductor layer of the source / drain contact region includes: Hydrogen is doped into the semiconductor layer of the source / drain contact region using a hydrogen-ion-containing plasma processing process, a hydrogen-ion-containing solution process, or a hydrogen-ion-containing thin film growth process.
8. The method for fabricating a semiconductor device according to any one of claims 1 to 7, characterized in that, The semiconductor layer is made of metal oxide semiconductor material.
9. A semiconductor device, characterized in that, include: A semiconductor layer, the semiconductor layer including a channel region and a source / drain contact region; The channel region is doped with fluorine, and the source / drain contact region is doped with hydrogen. A gate dielectric layer that covers the semiconductor layer of the channel region; Gate, covering the gate dielectric layer; The source / drain electrodes are located on the side of the semiconductor layer opposite to the gate dielectric layer and cover the semiconductor layer of the source / drain contact area.
10. The semiconductor device as claimed in claim 9, characterized in that, Also includes: The stacked structure includes multiple layers of first dielectric layers and multiple layers of second dielectric layers stacked alternately, a first hole penetrating each of the first dielectric layers and the second dielectric layers, a first receiving groove located in the first dielectric layer and surrounding the first hole, and a second receiving groove located in the second dielectric layer and respectively located on opposite sides of the first hole. The source / drain electrodes are located within the second accommodating groove; The semiconductor layer covers the sidewalls, part of the top surface, and part of the bottom surface of the source / drain electrodes; The gate dielectric layer is located within the first accommodating groove and the first hole and covers the surface of the semiconductor layer away from the source / drain electrodes; The gate is located on the surface of the gate dielectric layer opposite to the semiconductor layer.
11. The semiconductor device as claimed in claim 10, characterized in that, Also includes: An isolation layer located within the first dielectric layer and covering the exposed sidewalls of the semiconductor layer and the gate dielectric layer; The isolation layer is also located between adjacent source / drain electrodes in the stacking direction of the first dielectric layer and the second dielectric layer.
12. The semiconductor device as claimed in claim 10, characterized in that, Also includes: The character line located within the first hole; The word lines are correspondingly connected to the gates exposed within the same first hole.
13. The semiconductor device according to any one of claims 9 to 12, characterized in that, The semiconductor layer is made of metal oxide semiconductor material.
14. An electronic device, characterized in that, include: A semiconductor device manufactured by the method of fabrication of a semiconductor device according to any one of claims 1 to 8, or a semiconductor device according to any one of claims 9 to 13.