Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

This disclosure discloses a semiconductor structure and its fabrication method. The fabrication method includes: depositing a thin film stacked structure on a substrate; forming a first hole in the thin film stacked structure, the first hole penetrating the thin film stacked structure along the stacking direction of the thin film stacked structure, and exposing the substrate at the bottom of the first hole; growing an epitaxial silicon pillar in the first hole; etching the thin film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through the center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half-pillar and a second half-pillar; forming a first isolation layer, the first isolation layer filling the first trench; forming a first channel region of a first type of doping on the sidewall of the first half-pillar away from the first trench, and forming a second channel region of a second type of doping on the sidewall of the second half-pillar away from the first trench, wherein one of the first type of doping and the second type of doping is N-type and the other is P-type; and forming a gate dielectric layer and a gate conductive layer on the surface of both the first channel region and the second channel region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the development of the semiconductor industry, achieving higher storage density in pursuit of maximum profit has become a crucial research topic for many semiconductor researchers and professionals. Currently, traditional DRAM uses a 1T1C structure for its memory cells, meaning one transistor corresponds to one capacitor. However, facing the increasing demand for storage capacity and the miniaturization of process dimensions, memory cells using capacitor structures are facing the challenge of process limitations. Summary of the Invention

[0003] A primary objective of this disclosure is to overcome at least one of the deficiencies of the prior art and to provide a method for fabricating a semiconductor structure capable of specifically realizing a 3D NOP type capacitor-less DRAM device.

[0004] Another primary objective of this disclosure is to overcome at least one of the deficiencies of the prior art described above and to provide a semiconductor structure.

[0005] To achieve the above objectives, the present disclosure adopts the following technical solution:

[0006] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a substrate; depositing a thin film stack structure on the substrate; forming a first hole in the thin film stack structure, the first hole penetrating the thin film stack structure along a stacking direction and exposing the substrate at the bottom of the first hole; growing an epitaxial silicon pillar in the first hole; etching the thin film stack structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through the center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half-pillar and a second half-pillar; forming a first isolation layer filling the first trench; forming a first channel region of a first type of doping on the sidewall of the first half-pillar away from the first trench, and forming a second channel region of a second type of doping on the sidewall of the second half-pillar away from the first trench, wherein one of the first type of doping and the second type of doping is N-type and the other is P-type; and forming a gate dielectric layer and a gate conductive layer on the surfaces of both the first channel region and the second channel region.

[0007] According to another aspect of this disclosure, a semiconductor structure is provided, including a substrate, a thin-film stacked structure, an epitaxial silicon pillar, and a first isolation layer; the thin-film stacked structure is disposed on the surface of the substrate, the thin-film stacked structure has a first hole exposing the substrate, the epitaxial silicon pillar is disposed in the first hole, the first isolation layer is disposed in a first trench, the first trench is formed along a first direction by removing a portion of the thin-film stacked structure and the epitaxial silicon pillar, and the first trench passes through the center of the epitaxial silicon pillar and divides the epitaxial silicon pillar into a first half-pillar and a second half-pillar; a first channel region of a first type of doping is disposed on the sidewall of the first half-pillar away from the first trench, and a second channel region of a second type of doping is disposed on the sidewall of the second half-pillar away from the first trench, wherein one of the first type of doping and the second type of doping is N-type, and the other is P-type; a gate dielectric layer and a gate conductive layer are disposed on the surface of both the first channel region and the second channel region.

[0008] As can be seen from the above technical solution, the advantages and positive effects of the semiconductor structure fabrication method and the semiconductor structure proposed in this disclosure are as follows:

[0009] This disclosure discloses a first hole exposing the substrate in a thin-film stacked structure, in which an epitaxial silicon pillar is grown. A first trench is formed along a first direction, passing through the center of the epitaxial silicon pillar and dividing it into a first half-pillar and a second half-pillar. Based on this, a first channel region of a first type of doping is formed on the sidewall of the first half-pillar away from the first trench, and a second channel region of a second type of doping is formed on the sidewall of the second half-pillar away from the first trench. A gate dielectric layer and a gate conductive layer are formed on the surfaces of both the first and second channel regions. Through the above design, the semiconductor structure fabrication method proposed in this disclosure can specifically realize the fabrication of 3D NOP type Capacitor-Less DRAM devices. The semiconductor structure fabricated by this method does not have a capacitor structure, thus the process flow is simpler and it is easier to achieve high storage density, filling the technological gap in the industry for 3D NOP type Capacitor-Less DRAM devices. Attached Figure Description

[0010] The various objectives, features, and advantages of this disclosure will become more apparent from the following detailed description of preferred embodiments of the disclosure taken in conjunction with the accompanying drawings. The drawings are merely illustrative illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, the same reference numerals always denote the same or similar parts. Wherein:

[0011] Figure 1 This is a process flow diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0012] Figures 2 to 63 They are in Figure 1 The diagram shows the stacked structure of the semiconductor structure from different perspectives during several steps in the fabrication method of the semiconductor structure.

[0013] Figures 64 to 66 These are schematic diagrams of the stacked structure of the semiconductor structure in several steps of a method for fabricating a semiconductor structure according to another exemplary embodiment. Detailed Implementation

[0014] Typical embodiments embodying the features and advantages of this disclosure will be described in detail in the following description. It should be understood that this disclosure can have various variations in different embodiments without departing from the scope of this disclosure, and the descriptions and drawings therein are illustrative in nature and not intended to limit this disclosure.

[0015] In the following description of various exemplary embodiments of this disclosure, reference is made to the accompanying drawings, which form part of this disclosure, and which illustrate by way of example different exemplary structures, systems, and steps that can implement various aspects of this disclosure. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of this disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of this disclosure, these terms are used herein only for convenience, such as the orientation according to the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this disclosure.

[0016] See Figure 1 The illustration represents a process flow diagram of the semiconductor structure fabrication method proposed in this disclosure. In this exemplary embodiment, the semiconductor structure fabrication method proposed in this disclosure is described using a 3D NOP type Capacitor-Less DRAM device as an example. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below to apply the relevant designs of this disclosure to other types of semiconductor structures, and these changes remain within the scope of the principles of the semiconductor structure fabrication method proposed in this disclosure.

[0017] like Figure 1 As shown, in one embodiment of this disclosure, the method for fabricating a semiconductor structure proposed in this disclosure includes:

[0018] Step S1: Provide a substrate 100 and deposit a thin film stacked structure 200 on the substrate 100;

[0019] Step S2: A first hole V1 is formed in the thin film stacked structure 200. The first hole V1 penetrates the thin film stacked structure 200 along the stacking direction of the thin film stacked structure 200, and the bottom of the first hole V1 exposes the substrate 100.

[0020] Step S3: Grow epitaxial silicon pillars 110 in the first hole V1;

[0021] Step S4: Etch the thin film stack structure 200 and the epitaxial silicon pillar 110 along the first direction X to form a first trench G1. The first trench G1 passes through the center of the epitaxial silicon pillar 110 and divides the epitaxial silicon pillar 110 into a first half pillar 111 and a second half pillar 112.

[0022] Step S5: Form a first isolation layer 300, and fill the first trench G1 with the first isolation layer 300;

[0023] Step S6: A first channel region A of the first type of doping is formed on the sidewall of the first half-pillar 111 away from the first trench G1, and a second channel region B of the second type of doping is formed on the sidewall of the second half-pillar 112 away from the first trench G1. One of the first type of doping and the second type of doping is N-type, and the other is P-type.

[0024] Step S7: A gate dielectric layer and a gate conductive layer 430 are formed on the surfaces of both the first channel region A and the second channel region B.

[0025] Through the above design, the semiconductor structure fabrication method proposed in this disclosure can specifically realize the fabrication of 3D NOP type Capacitor-Less DRAM devices. Since the semiconductor structure fabricated by this method does not have a capacitor structure, the process flow is simpler and it is easier to achieve a high storage density, filling the technological gap in the industry for 3D NOP type Capacitor-Less DRAM devices.

[0026] See also Figures 2 to 63 , Figures 2 to 63 Representatively shown in Figure 1 The illustrated method for fabricating a semiconductor structure shows schematic diagrams of the stacked structure of the semiconductor structure from different perspectives during several steps. Specifically, Figure 2 , Figure 4 , Figure 6 ... Figure 62 The cross-sectional views of the semiconductor structure along the first direction X are shown representatively for each step. Figure 3 , Figure 5 , Figure 7 ... Figure 63The accompanying drawings show representative cross-sectional views of the semiconductor structure along the second direction Y in each step, where the first direction X is not parallel to the second direction Y. The following will, in conjunction with the above drawings, provide a detailed description of the specific processes, materials, and sequence of each major process step in the semiconductor structure fabrication method proposed in this disclosure.

[0027] like Figure 4 and Figure 5 As shown, in one embodiment of this disclosure, for step S2, the step of "forming a first hole V1 in the thin film stack structure 200" may specifically include: forming a patterned mask layer 800 (not shown in the figure) with a hole pattern on the thin film stack structure 200, and etching the thin film stack structure 200 along the hole pattern until the substrate 100 is exposed to form the first hole V1.

[0028] like Figure 6 and Figure 7 As shown, in one embodiment of this disclosure, for step S3, the step of "growing epitaxial silicon pillar 110 in the first hole V1" may specifically include: in the first hole V1, starting from the surface of the substrate 100 exposed by the first hole V1, growing epitaxial silicon pillar 110 by selective epitaxial growth until the top surface of the epitaxial silicon pillar 110 is not lower than the top surface of the patterned mask layer 800.

[0029] like Figure 9 As shown, in one embodiment of this disclosure, the width of the first trench G1 in the second direction Y accounts for 30% to 90% of the maximum width of the epitaxial silicon pillar 110 in the second direction Y, for example, 30%, 45%, 65%, 90%, etc. In some embodiments, the width of the first trench G1 in the second direction Y may also account for less than 30% or more than 90% of the maximum width of the epitaxial silicon pillar 110 in the second direction Y, for example, 28%, 91%, etc., and is not limited thereto.

[0030] like Figure 1 and Figure 2 As shown, in one embodiment of this disclosure, step S1, "depositing a thin film stacked structure 200 on the substrate 100," may specifically include: sequentially depositing a first insulating layer 210, a sacrificial layer 220, a second insulating layer 230, and a mask covering layer 240 on the substrate 100. The thickness of the sacrificial layer 220 may account for 50% to 90% of the total thickness of the thin film stacked structure 200, for example, 50%, 60%, 75%, 90%, etc. In some embodiments, the thickness of the sacrificial layer 220 may account for less than 50% or more than 90% of the total thickness of the thin film stacked structure 200, for example, 48%, 91%, etc., and is not limited thereto.

[0031] like Figure 14 and Figure 15 As shown, in one embodiment of this disclosure, for step S6, after the step of "forming the first isolation layer 300", it may further include: forming a first opening O1 in the thin film stack structure 200 on the first side of the first isolation layer 300, wherein the first opening O1 exposes at least a portion of the sacrificial layer 220.

[0032] like Figure 16 and Figure 17 As shown, in one embodiment of this disclosure, for step S6, after the step of "forming the first opening O1", the following step may be included: removing the sacrificial layer 220 of the first isolation layer 300 facing the first opening O1 by wet etching along the first opening O1, so as to expose the sidewall of the first half pillar 111 away from the first trench G1.

[0033] like Figures 18 to 21 As shown, in one embodiment of this disclosure, for step S6, the step of "forming a first channel region A of the first type of doping on the sidewall of the first half-pillar 111 away from the first trench G1" may specifically include: after the step of "exposing the sidewall of the first half-pillar 111 away from the first trench G1", selectively removing part of the first half-pillar 111 by wet etching to form a first notch O2 on the sidewall of the first half-pillar 111 away from the first trench G1, and forming a first channel region A of the first type of doping at the first notch O2 by selective epitaxial growth and in-situ doping.

[0034] like Figure 22 and Figure 23 As shown, in one embodiment of this disclosure, for step S7, the gate dielectric layer may include a first gate dielectric layer 410 and a second gate dielectric layer 420. The step of "forming a gate dielectric layer in the first channel region A and the second channel region B" may specifically include: forming a first gate dielectric layer 410 on the sidewall of the first channel region A to cover the surface of the first channel region A.

[0035] like Figure 24 and Figure 25 As shown, in one embodiment of this disclosure, for step S6, after the step of "forming a first gate dielectric layer 410 on the sidewall of the first channel region A to cover the surface of the first channel region A", it may further include: forming a second opening O3 in the thin film stack structure 200 on the second side of the first isolation layer 300, the second opening O3 exposing at least a portion of the sacrificial layer 220.

[0036] like Figure 26 and Figure 27As shown, in one embodiment of this disclosure, for step S6, after the step of "forming the second opening O3", the following step may be included: removing the sacrificial layer 220 of the first isolation layer 300 facing the second opening O3 by wet etching, so as to expose the sidewall of the second half pillar 112 away from the first trench G1.

[0037] like Figures 28 to 31 As shown, in one embodiment of this disclosure, for step S6, the step of "forming a second channel region B of the second type of doping on the sidewall of the second half-pillar 112 away from the first trench G1" may specifically include: after the step of "exposing the sidewall of the second half-pillar 112 away from the first trench G1", selectively removing part of the second half-pillar 112 by wet etching to form a second notch O4 on the sidewall of the second half-pillar 112 away from the first trench G1, and forming a second channel region B of the first type of doping at the second notch O4 by selective epitaxial growth and in-situ doping.

[0038] like Figure 32 and Figure 33 As shown, in one embodiment of this disclosure, for step S7, the gate dielectric layer may include a first gate dielectric layer 410 and a second gate dielectric layer 420. The step of "forming a gate dielectric layer in the first channel region A and the second channel region B" may specifically include: forming a second gate dielectric layer 420 on the sidewall of the second channel region B to cover the surface of the second channel region B.

[0039] like Figure 34 and Figure 35 As shown, in one embodiment of this disclosure, for step S7, the step of "forming a gate dielectric layer and a gate conductive layer 430 on the surface of the first channel region A and the second channel region B" may specifically include: after the step of "forming a second gate dielectric layer 420 on the sidewall of the second channel region B to cover the surface of the second channel region B", simultaneously filling the gate conductive layer 430 along the first opening O1 and the second opening O3 to the location where the sacrificial layer 220 is removed to cover the first gate dielectric layer 410 and the second gate dielectric layer 420.

[0040] In one embodiment of this disclosure, after step S7, the disclosure may further include the following steps:

[0041] A second trench is formed on the side of the first trench G1 facing the first opening O1, and a third trench is formed on the side of the first trench G1 facing the second opening O3. Both the second and third trenches are parallel to the first trench G1 and extend in the first direction X. The bottom of the second and third trenches exposes the first insulating layer 210 to isolate the gate conductive layer 430. The portion of the gate conductive layer 430 near the first channel region A is used as the first gate electrode, and the portion of the gate conductive layer 430 near the second channel region B is used as the second gate electrode. The second and third isolation layers are filled in the second and third trenches, respectively.

[0042] Based on the above design, the following will describe several key process steps in the method for fabricating the semiconductor structure proposed in this disclosure.

[0043] like Figure 2 and Figure 3 As shown, cross-sectional views of the semiconductor structure from different perspectives are presented representatively in step S1. In this step, the semiconductor structure includes a substrate 100 and a thin-film stacked structure 200, and the thin-film stacked structure 200 includes a first insulating layer 210, a sacrificial layer 220, a second insulating layer 230, and a mask cover layer 240. The substrate 100 can be a silicon substrate, i.e., the material of the substrate 100 includes silicon (Si). The first insulating layer 210 is deposited on the surface of the substrate 100, the sacrificial layer 220 is deposited on the surface of the first insulating layer 210, the second insulating layer 230 is deposited on the surface of the sacrificial layer 220, and the mask cover layer 240 is deposited on the surface of the second insulating layer 230.

[0044] In one embodiment of this disclosure, the material of the first insulating layer 210 may include silicon oxide (SiO2). In some embodiments, the material of the first insulating layer 210 may also include other materials, such as other oxides, and is not limited thereto.

[0045] In one embodiment of this disclosure, the material of the second insulating layer 230 may include silicon oxide. In some embodiments, the material of the second insulating layer 230 may also include other materials, such as other oxides, and is not limited thereto. Furthermore, the material of the second insulating layer 230 and the first insulating layer 210 may be, but is not limited to, the same.

[0046] In one embodiment of this disclosure, the material of the sacrificial layer 220 may include silicon nitride (Si3N4).

[0047] In one embodiment of this disclosure, the material of the mask covering layer 240 may include silicon oxynitride (SiON).

[0048] like Figure 4 and Figure 5The diagram shows cross-sectional views of the semiconductor structure from different perspectives during step S2. In this step, the semiconductor structure includes a substrate 100 and a thin-film stacked structure 200, with the thin-film stacked structure 200 having a first hole V1. The first hole V1 extends from the upper surface of the thin-film stacked structure 200 (i.e., the upper surface of the mask layer 240) to the lower surface of the thin-film stacked structure 200 (i.e., the lower surface of the first insulating layer 210). In other words, the thin-film stacked structure 200 is penetrated by the first hole V1 in the thickness direction, and the portion of the upper surface of the substrate 100 corresponding to the first hole V1 is exposed at the bottom of the first hole V1.

[0049] like Figure 6 and Figure 7 The diagram shows cross-sectional views of the semiconductor structure from different perspectives during step S3. In this step, the semiconductor structure includes a substrate 100, a thin-film stack structure 200, and epitaxial silicon pillars 110. The epitaxial silicon pillars 110 grow from the upper surface of the substrate 100 exposed to the first hole V1 and fill the first hole V1. Furthermore, the growth height of the epitaxial silicon pillars 110 can be approximately equal to the depth of the first hole V1, meaning the upper surface of the epitaxial silicon pillars 110 can be approximately flush with the top opening of the first hole V1 (i.e., the upper surface of the thin-film stack structure 200, and also the upper surface of the mask capping layer 240). In some embodiments, the growth height of the epitaxial silicon pillars 110 can also be slightly greater than the depth of the first hole V1, for example, extending beyond the top opening of the first hole V1, but this is not a limitation.

[0050] like Figure 8 and Figure 9 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in step S4. In this step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, an epitaxial silicon pillar 110, and a first photoresist layer PR1. The first photoresist layer PR1 covers the upper surface of the thin-film stacked structure 200 (i.e., the upper surface of the mask layer 240) and the upper surface of the epitaxial silicon pillar 110, and the first photoresist layer PR1 is patterned to form photoresist openings. Etching is performed using the photoresist openings of the first photoresist layer PR1 to remove the portion of the epitaxial silicon pillar 110 not covered by the first photoresist layer PR1, thereby forming a first trench G1 in the epitaxial silicon pillar 110. The first trench G1 passes through the center of the epitaxial silicon pillar 110, dividing the epitaxial silicon pillar 110 into a first half-pillar 111 and a second half-pillar 112.

[0051] In addition, after step S4, the following step may also be included: removing the remaining first photoresist layer PR1.

[0052] like Figure 10 and Figure 11As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in step S5. In this step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, and a first isolation layer 300. The first isolation layer 300 fills the first trench G1. Furthermore, the filling height of the first isolation layer 300 can be approximately equal to the depth of the first trench G1, meaning the upper surface of the first isolation layer 300 can be approximately flush with the top opening of the first trench G1 (i.e., the upper surfaces of the first half-pillar 111 and the second half-pillar, i.e., the upper surface of the thin-film stacked structure 200).

[0053] like Figure 12 and Figure 13 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin film stack structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, and a second photoresist layer PR2. The second photoresist layer PR2 covers the upper surface of the thin film stack structure 200 (i.e., the upper surface of the mask cover layer 240), the upper surfaces of the first half-pillar 111 and the second half-pillar 112, and the upper surface of the first isolation layer 300, and the second photoresist layer PR2 is patterned to form photoresist openings.

[0054] like Figure 14 and Figure 15 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin film stack structure 200, a first half-pillar 111, a second half-pillar 112, and a first insulating layer 300. This sub-step involves etching using the photoresist openings of the second photoresist layer PR2 to remove the portion of the thin film stack structure 200 not obscured by the second photoresist layer PR2, and the etching stops at the upper surface of the first insulating layer 210, thus forming a first opening O1 in the thin film stack structure 200.

[0055] In addition, after the above-mentioned sub-step of forming the first opening O1, the following step may also be included: removing the remaining second photoresist layer PR2.

[0056] like Figure 16 and Figure 17As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin-film stack structure 200, a first half-pillar 111, a second half-pillar 112, and a first isolation layer 300. This sub-step involves removing the sacrificial layer 220 of the first isolation layer 300 along the first opening O1 to expose the sidewall of the first half-pillar 111 away from the first trench G1.

[0057] In one embodiment of this disclosure, the above sub-steps may specifically employ a wet etching process to remove the sacrificial layer 220.

[0058] like Figure 18 and Figure 19 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin-film stack structure 200, a first half-pillar 111, a second half-pillar 112, and a first isolation layer 300. This sub-step involves selectively removing a portion of the first half-pillar 111 after exposing the sidewalls of the first half-pillar 111 away from the first trench G1 to form a first notch O2 on the sidewalls of the first half-pillar 111 away from the first trench G1.

[0059] In one embodiment of this disclosure, the selective removal of the first half-pillar 111 can be achieved by specifically employing a wet etching process in the above sub-steps.

[0060] See Figures 64 to 66 As shown, Figures 64 to 66 These are schematic diagrams illustrating the stacked structure of the semiconductor structure in several steps of a method for fabricating a semiconductor structure according to another exemplary embodiment.

[0061] like Figure 64 and Figure 65 As shown, in another embodiment of this disclosure, for a sub-step in step S6, after exposing the sidewall of the first half-pillar 111 away from the first groove G1, a portion of the first half-pillar 111 can be selectively removed to form a first notch O2 on the sidewall of the first half-pillar 111 away from the first groove G1. The first notch O2 may not penetrate the first half-pillar 111 in the second direction Y; that is, the first notch O2 forms a structure similar to a "groove" on the first half-pillar 111, rather than... Figure 19 The illustrated embodiment shows a structure similar to a "through groove".

[0062] like Figure 20 and Figure 21As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin film stack structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, and a first channel region A. Specifically, this sub-step involves forming the first channel region A, which is doped with a first type, at the first notch O2.

[0063] In one embodiment of this disclosure, the first channel region A can be formed by selective epitaxial growth and in-situ doping in the above sub-steps.

[0064] like Figure 22 and Figure 23 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S7. In this sub-step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, and a first gate dielectric layer 410. Specifically, this sub-step involves forming the first gate dielectric layer 410 on the sidewall of the first channel region A, covering the surface of the first channel region A.

[0065] In one embodiment of this disclosure, the material of the first gate dielectric layer 410 may include silicon oxide. In some embodiments, the material of the first gate dielectric layer 410 may also include other materials, such as other oxides, and is not limited thereto.

[0066] like Figure 24 and Figure 25 The diagram shows cross-sectional views of the semiconductor structure from different perspectives during a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first insulating layer 300, and a third photoresist layer PR3. The third photoresist layer PR3 covers the upper surface of the thin-film stacked structure 200 (i.e., the upper surface of the mask layer 240), the upper surfaces of the first half-pillar 111 and the second half-pillar 112, and the upper surface of the first insulating layer 300. The second photoresist layer PR2 is patterned to form photoresist openings. Etching is performed using the photoresist openings of the third photoresist layer PR3 to remove the portion of the thin-film stacked structure 200 not covered by the third photoresist layer PR3. The etching stops at the upper surface of the first insulating layer 210, thus forming a second opening O3 in the thin-film stacked structure 200.

[0067] In addition, after the above-mentioned sub-step of forming the second opening O3, the following step may also be included: removing the remaining third photoresist layer PR3.

[0068] like Figure 26 and Figure 27 The diagram shows cross-sectional views of the semiconductor structure from different perspectives during a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin-film stack structure 200, a first half-pillar 111, a second half-pillar 112, and a first isolation layer 300. This sub-step involves removing the sacrificial layer 220 of the first isolation layer 300 along the second opening O3 to expose the sidewalls of the second half-pillar 112 away from the first trench G1. At this point, the sacrificial layers 220 on both sides of the first isolation layer 300 are completely removed.

[0069] In one embodiment of this disclosure, the above sub-steps may specifically employ a wet etching process to remove the sacrificial layer 220.

[0070] like Figure 28 and Figure 29 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin-film stack structure 200, a first half-pillar 111, a second half-pillar 112, and a first isolation layer 300. This sub-step involves selectively removing a portion of the second half-pillar 112 after exposing the sidewalls of the second half-pillar 112 away from the first trench G1 to form a second notch O4 on the sidewalls of the second half-pillar 112 away from the first trench G1.

[0071] In one embodiment of this disclosure, the selective removal of the second half-pillar 112 can be achieved by specifically employing a wet etching process in the above sub-steps.

[0072] See Figure 66 As shown, Figure 66 This is a schematic diagram of the stacked structure of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to another exemplary embodiment.

[0073] like Figure 66 As shown, in another embodiment of this disclosure, for a sub-step in step S6, after exposing the sidewall of the second half-pillar 112 away from the first groove G1, a portion of the second half-pillar 112 can be selectively removed to form a second notch O4 on the sidewall of the second half-pillar 112 away from the first groove G1. The second notch O4 may not penetrate the second half-pillar 112 in the second direction Y; that is, the second notch O4 forms a structure similar to a "groove" on the second half-pillar 112, rather than... Figure 29 The illustrated embodiment shows a structure similar to a "through groove".

[0074] like Figure 30 and Figure 31As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S6. In this sub-step, the semiconductor structure includes a substrate 100, a thin film stack structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, and a second channel region B. Specifically, this sub-step involves forming the second channel region B, which is doped with a second type, at the second notch O4.

[0075] In one embodiment of this disclosure, the second channel region B can be formed by selective epitaxial growth and in-situ doping in the above sub-steps.

[0076] like Figure 32 and Figure 33 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S7. In this sub-step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, a second channel region B, a first gate dielectric layer 410, and a second gate dielectric layer 420. Specifically, this sub-step involves forming the second gate dielectric layer 420 on the sidewall of the second channel region B, covering the surface of the second channel region B.

[0077] In one embodiment of this disclosure, the material of the second gate dielectric layer 420 may include silicon oxide. In some embodiments, the material of the second gate dielectric layer 420 may also include other materials, such as other oxides, and is not limited thereto. Furthermore, the material of the second gate dielectric layer 420 may be, but is not limited to, the same as, the material of the first gate dielectric layer 410.

[0078] like Figure 34 and Figure 35 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in a sub-step of step S7. In this sub-step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, a second channel region B, a first gate dielectric layer 410, a second gate dielectric layer 420, and a gate conductive layer 430. This sub-step occurs after the step of forming the second gate dielectric layer 420 covering the surface of the second channel region B on the sidewalls of the second channel region B, simultaneously filling the gate conductive layer 430 along the first opening O1 and the second opening O3 towards the location where the sacrificial layer 220 is removed, and the gate conductive layer 430 covers the first gate dielectric layer 410 and the second gate dielectric layer 420.

[0079] In one embodiment of this disclosure, the material of the gate conductive layer 430 may include tungsten (W).

[0080] like Figure 36 and Figure 37 As shown, cross-sectional views of the semiconductor structure from different perspectives are presented, respectively. In this step, based on step S7, a portion of the gate conductive layer 430 filling the first opening O1 and the second opening O3 is removed from the semiconductor structure, exposing a portion of the upper surface of the first insulating layer 210 corresponding to the first opening O1 and the second opening O3.

[0081] like Figure 38 and Figure 39 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, after the removal of a portion of the gate conductive layer 430, a third insulating layer 500 is applied to the upper surface of the thin film stack structure 200, the upper surfaces of the first half-pillar 111 and the second half-pillar 112, and the upper surface of the first isolation layer 300. Furthermore, the third insulating layer 500 fills the spaces left by the removal of the portion of the gate conductive layer 430, including the first opening O1, the second opening O3, and the space where the portion of the sacrificial layer 220 was originally formed.

[0082] In one embodiment of this disclosure, the material of the third insulating layer 500 may include silicon oxide. In some embodiments, the material of the third insulating layer 500 may also include other materials, such as other oxides, and is not limited thereto.

[0083] like Figure 40 and Figure 41 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, after the formation of the third insulating layer 500, the third insulating layer 500 covering the surface of the thin film stack structure 200 is etched back to remove it, and the thin film stack structure 200 is partially removed, specifically the top portion of the mask cover layer 240 is removed. The remaining third insulating layer 500 is located in the first opening O1 and the second opening O3, and the upper surface of the remaining third insulating layer 500 is substantially flush with the upper surface of the remaining mask cover layer 240.

[0084] like Figure 42 and Figure 43 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, a second channel region B, a gate dielectric layer, a gate conductive layer 430, a third insulating layer 500, and a silicon layer 600. Specifically, this step involves covering the silicon layer 600 onto the upper surface of the remaining mask cover layer 240 and the upper surface of the remaining third insulating layer 500.

[0085] like Figure 44 and Figure 45 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, a second channel region B, a gate dielectric layer, a gate conductive layer 430, a third insulating layer 500, a silicon layer 600, and a SOC layer 700. Specifically, this step involves covering the upper surface of the silicon layer 600 with the SOC layer 700.

[0086] like Figure 46 and Figure 47 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, a second channel region B, a gate dielectric layer, a gate conductive layer 430, a third insulating layer 500, a silicon layer 600, a SOC layer 700, and a fourth photoresist layer PR4. Specifically, this step involves covering the upper surface of the SOC layer 700 with the fourth photoresist layer PR4.

[0087] like Figure 48 and Figure 49 As shown, cross-sectional views of the semiconductor structure from different perspectives are presented representatively in another step. In this step, after covering the fourth photoresist layer PR4, the fourth photoresist layer PR4 is patterned to form photoresist openings. Etching is performed using the photoresist openings of the fourth photoresist layer PR4 to remove the portion of the SOC layer 700 not covered by the fourth photoresist layer PR4. The etching stops at the upper surface of the silicon layer 600, thus forming a third opening O5 in the silicon layer 600.

[0088] In addition, after the above-mentioned sub-step of forming the third opening O5, the following step may also be included: removing the remaining fourth photoresist layer PR4.

[0089] like Figure 50 and Figure 51 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, a second channel region B, a gate dielectric layer, a gate conductive layer 430, a third insulating layer 500, a silicon layer 600, a SOC layer 700, and a patterned mask layer 800. Specifically, this step involves covering the upper surface of the SOC layer 700 and the upper surface of the silicon layer 600 exposed to the third opening O5 with the patterned mask layer 800, and the patterned mask layer 800 filling the third opening O5.

[0090] like Figure 52 and Figure 53 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, after the step of covering the patterned mask layer 800, the patterned mask layer 800 covering the upper surface of the SOC layer 700 is removed, and the remaining patterned mask layer 800 fills the third opening O5. Furthermore, the upper surface of the remaining patterned mask layer 800 may be approximately flush with or slightly higher than the upper surface of the SOC layer 700.

[0091] like Figure 54 and Figure 55 As shown, cross-sectional views of the semiconductor structure from different perspectives are presented, respectively, in another step. In this step, after the step of removing the patterned mask layer 800 covering the upper surface of the SOC layer 700, the remaining SOC layer 700 is removed, leaving the remaining patterned mask layer 800.

[0092] like Figure 56 and Figure 57 As shown, these represent cross-sectional views of the semiconductor structure from different perspectives during another step. In this step, after removing the remaining SOC layer 700, the silicon layer 600 not covered by the patterned mask layer 800 is etched away using the remaining patterned mask layer 800 as a mask, and the etching stops at the upper surface of the remaining mask capping layer 240. At this point, the remaining silicon layer 600 defines one end of the source / drain, and the epitaxial silicon pillar 110 located below the first channel region A and the second channel region B defines the other end of the source / drain.

[0093] like Figure 58 and Figure 59 As shown, these represent cross-sectional views of the semiconductor structure from different perspectives during another step. In this step, after defining one end of the source / drain, the remaining patterned mask layer 800 is removed.

[0094] like Figure 60 and Figure 61 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, the semiconductor structure includes a substrate 100, a thin-film stacked structure 200, a first half-pillar 111, a second half-pillar 112, a first isolation layer 300, a first channel region A, a second channel region B, a gate dielectric layer, a gate conductive layer 430, a third insulating layer 500, a silicon layer 600, and a fourth insulating layer 900. Specifically, this step involves covering the upper surface of the remaining mask cover layer 240, the upper surface of the third insulating layer 500, and the upper surface of the remaining silicon layer 600 with the fourth insulating layer 900.

[0095] In one embodiment of this disclosure, the material of the fourth insulating layer 900 may include silicon oxide. In some embodiments, the material of the fourth insulating layer 900 may also include other materials, such as other oxides, and is not limited thereto.

[0096] like Figure 62 and Figure 63 As shown, cross-sectional views of the semiconductor structure from different perspectives are representatively illustrated in another step. In this step, after the step of covering the fourth insulating layer 900, a portion of the fourth insulating layer 900 is removed, exposing the upper surface of the remaining silicon layer 600 (i.e., one end of the source / drain).

[0097] It should be noted that the semiconductor structure fabrication methods shown in the accompanying drawings and described in this specification are merely a few examples of many fabrication methods that can employ the principles of this disclosure. It should be clearly understood that the principles of this disclosure are by no means limited to any detail or step of the semiconductor structure fabrication methods shown in the accompanying drawings or described in this specification.

[0098] Based on the detailed description of several exemplary embodiments of the semiconductor structure fabrication method proposed in this disclosure above, an exemplary embodiment of the semiconductor structure proposed in this disclosure will be described below.

[0099] like Figure 62 and Figure 63 As shown, in one embodiment of this disclosure, the semiconductor structure proposed in this disclosure may include a substrate 100, a thin-film stacked structure 200, an epitaxial silicon pillar 110, and a first isolation layer 300. Specifically, the thin-film stacked structure 200 is disposed on the surface of the substrate 100, and a first hole V1 is provided in the thin-film stacked structure 200 to expose the substrate 100. The epitaxial silicon pillar 110 is disposed in the first hole V1. The first isolation layer 300 is disposed in a first trench G1, and the first isolation layer 300 fills the first trench G1. The first trench G1 is formed along a first direction X by removing a portion of the thin-film stacked structure 200 and the epitaxial silicon pillar 110, and the first trench G1 passes through the center of the epitaxial silicon pillar 110 and divides the epitaxial silicon pillar 110 into a first half-pillar 111 and a second half-pillar 112. A first channel region A of a first type of doping is provided on the sidewall of the first half-pillar 111 away from the first trench G1. A second channel region B of a second type of doping is provided on the sidewall of the second half-pillar 112 away from the first trench G1. One of the first type of doping and the second type of doping is N-type, and the other is P-type. A gate dielectric layer and a gate conductive layer 430 are both disposed on the surface of the first channel region A and the second channel region B.

[0100] In one embodiment of this disclosure, the gate dielectric layer includes a first gate dielectric layer 410 and a second gate dielectric layer 420, and the gate conductive layer 430 includes a first gate conductive layer and a second gate conductive layer. The first gate dielectric layer 410 and the first gate conductive layer are located on the side of the first channel region A away from the first trench G1, and the second gate dielectric layer 420 and the second gate conductive layer are located on the side of the second channel region B away from the first trench G1, and the first gate conductive layer and the second gate conductive layer are isolated from each other.

[0101] It should be noted that the semiconductor structures shown in the accompanying drawings and described in this specification are merely a few examples of many semiconductor structures capable of employing the principles of this disclosure. It should be clearly understood that the principles of this disclosure are by no means limited to any detail or component of the semiconductor structures shown in the accompanying drawings or described in this specification.

[0102] In summary, this disclosure provides a first hole V1 in the thin film stacked structure 200 to expose the substrate 100, grows an epitaxial silicon pillar 110 in the first hole V1, and provides a first trench G1 along the first direction X. The first trench G1 passes through the center of the epitaxial silicon pillar 110, dividing it into a first half-pillar 111 and a second half-pillar 112. Based on this, this disclosure provides a first channel region A of the first type of doping formed on the sidewall of the first half-pillar 111 away from the first trench G1, and a second channel region B of the second type of doping formed on the sidewall of the second half-pillar 112 away from the first trench G1. Furthermore, a gate dielectric layer and a gate conductive layer 430 are formed on the surfaces of both the first channel region A and the second channel region B. Through the above design, the semiconductor structure fabrication method proposed in this disclosure can specifically realize the fabrication of 3D NOP type Capacitor-Less DRAM devices. Since the semiconductor structure fabricated by this method does not have a capacitor structure, the process flow is simpler and it is easier to achieve a high storage density, filling the technological gap in the industry for 3D NOP type Capacitor-Less DRAM devices.

[0103] Although the semiconductor structure and method of fabrication of the semiconductor structure have been described according to different specific embodiments, those skilled in the art will recognize that modifications may be made to the implementation of the disclosure within the spirit and scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, comprising: A substrate is provided, on which a thin film stack structure is deposited; A first hole is formed in the thin film stack structure, the first hole penetrates the thin film stack structure along the stacking direction of the thin film stack structure, and the bottom of the first hole exposes the substrate; An epitaxial silicon pillar is grown in the first cavity; The thin film stack structure and the epitaxial silicon pillar are etched along a first direction to form a first trench, the first trench passing through the center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; A first isolation layer is formed, and the first isolation layer fills the first trench; A first channel region of the first type of doping is formed on the sidewall of the first half-pillar away from the first trench, and a second channel region of the second type of doping is formed on the sidewall of the second half-pillar away from the first trench. One of the first type of doping and the second type of doping is N-type, and the other is P-type. A gate dielectric layer and a gate conductive layer are formed on the surfaces of both the first channel region and the second channel region.

2. The method for fabricating a semiconductor structure as described in claim 1, wherein, The step of forming the first hole in the thin film stack structure includes: A patterned mask layer with a hole pattern is formed on the thin film stack structure, and the thin film stack structure is etched along the hole pattern until the substrate is exposed to form the first hole.

3. The method for fabricating a semiconductor structure as described in claim 2, wherein, The step of growing an epitaxial silicon pillar in the first cavity includes: In the first hole, starting from the substrate surface exposed by the first hole, an epitaxial silicon pillar is grown by selective epitaxial growth until the top surface of the epitaxial silicon pillar is not lower than the top surface of the patterned mask layer.

4. The method for fabricating a semiconductor structure as described in claim 1, wherein, The width of the first trench accounts for 30% to 90% of the maximum width of the epitaxial silicon pillar in the second direction.

5. The method for fabricating a semiconductor structure as described in claim 1, wherein, The step of depositing a thin film stack structure on the substrate includes: A first insulating layer, a sacrificial layer, a second insulating layer, and a masking layer are sequentially deposited on the substrate, wherein the thickness of the sacrificial layer accounts for 50% to 90% of the thickness of the thin film stack structure.

6. The method for fabricating a semiconductor structure as described in claim 5, wherein, After the step of forming the first isolation layer, a first opening is formed in the thin film stack structure on the first side of the first isolation layer, and the first opening exposes at least a portion of the sacrificial layer.

7. The method for fabricating a semiconductor structure as described in claim 6, wherein, Following the step of forming the first opening, the following steps are also included: The sacrificial layer of the first isolation layer facing the first opening is removed by wet etching along the first opening to expose the sidewall of the first half-pillar away from the first trench.

8. The method for fabricating a semiconductor structure as described in claim 7, wherein, The formation of a first channel region of the first type of doping on the sidewall of the first half-pillar away from the first trench includes: After the step of exposing the sidewall of the first half-pillar away from the first trench, a portion of the first half-pillar is selectively removed by wet etching to form a first notch on the sidewall of the first half-pillar away from the first trench, and the first channel region of the first type is formed at the first notch by selective epitaxial growth and in-situ doping.

9. The method for fabricating a semiconductor structure as described in claim 8, wherein, The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, and the step of forming the gate dielectric layer and the gate conductive layer on the surfaces of the first channel region and the second channel region includes: A first gate dielectric layer is formed on the sidewall of the first channel region to cover the surface of the first channel region.

10. The method for fabricating a semiconductor structure as described in claim 9, wherein, After forming a first gate dielectric layer on the sidewall of the first channel region to cover the surface of the first channel region, a second opening is formed in the thin film stack structure on the second side of the first isolation layer, and the second opening exposes at least a portion of the sacrificial layer.

11. The method for fabricating a semiconductor structure as described in claim 10, wherein, Following the step of forming the second opening, the following steps are also included: The sacrificial layer, with the first isolation layer facing the second opening, is removed by wet etching along the second opening to expose the sidewall of the second half-pillar away from the first trench.

12. The method for fabricating a semiconductor structure as described in claim 11, wherein, The step of forming a second type of doped second channel region on the sidewall of the second half-pillar away from the first trench includes: After the step of exposing the sidewall of the second half-pillar away from the first trench, a portion of the second half-pillar is selectively removed by wet etching to form a second notch on the sidewall of the second half-pillar away from the first trench. The second channel region of the second type is formed at the second notch by selective epitaxial growth and in-situ doping.

13. The method for fabricating a semiconductor structure as described in claim 12, wherein, The step of forming the gate dielectric layer and the gate conductive layer on the surfaces of the first channel region and the second channel region includes: A second gate dielectric layer is formed on the sidewall of the second channel region to cover the surface of the second channel region.

14. The method for fabricating a semiconductor structure as described in claim 13, wherein, The step of forming a gate dielectric layer and a gate conductive layer on the surfaces of the first channel region and the second channel region includes: After the step of forming a second gate dielectric layer covering the surface of the second channel region on the sidewall of the second channel region, the gate conductive layer is simultaneously filled along the first opening and the second opening toward the location where the sacrificial layer is removed, covering the first gate dielectric layer and the second gate dielectric layer.

15. The method for fabricating a semiconductor structure as described in claim 14, further comprising the following step after the step of forming the gate conductive layer: A second trench is formed on the side of the first trench facing the first opening, and a third trench is formed on the side of the first trench facing the second opening. Both the second trench and the third trench are parallel to the first trench and extend in the first direction. The bottom of the second trench and the third trench exposes the first insulating layer to isolate the gate conductive layer. A portion of the gate conductive layer near the first channel region is used as the first gate electrode, and a portion of the gate conductive layer near the second channel region is used as the second gate electrode. The second trench and the third trench are respectively filled with a second isolation layer and a third isolation layer.

16. A semiconductor structure comprising a substrate, a thin-film stacked structure, an epitaxial silicon pillar, and a first isolation layer; the thin-film stacked structure is disposed on the surface of the substrate, the thin-film stacked structure having a first hole exposing the substrate, the epitaxial silicon pillar being disposed in the first hole, the first isolation layer being disposed in a first trench, the first trench being formed along a first direction by removing a portion of the thin-film stacked structure and the epitaxial silicon pillar, and the first trench passing through the center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half-pillar and a second half-pillar; a first channel region of a first type of doping is disposed on the sidewall of the first half-pillar away from the first trench, and a second channel region of a second type of doping is disposed on the sidewall of the second half-pillar away from the first trench, wherein one of the first type of doping and the second type of doping is N-type and the other is P-type; a gate dielectric layer and a gate conductive layer are disposed on the surfaces of both the first channel region and the second channel region.

17. The semiconductor structure of claim 16, wherein, The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, and the gate conductive layer includes a first gate conductive layer and a second gate conductive layer. The first gate dielectric layer and the first gate conductive layer are located on the side of the first channel region away from the first trench, and the second gate dielectric layer and the second gate conductive layer are located on the side of the second channel region away from the first trench. The first gate conductive layer and the second gate conductive layer are isolated from each other.

Images