Semiconductor device including a memory cell array region and an interface region

Abstract

A semiconductor device is provided. The semiconductor device includes: a first memory cell array region and a second memory cell array region spaced apart from each other; a first interface region located between the first memory cell array region and the second memory cell array region; a first word line and a second word line crossing the first memory cell array region, the first interface region, and the second memory cell array region; a first back gate electrode located between the first word line and the second word line in the first memory cell array region and extending into the first interface region; and a first back gate dielectric layer. The first back gate dielectric layer includes a first portion located between the first word line and the first back gate electrode in the first memory cell array region and a second portion located between the second word line and the first back gate electrode.

Description

Technical Field

[0001] The example embodiments relate to a semiconductor device including a memory cell array region and an interface region located between the memory cell array region, and a method for forming the semiconductor device. Background Technology

[0002] Research is underway to reduce the size of the components that make up semiconductor devices and to improve the performance of semiconductor devices. For example, research is being conducted to reliably and stably fabricate components with reduced size, but as the size of the components decreases, the dispersion property of the semiconductor device deteriorates. Summary of the Invention

[0003] The example embodiment provides a semiconductor device that can improve integration.

[0004] An example embodiment provides a method for forming a semiconductor device.

[0005] According to an example embodiment, a semiconductor device includes: a first memory cell array region and a second memory cell array region, the first memory cell array region and the second memory cell array region being spaced apart from each other in a first horizontal direction; a first interface region, the first interface region being located between the first memory cell array region and the second memory cell array region; a first word line and a second word line, the first word line and the second word line spanning the first memory cell array region, the first interface region and the second memory cell array region, and being spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a first back gate electrode, the first back gate electrode being located between the first word line and the second word line in the first memory cell array region and extending into the first interface region; and a first back gate dielectric layer, the first back gate dielectric layer being located between the first word line and the second word line and spanning the first memory cell array region, wherein the first back gate dielectric layer includes a first portion and a second portion, the first portion being located between the first word line and the first back gate electrode in the first memory cell array region, and the second portion being located between the second word line and the first back gate electrode in the first memory cell array region.

[0006] According to an example embodiment, a semiconductor device includes: a first memory cell array region and a second memory cell array region, the first memory cell array region and the second memory cell array region being spaced apart from each other in a first horizontal direction; a first interface region located between the first memory cell array region and the second memory cell array region; and word lines spanning the first memory cell array region, the first interface region and the second memory cell array region, and being spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, wherein the word lines include first word lines and second word lines that are adjacent to each other, and the minimum distance between the first word lines and the second word lines in the first memory cell array region is greater than the minimum distance between the first word lines and the second word lines in the first interface region.

[0007] According to an example embodiment, a semiconductor device includes: a first structure including a first memory cell region; the first memory cell region including memory cells; and a second structure including a second memory cell region including peripheral circuitry, wherein the second structure overlaps perpendicularly with the first structure, wherein the first memory cell region includes: a first memory cell array region and a second memory cell array region, the first memory cell array region and the second memory cell array region being spaced apart from each other in a first horizontal direction; a first interface region located between the first memory cell array region and the second memory cell array region; and a first word line and a second word line, the first word line and the second word line crossing the first memory cell array region, the first interface region and the second memory cell array region, and being spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, wherein the minimum distance between the first word line and the second word line in the first memory cell array region is greater than the minimum distance between the first word line and the second word line in the first interface region. Attached Figure Description

[0008] The above and other aspects, features, and advantages of the present invention will become more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: Figure 1A , Figure 1B , Figure 2 and Figure 3 This is a diagram illustrating a semiconductor device according to an embodiment of the concept of the present invention; Figure 4 This is a perspective view conceptually illustrating an example of a semiconductor device according to an embodiment of the present invention; Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8 and Figure 9 This is a diagram illustrating an example of a semiconductor device according to an embodiment of the concept of the present invention; Figure 10 This is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the concept of the present invention; Figure 11 This is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the concept of the present invention; Figure 12A , Figure 12B and Figure 13 This is a diagram illustrating an example of a semiconductor device according to an embodiment of the concept of the present invention; Figure 14 This is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the concept of the present invention; Figure 15 , Figure 16 and Figure 17 These are diagrams illustrating examples of semiconductor devices according to embodiments of the present invention; and Figure 18 , Figure 19A , Figure 19B , Figure 19C , Figure 20 , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C This is a diagram illustrating an example of a method for forming a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0009] In the following text, ordinal numbers such as "first," "second," and "third" may simply be used as labels for certain elements, steps, etc., to distinguish them from one another. For example, terms such as "upper," "middle," and "lower" may be replaced by other terms such as "first," "second," and "third" to describe the elements in the specification. While terms such as "first," "second," and "third" may be used to describe a variety of elements, these elements are not limited to these terms, and "first element" may be referred to as "second element." In the specification, terms such as "lower," "upper," "top," and "bottom" may be terms used based on the accompanying drawings.

[0010] Items described in the singular in this document may be provided in the plural, as can be seen, for example, in the accompanying figures. Therefore, unless the context otherwise indicates, a description of a single item provided in the plural should be understood to apply to the remaining multiple items.

[0011] Throughout this specification, when a component is described as “comprising” a specific element or group of elements, it should be understood that, unless the context otherwise indicates, the component is formed solely by the element or group of elements, or the element or group of elements may be combined with additional elements to form the component. On the other hand, the term “composed of” indicates that the component is formed solely by the listed (one or more) elements.

[0012] Unless the context or other statements indicate otherwise, terms such as “same,” “equal,” “constant,” and “flat” as used herein are intended to encompass meanings including typical variations caused by conventional manufacturing processes and / or acceptable tolerances in manufacturing processes containing semiconductor devices. For example, “same” and “equal” can include exactly or nearly exactly the same. The term “substantially” may be used herein to emphasize this meaning.

[0013] In the specification, "memory cell array area" can refer to an area where memory cells are provided. In the specification, "interface area" can be an area adjacent to the memory cell array area, and can be an area without memory cells but with word line contacts connected to word lines, an area with back gate contacts connected to back gate electrodes, or an area with bit line contacts connected to bit lines.

[0014] As used herein, the term "dummy" refers to a component that has the same or similar structure and shape as other components but does not have a substantial function (e.g., transmitting information). A "dummy" element may exist merely as a pattern in a device. In some cases, a "dummy" element may be electrically floating or connected to various voltage sources, yet in other respects does not provide the same functionality as the non-dummy element it represents. For example, a dummy word line may not be connected to a memory cell, or may have a dummy memory cell connected to that dummy word line (here, no data is read from the dummy memory cell). For example, in the specification, among the active patterns arranged in the memory cell array region, an active pattern electrically connected to the bit line and the data storage structure may be a cell active pattern (e.g., having a similar structure), and an active pattern not electrically connected to one or both of the bit line and the data storage structure may be a dummy active pattern.

[0015] First, refer to Figure 1A , Figure 1B , Figure 2 and Figure 3 A semiconductor device 1 according to an embodiment of the concept of the present invention is described. Figure 1A , Figure 1B , Figure 2 and Figure 3 This is a diagram illustrating a semiconductor device 1 according to an embodiment of the present invention, wherein, Figure 1A This is a conceptual three-dimensional view of semiconductor device 1. Figure 1B This is a three-dimensional diagram conceptually illustrating the electrical connection relationship between the first structure ST1 and the second structure ST2 in Figure 1. Figure 2 It is a conceptual representation Figure 1A and Figure 1B A plan view of a portion of the first structure ST1. Figure 3 It shows the result of Figure 2 The circuit diagram for the area indicated by "A" in the diagram.

[0016] refer to Figure 1A , Figure 1B , Figure 2 and Figure 3 According to an embodiment of the present invention, the semiconductor device 1 may include a first structure ST1 and a second structure ST2 that overlaps the first structure ST1 perpendicularly. The second structure ST2 may be disposed on the first structure ST1. According to an embodiment, the second structure ST2 may be disposed below the first structure ST1.

[0017] In one embodiment, the first structure ST1 may include a storage unit ( Figure 3 The first chip comprises the memory cell MC and a portion of the peripheral circuit region PERI, and the second structure ST2 may be a second chip comprising other portions of the peripheral circuit region PERI. The peripheral circuit region PERI may include a first peripheral circuit region PERI1 and a second peripheral circuit region PERI2. Within the peripheral circuit region PERI, a portion of the peripheral circuitry for the operation of the memory cell MC is formed.

[0018] In one embodiment, the first structure ST1 and the second structure ST2 can be joined by a joining process such as a wafer bonding process. For example, the first structure ST1 can be joined to the second structure ST2 while in contact with the second structure ST2.

[0019] Semiconductor device 1 may include multiple bank areas (BA) and peripheral areas (PERI).

[0020] The peripheral area PERI may include the first peripheral area PERI1 in the first structure ST1 and the second peripheral area PERI2 in the second structure ST2. The peripheral area PERI may be a peripheral area provided with a first peripheral circuit for data or command input / output, or power / ground input.

[0021] Each of the multiple memory regions BA may include a first memory region BA1 in the first structure ST1 and a second memory region BA2 in the second structure ST2. Memory cells ( ) can be formed in the first memory region BA1. Figure 3 (MC in the first memory bank). A second peripheral circuit can be formed in the second memory bank region BA2. The second peripheral circuit may include a sub-word line driver. For example, each pair of circuits in the first memory bank region BA1 and the corresponding circuit in the second memory bank region BA2 can constitute a memory bank.

[0022] The first structure ST1 and the second structure ST2 may further include a routing interconnection structure RTa that electrically connects the first memory bank region BA1 and the second memory bank region BA2. For example, the routing interconnection structure RTa may include first routing interconnection structures RT_La and RT_Lb disposed in the first structure ST1 and second routing interconnection structures RT_Ua and RT_Ub disposed in the second structure ST2.

[0023] The first wiring interconnect structures RT_La and RT_Lb may include a first interconnect structure RT_La electrically connected to the first memory bank region BA1 and a first bonding pad RT_Lb electrically connected to the first interconnect structure RT_La. The second wiring interconnect structures RT_Ua and RT_Ub may include a second interconnect structure RT_Ua electrically connected to the second memory bank region BA2 and a second bonding pad RT_Ub electrically connected to the second interconnect structure RT_Ua.

[0024] The first bonding pad RT_Lb and the second bonding pad RT_Ub can contact and bond to each other. For example, the first bonding pad RT_Lb and the second bonding pad RT_Ub can include copper and can be bonded to each other by a metal-to-metal bonding process. Therefore, the bonding surface JN1 between the first structure ST1 and the second structure ST2 can include: a metal-to-metal bonding region JNa, in which the first bonding pad RT_Lb of the first structure ST1 and the second bonding pad RT_Ub of the second structure ST2 are bonded to each other; and a dielectric bonding region JNb, in which the dielectric of the first structure ST1 and the dielectric of the second structure ST2 are bonded to each other.

[0025] In the first structure ST1, each first storage area BA1 may include a storage cell array area ( Figure 2 and Figure 3 The MCA in the memory cell array region and the interface region adjacent to the MCA in the memory cell array region ( Figure 2 and Figure 3 (IF1, IF2, and IF3 in the code).

[0026] The memory cell array regions (MCAs) can be arranged along a first horizontal direction X and a second horizontal direction Y, which are perpendicular to each other. Interface regions IF1, IF2, and IF3 can include: a first interface region IF1, which is disposed between the memory cell array regions (MCAs) arranged along the first horizontal direction X; a third interface region IF3, which is disposed on the outermost side of the first horizontal direction X; and a second interface region IF2, which is adjacent to the memory cell array regions (MCAs) in the second horizontal direction Y. The memory cell array regions (MCAs) arranged along the first horizontal direction X and the first interface region IF1 can be disposed between the third interface region IF3. Each first interface region IF1 can be disposed between adjacent memory cell array regions (MCAs) in the first horizontal direction X.

[0027] The storage cell array region (MCA) can be a region where storage cells (MCs) are located. In other words, storage cells (MCs) can be located within the storage cell array region (MCA).

[0028] Each memory cell MC may include a data storage structure DS that can be used to store data and a cell transistor cTR electrically connected to the data storage structure DS. In a memory such as DRAM, the data storage structure DS may be a cell capacitor that can store data. The data storage structure DS may be any kind of capacitor (e.g., a ferroelectric capacitor) used in a single transistor single capacitor (1T1C) memory cell, which is a type of memory. However, the invention is not limited thereto. For example, the data storage structure DS may be any type of resistor, including MTJ (magnetic tunnel junction), ferroelectric tunnel junction (FTJ), and combinations thereof used in a single transistor single resistor (1T1R) memory cell. For example, the data storage structure DS may be selected from the group consisting of data storage structures such as phase change memory (PCM, PRAM, PCRAM, PC-RAM), resistive memory (RRAM), magnetoresistive memory (MRAM), polymer memory (PRAM), molecular memory, ferroelectric memory (FeRAM), ion memory (PMC), memristor memory, spin memory, oxide memory (such as ReRAM and 0xRAM), conductive bridged random access memory (CBRAM), and combinations thereof.

[0029] In the first structure ST1, each first storage area BA1 may include: a storage cell ( Figure 3 MC in (the text is incomplete and cannot be translated.) Figure 2 and Figure 3 The word line (WL) is electrically connected to the memory cell MC; the bit line ( Figure 2 and Figure 3The BL in the middle, the bit line is electrically connected to the memory cell MC; and the back gate electrode ( Figure 2 and Figure 3 (BG in the text). For example Figure 3 As shown, the word line WL can extend in the row direction (X direction) and can be connected to the gate terminal of the access transistor of the memory cell MC in each row. The bit line BL can extend in the column direction (Y direction) and can be connected to the drain terminal of the access transistor of the memory cell MC in each column.

[0030] Each word line WL can cross the memory cell array region MCA and the first interface region IF1 in the first horizontal direction X, and extend into the third interface region IF3. The word lines WL can be spaced apart from each other in the second horizontal direction Y. Each word line WL can cross the memory cell array region MCA and the first interface region IF1 arranged sequentially in the first horizontal direction X, and extend into the third interface region IF3.

[0031] Bit lines BL can cross the memory cell array region MCA in the second horizontal direction Y and extend into the second interface region IF2. For example, each bit line in bit lines BL can cross the corresponding memory cell array region MCA in the second horizontal direction Y and extend into the second interface region IF2 adjacent to the corresponding memory cell array region MCA in the second horizontal direction Y.

[0032] The back gate electrode BG can span the memory cell array region MCA in the first horizontal direction X and extend into the first interface region IF1 and the third interface region IF3 adjacent to the memory cell array region MCA. For example, each back gate electrode BG can span the corresponding memory cell array region MCA in the memory cell array region MCA. Each back gate electrode BG can extend into the first interface region IF1 adjacent to the corresponding memory cell array region MCA in the first horizontal direction X, or it can extend into the first interface region IF1 and the third interface region IF3 adjacent to the corresponding memory cell array region MCA in the first horizontal direction X.

[0033] The second memory bank region BA2 in the second structure ST2 may include a region provided with circuitry for operating the memory cell MC. For example, the second memory bank region BA2 may include: a sense amplifier region, wherein a sense amplifier for reading data from the memory cell MC is provided; a sub-word line driver region, wherein a sub-word line driver capable of activating or deactivating the memory cell MC is provided; a back gate circuit region for applying a back gate voltage to the back gate electrode BG; and a peripheral circuit region for controlling at least one of the circuitry in the sense amplifier region, the sub-word line driver region, and the back gate circuit region.

[0034] Wiring interconnect structure (e.g., Figure 1B The RTa in the diagram can be a conductor forming a signal path, including bit line routing interconnects (not shown), word line routing interconnects (not shown), back gate routing interconnects (not shown), and control routing interconnects (not shown). The routing interconnect structure can be referred to as an interconnect.

[0035] Next, refer to Figure 4 The above wiring interconnection structure will be described. Figure 1B RTa in the middle) and joint surface ( Figure 1B Another example of JN1 in the example. Figure 4 It conceptually shows that they correspond to respectively Figure 1B A perspective view of the wiring interconnect structure RTa and the bonding surface JN1, and the wiring interconnect structure RTb and the bonding surface JN2 according to another example.

[0036] In the embodiment, reference Figure 4 , Figure 1B The routing interconnect structure RTa in the code can be replaced by a routing interconnect structure RTb that omits the first bonding pad RT_Lb and the second bonding pad RT_Ub, and... Figure 1B The bonding surface JN1 in the middle can be replaced by the bonding surface JN2, which omits the intermetallic bonding region JNa.

[0037] The wiring interconnect structure RTb may include: a first interconnect structure RT_Laa, which is included in a first structure ST1 and electrically connected to a first memory bank region BA1; a second interconnect structure RT_Uaa, which is included in a second structure ST2 and electrically connected to a second memory bank region BA2; and a connection structure RT_C, which extends from the first structure ST1 to the second structure ST2 and electrically connects the first interconnect structure RT_Laa and the second interconnect structure RT_Uaa. The bonding surface JN2 between the first structure ST1 and the second structure ST2 can create a dielectric indirect bonding surface where the dielectrics of the first structure ST1 and the second structure ST2 are directly bonded (fused) to each other. The connection structure RT_C may include a through-path or through-connection plug that can penetrate the bonding surface JN2. For example... Figure 1B The mating surface JN1 can be replaced by mating surface JN2. In mating surface JN2, the through passage and through connecting plug in the first structure ST1 can be connected to the through passage or through connecting plug in the second structure ST2 by a mating mechanism other than metal-to-metal mating.

[0038] In the following text, we will refer to them together. Figure 1A , Figure 1B, Figure 2 and Figure 3 An exemplary example of the first structure ST1 of semiconductor device 1 is described below. Figure 1A , Figure 1B , Figure 2 and Figure 3 The first structure ST1 of the semiconductor device 1 described herein is an exemplary example, but in the embodiments described below, Figure 1B The wiring interconnect structure RTa and the bonding surface JN1 described herein can be derived from... Figure 4 The wiring interconnect structure RTb and bonding surface JN2 described herein are replaced. Furthermore, the example embodiments described below can be combined with each other to form other example embodiments.

[0039] The description will focus on the memory cell array region MCA in each of the first memory areas BA1 described above, as well as the elements set in the first interface region IF1, the second interface region IF2, and the third interface region IF3.

[0040] First, together with Figure 1A , Figure 1B , Figure 2 and Figure 3 Let's refer to each other. Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8 and Figure 9 An exemplary example of semiconductor device 1 will be described below. Figure 5A This is a plan view illustrating an exemplary example of the memory cell array region MCA and the first interface region IF1, the second interface region IF2, and the third interface region IF3. Figure 5B It shows the setting Figure 5A A plan view of the memory cell array region MCA and some components in the first interface region IF1, the second interface region IF2 and the third interface region IF3. Figure 6A It shows the setting Figure 5A and Figure 5B A plan view of some elements in the area indicated by "B". Figure 6B It shows the setting Figure 5A and Figure 5B A plan view of some elements in the area indicated by "C". Figure 6C It shows the setting Figure 5A and Figure 5B A plan view of some elements in the area indicated by "D". Figure 7A It shows along Figure 6A and Figure 6CA cross-sectional view of the area intercepted by line I-I' in the diagram. Figure 7B yes Figure 7A A magnified partial view of the area indicated by "E". Figure 8 It shows along Figure 6A and Figure 6C A cross-sectional view of the area intercepted by line II-II', and Figure 9 It shows along Figure 6A and Figure 6C A cross-sectional view of the area intercepted by line III-III'.

[0041] Together Figure 1A , Figure 1B , Figure 2 and Figure 3 Let's refer to each other. Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8 and Figure 9 The semiconductor device 1 may include the memory cell array region MCA described above, as well as the first interface region IF1, the second interface region IF2, and the third interface region IF3.

[0042] In the following description, within the memory cell array region MCA, the focus will be on the first memory cell array region MCA1 and the second memory cell array region MCA2 that are adjacent to each other in the first horizontal direction X, and the first memory cell array region MCA1 and the third memory cell array region MCA3 that are adjacent to each other in the second horizontal direction Y; while within the interface regions IF1, IF2 and IF3, the focus will be on the first interface region IF1 located between the first memory cell array region MCA1 and the second memory cell array region MCA2, the second interface region IF2 located between the first memory cell array region MCA1 and the third memory cell array region MCA3, and the third interface region IF3 adjacent to the second memory cell array region MCA2.

[0043] The semiconductor device 1 may also include a unit gate electrode 27, a back gate electrode 18, a back gate dielectric layer 15, an active pattern 9, and a unit gate dielectric layer 24.

[0044] The cell gate electrode 27 may be a portion of the word line WL described above (for example, the cell gate electrode of a row of memory cells may form a portion corresponding to a single electrical node of the word line). The cell gate electrode 27 may include a first word line WL_1 and a second word line WL_2 that are spaced apart from and adjacent to each other in the second horizontal direction Y. The first word line WL_1 and the second word line WL_2 may span the first memory cell array region MCA1, the first interface region IF1, and the second memory cell array region MCA2. The back gate electrode 18 may be the back gate electrode BG described above.

[0045] The minimum distance between the first word line WL_1 and the second word line WL_2 in the first memory cell array region MCA1 can be greater than the minimum distance between the first word line WL_1 and the second word line WL_2 in the first interface region IF1.

[0046] The first word line WL_1 and the second word line WL_2 may include a first portion of the first memory cell array region MCA1 that faces each other. Figure 6B 27a), the second part of the first memory cell array region MCA1 facing each other ( Figure 6B 27b in the first interface area IF1, the third part facing each other ( Figure 6B 27c in the first interface area IF1, the fourth part facing each other ( Figure 6B 27d in the middle), and the fifth part facing each other in the first interface area IF1 (in the middle). Figure 6B (27e in the middle).

[0047] Part One ( Figure 6B 27a in the text can be the first part 27a of the first word line WL_1 and the first part 27a of the second word line WL_2, the second part ( Figure 6B 27b in the text can be the second part 27b of the first word line WL_1 and the second part 27b of the second word line WL_2, the third part ( Figure 6B 27c in the text can be the third part 27c of the first word line WL_1 and the third part 27c of the second word line WL_2, the fourth part ( Figure 6B 27d in the text can be the fourth part 27d of the first word line WL_1 and the fourth part 27d of the second word line WL_2, and the fifth part ( Figure 6B 27e in the text can be the fifth part 27e of the first word line WL_1 and the fifth part 27e of the second word line WL_2.

[0048] The active pattern 9 can be symmetrical in its arrangement in the plan view. The first unit active pattern 9a_1 and the second unit active pattern 9a_2 face each other along an imaginary plane extending in the first horizontal direction X and the vertical direction Z, and the first unit active pattern 9a_1 and the second unit active pattern 9a_2 can be arranged between the first portions 27a. In the plan view, the first unit active pattern 9a_1 and the second unit active pattern 9a_2 can be arranged symmetrically about this imaginary plane.

[0049] The second part 27b of the first word line WL_1 can be set between two adjacent first unit active patterns 9a_1 in the first unit active pattern 9a_1, and the second part 27b of the second word line WL_2 can be set between two adjacent second unit active patterns 9a_2 in the second unit active pattern 9a_2.

[0050] The first dummy active pattern 9b_1 and the second dummy active pattern 9b_2 can be disposed between the third part 27c. The first back gate electrode BG_1 of the back gate electrode BG can be disposed between the first part 27a, the second part 27b, the third part 27c, or the fourth part 27d, and may not be disposed between the fifth part 27e.

[0051] The spacing between the first part 27a can be greater than the spacing between the second part 27b. The spacing between the third part 27c, the spacing between the fourth part 27d, and the spacing between the fifth part 27e can be different from each other.

[0052] The spacing between the third part 27c can be greater than the spacing between the fourth part 27d.

[0053] The spacing between the fourth part 27d can be greater than the spacing between the fifth part 27e.

[0054] The spacing between the fifth part 27e can be smaller than the spacing between the second part 27b.

[0055] The spacing between the third part 27c can be substantially the same as the spacing between the first part 27a.

[0056] The spacing between the fourth part 27d can be substantially the same as the spacing between the second part 27b.

[0057] In the first memory cell array region MCA1, the minimum spacing between the first word line WL_1 and the second word line WL_2 can be the spacing between the second parts 27b.

[0058] In the first memory cell array region MCA1, the maximum spacing between the first word line WL_1 and the second word line WL_2 can be the spacing between the first portions 27a.

[0059] In the first interface area IF1, the minimum distance between the first character line WL_1 and the second character line WL_2 can be the spacing between the fifth part 27e.

[0060] In the first interface area IF1, the maximum distance between the first character line WL_1 and the second character line WL_2 can be the spacing between the third part 27c.

[0061] The maximum distance between the first word line WL_1 and the second word line WL_2 in the first memory cell array region MCA1 can be substantially equal to the maximum distance between the first word line WL_1 and the second word line WL_2 in the first interface region IF1.

[0062] The first back gate electrode BG_1 may include: a first back gate portion 18a, which passes through the space between the first portions 27a and the second portions 27b in the first memory cell array region MCA1; a second back gate portion 18b, which is disposed in the space between the third portions 27c in the first interface region IF1; and a third back gate portion 18c, which is disposed in the space between the fourth portions 27d in the first interface region IF1. The first back gate electrode BG_1 may not be disposed in the space between the fifth portions 27e in the first interface region IF1.

[0063] The first back grille portion 18a, the second back grille portion 18b, and the third back grille portion 18c may have substantially the same width.

[0064] The first interface area IF1 may include a first area IF1a with a third part 27c and a second back gate part 18b, a second area IF1b with a fourth part 27d and a third back gate part 18c, and an intermediate area IF1c with a fifth part 27e.

[0065] In the first interface region IF1, the first region IF1a may be adjacent to the storage cell array region MCA, and the second region IF1b may be located between the first region IF1a and the intermediate region IF1c.

[0066] In the first interface region IF1, the length of the middle region IF1c in the first horizontal direction X can be greater than the length of each of the first region IF1a and the second region IF1b in the first horizontal direction X.

[0067] In the first interface region IF1, the length of the first region IF1a in the first horizontal direction X can be greater than the length of the second region IF1b in the first horizontal direction X.

[0068] For example, in a planar view, the first word line WL_1 and the second word line WL_2 can have a wavy shape and can be arranged symmetrically about an imaginary plane. Corresponding segments (or portions) 27a, 27b, 27c, 27d, and 27e of the paired first word lines WL_1 and WL_2 can face each other in each of the different regions including regions MCA1, IF1a, IF1b, and IF1c. Therefore, the minimum facing distance (or the spacing distance in the planar view) in one region can be different from the minimum facing distance in other regions. The imaginary plane can extend along a corresponding back gate electrode in the back gate electrode BG, and the corresponding back gate electrode in the back gate electrode BG can be positioned between the first word line WL_1 and the second word line WL_2.

[0069] The unit gate electrode 27 can be formed of a conductive material. For example, each unit gate electrode in the unit gate electrode 27 can be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof, but is not limited thereto. Each unit gate electrode in the unit gate electrode 27 may comprise a single layer or multiple layers of the aforementioned conductive material.

[0070] The back gate electrode 18 may include a first back gate electrode BG_1 spanning a first memory cell array region MCA1 and a second back gate electrode BG_2 spanning a second memory cell array region MCA2. The first back gate electrode BG_1 may have a first end BG_1e located in a first interface region IF1, and the second back gate electrode BG_2 may have a second end BG_2e located in the first interface region IF1. The first end BG_1e of the first back gate electrode BG_1 may face the second end BG_2e of the second back gate electrode BG_2 in a first horizontal direction X. At least a portion of each back gate electrode 18 may be disposed at the same vertical height as the cell gate electrode 27. At least a portion of each cell gate electrode 27 may be disposed at the same vertical height as the back gate electrode 18.

[0071] The back gate electrode 18 can be formed of a conductive material. For example, each back gate electrode 18 can be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof, but is not limited thereto. Each back gate electrode 18 may comprise a single layer or multiple layers of the aforementioned conductive materials.

[0072] The back gate dielectric layer 15 may contact the back gate electrode 18. The back gate dielectric layer 15 may surround the side surface of the back gate electrode 18. The back gate dielectric layer 15 may extend along a first horizontal direction X, across the memory cell array region MCA and the first interface region IF1, and extend into the third interface region IF3.

[0073] In a plan view, the back gate dielectric layer 15 can be arranged symmetrically about an imaginary plane. The back gate dielectric layer 15 may include a first back gate dielectric layer 15_1 disposed between the first word line and the second word line.

[0074] The first back gate dielectric layer 15_1 may include a first portion 15a disposed between the first word line WL_1 and the first back gate electrode BG_1 in the first memory cell array region MCA1, and a second portion 15b disposed between the second word line WL_2 and the first back gate electrode BG_1.

[0075] The first back gate dielectric layer 15_1 may include a third portion 15c disposed between the first word line WL_1 and the second back gate electrode BG_2 in the second memory cell array region MCA2, and a fourth portion 15d disposed between the second word line WL_2 and the second back gate electrode BG_2.

[0076] The first back gate dielectric layer 15_1 may further include a fifth portion 15e covering the first end BG_1e of the first back gate electrode BG_1 and the second end BG_2e of the second back gate electrode BG_2 in the first interface region IF1.

[0077] The active pattern 9 may include a semiconductor material that can be used as a channel region for a transistor. For example, the active pattern 9 may include a semiconductor material such as single-crystal silicon. The active patterns 9 may be disposed at the same height as each other. The active pattern 9 may include a semiconductor material such as oxide semiconductor.

[0078] The active pattern 9 may include cell active patterns 9a disposed in the memory cell array region MCA and dummy active patterns 9b disposed in the first interface region IF1 and the third interface region IF3. Each active pattern 9 may have an elongated strip shape, an elliptical shape, or a strip shape that is close to an elliptical shape in the first horizontal direction X. The cell active patterns 9a may be spaced apart from each other in the first horizontal direction X and the second horizontal direction Y in the memory cell array region MCA. In the first horizontal direction X, the length of each dummy active pattern 9b may be greater than the length of each cell active pattern 9a. In the second horizontal direction Y, the width of each dummy active pattern 9b may be substantially the same as the width of each cell active pattern 9a. The dummy active patterns 9b may include dummy active patterns disposed adjacent to the cell active patterns 9a in the first interface region IF1 and dummy active patterns disposed adjacent to the cell active patterns 9a in the second memory cell array region MCA2.

[0079] Each cell active pattern 9a may include: a first source / drain region ( Figure 7B SD1 in the middle); second source / drain region ( Figure 7B SD2), the second source / drain region is located at a different height than the first source / drain region SD1; and the channel region ( Figure 7B (CH in the text), the channel region is located between the first source / drain region SD1 and the second source / drain region SD2.

[0080] In the example, the second source / drain region SD2 can be set on the first source / drain region SD1.

[0081] The cell gate dielectric layer 24 may surround the side surface of the back gate dielectric layer 15, and the active pattern 9 may be disposed between the cell gate dielectric layer 24 and the back gate dielectric layer 15.

[0082] Each active pattern 9 may have side surfaces opposite to each other in a first horizontal direction X and side surfaces opposite to each other in a second horizontal direction Y. The side surfaces of the active pattern 9 opposite to each other in the first horizontal direction X may be covered by the cell gate dielectric layer 24. Among the side surfaces of the active pattern 9 opposite to each other in the second horizontal direction Y, the side surface facing the back gate electrode 18 may be covered by the back gate dielectric layer 15, and the side surface facing the cell gate electrode 27 may be covered by the cell gate dielectric layer 24. The cell gate dielectric layer 24 may be disposed between the cell gate electrode 27 and the active pattern 9.

[0083] The cell gate dielectric layer 24 may include a first cell gate dielectric layer 24_1 in contact with the first word line WL_1 and a second cell gate dielectric layer 24_2 in contact with the second word line WL_2. In a plan view, the first cell gate dielectric layer 24_1 and the second cell gate dielectric layer 24_2 may have a wavy shape and may be arranged symmetrically about an imaginary plane.

[0084] The active cell pattern 9a may include: a first active cell pattern 9a_1, which is disposed in the first memory cell array region MCA1 between the first word line WL_1 and the first back gate dielectric layer 15_1; a second active cell pattern 9a_2, which is disposed in the first memory cell array region MCA1 between the second word line WL_2 and the first back gate dielectric layer 15_1; a third active cell pattern 9a_3, which is disposed in the second memory cell array region MCA2 between the first word line WL_1 and the first back gate dielectric layer 15_1; and a fourth active cell pattern 9a_4, which is disposed in the second memory cell array region MCA2 between the second word line WL_2 and the first back gate dielectric layer 15_1.

[0085] The first active pattern 9a_1 can be disposed in the first memory cell array region MCA1 between the first cell gate dielectric layer 24_1 and the first back gate dielectric layer 15_1, and the second active pattern 9a_2 can be disposed in the first memory cell array region MCA1 between the second cell gate dielectric layer 24_2 and the first back gate dielectric layer 15_1.

[0086] The first unit gate dielectric layer 24_1 may extend from the portion disposed between the first unit active pattern 9a_1 and the first word line WL_1 between adjacent first unit active patterns 9a_1 in the first horizontal direction X, and the second unit gate dielectric layer 24_2 may extend from the portion disposed between the second unit active pattern 9a_2 and the second word line WL_2 between adjacent second unit active patterns 9a_2 in the first horizontal direction X.

[0087] The dummy active pattern 9b may include: a first dummy active pattern 9b_1, which is disposed in the first interface region IF1 between the first word line WL_1 and the first back gate dielectric layer 15_1; and a second dummy active pattern 9b_2, which is disposed in the first interface region IF1 between the second word line WL_2 and the first back gate dielectric layer 15_1. The first dummy active pattern 9b_1 and the second dummy active pattern 9b_2 may face each other in the second horizontal direction Y, and in the first horizontal direction X, the length of each of the first dummy active pattern 9b_1 and the second dummy active pattern 9b_2 may be greater than the length of each of the first unit active pattern 9a_1 and the second unit active pattern 9a_2.

[0088] In an embodiment, the channel region CH of the unit transistor cTR can be a floating body, and the back gate electrode 18 facing the channel region CH can suppress or prevent the performance of the unit transistor cTR from deteriorating due to the floating body effect.

[0089] Each of the aforementioned cell transistors (cTRs) may include: a first source / drain region SD1, a second source / drain region SD2, and a channel region CH disposed in a corresponding cell active pattern 9a; a cell gate electrode 27 facing the channel region CH; and a cell gate dielectric layer 24 located between the channel region CH and the cell gate electrode 27. In each cell transistor (cTR), the cell gate electrode 27 may have a side surface facing the side surface of the channel region CH.

[0090] The semiconductor device 1 may also include a first insulating back gate cover pattern 21 located on the back gate electrode 18 and a second insulating back gate cover pattern 88a located below the back gate electrode 18.

[0091] The back gate dielectric layer 15 can extend upward and downward from the portion disposed between the back gate electrode 18 and the active pattern 9. Therefore, the back gate dielectric layer 15 can be disposed between the back gate electrode 18 and the active pattern 9, between the first insulating back gate cover pattern 21 and the active pattern 9, and between the second insulating back gate cover pattern 88a and the active pattern 9.

[0092] The semiconductor device 1 may also include a first insulating gate cover pattern 29 disposed on the unit gate electrode 27 and a second insulating gate cover pattern 88b disposed below the unit gate electrode 27.

[0093] The cell gate dielectric layer 24 can extend upward and downward from the portion disposed between the cell gate electrode 27 and the active pattern 9. Therefore, the cell gate dielectric layer 24 can be disposed between the cell gate electrode 27 and the active pattern 9, between the first insulating gate cover pattern 29 and the active pattern 9, and between the second insulating gate cover pattern 88b and the active pattern 9.

[0094] The semiconductor device 1 may further include an insulating pattern 30 disposed between adjacent unit gate electrodes 27, between first insulating gate cover patterns 29, and between second insulating gate cover patterns 88b. For example, the unit gate electrodes 27 may include a first word line WL_1, a second word line WL_2, a third word line WL_3, and a fourth word line WL_4 arranged sequentially in the second horizontal direction Y, and the back gate electrode 18 may be disposed between the first word line WL_1 and the second word line WL_2, and between the third word line WL_3 and the fourth word line WL_4, while the back gate electrode 18 may not be disposed between the second word line WL_2 and the third word line WL_3, and the insulating pattern 30 may be disposed between the second word line WL_2 and the third word line WL_3.

[0095] Semiconductor device 1 may include bit line 90. Bit line 90 may be bit line BL as described above. Bit line 90 may be disposed below cell active pattern 9a and may be connected to the lower surface of cell active pattern 9a. Bit line 90 may be electrically connected to the first source / drain region SD1 of cell active pattern 9a. Bit line 90 may be as described above. Figure 2 and 3 The part describing the bit line BL.

[0096] Bit line 90 may include: a first bit line BL_1, which crosses a first memory cell array region MCA1 in a second horizontal direction Y and extends into a second interface region IF2; and a second bit line BL_2, which crosses a third memory cell array region MCA3 in the second horizontal direction Y and extends into the second interface region IF2. In the second interface region IF2, the ends of the first bit line BL_1 and the ends of the second bit line BL_2 may face each other.

[0097] The width of the first interface region IF1 in the first horizontal direction X can be greater than the width of the second interface region IF2 in the second horizontal direction Y. The distance between the first memory cell array region MCA1 and the second memory cell array region MCA2 can be greater than the distance between the first memory cell array region MCA1 and the third memory cell array region MCA3.

[0098] Semiconductor device 1 may also include a back gate contact plug (BGC) and a back gate interconnect structure (BGI).

[0099] The back gate contact plug BGC can be connected to the back gate electrode 18. The back gate contact plug BGC can be connected to a region adjacent to the memory cell array region MCA, such as the second back gate portion 18b disposed in the first region IF1a of the first interface region IF1. For example, the back gate contact plug BGC is connected to the first back gate electrode ( Figure 6A and Figure 6B The first back gate contact plug BGC1 of BG_1 can be connected to the portion of the first back gate electrode BG_1 located between the first dummy active pattern 9b_1 and the second dummy active pattern 9b_2, for example, the second back gate portion 18b.

[0100] The back gate interconnect structure (BGI) can be connected to the dummy active pattern 9b below the dummy active pattern 9b. The back gate interconnect structure (BGI) can be located at the same height as the bit line BL and can be formed of the same material as the bit line BL.

[0101] Each of the bit line 90 and the back gate interconnect structure BGI may include a first material layer 90a, a second material layer 90b below the first material layer 90a, and a third material layer 90c below the second material layer 90b. The first material layer 90a may include at least one of doped silicon, doped germanium, or doped silicon-germanium. The second material layer 90b may include at least one of a metal semiconductor compound layer or a metal nitride. The third material layer 90c may include at least one of a metal or a metal nitride.

[0102] Each back gate interconnect (BGI) can extend in the second horizontal direction Y. The width of each BGI can be greater than the width of each bit line (BL).

[0103] A back gate contact plug (BGC) can be disposed between the back gate interconnect structure (BGI) and the back gate electrode 18. The back gate contact plug (BGC) can be connected to the lower surface of the back gate electrode 18 and the side surface of the lower region of the back gate electrode 18.

[0104] The semiconductor device 1 may further include an insulating overlay pattern 91 disposed below and aligned with the bit line 90 and the back gate interconnect structure BGI. The overlay pattern 91 may be formed of an insulating material.

[0105] The semiconductor device 1 may also include an insulating pad 92 that covers the lower surface of a structure including bit lines 90, back gate interconnect structure BGI, and overlay pattern 91.

[0106] The semiconductor device 1 may further include a bit line shielding pattern 93 disposed below the insulating pad 92 between the bit lines 90 and extending below the lower surface of the overlay pattern 91 disposed below the bit lines 90. The bit line shielding pattern 93 may be formed of a conductive material. Since the bit line shielding pattern 93 can reduce the parasitic capacitance between the bit lines 90, it can prevent a reduction in the signal transmission speed of the bit lines 90.

[0107] The semiconductor device 1 may further include: a first lower insulating layer 94 disposed below the bit line shielding pattern 93 and the insulating pad 92; and a second lower insulating layer 98 disposed below the first lower insulating layer 94.

[0108] The semiconductor device 1 may further include rear contact plugs 95a and 95b disposed in the second interface region IF2. The rear contact plugs 95a and 95b may extend through the first lower insulating layer 94, the insulating pad 92, and the overlay pattern 91. The rear contact plugs 95a and 95b may include a first rear contact plug 95a connected to the bit line 90 and a second rear contact plug 95b connected to the back gate interconnect structure BGI.

[0109] The semiconductor device 1 may further include word line contact plugs WLC connected to word lines 27 in a first interface region IF1 and a third interface region IF3. For example, each word line WL spanning each memory cell array region MCA1 may be connected to a word line contact plug WLC disposed on both sides of each memory cell array region MCA1 in the first interface region IF1, or to word line contact plugs WLC disposed on both sides of each memory cell array region MCA1 in the first interface region IF1 and the third interface region IF3. For example, each word line WL spanning each memory cell array region MCA1 may be connected to two word line contact plugs WLC disposed on both sides of each memory cell array region MCA1.

[0110] The word line contact plug WLC can contact the lower surface of the word line 27 and the side surface of the lower region of the word line 27 in the first interface region IF1 and the third interface region IF3. The word line contact plug WLC can extend downward from the portion that contacts the word line 27 and penetrate the insulating pad 92 and the first lower insulating layer 94.

[0111] The semiconductor device 1 may further include rear interconnects 96a, 96b, and WLI disposed below the first lower insulating layer 94. The rear interconnects 96a, 96b, and WLI may include: a first rear interconnect 96a connected to a first rear contact plug 95a; a second rear interconnect 96b connected to a second rear contact plug 95b; and a third rear interconnect WLI connected to a word line contact plug WLC. The second lower insulating layer 98 may cover the rear interconnects 96a, 96b, and WLI.

[0112] The semiconductor device 1 may also include a contact structure 48 and an insulating structure 51. The contact structure 48 may be disposed on the cell active pattern 9a. The contact structure 48 may be connected to the cell active pattern 9a. For example, the contact structure 48 may be electrically connected to the second source / drain region SD2.

[0113] Each contact structure in contact structure 48 may include a first material layer 42 and a second material layer 45 located on the first material layer 42. The first material layer 42 may include a material such as doped silicon. The second material layer 45 may include one of a metal, a metal nitride, or a metal semiconductor compound. An insulating structure 51 may surround the side surface of the contact structure 48.

[0114] The semiconductor device 1 may also include an insulating etch stop layer 61 disposed on the contact structure 48 and the insulating structure 51.

[0115] The data storage structure DS described above may include: a first electrode 63a that penetrates the insulating etch stop layer 61, connects to the contact structure 48, and extends upward; a dielectric layer 63b that covers the first electrode 63a and the etch stop layer 61; and a second electrode 63c that covers the dielectric layer 63b. The data storage structure DS may be a cell capacitor capable of storing data in a memory such as DRAM.

[0116] As described above, each memory cell MC may include a data storage structure DS and a cell transistor cTR.

[0117] Contact structure 48 can be disposed between data storage structure DS and unit transistor cTR. Data storage structure DS can be electrically connected to unit transistor cTR through contact structure 48.

[0118] The semiconductor device 1 may further include: a first upper insulating layer 66 located on the data storage structure DS and the insulating etch stop layer 61; an upper contact plug 69 penetrating the first upper insulating layer 66 and connected to the second electrode 63c; an upper interconnect 77 connected to the upper contact plug 69 on the first upper insulating layer 66; and a second upper insulating layer 86 covering the first upper insulating layer 66 and the upper interconnect 77.

[0119] In this embodiment, in each memory cell region BA1, each word line WL can span multiple memory cell array regions MCA arranged along a first horizontal direction and a first interface region IF1 located between the multiple memory cell array regions MCA. This minimizes the space occupied by the first interface region IF1 within the memory cell region BA1, thereby improving the integration density of the semiconductor device 1.

[0120] In an embodiment, each word line WL spanning each memory cell array region MCA1 can be connected to two word line contact plugs WLC disposed in the interface regions located on both sides of the memory cell array region MCA1. The word line contact plugs WLC can be the wiring interconnect structure described above ( Figure 1B or Figure 4 This is part of the RTa (in the memory cell array). Thus, since each word line WL spanning each memory cell array region MCA1 is directly electrically connected to two word line contact plugs WLC arranged on both sides, the transmission speed of the signal applied to the entire word line WL can be increased. Therefore, the performance of the semiconductor device 1 can be improved.

[0121] Various example embodiments of the semiconductor device 1 will be described below. The various example embodiments described below and the previously described embodiments can be combined to form other example embodiments. In the following, elements described above may be directly referenced without separate detailed description, or their description may be omitted. Furthermore, elements that can be modified or replaced as described below will be described with reference to the accompanying drawings; however, elements that can be modified, replaced, or added may be combined with each other or with the elements described above to form a semiconductor device according to an example embodiment of this disclosure. Additionally, in cases where multiple of the above-described elements are provided, the following description will focus on the case where the number of the above-described elements is one.

[0122] refer to Figure 10 An example embodiment of semiconductor device 1 will be described below. Figure 10 This shows the above Figure 8 A sectional view of the component of the II-II' section structural variant.

[0123] In the embodiment, reference Figure 10 The back grid contact plug described above ( Figure 8 The BGC in the diagram can be replaced by a back gate contact plug BGCa that contacts the upper surface of the back gate electrode 18. The back gate contact plug BGCa can contact the upper surface of the back gate electrode 18 and the side surface of the upper region of the back gate electrode 18. The back gate contact plug BGCa can contact the back gate electrode 18 and extend upward to penetrate the insulating structure 51.

[0124] The second rear interconnect 96b described above can be replaced by a back gate contact plug 73a and a back gate interconnect 81a, the back gate contact plug 73a penetrating the first upper insulating layer 66 and connected to the back gate contact plug BGCa, and the back gate interconnect 81a connected to the back gate contact plug 73a on the first upper insulating layer 66.

[0125] refer to Figure 11 An example embodiment of semiconductor device 1 will be described below. Figure 11 This shows the above Figure 9 A cross-sectional view of the structurally modified element of section III-III'.

[0126] In one embodiment, reference Figure 11 The above-described word line contact plug ( Figure 9 The word line contact plug (WLC) in the cell gate electrode 27 can be replaced by a word line contact plug WLCa that contacts the upper surface of the cell gate electrode 27. The word line contact plug WLCa can contact the upper surface of the cell gate electrode 27 and the side surface of the upper region of the cell gate electrode 27. The word line contact plug WLCa can contact the cell gate electrode 27 and extend upward to penetrate the insulating structure 51.

[0127] The third rear interconnect WLI described above can be replaced by a word line contact plug 73b and a word line interconnect 81b, wherein the word line contact plug 73b passes through the first upper insulating layer 66 and is connected to the word line contact plug WLCa, and the word line interconnect 81b is connected to the word line contact plug 73b on the first upper insulating layer 66.

[0128] refer to Figure 12A , Figure 12B and Figure 13 An example embodiment of semiconductor device 1 will be described below. Figure 12A This shows the above Figure 6A A planar diagram of a component with a planar structural variation. Figure 12B This shows the above Figure 6B A planar diagram of the components of the planar structural variant, and Figure 13 It is along Figure 12A A cross-sectional view taken from line IIa-IIa' in the middle, which can show from Figure 8 The element with the II-II' cross-section structural variation.

[0129] In the embodiment, reference Figure 12A , Figure 12B and Figure 13The dummy active pattern 9b described above can be removed, and the back gate dielectric layer 15 and back gate electrode 18 described above can extend into the space where the dummy active pattern 9b has been removed. Therefore, the back gate dielectric layer 15 and back gate electrode 18 described above can be replaced by a back gate dielectric layer 115 and back gate electrode 118 including portions disposed in the space where the dummy active pattern 9b has been removed.

[0130] As described above, the first back gate electrode BG_1 may include: a first back gate portion 118a, which passes through the first portion 27a and the second portion 27b in the first memory cell array region MCA1; a second back gate portion 118b, which is disposed in the first interface region IF1 between the third portions 27c; and a third back gate portion 118c, which is disposed in the first interface region IF1 between the fourth portions 27d.

[0131] The width of the second back gate portion 118b may be greater than the width of each of the first back gate portion 118a and the third back gate portion 118c.

[0132] The first back grille portion 118a and the third back grille portion 118c may have substantially the same width.

[0133] The back gate contact plug BGC described above can contact and connect to the second back gate portion 118b. Due to the increased width of the second back gate portion 118b, the back gate contact plug BGC can be stably connected to the second back gate portion 118b.

[0134] refer to Figure 14 An example embodiment of semiconductor device 1 will be described below. Figure 14 This shows the above Figure 13 A cross-sectional view of the component with the cross-sectional structural variation of IIa-IIa'.

[0135] In the embodiment, reference Figure 14 The back grid contact plug described above ( Figure 13 The back gate contact plug (BGC) in the first upper insulating layer 66 can be replaced by a back gate contact plug BGCa that contacts the upper surface of the back gate electrode 118. The back gate contact plug BGCa can contact the back gate electrode 118 and extend upward to penetrate the insulating structure 51. The second rear interconnect 96b described above can be replaced by a back gate upper contact plug 73a and a back gate upper interconnect 81a, wherein the back gate upper contact plug 73a penetrates the first upper insulating layer 66 and is connected to the back gate contact plug BGCa, and the back gate upper interconnect 81a is connected to the back gate upper contact plug 73a on the first upper insulating layer 66.

[0136] refer to Figure 15 , Figure 16 and Figure 17An example embodiment of semiconductor device 1 will be described below. Figure 15 This shows the above Figure 12A A planar diagram of a component with a planar structural variation. Figure 16 This shows the above Figure 12B A planar diagram of the component with a planar structural variant, and Figure 17 It is along Figure 16 A cross-sectional view taken from line IIb-IIb' in the middle, which can show the cross-section from... Figure 8 The element with the II-II' cross-section structural variation.

[0137] In the embodiment, reference Figure 15 , Figure 16 and Figure 17 In the dummy active pattern 9b arranged along the second horizontal direction Y as described above, some dummy active patterns can be removed by retaining a pair of dummy active patterns and removing a pair of dummy active patterns at the same time.

[0138] The back gate dielectric layer 15 and back gate electrode 18 described above can be replaced by back gate dielectric layer 215 and back gate electrode 218.

[0139] When observing the first memory cell array region MCA1, the first interface region IF1, and the second memory cell array region MCA2, among the dummy active patterns 9b set between the first word line WL_1 and the second word line WL_2, a pair of dummy active patterns 9b adjacent to the first memory cell array region MCA1 can be retained. Among the dummy active patterns 9b set between the first word line WL_1 and the second word line WL_2, a pair of dummy active patterns adjacent to the second memory cell array region MCA2 (…) Figure 6A 9b in the middle can be removed. In the dummy active pattern 9b set between the third word line WL_3 and the fourth word line WL_4, a pair of dummy active patterns adjacent to the first memory cell array region MCA1 ( Figure 6A 9b) is removed, and in the dummy active pattern 9b set between the third word line WL_3 and the fourth word line WL_4, a pair of dummy active patterns 9b adjacent to the second memory cell array region MCA2 can be retained.

[0140] The back gate electrode 218 passing through the retained dummy active pattern 9b can have the same back gate electrode as described above. Figure 6A 18) The same shape.

[0141] Passing through the removal of the dummy source pattern ( Figure 6A The back gate electrode 218 of portion 9b) can have the same characteristics as... Figure 12A , Figure 12B and Figure 13It has the same shape as the back gate electrode 118 described in the text.

[0142] Next, along with Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C Let's refer to each other. Figure 18 , Figure 19A , Figure 19B , Figure 19C , Figure 20 , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C Examples of methods for forming semiconductor devices according to embodiments of the present invention will be described. Figure 18 , Figure 19A , Figure 19B , Figure 19C , Figure 20 , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C middle, Figure 18 and Figure 20 It is shown by Figure 5B The plan view of the area indicated by "D" in the diagram. Figure 19A , Figure 21A , Figure 22A , Figure 23A and Figure 24A It shows along Figure 6A and Figure 6C A cross-sectional view of the area intercepted by line I-I' in the diagram, and Figure 19B , Figure 21B , Figure 22B , Figure 23B and Figure 24B It shows along Figure 6A and Figure 6C A cross-sectional view of the area intercepted by line II-II' in the diagram, and Figure 19C , Figure 21C , Figure 22C , Figure 23C and Figure 24CIt is along Figure 6A and Figure 6C A cross-sectional view of the area intercepted by line III-III'. The following description will focus on the method of forming the aforementioned elements. Since the arrangement or shape of the aforementioned elements can be understood from the above, its description may be omitted.

[0143] Together Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C Let's refer to each other. Figure 18 , Figure 19A , Figure 19B and Figure 19C A sacrificial insulating layer 6 can be formed on the substrate 3. A semiconductor layer 7 can be formed on the sacrificial insulating layer 6. The semiconductor layer 7 can be formed in the aforementioned memory cell array region ( Figure 2 , Figure 3 , Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C MCA in the middle) and interface area ( Figure 2 , Figure 3 , Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C In IF1, IF2 and IF3).

[0144] The semiconductor layer 7 can be patterned to form an opening 8 that spans the memory cell array region MCA and the first interface region IF1 and extends into the third interface region IF3. The opening 8 can penetrate the semiconductor layer 7 and expose the sacrificial insulating layer 6.

[0145] Each of the openings 8 may extend in a first horizontal direction X. The openings 8 may be spaced apart from each other in a second horizontal direction Y.

[0146] Each of the openings 8 may include a first portion 8a having a first width in the second horizontal direction Y, and a second portion 8b and a third portion 8c having a second width in the second horizontal direction Y that is less than the first width.

[0147] In each of the openings 8, a first portion 8a may be formed in the memory cell array region MCA, a second portion 8b may be formed in the middle region of each first interface region IF1, and a third portion 8c may be formed in the region of a third interface region IF3 corresponding to the middle region of the first interface region IF1. In each of the openings 8, the first portion 8a may extend across the memory cell array region MCA to the second portion 8b and the third portion 8c.

[0148] In this embodiment, the middle region of each first interface region IF1 may be the middle region of the first interface region IF1 described above ( Figure 6B (IF1c in the text).

[0149] Together Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C Let's refer to each other. Figure 20 , Figure 21A , Figure 21B and Figure 21C Back gate structures 15, 17, and 21 can be formed in the opening 8. Forming each of the back gate structures 15, 17, and 21 may include: forming a back gate dielectric layer 15 that fills and conformally covers the first portion 8a of the opening 8, filling the second portion 8b and the third portion 8c of the opening 8; forming a conductive layer on the back gate dielectric layer 15; partially etching the conductive layer to form an initial back gate electrode 17 in the first portion 8a; and forming a first insulating back gate overlay pattern 21 on the initial back gate electrode 17. The initial back gate electrode 17 may not be formed in the second portion 8b and the third portion 8c of the opening 8.

[0150] Together Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C Let's refer to each other. Figure 22A , Figure 22B and Figure 22C The semiconductor layer 7 can be patterned to form an active pattern 9. As described above, the active pattern 9 may include cell active patterns 9a disposed in the memory cell array region MCA and dummy active patterns 9b disposed in the first interface region IF1 and the third interface region IF3.

[0151] Gate structures 24, 26, 29 and 30 can be formed on the side surface of the combination of active pattern 9 and back gate structures 15, 17 and 21.

[0152] Forming gate structures 24, 26, 29 and 30 may include: sequentially forming a unit gate dielectric layer 24 that conformally covers the active pattern 9 and the back gate structures 15, 17 and 21, and an initial gate layer that conformally covers the unit gate dielectric layer 24; forming an insulating layer on the initial gate layer; planarizing the insulating layer to form an insulating pattern 30; partially etching the initial gate layer exposed by the insulating pattern 30 to form an initial gate electrode 26; and forming a first insulating gate cover pattern 29 on the initial gate electrode 26.

[0153] Together Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C Let's refer to each other. Figure 23A , Figure 23B and Figure 23C A contact structure 48 and an insulating structure 51 can be formed. The contact structure 48 can be connected to the cell active pattern 9a. Each of the contact structures 48 can include a first material layer 42 and a second material layer 45 located on the first material layer 42. The first material layer 42 can include a material such as doped silicon. The second material layer 45 can include at least one of a metal, a metal nitride, or a metal semiconductor compound. The insulating structure 51 can surround the side surface of the contact structure 48.

[0154] An insulating etch stop layer 61 can be formed on the contact structure 48 and the insulating structure 51. A data storage structure DS can be formed. The data storage structure DS may include: a first electrode 63a that penetrates the insulating etch stop layer 61, is connected to the contact structure 48, and extends upward; a dielectric layer 63b that covers the first electrode 63a and the etch stop layer 61; and a second electrode 63c that covers the dielectric layer 63b.

[0155] A first upper insulating layer 66 may be formed on the data storage structure DS and the insulating etch stop layer 61. An upper contact plug 69 may be formed through the first upper insulating layer 66. An upper interconnect 77 may be formed on the first upper insulating layer 66 and the upper contact plug 69. A second upper insulating layer 86 may be formed on the first upper insulating layer 66 and the upper interconnect 77.

[0156] Together Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C Let's refer to each other. Figure 24A , Figure 24B and Figure 24C After positioning the substrate 3 face up, the substrate 3 and the sacrificial insulating layer 6 can be removed. With the sacrificial insulating layer 6 removed, the active pattern 9 can be exposed. Subsequently, the upper surfaces of the initial back gate electrode 17 and the initial gate electrode 26 can be exposed.

[0157] The initial back gate electrode 17 and the initial gate electrode 26 can be partially etched to form the back gate electrode 18 and the word line 27. Insulating overlay patterns 88a and 88b can be formed on the back gate electrode 18 and the word line 27. The insulating overlay patterns 88a and 88b may include a second insulating gate overlay pattern 88b on the word line 27 and a second insulating back gate overlay pattern 88a on the back gate electrode 18.

[0158] A back gate contact plug BGC can be formed that extends through the second insulating back gate cover pattern 88a and is connected to the back gate electrode 18.

[0159] Bit lines 90 and back gate interconnect (BGI) structures can be formed. Forming bit lines 90 and back gate interconnect (BGI) structures can include: sequentially stacking a first material layer 90a, a second material layer 90b, and a third material layer 90c; forming an insulating overlay pattern 91 on the third material layer 90c; using the overlay pattern 91 as an etching mask to perform an etching process; and patterning the first material layer 90a, the second material layer 90b, and the third material layer 90c.

[0160] Refer again Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8 and Figure 9 An insulating pad 92 can be formed, which conformally covers structures 90, BGI, and 91, including bit lines 90, back gate interconnect structure BGI, and overlay pattern 91. A bit line shielding pattern 93 can be formed on the insulating pad 92. The bit line shielding pattern 93 can be formed between the bit lines 90 and on the overlay pattern 91 on the bit lines 90. Subsequently, a first lower insulating layer 94 can be formed covering the bit line shielding pattern 93 and the insulating pad 92. In the second interface region IF2, rear contact plugs 95a and 95b can be formed through the first lower insulating layer 94, the insulating pad 92, and the overlay pattern 91. The rear contact plugs 95a and 95b can include a first rear contact plug 95a connected to the bit line 90 and a second rear contact plug 95b connected to the back gate interconnect structure BGI.

[0161] In the first interface region IF1 and the third interface region IF3, a word line contact plug WLC can be formed, which penetrates the first lower insulating layer 94, the insulating pad 92 and the second insulating gate cover pattern 88b and is connected to the word line 27.

[0162] Rear interconnects 96a, 96b, and WLI can be formed on the first lower insulating layer 94. The rear interconnects 96a, 96b, and WLI may include: a first rear interconnect 96a connected to a first rear contact plug 95a; a second rear interconnect 96b connected to a second rear contact plug 95b; and a third rear interconnect WLI connected to a word line contact plug WLC.

[0163] A second lower insulating layer 98 covering the interconnects 96a, 96b and WLI can be formed on the first lower insulating layer 94.

[0164] According to an embodiment, in each memory cell region, each word line can span multiple memory cell array regions arranged along a first horizontal direction and an interface region located between the multiple memory cell array regions. In this way, since the space occupied by the interface region in each memory cell region can be minimized, the integration density of the semiconductor device can be improved.

[0165] According to an embodiment, since each word line WL spanning each memory cell array region is electrically connected to two word line contact plugs arranged on both sides, the transmission speed of the signal applied to the entire word line can be increased. Therefore, the performance of the semiconductor device can be improved.

[0166] According to an embodiment, a back gate electrode can be provided facing the channel region of the cell transistor. The back gate electrode can suppress or prevent the performance of the cell transistor from deteriorating due to the floating body effect.

[0167] The various beneficial advantages and effects of the present invention are not limited to those described above, and can be more easily understood by describing specific embodiments of the present invention.

[0168] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that variations and modifications may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A first memory cell array region and a second memory cell array region are spaced apart from each other in a first horizontal direction; A first interface region, which is located between the first storage cell array region and the second storage cell array region; The first word line and the second word line cross the first memory cell array region, the first interface region and the second memory cell array region, and are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction. A first back gate electrode is located between the first word line and the second word line in the first memory cell array region and extends into the first interface region; as well as A first back gate dielectric layer is located between the first word line and the second word line, and spans the first memory cell array region, the first interface region, and the second memory cell array region. The first back gate dielectric layer includes a first portion and a second portion. The first portion is located between the first word line and the first back gate electrode in the first memory cell array region, and the second portion is located between the second word line and the first back gate electrode in the first memory cell array region.

2. The semiconductor device according to claim 1, wherein, The first back gate electrode has a first end in the first horizontal direction in the first interface region, and The first back gate dielectric layer covers the first end of the first back gate electrode in the first interface region.

3. The semiconductor device of claim 2, further comprising a second back gate electrode, the second back gate electrode being located between the first word line and the second word line in the second memory cell array region and extending into the first interface region. in, The first back gate dielectric layer further includes a third portion and a fourth portion, wherein the third portion is located between the first word line and the second back gate electrode in the second memory cell array region, and the fourth portion is located between the second word line and the second back gate electrode in the second memory cell array region. The second back gate electrode has a second end in the first interface region, the second end facing the first end of the first back gate electrode, and The first back gate dielectric layer covers the second end of the second back gate electrode in the first interface region.

4. The semiconductor device according to claim 1, further comprising: The first cell active pattern is located in the first memory cell array region between the first word line and the first back gate dielectric layer. The second active pattern is located in the first memory cell array region between the second word line and the first back gate dielectric layer. The third active pattern is located in the second memory cell array region between the first word line and the first back gate dielectric layer; as well as The fourth active pattern is located in the second memory cell array region between the second word line and the first back gate dielectric layer.

5. The semiconductor device according to claim 4, further comprising: The first unit gate dielectric layer is in contact with the first word line; as well as The second unit gate dielectric layer is in contact with the second word line. Wherein, the first cell active pattern is located in the first memory cell array region between the first cell gate dielectric layer and the first back gate dielectric layer, and The second cell active pattern is located between the second cell gate dielectric layer and the first back gate dielectric layer in the first memory cell array region.

6. The semiconductor device according to claim 5, wherein, The first cell gate dielectric layer extends from the portion located between the first cell active pattern and the first word line to the portion located between the first cell active patterns adjacent to each other in the first horizontal direction, and The second cell gate dielectric layer extends from the portion located between the second cell active pattern and the second word line to the portion located between the second cell active patterns that are adjacent to each other in the first horizontal direction.

7. The semiconductor device according to claim 4, further comprising: The first dummy active pattern is located in the first interface region between the first word line and the first back gate dielectric layer; as well as The second dummy active pattern is located in the first interface region between the second word line and the first back gate dielectric layer. Wherein, the first dummy active pattern and the second dummy active pattern face each other in the second horizontal direction, and In the first horizontal direction, the length of each of the first dummy active pattern and the second dummy active pattern is greater than the length of each of the first unit active pattern and the second unit active pattern.

8. The semiconductor device according to claim 7, further comprising: A back-gate contact plug is connected to the portion of the first back-gate electrode located between the first dummy active pattern and the second dummy active pattern.

9. The semiconductor device according to claim 8, further comprising: The first word line contact plug is located in the first interface area and connected to the first word line; as well as The second word line contact plug is located in the first interface area and is connected to the second word line.

10. The semiconductor device of claim 1, further comprising: A third storage cell array region, which is spaced apart from the first storage cell array region in the second horizontal direction; as well as The second interface region is located between the third storage cell array region and the first storage cell array region. The third storage cell array region includes a fifth active pattern, and The distance between the first storage cell array region and the second storage cell array region is greater than the distance between the first storage cell array region and the third storage cell array region.

11. The semiconductor device of claim 10, further comprising: The first bit line extends in the second horizontal direction, crosses the first memory cell array region, and extends into the second interface region; as well as The second bit line extends in the second horizontal direction, crosses the second memory cell array region, extends into the second interface region, is spaced apart from the first bit line, and has an end facing the end of the first bit line.

12. A semiconductor device, the semiconductor device comprising: A first memory cell array region and a second memory cell array region are spaced apart from each other in a first horizontal direction; A first interface region, which is located between the first storage cell array region and the second storage cell array region; as well as Word lines, which span the first memory cell array region, the first interface region, and the second memory cell array region, and are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction. The word lines include first and second word lines that are adjacent to each other, and The minimum distance between the first word line and the second word line in the first storage cell array region is greater than the minimum distance between the first word line and the second word line in the first interface region.

13. The semiconductor device according to claim 12, wherein, The first character line and the second character line include: The first part is located in the first storage cell array region and faces each other; The second part is located in the first storage cell array region and faces each other; The third part is located in the first interface area and faces each other; The fourth part, located in the first interface area and facing each other; and The fifth part, located in the first interface area and facing each other, Wherein, the spacing between the first parts is greater than the spacing between the second parts, and The spacing between the third part, the spacing between the fourth part, and the spacing between the fifth part are different from each other.

14. The semiconductor device according to claim 13, wherein, The spacing between the third parts is greater than the spacing between the fourth parts. The spacing between the fourth parts is greater than the spacing between the fifth parts.

15. The semiconductor device according to claim 14, wherein, The spacing between the fifth parts is smaller than the spacing between the second parts.

16. The semiconductor device of claim 13, further comprising: The first back gate electrode is located between the first word line and the second word line. The first back gate electrode includes: A first back gate portion, the first back gate portion passing through the spaces between the first portions and the spaces between the second portions in the first memory cell array region; The second back grille portion is located between the third portions in the first interface region; and The third back grille portion is located between the fourth portions in the first interface region, and The first back gate electrode is not located between the fifth portions of the first interface region.

17. The semiconductor device according to claim 16, wherein, The first back grid portion, the second back grid portion, and the third back grid portion have the same width.

18. The semiconductor device according to claim 16, wherein, The width of the second back gate portion is greater than the width of each of the first back gate portion and the third back gate portion.

19. A semiconductor device, said semiconductor device comprising: A first structure, the first structure including a first storage area, the first storage area including storage cells; as well as The second structure includes a second memory region, which in turn includes peripheral circuitry. The second structure overlaps perpendicularly with the first structure. The first storage area includes: A first memory cell array region and a second memory cell array region are spaced apart from each other in a first horizontal direction; A first interface region, located between the first storage cell array region and the second storage cell array region; and A first word line and a second word line, the first word line and the second word line spanning the first memory cell array region, the first interface region and the second memory cell array region, and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and Wherein, the minimum distance between the first word line and the second word line in the first storage cell array region is greater than the minimum distance between the first word line and the second word line in the first interface region.

20. The semiconductor device according to claim 19, wherein, The first structure and the second structure further include a wiring interconnect structure, the wiring interconnect structure electrically connecting the first memory region and the second memory region. The first storage area further includes: A first back gate electrode, located between the first word line and the second word line in the first memory cell array region, and extending into the first interface region; and A first back-gate dielectric layer is located between the first word line and the second word line and spans the first memory cell array region, the first interface region, and the second memory cell array region. The first back gate dielectric layer includes a first portion and a second portion. The first portion is located between the first word line and the first back gate electrode in the first memory cell array region, and the second portion is located between the second word line and the first back gate electrode in the first memory cell array region.

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