memory cells, integrated circuits, memories, logic chips, and electronic devices

Abstract

This application provides a memory cell, integrated circuit, memory, logic chip, and electronic device. The memory cell includes: a substrate; a first gate oxide layer and a control gate, wherein the first gate oxide layer is disposed on one side of the substrate along the thickness direction, and the control gate is disposed on the side of the first gate oxide layer opposite to the substrate; a second gate oxide layer and a floating gate; the second gate oxide layer is disposed on the substrate and is located on the same side of the substrate along the thickness direction as the first gate oxide layer, and the second gate oxide layer and the first gate oxide layer are spaced apart along the length direction of the substrate; the floating gate is disposed on the side of the second gate oxide layer opposite to the substrate; wherein the first gate oxide layer includes a first dielectric layer, and the dielectric constant of the first dielectric layer is greater than 16. Using this memory cell can solve the problem of using multiple masks in existing Flash memories because the memory cell has a multi-layer vertical structure, which helps to reduce the cost of the memory.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and more particularly to a storage unit, integrated circuit, memory, logic chip, and electronic device. Background Technology

[0002] Memory, as a crucial function in chips, has always received widespread attention. There are various types of memory, which can be categorized based on their storage principles, including electrical, magnetic, phase-change, and resistive memory. Electrical memory is the most widely used. Based on electricity, and depending on the charge storage medium and wafer fabrication process, memory can be further subdivided into Flash memory, SONOS (Silicon-Oxide-Nitride-Oxide-Silicon memory), and Logic NVM (Logic Non-Volatile Memory), among others. Flash memory, in particular, has a multi-layered vertical structure, requiring multiple masks during fabrication, making the process complex and costly. Summary of the Invention

[0003] The purpose of this application is to provide a storage unit, integrated circuit, memory, logic chip, and electronic device. Using this storage unit can solve the problem that existing Flash memories require multiple MASK layers due to the multi-layer vertical structure of the storage unit, thereby reducing the cost of the memory.

[0004] This application embodiment provides a storage unit, the storage unit comprising:

[0005] Substrate;

[0006] The first gate oxide layer and the control gate are disposed along the thickness direction of the substrate. The first gate oxide layer is disposed on one side of the substrate, and the control gate is disposed on the side of the first gate oxide layer away from the substrate.

[0007] A second gate oxide layer and a floating gate; the second gate oxide layer is disposed on the substrate and is located on the same side of the substrate along the thickness direction as the first gate oxide layer. The second gate oxide layer and the first gate oxide layer are spaced apart along the length direction of the substrate. The floating gate is disposed on the side of the second gate oxide layer away from the substrate.

[0008] The first gate oxide layer includes a first dielectric layer, and the dielectric constant of the first dielectric layer is greater than 16.

[0009] In the memory cell provided in this application embodiment, by disposing the first gate oxide layer and the second gate oxide layer on the same side of the substrate along the thickness direction and spaced apart along the length direction of the substrate, and by disposing the control gate on the side of the first gate oxide layer away from the substrate and the floating gate on the side of the second gate oxide layer away from the substrate, a structure in which the control gate and the floating gate are arranged horizontally in the lateral direction of the memory cell is formed, that is, a horizontally structured memory cell is formed. This solves the problem that existing Flash memories need to use multiple MASKs because the memory cell is a multi-layer vertical structure, and reduces the cost of the memory.

[0010] Furthermore, by providing a first dielectric layer with a high dielectric constant in the first gate oxide layer, the dielectric constant of the first gate oxide layer is increased, thereby increasing the capacitance per unit area of ​​the control gate. This allows for a reduction in the size of the memory cell by decreasing the area of ​​the control gate, which is beneficial for reducing the overall size of the memory.

[0011] In one possible implementation, the first gate oxide layer includes a first oxide layer and a first dielectric layer stacked sequentially, the first oxide layer being disposed on a substrate, the first dielectric layer being disposed on the side of the first oxide layer facing away from the substrate, and the control gate being disposed on the side of the first dielectric layer facing away from the first oxide layer.

[0012] Alternatively, the first gate oxide layer can be a first dielectric layer, which is disposed on the substrate, and the control gate is disposed on the side of the first dielectric layer away from the substrate. By setting the first gate oxide layer as a single-layer first dielectric layer, the increase in capacitance brought by the first dielectric layer will not be diluted, and the increase in capacitance is significant, thereby significantly improving the capacitance value per unit area of ​​the control gate, and thus significantly reducing the size of the memory cell.

[0013] Alternatively, the first gate oxide layer includes a first oxide layer, a first transition layer, and a first dielectric layer stacked sequentially. The first oxide layer is disposed on a substrate, the first transition layer is disposed on the side of the first oxide layer away from the substrate, the first dielectric layer is disposed on the side of the first transition layer away from the first oxide layer, and the control gate is disposed on the side of the first dielectric layer away from the first transition layer. The material of the first transition layer includes the material of the first oxide layer and the material of the first dielectric layer. From the first oxide layer to the first dielectric layer, the content of the material of the first oxide layer in the first transition layer gradually decreases, and the content of the material of the first dielectric layer gradually increases.

[0014] Alternatively, the first gate oxide layer includes a first dielectric layer and a first oxide layer stacked sequentially, the first dielectric layer being disposed on the substrate, the first oxide layer being disposed on the side of the first dielectric layer away from the substrate, and the control gate being disposed on the side of the first oxide layer away from the first dielectric layer.

[0015] Alternatively, the first gate oxide layer includes a first dielectric layer, a first transition layer, and a first oxide layer stacked sequentially. The first dielectric layer is disposed on a substrate, the first transition layer is disposed on the side of the first dielectric layer away from the substrate, the first oxide layer is disposed on the side of the first transition layer away from the first dielectric layer, and the control gate is disposed on the side of the first oxide layer away from the first transition layer. The material of the first transition layer includes the material of the first oxide layer and the material of the first dielectric layer. From the first oxide layer to the first dielectric layer, the content of the material of the first oxide layer in the first transition layer gradually decreases, and the content of the material of the first dielectric layer gradually increases.

[0016] In one possible implementation, the thickness of the first dielectric layer is 1 nm to 2 nm. The high dielectric constant of the first dielectric layer has a strong ability to bind electrons, and even a thinner first dielectric layer can ensure that the first gate oxide layer is not broken down.

[0017] In one possible implementation, the material of the first dielectric layer includes HfO2. As the thickness of the first dielectric layer decreases, the recrystallization temperature of the HfO2 material increases from 500°C to 700°C, thereby significantly reducing the degree of recrystallization of the material when using the same atomic layer deposition (ALD) process. This avoids long-distance Coulomb scattering caused by recrystallization, which leads to a decrease in electronic activity and ensures the performance of the memory.

[0018] In one possible implementation, the second gate oxide layer includes a second dielectric layer, wherein the dielectric constant of the material of the second dielectric layer is less than 3.

[0019] By including a second dielectric layer with a low dielectric constant in the second gate oxide layer, the dielectric constant of the second gate oxide layer is reduced, thereby reducing the capacitance per unit area of ​​the floating gate and increasing the proportion of capacitance of the control gate, which in turn improves the coupling coefficient. On the one hand, when the charge of the floating gate remains constant, the increase in coupling coefficient reduces the voltage applied to the control gate. That is, during data writing, the voltage of the control gate is reduced, which helps improve the long-term reliability of the first gate oxide layer below the control gate, thereby improving the lifespan of the memory cell and the long-term reliability of the memory. At the same time, it reduces the write voltage requirement, achieving the goal of completing data writing at a relatively low control gate voltage.

[0020] On the other hand, when the voltage of the control gate remains constant, the increase in coupling coefficient can increase the voltage of the second gate oxide layer, that is, the voltage formed on the floating gate is increased, so as to increase the electric field strength of the second gate oxide layer, which in turn increases the amount of electricity written to the floating gate within a certain time. As a result, the data writing speed (current) within the range that the second gate oxide layer can withstand will be significantly improved by the influence of the electric field strength, thereby improving the data writing speed of the memory cell and improving the data writing efficiency.

[0021] In one possible implementation, the second gate oxide layer includes a second oxide layer and a second dielectric layer, with the second oxide layer disposed between the substrate and the second dielectric layer, and the floating gate disposed on the side of the second dielectric layer opposite to the second oxide layer. A low dielectric constant leads to a decrease in the charge-binding ability of the second dielectric layer, making it prone to additional leakage or data loss. By adding a second oxide layer and placing it between the substrate and the second dielectric layer, the risk of leakage and data loss can be reduced. Furthermore, the high lattice matching between the second oxide layer and the substrate can alleviate stress caused by lattice distortion during processing, thereby ensuring the integrity of the second oxide layer and thus guaranteeing the performance of the memory cell.

[0022] In one possible implementation, the second gate oxide layer further includes a second transition layer, which is disposed between the second oxide layer and the second dielectric layer;

[0023] The material of the second transition layer includes the material of the second oxide layer and the material of the second dielectric layer. From the second oxide layer to the second dielectric layer, the content of the material of the second oxide layer in the second transition layer gradually decreases, and the content of the material of the second dielectric layer gradually increases.

[0024] By using a second transition layer in the second gate oxide layer, a gradient change in the material of the second dielectric layer in the second gate oxide layer can be achieved, thereby reducing interface defects generated between the second oxide layer and the second dielectric layer, preventing interface defects from trapping electrons and causing threshold voltage fluctuations, ensuring the floating gate's ability to retain data and low leakage current, and thus improving the performance of the memory cell.

[0025] In one possible implementation, the thickness of the second gate oxide layer is greater than that of the first gate oxide layer, which can significantly reduce the capacitance of the floating gate and increase the proportion of the capacitance of the control gate, thereby improving the coupling coefficient. This enables data writing to be completed at a relatively low control gate voltage, and also increases the charge in the floating gate at the same control gate voltage, thereby improving the data writing speed of the memory cell.

[0026] This application also provides an integrated circuit, which includes one or more memory cells as described above.

[0027] This application embodiment also provides a memory, which includes a controller and one or more storage units as described above, the controller being used to control access to the storage units.

[0028] This application also provides a logic chip, which includes a circuit board and a memory as described above, with the memory integrated on the circuit board.

[0029] This application also provides an electronic device, which includes a processor and a memory as described above, the processor being used to access the memory; or the electronic device includes a processor and a logic chip as described above, the processor being used to access the memory in the logic chip. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of an existing Flash memory.

[0032] Figure 2 This is a schematic diagram of the structure of a memory applied to an electronic device according to an embodiment of this application;

[0033] Figure 3 This is a schematic diagram of the structure of a memory applied to a logic chip according to an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of the memory structure provided in an embodiment of this application;

[0035] Figure 5 for Figure 4 A schematic diagram of the storage cell in the memory in the first embodiment is shown.

[0036] Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure of the storage cell shown;

[0037] Figure 7 for Figure 4 A schematic cross-sectional view of the storage cell in the memory in the second embodiment;

[0038] Figure 8 for Figure 4 A schematic diagram of the cross-sectional structure of the storage cell in the memory in the third embodiment is shown;

[0039] Figure 9 for Figure 4 The diagram shows a cross-sectional view of the storage cell in the memory in the fourth embodiment.

[0040] Figure 10 for Figure 4 The diagram shows a cross-sectional view of the storage cell in the memory in the fifth embodiment.

[0041] Figure 11 for Figure 4 A schematic diagram of the cross-sectional structure of the storage cell in the memory shown in the sixth embodiment;

[0042] Figure 12 for Figure 4 A schematic cross-sectional view of the memory cell in the seventh embodiment shown;

[0043] Figure 13 for Figure 4 The diagram shows a cross-sectional view of the storage cell in the memory in the eighth embodiment.

[0044] Figure 14 for Figure 4 A schematic cross-sectional view of the memory cell in the ninth embodiment is shown.

[0045] Figure 15 for Figure 4 The diagram shows a structural schematic of the storage cell in the tenth embodiment of the memory.

[0046] Figure 16 for Figure 15 The diagram shows a cross-sectional view of the storage cell. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] See Figure 1 , Figure 1 This is a schematic diagram of the existing Flash memory 500.

[0049] like Figure 1As shown, in the cell structure of a Flash memory 500 formed using Flash technology (a non-volatile memory technology), an oxide layer 530, a floating gate 90, an intermediate layer 540, and a control gate 50 are sequentially stacked on the source 510 and drain 520. Exemplarily, the oxide layer 530 is a SiO2 layer. The floating gate 90 is disposed on the oxide layer 530. The floating gate 90 is a polysilicon layer. The intermediate layer 540 includes a first layer 541, a second layer 542, and a third layer 543 sequentially stacked on the floating gate 90. The first layer 541 is a SiO2 layer, the second layer 542 is a Si3N4 layer, and the third layer 543 is a SiO2 layer. The control gate 50 is disposed on the side of the intermediate layer 540 opposite to the floating gate 90, and the control gate 50 is a polysilicon layer.

[0050] from Figure 1 As can be seen, the existing Flash Memory 500 has a multi-layer vertical cell structure, with the intermediate layer 540 between the control gate 50 and the floating gate 90 using ONO (SiO2 / Si3N4 / SiO2) for insulation. This type of Flash Memory 500 has high vertical structure density and fast read / write speeds, but compared to traditional CMOS (Complementary Metal Oxide Semiconductor) processes which require more than five mask layers, the cost increases by more than 50%. Furthermore, the Flash Memory 500 formed using Flash technology only has storage functionality and is incompatible with logic areas, meaning it cannot be used to form logic chips.

[0051] As chip technology becomes increasingly integrated, there is a growing desire to integrate simple storage functions—OTP (One-Time Programmable) and MTP (Multiple-Time Programmable)—onto logic chips, i.e., to implement storage functions using CMOS technology. To address this, this application provides an embodiment of a memory 300, which is an LNVM (Logic Non-Volatile Memory). Information stored in the memory 300 is typically represented as either "logic 0" or "logic 1".

[0052] Please refer to the following: Figure 2 , Figure 3 and Figure 4 , Figure 2This is a schematic diagram of the structure of the memory 300 provided in the embodiments of this application applied to the electronic device 1. Figure 3 This is a schematic diagram of the structure of the memory 300 applied to the logic chip 2 according to an embodiment of this application. Figure 4 This is a schematic diagram of the structure of the memory 300 provided in an embodiment of this application.

[0053] This application provides an electronic device 1, which can be a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products can include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle high-density digital video discs (DVDs), etc. Financial terminal products can include automated teller machines (ATMs), self-service terminals, etc. Communication electronics products can include communication equipment such as servers, radar, and base stations.

[0054] For example, such as Figure 2 As shown, electronic device 1 includes a processor 100 and a memory 300. The processor 100 is used to access the memory 300 to write data to or read data from the memory 300. For example, the processor 100 may be the central processing unit (CPU) of electronic device 1.

[0055] This application embodiment also provides a logic chip 2, which includes a circuit board 400 and the aforementioned memory 300, with the memory 300 disposed on the circuit board 400. There may be multiple memories 300, including a first memory 310 and a second memory 330. For example, the first memory 310 is an OTP (One-Time Programmable) memory, and the second memory 330 is an MTP (Multiple-Time Programmable) memory, to integrate the functions of the OTP and MTP memories into the logic chip 2. It is understood that in some embodiments, the electronic device 1 may also include a processor 100 and the logic chip 2, with the processor 100 used to access the memory 300 in the logic chip 2.

[0056] The memory 300 includes a memory array and a controller 303, or the memory 300 includes a memory circuit and a controller 303. The memory array or memory circuit includes one or more memory cells 301. The controller controls access to the memory cells 301, writes data to the memory cells 301, erases data, and reads data from the memory cells 301, thereby enabling write-erase and read operations on the memory array or memory circuit. For example, the memory array includes multiple memory cells 301 arranged in an array.

[0057] Based on the storage unit 301 provided in the embodiments of this application, the embodiments of this application also provide an integrated circuit (IC) including one or more storage units 301. The specific structure of the storage unit 301 will be described below.

[0058] See Figure 5 and Figure 6 , Figure 5 for Figure 4 The diagram shows the structure of storage cell 301 in the first embodiment of the memory 300. Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure of the storage unit 301 shown.

[0059] For ease of description, the following definitions are provided. Figure 5 The length direction of the storage cell 301 shown is the X-axis direction, the width direction is the Y-axis direction, and the thickness direction is the Z-axis direction. The X-axis, Y-axis, and Z-axis directions are all perpendicular to each other. When describing the storage cell 301 in this application embodiment, the vertical direction mentioned is the Z-axis direction, and the horizontal direction is the plane direction formed by the X-axis and Y-axis. This does not constitute a limitation on the storage cell 301 in actual application scenarios.

[0060] Specifically, the memory cell 301 includes a substrate 10, a first gate oxide layer 30, a control gate 50, a second gate oxide layer 70, and a floating gate 90.

[0061] The substrate 10 can be a silicon substrate, an epitaxial silicon substrate, a silicon Germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. In this embodiment, the substrate 10 is a p-type silicon substrate.

[0062] The substrate 10 includes a first substrate region 11 and a second substrate region 13. The first substrate region 11 and the second substrate region 13 are spaced apart along the length of the substrate 10. In this embodiment, the first substrate region 11 is the source region, and the second substrate region 13 is the drain region, which are spaced apart along the X-axis. For example, the source and drain regions can be formed by p-type doping in the substrate 10. For example, the p-type doping element can be boron (B).

[0063] In this embodiment, the substrate 10 includes a first surface 15 and a second surface 17 disposed opposite to each other along the thickness direction. In this embodiment, the first surface 15 is the surface of the substrate 10 facing the negative Z-axis direction, and the second surface 17 is the surface of the substrate 10 facing the positive Z-axis direction. In this embodiment, the substrate 10 may further include a first doped well 101 and a second doped well 103, which are spaced apart from each other. In this embodiment, the first doped well 101 and the second doped well 103 are both n-wells, which can be obtained by forming an n-type doped region on a p-type substrate. The first doped well 101 and the second doped well 103 are spaced apart along the X-axis direction, and both the first doped well 101 and the second doped well 103 are doped from the second surface 17 of the substrate 10 towards the first surface 15. The first doped well 101 is located on one side of the positive X-axis direction, and the second doped well 103 is located on one side of the negative X-axis direction. In this embodiment, the first substrate region 11 and the second substrate region 13 are both located within the second doped well 103.

[0064] The first gate oxide layer 30 is disposed on one side of the substrate 10 along the thickness direction. In this embodiment, the first gate oxide layer 30 is disposed on the second surface 17 of the substrate 10 and located on one side of the first doped well 101 along the positive Z-axis. The projection of the first doped well 101 onto the first gate oxide layer 30 covers the first gate oxide layer 30. The control gate 50 is disposed on the side of the first gate oxide layer 30 opposite to the substrate 10. Exemplarily, the material of the control gate 50 is polysilicon.

[0065] The second gate oxide layer 70 is disposed on the substrate 10 and is located on the same side of the substrate 10 along the thickness direction as the first gate oxide layer 30, and is spaced apart along the length direction of the substrate 10. In this embodiment, the second gate oxide layer 70 and the first gate oxide layer 30 are spaced apart along the X-axis direction. The first gate oxide layer 30 is located on the side of the positive X-axis direction, and the second gate oxide layer 70 is located on the side of the negative X-axis direction. In this embodiment, the second gate oxide layer 70 is disposed on the second surface 17 of the substrate 10 and is located on the side of the second doped well 103 along the positive Z-axis direction, and the projection of the second doped well 103 onto the second gate oxide layer 70 covers the second gate oxide layer 70. A floating gate 90 is disposed on the side of the second gate oxide layer 70 away from the substrate 10, so that the floating gate 90 and the control gate 50 are arranged sequentially along the horizontal direction of the memory cell 301. For example, the material of the floating gate 90 is polysilicon.

[0066] In this embodiment, the memory cell 301 further includes an STI (shallow trench isolation) layer 91. The STI layer 91 is disposed on the substrate 10 and located between the first gate oxide layer 30 and the second gate oxide layer 70. The STI layer can be fabricated using existing processes, which will not be described in detail here.

[0067] When the memory cell 301 is operating, a voltage can be applied to the control gate 50, and then a voltage can be formed on the floating gate 90 through capacitive coupling. This allows electrons in the substrate 10 to migrate out from the second surface 17 of the substrate 10, pass through the second gate oxide layer 70, and enter and be stored in the floating gate 90, thereby storing electrons in the floating gate 90 and writing data into the memory cell 301. By changing the voltage on the floating gate 90, the electrons stored in the floating gate 90 can pass through the second gate oxide layer 70 to reach the substrate 10, thereby discharging the electrons stored in the floating gate 90 and erasing data from the memory cell 301. By applying a voltage difference between the source (S) and drain (D) of the memory cell 301 and reading the current of the memory cell 301, the presence or absence of electrons in the floating gate 90 affects the magnitude of the read current, which is then used to determine whether the data in the memory cell 301 is "logic 1" or "logic 0".

[0068] In the memory cell 301 of the memory 300 provided in this application embodiment, by disposing the first gate oxide layer 30 and the second gate oxide layer 70 on the same side of the substrate 10 along the thickness direction and spaced apart along the length direction of the substrate 10, and by disposing the control gate 50 on the side of the first gate oxide layer 30 away from the substrate 10 and the floating gate 90 on the side of the second gate oxide layer 70 away from the substrate 10, a structure in which the control gate 50 and the floating gate 90 are arranged in the horizontal direction is formed in the lateral direction of the memory cell 301, that is, a horizontal structure memory cell 301 is formed. This solves the problem that existing Flash memory 500 requires the use of multiple MASKs because the memory cell is a multi-layer vertical structure, and reduces the cost of the memory 300.

[0069] Furthermore, existing Flash memory technologies use two polysilicon layers, while traditional CMOS technologies only use a single gate (polysilicon) layer and lack an ONO isolation structure. Therefore, to achieve storage functionality, this embodiment incorporates a horizontally placed MOSCAP capacitor to control the voltage of the floating gate. This means the control gate and the floating gate are arranged horizontally along the memory cell, forming a structure as shown below. Figure 1 The image shows an LNVM memory with horizontally structured memory cells. However, this structure requires much larger memory cells. For example, using a 180nm process, the size of a typical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) memory cell is 0.2μm. 2 The size of a flash memory cell is 0.13μm. 2 (Vertical structure), while the storage cells of LNVM memory (horizontal structure) exceed 50μm. 2 This significantly increases the overall area of ​​the logic chip assembled from the memory, thus raising the cost of the logic chip.

[0070] To further address the size issue of storage cells in horizontally structured LNVM memories, this application, through research and analysis, controls the capacitance C of the gate 50. CG Reference Formula 1:

[0071] (Formula 1).

[0072] Among them, the capacitor C of the control gate 50 CG This refers to the capacitance formed between the control gate 50 and the substrate 10. A1 represents the area of ​​the control gate 50, and d1 represents the thickness of the first gate oxide layer 30. This represents the dielectric constant of the first gate oxide layer 30. It is understood that the dielectric constant of the first gate oxide layer 30 can also be represented by k.

[0073] As can be seen from Formula 1, the capacitance C of the control gate 50 is... CG The thickness d1 of the first gate oxide layer 30, the area A1 of the control gate 50, and the dielectric constant of the first gate oxide layer 30 between the control gate 50 and the substrate 10 are all affected by three factors. The thickness d of the first gate oxide layer 30 is influenced by the CMOS process and is typically a fixed value (3.3V IO 7mm). Here, 3.3V IO indicates that the first gate oxide layer 30 will break down at 3.3V. Therefore, the area A of the control gate 50 and the dielectric constant of the first gate oxide layer 30 are... The larger the value, the greater the capacitance C of the control gate 50. CG The larger the dielectric constant, that is, the higher the dielectric constant of the first gate oxide layer 30. This determines the capacitance per unit area of ​​the control gate 50.

[0074] Based on the above research and analysis, this application provides a feasible technical solution to reduce the area of ​​the memory cell 301 of the memory 300. Specifically, this application provides a memory cell 301 of the memory 300, wherein the first gate oxide layer 30 includes a first dielectric layer 33, and the dielectric constant of the first dielectric layer 33 is greater than 16. For example, the material of the first dielectric layer 33 can be TiN-ZAZ-TiN, Hf-doped ZrO2 (HZO) thin film, TiO2, Al-doped TiO2, perovskite SrTiO3 (STO), HfO2, or other high-k materials. This application does not limit the type of material of the first dielectric layer 33 and can choose according to the compatibility with CMOS and cost. Among them, ZAZ is a ZrO2-Al2O3-ZrO2 composite film, and the ZrO2 film is a tetragonal phase with a dielectric constant of approximately 47.

[0075] In the memory cell 301 of the memory 300 provided in this application embodiment, by adding a first dielectric layer 33 with a high dielectric constant to the first gate oxide layer 30, the dielectric constant of the first gate oxide layer 30 is increased, thereby increasing the capacitance value per unit area of ​​the control gate 50. In turn, the size of the memory cell 301 can be reduced by reducing the area A of the control gate 50, which is beneficial to reducing the overall size of the memory 300.

[0076] Specifically, in the memory cell 301 of the first embodiment, the first gate oxide layer 30 includes a first oxide layer 31 and a first dielectric layer 33. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10. The first dielectric layer 33 is disposed on the side of the first oxide layer 31 facing away from the substrate 10 and is located between the first oxide layer 31 and the control gate 50. In this embodiment, the first oxide layer 31 is a SiO2 layer. For example, the thickness of the first oxide layer 31 is 3 nm, and the thickness of the first dielectric layer 33 is 1 nm. The first dielectric layer 33 has a stronger electron-binding ability than the first oxide layer 31, thereby making the insulating effect of the first dielectric layer 33 better than that of the first oxide layer 31. In this embodiment, the first dielectric layer 33, which has a high dielectric constant, has a strong electron-binding ability, and the first dielectric layer 33 of about 1 nm and the 3 nm SiO2 layer are sufficient to ensure that the first gate oxide layer 30 is not broken down.

[0077] In the memory cell 301 of the first embodiment, the first gate oxide layer 30 includes a first oxide layer 31 and a first dielectric layer 33. The first dielectric layer 33 has a higher dielectric constant, which can improve the dielectric constant of the first gate oxide layer 30, thereby increasing the capacitance per unit area of ​​the memory cell 301. In this way, the memory cell 301 can be reduced in size by reducing the area A of the control gate 50.

[0078] It is understood that, since the first dielectric layer 33 has a relatively high electron binding capacity, in other embodiments, the positions of the first oxide layer 31 and the first dielectric layer 33 can also be interchanged. That is, the first gate oxide layer 30 may include the first dielectric layer 33 and the first oxide layer 31 stacked sequentially. The first dielectric layer 33 is disposed on the second surface 17 of the substrate 10, the first oxide layer 31 is disposed on the side of the first dielectric layer 33 away from the substrate 10, and the control gate 50 is disposed on the side of the first oxide layer 31 away from the first dielectric layer 33.

[0079] See Figure 7 , Figure 7 for Figure 4 The memory cell 301 in the memory 300 shown is a cross-sectional structural diagram of the second embodiment.

[0080] The difference between the storage cell 301 in the second embodiment and the storage cell 301 in the first embodiment is that the first gate oxide layer 30 of the storage cell 301 in the second embodiment does not contain a SiO2 layer.

[0081] This application also found that, according to the capacitance series calculation formula (Formula 2), the increase in capacitance brought about by the first dielectric layer 33 with a high dielectric constant in the first gate oxide layer 30 of the memory cell 301 of the first embodiment will be greatly diluted by the first oxide layer 31 (SiO2 layer), and the capacitance will decrease by about 96%.

[0082] (Formula 2).

[0083] Wherein, C represents the capacitance of the first gate oxide layer 30, C1 represents the capacitance of the first dielectric layer 33, and C2 represents the capacitance of the first oxide layer 31.

[0084] Therefore, this application embodiment also provides a memory cell 301 of the second embodiment, wherein the first gate oxide layer 30 is a first dielectric layer 33, the first dielectric layer 33 is disposed on the second surface 17 of the substrate 10, and the control gate 50 is disposed on the side of the first dielectric layer 33 away from the substrate 10, so that the first dielectric layer 33 is disposed between the substrate 10 and the control gate 50. For example, the thickness of the first dielectric layer 33 is 1nm~2nm.

[0085] Compared to the memory cell 301 of the first embodiment, the memory cell 301 provided in the second embodiment has a single-layer first dielectric layer 33 for the first gate oxide layer 30, which does not contain a SiO2 layer. On the one hand, the increase in capacitance brought by the first dielectric layer 33 is not diluted, and the increase in capacitance is significant, thereby significantly improving the capacitance value per unit area of ​​the control gate 50, and thus significantly reducing the size of the memory cell 301. On the other hand, the first dielectric layer 33 with a high dielectric constant has a strong ability to bind electrons, and even using a thinner first dielectric layer 33 can ensure that the first gate oxide layer 30 is not broken down. On the other hand, since electrons are only stored in the second gate oxide layer 70 of the floating gate 90, rather than the first gate oxide layer 30 below the control gate 50, when the memory 300 is working, the interface defects of the first dielectric layer 33 with a high dielectric constant have a small impact on the performance of the memory 300, and the performance of the memory 300 can be guaranteed. It should be noted that, in the memory cell 301 of the first embodiment, although the use of the first oxide layer 31 (SiO2 layer) greatly dilutes the effect of the increased capacitance brought about by the first dielectric layer 33, compared with the conventional structure that does not use a first dielectric layer 33 with a high dielectric constant, the capacitance C of the control gate 50 is still significantly reduced. CG There will still be a 123% increase.

[0086] In addition, in the memory cell 301 of the second embodiment, a single-layer first dielectric layer 33 is used, and the thickness of the first dielectric layer 33 is 1nm~2nm. The thickness of the first dielectric layer 33 is ultra-thin, which can significantly increase the capacitance of the control gate 50, thereby significantly increasing the capacitance value per unit area of ​​the control gate 50, and thus significantly reducing the size of the memory cell 301.

[0087] In this embodiment, the material of the first dielectric layer 33 is 1nm~2nm HfO2 (hafnium dioxide). When the material of the first dielectric layer 33 includes HfO2, as the thickness of the first dielectric layer 33 decreases, the recrystallization temperature of the HfO2 material increases from 500°C to 700°C, thereby significantly reducing the degree of recrystallization of the material when using the same atomic layer deposition (ALD) process. Long-distance Coulomb scattering caused by recrystallization significantly reduces electronic activity, leading to a decrease in the performance of the memory 300. Therefore, compared to other types of high dielectric constant materials, the memory 300 formed when the material of the first dielectric layer 33 includes HfO2 has better performance.

[0088] See Figure 8 , Figure 8 for Figure 4 The diagram shows a cross-sectional view of the storage cell 301 in the third embodiment of the memory 300. Figure 8 The trend of the curve on the right side of the middle section represents the changing trend of the material content in each layer of the first gate oxide layer 30, the trend of the real curve represents the changing trend of the material content in the first oxide layer 31, and the trend of the dashed curve represents the changing area of ​​the material content in the first dielectric layer 33.

[0089] The difference between the storage unit 301 in the third embodiment and the storage unit 301 in the first embodiment is that the storage unit 301 in the third embodiment further includes a first transition layer 32.

[0090] Specifically, in the memory cell 301 of the third embodiment, the first gate oxide layer 30 includes a first oxide layer 31, a first transition layer 32, and a first dielectric layer 33 stacked sequentially. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10, the first transition layer 32 is disposed on the side of the first oxide layer 31 facing away from the substrate 10, and the first dielectric layer 33 is disposed on the side of the first transition layer 32 facing away from the first oxide layer 31. The control gate 50 is disposed on the side of the first dielectric layer 33 facing away from the first transition layer 32.

[0091] The material of the first transition layer 32 includes the material of the first oxide layer 31 and the material of the first dielectric layer 33. From the first oxide layer 31 towards the first dielectric layer 33, that is, along the positive Z-axis in this embodiment, the content of the first oxide layer 31 material in the first transition layer 32 gradually decreases (see...). Figure 8 (See the solid curve trend on the right side of the middle section) The content of the material in the first dielectric layer 33 gradually increases (see...) Figure 8 The trend of the dashed curve on the right side of the middle section.

[0092] For example, in this embodiment, the material of the first oxide layer 31 is SiO2, and the material of the first dielectric layer 33 is HfO2. The material of the first transition layer 32 includes both SiO2 and HfO2. From the first oxide layer 31 to the first dielectric layer 33, the content of SiO2 in the first transition layer 32 gradually decreases, while the content of HfO2 gradually increases. For example, the first transition layer 32 can be prepared using an LLDA (Layer by Layer Deposition and Annealing) process. Specifically, under high-temperature annealing, some of the material of the first dielectric layer 33 will diffuse into the SiO2 layer through atomic diffusion. Therefore, the first transition layer 32 can be obtained by repeatedly depositing atomic layers of the material of the first dielectric layer 33 on the surface of the SiO2 layer and performing synchronous annealing through programming.

[0093] In the memory cell 301 of the third embodiment, on the one hand, by providing a first dielectric layer 33 with a high dielectric constant in the first gate oxide layer 30, the dielectric constant of the first gate oxide layer 30 is increased, thereby increasing the capacitance per unit area of ​​the memory cell 301. This allows for a reduction in the area A of the control gate 50, thus achieving a smaller memory cell 301. On the other hand, by providing a first transition layer 32 between the first oxide layer 31 and the first dielectric layer 33, the concentration of the high dielectric constant first dielectric layer 33 material is gradually increased in the material of the first oxide layer 31, achieving a gradient change in the material of the first dielectric layer 33 in the first gate oxide layer 30. The first transition layer 32 acts as a transition buffer between the first oxide layer 31 and the first dielectric layer 33, which can, to some extent, prevent interface defects between the first oxide layer 31 and the first dielectric layer 33, thereby improving the performance of the memory cell 301 to some extent.

[0094] It is understandable that, since the first dielectric layer 33 has a relatively high electron binding capacity, in other embodiments, the positions of the first oxide layer 31 and the first dielectric layer 33 can also be interchanged. That is, the first gate oxide layer 30 may include the first dielectric layer 33, the first transition layer 32 and the first oxide layer 31 stacked sequentially. The first dielectric layer 33 is disposed on the second surface 17 of the substrate 10, the first transition layer 32 is disposed on the side of the first dielectric layer 33 away from the substrate 10, the first oxide layer 31 is disposed on the side of the first transition layer 32 away from the first dielectric layer 33, and the control gate 50 is disposed on the side of the first oxide layer 31 away from the first transition layer 32.

[0095] Furthermore, this application also studies and analyzes how to control the electrical charge Q in the floating gate 90. FG A voltage needs to be applied to the control gate 50, and the voltage of the floating gate 90 needs to be changed through capacitive coupling. The voltage V of the control gate 50 is... CG The charge Q of the floating gate 90 FGThe relationship between them satisfies formulas 3 and 4:

[0096] (Formula 3), (Formula 4).

[0097] Among them, V OX This indicates the voltage of the second gate oxide layer 70. V CG This indicates the voltage at control gate 50. V b Q represents the voltage across substrate 10. FG α represents the electrical charge in the floating gate 90, in coulombs. CG C represents the coupling coefficient. CG C represents the capacitance of the control gate 50. FG This represents the capacitance of the floating gate 90. In this embodiment, the capacitance C controlling the gate 50 is... CG This refers to the capacitance formed between the control gate 50 and the substrate 10, and the capacitance C of the floating gate 90. FG This refers to the capacitance formed between the floating gate 90 and the substrate 10.

[0098] Understandably, substrate 10 is typically grounded, at which point the potential of substrate 10 is zero, V b The value is zero at this point.

[0099] As can be seen from Formula 3, in V OX V b Q FG While remaining constant, the voltage V of control gate 50 CG With the coupling coefficient α CG The voltage V of the control gate 50 decreases as the value increases. CG With the coupling coefficient α CG The coupling coefficient α increases as the coupling decreases. As can be seen from Equation 4, the coupling coefficient α... CG Simultaneously controlled by the capacitance C of gate 50 CG And the capacitance C of the floating gate 90 FG The combined effects of these factors. Among them, the capacitance C of the control gate 50... CG The larger the proportion, the higher the coupling coefficient α. CG The higher the coupling coefficient α, the better. However, in actual storage operation, the coupling coefficient α... CG If the voltage is too low, it will require a higher voltage on the control gate 50. Excessive voltage will severely damage the first gate oxide layer 30 between the control gate 50 and the substrate 10, as well as the second gate oxide layer 70 between the floating gate 90 and the substrate 10, thereby causing the entire memory cell 301 to fail.

[0100] By reducing the voltage V of the control gate 50 CGThis ensures that the first gate oxide layer 30 and the second gate oxide layer 70 are not broken down. Furthermore, according to Formula 3, when the voltage V of the control gate 50... CG When the coupling coefficient α remains unchanged CG When the voltage decreases, the charge Q of the floating gate 90 FG This will decrease the number of electrons in the floating gate 90 under the same voltage write, which greatly increases the probability of data read errors in the memory cell 301. It is easy to read "logic 0" as "logic 1" or "logic 1" as "logic 0", which will lead to bit flip.

[0101] Based on the above research and analysis, this application also provides a feasible technical solution by increasing the coupling coefficient α. CG To achieve a relatively low control gate voltage V CG The purpose of writing data is to achieve the same voltage V at the control gate 50. CG The charge Q in the floating gate 90 is increased. FG This aims to improve the data writing speed of storage unit 301.

[0102] See also Figure 9 , Figure 9 for Figure 4 The diagram shows a cross-sectional view of the storage cell 301 in the fourth embodiment of the memory 300.

[0103] The difference between the storage cell 301 of the fourth embodiment and the storage cell 301 of the first embodiment is that, in the storage cell 301 of the fourth embodiment, the second gate oxide layer 70 includes a second dielectric layer 73, and the dielectric constant of the second dielectric layer 73 is less than 3.

[0104] Specifically, in the memory cell 301 of the fourth embodiment, the first gate oxide layer 30 includes a first oxide layer 31 and a first dielectric layer 33. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10. In this embodiment, the first oxide layer 31 is a SiO2 layer, and the thickness of the first oxide layer 31 is 3 nm. The first dielectric layer 33 is disposed on the side of the first oxide layer 31 facing away from the substrate 10. In this embodiment, the thickness of the first dielectric layer 33 is 1 nm. The control gate 50 is disposed on the side of the first dielectric layer 33 facing away from the first oxide layer 31.

[0105] The second gate oxide layer 70 includes a second oxide layer 71 and a second dielectric layer 73. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first oxide layer 31 along the length direction of the substrate 10. In this embodiment, the second oxide layer 71 is a SiO2 layer. The second dielectric layer 73 is disposed on the side of the second oxide layer 71 facing away from the substrate 10, and the floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second oxide layer 71. In this embodiment, the thickness of the second gate oxide layer 70 is greater than the thickness of the first gate oxide layer 30. For example, the thickness of the second oxide layer 71 is 3 nm, and the thickness of the second dielectric layer 73 is 7 nm. In this embodiment, the thickness of the second dielectric layer 73 is greater than the thickness of the second oxide layer 71.

[0106] For example, the material of the second dielectric layer 73 can be a silicon-based polymer HSQ (Hydrogensilsesquioxane), MSQ (methylsilsesquioxane), porous HSQ or porous MSQ, or other low-k materials. This application does not limit the choice of material for the second dielectric layer 73, as long as it can reduce the capacitance C of the floating gate 90. FG That is the purpose.

[0107] Among them, porous HSQ and porous MSQ are formed by adding nanoscale voids to HSQ and MSQ materials, respectively. For example, nanoscale voids are usually achieved by synthesizing block copolymers. Taking the preparation of porous MSQ as an example, MSQ is usually provided in solution form, distributed on a silicon wafer by spin coating, and then crosslinked by heating under a protective atmosphere. Then, the void-forming groups are removed to form a silica-like porous structure.

[0108] Based on research and analysis, this application shows that in the memory cell 301 of memory 300, the capacitance C of the floating gate 90 is... FG Refer to formula 5: (Formula 5). Where A2 represents the area of ​​the floating gate 90, and d2 represents the thickness of the second gate oxide layer 70. This represents the dielectric constant of the second gate oxide layer 70. It is understood that the dielectric constant of the second gate oxide layer 70 can also be represented by k.

[0109] Combining Equations 5 and 4, it can be seen that by setting the second dielectric layer 73 to have a lower dielectric constant, the dielectric constant of the second gate oxide layer 70 can be reduced. This reduces the capacitance C per unit area of ​​the floating gate by 90%. FG The capacitance C of the control gate 50 was increased. CGThe proportion of this, thereby enabling the coupling coefficient α to be achieved. CG The improvement. On the one hand, when the charge Q of the floating gate 90... FG When the coupling coefficient α remains unchanged CG The increase can make the voltage V applied to the control gate 50 CG The voltage V of the control gate 50 is reduced during the data writing process of the memory cell 301. CG This reduction improves the long-term reliability of the first gate oxide layer 30 below the control gate 50, thereby increasing the lifespan of the memory cell 301 and ultimately improving the long-term reliability of the memory 300. Simultaneously, it reduces the required write voltage, achieving a relatively low control gate 50 voltage V. CG The purpose of writing data is to complete the task.

[0110] On the other hand, the current I of the floating gate 90 FG Satisfying formulas 6 and 7, where I FG E represents the current at the floating gate 90. OX V represents the electric field strength of the second gate oxide layer 70. OX d1 represents the voltage of the second gate oxide layer 70, and d2 represents the thickness of the second gate oxide layer 70.

[0111] (Formula 6), (Formula 7).

[0112] When the voltage V of the control gate 50 CG When the coupling coefficient α remains unchanged CG The increase in voltage allows for an increase in the voltage of the second gate oxide layer 70, which in turn increases the voltage formed on the floating gate 90. This, in turn, increases the electric field strength of the second gate oxide layer 70, thereby increasing the amount of charge Q written to the floating gate 90 within a certain time. FG This significantly improves the speed (current) of data writing within the tolerance range of the second gate oxide layer 70, which is affected by the electric field strength, thereby increasing the data writing speed of the storage cell 301 and improving the efficiency of data writing.

[0113] Furthermore, the thickness of the second gate oxide layer 70 is greater than the thickness of the first gate oxide layer 30, which can significantly reduce the capacitance C of the floating gate 90. FG The capacitance C of the control gate 50 was increased. CG The proportion of this, thereby enabling the coupling coefficient α to be achieved. CG The improvement.

[0114] Furthermore, existing dielectric materials with a dielectric constant less than 3 are mainly used for filling dielectric layers between back-end metal layers on wafers. As the density of integrated circuits (ICs) increases, the number of back-end interconnects also increases. The resistive-capacitive delay (RC delay) caused by metal interconnects not only affects chip speed but also poses a serious threat to operational reliability. Circuit signal transmission speed depends on the product of parasitic resistance and parasitic capacitance. To solve the RC delay problem, it is necessary to reduce parasitic resistance (using copper interconnects instead of aluminum interconnects) and parasitic capacitance. Parasitic capacitance is proportional to the dielectric constant k of the circuit layer isolation medium; therefore, using a material with a low dielectric constant (dielectric constant k < 3) as the isolation medium between different circuit layers can reduce parasitic capacitance. In this embodiment, a second dielectric layer 73 with a dielectric constant less than 3 is applied to the second gate oxide layer 70 to improve the coupling coefficient α by reducing the dielectric constant of the second gate oxide layer 70. CG The purpose is to improve the long-term reliability of the memory 300 at a relatively low control gate voltage V. CG The purpose of writing data is to achieve the same voltage V at the control gate 50. CG This aims to improve the data write speed of the memory cell 301. Simultaneously, using a second dielectric layer 73 with a low dielectric constant in the second gate oxide layer 70 can also reduce parasitic capacitance.

[0115] In the memory cell 301 of the fourth embodiment, on the one hand, by providing the first gate oxide layer 30 including a first dielectric layer 33 with a high dielectric constant, the dielectric constant of the first gate oxide layer 30 is increased, thereby increasing the capacitance per unit area of ​​the control gate 50. This allows for a reduction in the size of the memory cell 301 by decreasing the area A of the control gate 50. On the other hand, by providing the second gate oxide layer 70 including a second dielectric layer 73 with a low dielectric constant, the dielectric constant of the second gate oxide layer 70 is reduced, thereby decreasing the capacitance C of the floating gate 90. FG This achieved an increase in the coupling coefficient α. CG The purpose is to improve the long-term reliability of the memory 300 at a relatively low control gate voltage V. CG The purpose of writing data is to achieve the same voltage V at the control gate 50. CG The purpose is to improve the data write speed of storage unit 301.

[0116] In addition, the purpose of adding a second dielectric layer 73 with a low dielectric constant in the second gate oxide layer 70 is to reduce the capacitance C of the floating gate 90. FGHowever, a low dielectric constant reduces the charge-binding ability of the second dielectric layer 73, making it prone to leakage or data loss when the second dielectric layer 73 is thin. Increasing the thickness of the second dielectric layer 73 and placing the second oxide layer 71 between the substrate 10 and the second dielectric layer 73 can reduce the risk of leakage and prevent data loss. Furthermore, the high lattice matching between the second oxide layer 71 (a SiO2 layer in this embodiment) and the substrate 10 (a Si substrate in this embodiment) can alleviate stress caused by lattice distortion during processing, thereby ensuring the integrity of the second oxide layer 71 and thus guaranteeing the performance of the memory cell 301.

[0117] Furthermore, in the memory cell 301 of the fourth embodiment, the first gate oxide layer 30 retains the first oxide layer 31, which can be grown simultaneously with the second oxide layer 71 in the second gate oxide layer 70, simplifying the fabrication process of the memory cell 301. Specifically, in the memory cell 301 of the fourth embodiment, the first gate oxide layer 30 retains a SiO2 layer of approximately 3 nm, which can be generated simultaneously with the approximately 3 nm SiO2 layer in the second gate oxide layer 70, further simplifying the fabrication process of the memory cell 301.

[0118] See Figure 10 , Figure 10 for Figure 4 The diagram shows a cross-sectional view of the storage cell 301 in the fifth embodiment of the memory 300. Figure 10 The trend of the curve on the left side of the middle graph represents the variation area of ​​material content in each layer of the second gate oxide layer 70, the trend of the solid curve represents the variation trend of material content in the second oxide layer 71, and the trend of the dashed curve represents the variation trend of material content in the second dielectric layer 73.

[0119] The difference between the storage cell 301 of the fifth embodiment and the storage cell 301 of the fourth embodiment is that the second gate oxide layer 70 in the storage cell 301 of the fifth embodiment further includes a second transition layer 72.

[0120] Specifically, in the memory cell 301 of the fifth embodiment, the first gate oxide layer 30 includes a first oxide layer 31 and a first dielectric layer 33 stacked sequentially. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10. In this embodiment, the first oxide layer 31 is a SiO2 layer. The first dielectric layer 33 is disposed on the side of the first oxide layer 31 facing away from the substrate 10, and the control gate 50 is disposed on the side of the first dielectric layer 33 facing away from the first oxide layer 31.

[0121] The second gate oxide layer 70 includes a second oxide layer 71, a second transition layer 72, and a second dielectric layer 73, which are sequentially stacked. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first oxide layer 31 along the length direction of the substrate 10. In this embodiment, the second oxide layer 71 is a SiO2 layer. The second transition layer 72 is disposed on the side of the second oxide layer 71 facing away from the substrate 10. The second dielectric layer 73 is disposed on the side of the second transition layer 72 facing away from the second oxide layer 71. For example, the thickness of the second oxide layer 71 is 3 nm, the thickness of the second transition layer 72 is 4 nm, and the thickness of the second dielectric layer 73 is 3 nm. The floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second transition layer 72.

[0122] The material of the second transition layer 72 includes the material of the second oxide layer 71 and the material of the second dielectric layer 73. From the second oxide layer 71 towards the second dielectric layer 73, that is, along the positive Z-axis in this embodiment, the content of the material of the second oxide layer 71 in the second transition layer 72 gradually decreases (see...). Figure 10 (See the trend of the solid curve on the left side of the middle section) The content of the material in the second dielectric layer 73 gradually increases (see...) Figure 10 The trend of the dashed curve on the left side of the middle section.

[0123] For example, in this embodiment, the material of the second oxide layer 71 is SiO2, and the material of the second dielectric layer 73 is HSQ. The material of the second transition layer 72 includes both SiO2 and HSQ. From the second oxide layer 71 to the second dielectric layer 73, the content of SiO2 in the second transition layer 72 gradually decreases, while the content of HSQ gradually increases. For example, the second transition layer 72 can be prepared using an LLDA (Layer by Layer Deposition and Annealing) process. Specifically, under high-temperature annealing, some of the material of the second dielectric layer 73 will diffuse into the SiO2 layer through atomic diffusion. Therefore, the second transition layer 72 can be obtained by repeatedly depositing atomic layers of the material of the second dielectric layer 73 on the surface of the SiO2 layer and performing synchronous annealing through programming.

[0124] This application research found that although the lattice matching between the second oxide layer 71 (a SiO2 layer in this embodiment) and the substrate 10 (a Si substrate in this embodiment) is high, which can alleviate the stress caused by lattice distortion during processing and ensure the integrity of the second oxide layer 71, interface defects will inevitably be generated at the interface between the second oxide layer 71 and the second dielectric layer 73 during the processing of the second gate oxide layer 70. During the process of electrons passing through the second gate oxide layer 70 from the substrate 10 and migrating to the floating gate 90, electrons are prone to be stuck at the interface defects, or slowly diffuse back into the floating gate 90 over time, thereby reducing the ability of the floating gate 90 to retain data (electrons). During the process of reading data from the memory cell 301, "logic 1" is easily misread as "logic 0" or "logic 1" is misread as "logic 0", which in turn affects the accuracy of data reading from the memory cell 301.

[0125] To further enhance the data (electron) retention capability of the floating gate 90 and alleviate threshold voltage fluctuations caused by electron capture due to interface defects, this embodiment provides a second transition layer 72 between the second oxide layer 71 and the second dielectric layer 73. This achieves a gradual decrease in the material content of the second oxide layer 71 and a gradual increase in the material content of the second dielectric layer 73 in the second gate oxide layer 70 from the second oxide layer 71 to the second dielectric layer 73. This is equivalent to gradually increasing the concentration of the low-dielectric-constant second dielectric layer 73 material in the material of the second oxide layer 71, realizing a gradient change in the material of the second dielectric layer 73 in the second gate oxide layer 70. This allows the second transition layer 72 to play a good transition buffer role between the second oxide layer 71 and the second dielectric layer 73, thereby reducing interface defects between the second oxide layer 71 and the second dielectric layer 73, and thus ensuring the data retention capability and low leakage current of the floating gate 90.

[0126] In the memory cell 301 provided in the fifth embodiment, on the one hand, by providing a first dielectric layer 33 with a high dielectric constant in the first gate oxide layer 30, the dielectric constant of the first gate oxide layer 30 is increased, thereby increasing the capacitance per unit area of ​​the memory cell 301. This allows for a reduction in the size of the memory cell 301 by decreasing the area A of the control gate 50. On the other hand, by providing a second gate oxide layer 70 including a second dielectric layer 73 with a low dielectric constant, the dielectric constant of the second gate oxide layer 70 is reduced, thereby decreasing the capacitance C of the floating gate 90. FG This achieved an increase in the coupling coefficient α. CG The purpose is to improve the long-term reliability of the memory 300 at a relatively low control gate voltage V. CG The purpose of writing data is to achieve the same voltage V at the control gate 50. CGThe purpose is to improve the data write speed of the memory cell 301. On the other hand, by setting a second transition layer 72 between the second oxide layer 71 and the second dielectric layer 73, it is equivalent to gradually increasing the concentration of the low dielectric constant material of the second dielectric layer 73 in the material of the second oxide layer 71, so as to achieve a gradient change of the material of the second dielectric layer 73 in the second gate oxide layer 70. This reduces the interface defects generated between the second oxide layer 71 and the second dielectric layer 73, prevents the interface defects from trapping electrons and causing threshold voltage fluctuations, ensures the data retention capability and low leakage current of the floating gate 90, and thus improves the performance of the memory cell 301.

[0127] See Figure 11 , Figure 11 for Figure 4 A cross-sectional structural diagram of storage cell 301 in the sixth embodiment of the memory 300 shown.

[0128] The difference between the storage unit 301 of the sixth embodiment and the storage unit 301 of the fourth embodiment is that the first gate oxide layer 30 in the storage unit 301 of the sixth embodiment is a first dielectric layer 33.

[0129] Specifically, in the memory cell 301 of the sixth embodiment, a first dielectric layer 33 is disposed on the second surface 17 of the substrate 10, and a control gate 50 is disposed on the side of the first dielectric layer 33 facing away from the substrate 10. The second gate oxide layer 70 includes a second oxide layer 71 and a second dielectric layer 73. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first dielectric layer 33 along the length direction of the substrate 10. The second dielectric layer 73 is disposed on the side of the second oxide layer 71 facing away from the substrate 10, and a floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second oxide layer 71.

[0130] The memory cell 301 provided in the sixth embodiment significantly increases the dielectric constant of the first gate oxide layer 30 by setting the first gate oxide layer 30 to a first dielectric layer 33 with a high dielectric constant. This significantly increases the capacitance per unit area of ​​the control gate 50, thereby reducing the size of the memory cell 301 by decreasing the area A of the control gate 50. Furthermore, by including a second dielectric layer 73 with a low dielectric constant in the second gate oxide layer 70, the dielectric constant of the second gate oxide layer 70 is reduced, thereby decreasing the capacitance C of the floating gate 90. FG This achieved an increase in the coupling coefficient α. CG The purpose is to improve the long-term reliability of the memory 300 at a relatively low control gate voltage V. CG The purpose of writing data is to achieve the same voltage V at the control gate 50. CG The purpose is to improve the data write speed of storage unit 301.

[0131] See Figure 12 , Figure 12 for Figure 4 A cross-sectional structural diagram of storage cell 301 in the seventh embodiment of the memory 300 shown.

[0132] The difference between the storage unit 301 of the seventh embodiment and the storage unit 301 of the fifth embodiment is that the first gate oxide layer 30 in the storage unit 301 of the seventh embodiment is a first dielectric layer 33.

[0133] Specifically, in the memory cell 301 of the seventh embodiment, a first dielectric layer 33 is disposed on the second surface 17 of the substrate 10, and a control gate 50 is disposed on the side of the first dielectric layer 33 facing away from the substrate 10. The second gate oxide layer 70 includes a second oxide layer 71, a second transition layer 72, and a second dielectric layer 73 stacked sequentially. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first dielectric layer 33 along the length direction of the substrate 10. The second transition layer 72 is disposed on the side of the second oxide layer 71 facing away from the substrate 10, the second dielectric layer 73 is disposed on the side of the second transition layer 72 facing away from the second oxide layer 71, and the floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second transition layer 72.

[0134] The memory cell 301 provided in the seventh embodiment significantly increases the dielectric constant of the first gate oxide layer 30 by setting the first gate oxide layer 30 to a first dielectric layer 33 with a high dielectric constant. This significantly increases the capacitance per unit area of ​​the control gate 50, thereby reducing the size of the memory cell 301 by decreasing the area A of the control gate 50. Furthermore, by setting the second gate oxide layer 70 to include a second dielectric layer 73 with a low dielectric constant, the dielectric constant of the second gate oxide layer 70 is reduced, thereby decreasing the capacitance C of the floating gate 90. FG This achieved an increase in the coupling coefficient α. CG The purpose is to improve the long-term reliability of the memory 300 at a relatively low control gate voltage V. CG The purpose of writing data is to achieve the same voltage V at the control gate 50. CG The purpose is to improve the data write speed of the memory cell 301. On the other hand, by setting the second gate oxide layer 70 to include a second transition layer 72, interface defects are avoided between the second oxide layer 71 and the second dielectric layer 73, thereby ensuring the data retention capability of the floating gate 90.

[0135] See Figure 13 , Figure 13 for Figure 4 A cross-sectional structural diagram of storage cell 301 in the memory 300 shown in the eighth embodiment.

[0136] The difference between the storage cell 301 of the eighth embodiment and the storage cell 301 of the fourth embodiment is that, in the storage cell 301 of the eighth embodiment, the first gate oxide layer 30 includes a first oxide layer 31, a first transition layer 32 and a first dielectric layer 33.

[0137] Specifically, in the memory cell 301 of the eighth embodiment, a first oxide layer 31 is disposed on the second surface 17 of the substrate 10, a first transition layer 32 is disposed on the side of the first oxide layer 31 away from the substrate 10, and a first dielectric layer 33 is disposed on the side of the first transition layer 32 away from the first oxide layer 31. A control gate 50 is disposed on the side of the first dielectric layer 33 away from the first transition layer 32.

[0138] The second gate oxide layer 70 includes a second oxide layer 71 and a second dielectric layer 73. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first oxide layer 31 along the length direction of the substrate 10. The second dielectric layer 73 is disposed on the side of the second oxide layer 71 opposite to the substrate 10, and the floating gate 90 is disposed on the side of the second dielectric layer 73 opposite to the second oxide layer 71.

[0139] In the memory cell 301 of the eighth embodiment, on the one hand, by providing a first dielectric layer 33 with a high dielectric constant in the first gate oxide layer 30, the dielectric constant of the first gate oxide layer 30 is increased, thereby increasing the capacitance per unit area of ​​the memory cell 301. This allows for a reduction in the area A of the control gate 50, thus achieving a smaller memory cell 301. On the other hand, by providing a first transition layer 32 between the first oxide layer 31 and the first dielectric layer 33, the concentration of the high dielectric constant first dielectric layer 33 material is gradually increased in the material of the first oxide layer 31. This achieves a gradient change in the material of the first dielectric layer 33 in the first gate oxide layer 30, thereby avoiding interface defects and improving the performance of the memory cell 301. On the other hand, by providing a second gate oxide layer 70 including a second dielectric layer 73 with a low dielectric constant, the dielectric constant of the second gate oxide layer 70 is reduced, thereby reducing the capacitance C of the floating gate 90. FG This achieved an increase in the coupling coefficient α. CG The purpose is to improve the long-term reliability of the memory 300 at a relatively low control gate voltage V. CG The purpose of writing data is to achieve the same voltage V at the control gate 50. CG The purpose is to improve the data write speed of storage unit 301.

[0140] See Figure 14 , Figure 14 for Figure 4 A cross-sectional structural diagram of storage cell 301 in the memory 300 shown in the ninth embodiment.

[0141] The difference between the storage cell 301 of the ninth embodiment and the storage cell 301 of the eighth embodiment is that the second gate oxide layer 70 in the storage cell 301 of the fifth embodiment further includes a second transition layer 72.

[0142] Specifically, in the memory cell 301 of the ninth embodiment, the first gate oxide layer 30 includes a first oxide layer 31, a first transition layer 32, and a first dielectric layer 33 stacked sequentially. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10, the first transition layer 32 is disposed on the side of the first oxide layer 31 facing away from the substrate 10, and the first dielectric layer 33 is disposed on the side of the first transition layer 32 facing away from the first oxide layer 31. The control gate 50 is disposed on the side of the first dielectric layer 33 facing away from the first transition layer 32.

[0143] The second gate oxide layer 70 includes a second oxide layer 71, a second transition layer 72, and a second dielectric layer 73, which are sequentially stacked. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first oxide layer 31 along the length direction of the substrate 10. The second transition layer 72 is disposed on the side of the second oxide layer 71 facing away from the substrate 10, the second dielectric layer 73 is disposed on the side of the second transition layer 72 facing away from the second oxide layer 71, and the floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second transition layer 72.

[0144] In the memory cell 301 of the ninth embodiment, on the one hand, by setting the first gate oxide layer 30 to a first dielectric layer 33 with a high dielectric constant, the dielectric constant of the first gate oxide layer 30 is significantly improved, thereby significantly increasing the capacitance per unit area of ​​the control gate 50. This allows for a reduction in the size of the memory cell 301 by decreasing the area A of the control gate 50. On the other hand, by setting a first transition layer 32 between the first oxide layer 31 and the first dielectric layer 33, the concentration of the high dielectric layer 33 material is gradually increased in the material of the first oxide layer 31. This achieves a gradient change in the material of the first dielectric layer 33 in the first gate oxide layer 30, thereby avoiding interface defects and improving the performance of the memory cell 301.

[0145] On the one hand, by including a second dielectric layer 73 with a low dielectric constant in the second gate oxide layer 70, the dielectric constant of the second gate oxide layer 70 is reduced, thereby reducing the capacitance C of the floating gate 90. FG This achieved an increase in the coupling coefficient α. CG The purpose is to improve the long-term reliability of the memory 300 at a relatively low control gate voltage V. CG The purpose of writing data is to achieve the same voltage V at the control gate 50. CGThe purpose is to improve the data write speed of the memory cell 301. On the other hand, by setting the second gate oxide layer 70 to include a second transition layer 72, interface defects are avoided between the second oxide layer 71 and the second dielectric layer 73, thereby ensuring the data retention capability of the floating gate 90.

[0146] See Figure 15 and Figure 16 , Figure 15 for Figure 4 The schematic diagram of the storage cell 301 in the memory 300 shown in the tenth embodiment is a structural diagram. Figure 16 for Figure 15 A schematic diagram of the cross-sectional structure of the storage unit 301 shown.

[0147] The difference between the storage cell 301 of the tenth embodiment and the storage cell 301 of the first embodiment is that, in the storage cell 301 of the tenth embodiment, the floating gate 90 and the control gate 50 are located on the same layer.

[0148] Specifically, a polysilicon layer can be formed on the side of the first gate oxide layer 30 and the second gate oxide layer 70 away from the substrate 10, and the floating gate 90 and the control gate 50 are located in different regions of the polysilicon layer along the length of the substrate 10.

[0149] It is understood that in the storage cell 301 of the tenth embodiment, the first gate oxide layer 30 and the second gate oxide layer 70 can be selected from any of the structures of the first gate oxide layer 30 and the second gate oxide layer 70 in the storage cell 301 of the first to ninth embodiments.

[0150] The effects of the storage unit 301 provided in the embodiments of this application will be explained below with reference to specific calculation data.

[0151] Taking the structure of the memory cell 301 in the second embodiment as an example, compared to the scheme where the first gate oxide layer 30 is entirely made of SiO2, the first gate oxide layer 30 in the memory cell 301 of the second embodiment is entirely made of dielectric constant. When the dielectric material is 30, the gate oxide capacitance per unit area of ​​the control gate 50 can be increased by more than 5000%. Referring to Formula 1, while ensuring the same capacitance C of the control gate 50... CGIn this case, the area of ​​the control gate 50 can be reduced laterally to 2% of its original size, a reduction of 98%. Assuming the structural dimensions of the floating gate 90 are comparable to those of the control gate 50, the area of ​​the entire memory cell 301 in the memory 300 is reduced to half the area of ​​the control gate 50, approximately 4%, a reduction of 96%. In the actual memory cell 301 structure, the area of ​​the control gate 50 accounts for a much larger proportion than that of the floating gate 90. Therefore, the overall size reduction of the memory cell 301 will approach 2% rather than 4%, and the area of ​​the memory cell 301 will be approximately 1 μm. 2 This reduction significantly decreases the area used by MTP and OTP memories on logic chip 2, bringing it very close to the area of ​​a vertically oriented Flash memory cell (approximately 0.13 μm). 2 This expands the cost advantage of the memory 300.

[0152] Taking the structure of the memory cell 301 in the fourth embodiment as an example, assuming that the material of the second oxide layer 71 in the second gate oxide layer 70 is a SiO2 layer with a dielectric constant k value of 4, and the material of the second dielectric layer 73 is a dielectric constant k value of 4, (k) A material with a low dielectric constant and a value of 2. If the original coupling coefficient α CG The new coupling coefficient α is 60%, referring to formulas 3 and 4. CG It can be increased to 70%, and the total capacitance of the memory cell 301 structure is reduced to 85% of the original, when the charge Q in the floating gate 90 FG To maintain consistency, the voltage required to be applied to control gate 50 is from 5 / 3V. ox Reduced to 4 / 3V ox This reduces the voltage applied to the control gate 50 by approximately 20% during data writing. This means that the voltage applied to the control gate 50 during data writing in memory cell 301 can be reduced by 20% compared to conventional solutions, thereby improving the long-term reliability of the first gate oxide layer 30. Similarly, it is possible to choose not to reduce the voltage V of the control gate 50. CG Referring to Formulas 6 and 7, the data writing speed (current) within the tolerance range of the second gate oxide layer 70 will be significantly improved due to the influence of the electric field strength.

[0153] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art will understand that all or part of the processes for implementing the above embodiments and equivalent variations made in accordance with the claims of this application are still within the scope of this application.

Claims

1. A storage unit, characterized in that, The storage unit includes: Substrate; A first gate oxide layer and a control gate, wherein the first gate oxide layer includes a first dielectric layer along the thickness direction of the substrate, the first dielectric layer is disposed on the surface of the substrate, the dielectric constant of the first dielectric layer is greater than 16, and the control gate is disposed on the surface of the first dielectric layer opposite to the substrate. A second gate oxide layer and a floating gate are provided. The thickness of the second gate oxide layer is greater than that of the first gate oxide layer. The second gate oxide layer includes a second oxide layer, a second transition layer, and a second dielectric layer. The second oxide layer is disposed on one side of the substrate and is located on the same side of the substrate along the thickness direction as the first dielectric layer, and is spaced apart from the first dielectric layer along the length direction of the substrate. The second transition layer is disposed on the side of the second oxide layer away from the substrate. The material of the second transition layer includes the material of the second oxide layer and the material of the second dielectric layer. From the second oxide layer to the second dielectric layer, the content of the material of the second oxide layer in the second transition layer gradually decreases, and the content of the material of the second dielectric layer gradually increases. The second dielectric layer is disposed on the side of the second transition layer away from the second oxide layer, and the dielectric constant of the material of the second dielectric layer is less than 3. The floating gate is disposed on the side of the second dielectric layer away from the second transition layer.

2. The storage unit according to claim 1, characterized in that, The thickness of the first dielectric layer is 1 nm to 2 nm.

3. The storage unit according to claim 1, characterized in that, The material of the first dielectric layer includes HfO2.

4. An integrated circuit, characterized in that, The integrated circuit includes one or more memory cells as described in any one of claims 1 to 3.

5. A memory, characterized in that, The memory includes a controller and one or more storage units as described in any one of claims 1 to 3, wherein the controller is configured to control access to the storage units.

6. A logic chip, characterized in that, The logic chip includes a circuit board and a memory as described in claim 5, wherein the memory is integrated into the circuit board.

7. An electronic device, characterized in that, The electronic device includes a processor and a memory as described in claim 5, the processor being configured to access the memory; or the electronic device includes a processor and a logic chip as described in claim 6, the processor being configured to access the memory in the logic chip.

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