Memory devices with vertical transistors and their fabrication methods

Abstract

In some aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes peripheral circuitry. The second semiconductor structure includes a memory cell array and multiple bit lines coupled to the memory cells and each extending in a second direction perpendicular to a first direction. Each memory cell includes a vertical transistor extending in the first direction and a memory cell coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction and a gate structure contacting two opposite sides of the semiconductor body in the second direction. A corresponding bit line and a corresponding memory cell are coupled in the first direction to opposite ends of each memory cell in the memory cell. The memory cell array is coupled to the peripheral circuitry via the bonding interface.

Description

Background Technology

[0001] This disclosure relates to memory devices and methods of manufacturing the same.

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the memory density for planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] In one aspect, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes peripheral circuitry. The second semiconductor structure includes a memory cell array and multiple bit lines coupled to the memory cells and each extending in a second direction perpendicular to a first direction. Each memory cell includes a vertical transistor extending in the first direction and a memory cell coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction and a gate structure contacting two opposite sides of the semiconductor body in the second direction. A corresponding bit line and a corresponding memory cell are coupled in the first direction to opposite ends of each memory cell in the memory cell. The memory cell array is coupled to the peripheral circuitry via the bonding interface.

[0005] In another aspect, a memory system includes a memory device configured to store data and a memory controller coupled to the memory device. The memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes peripheral circuitry. The second semiconductor structure includes a memory cell array and multiple bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each memory cell includes a vertical transistor extending in the first direction and a memory cell coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction and a gate structure contacting two opposite sides of the semiconductor body in the second direction. A corresponding bit line and a corresponding memory cell are coupled in the first direction to opposite ends of each memory cell in the memory cell array. The memory cell array is coupled to the peripheral circuitry via the bonding interface. The memory controller is configured to control the memory cell array via the peripheral circuitry and the bit lines.

[0006] In another aspect, a method for forming a 3D memory device is disclosed. A first semiconductor structure including peripheral circuitry is formed. A second semiconductor structure is formed. To form the second semiconductor structure, a memory cell array is formed, and multiple bit lines coupled to the memory cells are formed. Each memory cell includes a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction and a gate structure contacting two opposite sides of the semiconductor body in a second direction. A corresponding bit line and a corresponding memory cell are perpendicularly coupled to opposite ends of each memory cell in the memory cell. The first and second semiconductor structures are bonded face-to-face, such that the memory cell array is coupled to the peripheral circuitry via the bonding interface. Attached Figure Description

[0007] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0008] Figure 1A A schematic diagram of a cross-section of a 3D memory device according to some aspects of this disclosure is shown.

[0009] Figure 1B A schematic cross-sectional view of another 3D memory device according to some aspects of this disclosure is shown.

[0010] Figure 2 A schematic diagram of a memory device including peripheral circuitry and an array of memory cells, each having a vertical transistor, is shown, according to some aspects of this disclosure.

[0011] Figure 3 A schematic circuit diagram of a memory device including peripheral circuitry and a dynamic random access memory (DRAM) cell array, according to some aspects of this disclosure, is shown.

[0012] Figure 4 A schematic circuit diagram of a memory device including peripheral circuitry and a phase-change memory (PCM) cell array, according to some aspects of this disclosure, is shown.

[0013] Figure 5 A plan view of memory cell arrays, each including a vertical transistor, in a memory device according to some aspects of this disclosure is shown.

[0014] Figure 6A A side view of a cross-section of a 3D memory device including vertical transistors, according to some aspects of this disclosure, is shown.

[0015] Figure 6B A side view of a cross-section of another 3D memory device including a vertical transistor, according to some aspects of this disclosure, is shown.

[0016] Figure 6C A side view of a cross-section of another 3D memory device including a vertical transistor, according to some aspects of this disclosure, is shown.

[0017] Figure 6D A side view of a cross-section of another 3D memory device including a vertical transistor, according to some aspects of this disclosure, is shown.

[0018] Figure 6E A side view of a cross-section of another 3D memory device including a vertical transistor, according to some aspects of this disclosure, is shown.

[0019] Figure 7 A side view of a cross-section of another 3D memory device including a vertical transistor, according to some aspects of this disclosure, is shown.

[0020] Figure 8 A plan view of another array of memory cells, each including a vertical transistor, in a memory device according to some aspects of this disclosure is shown.

[0021] Figure 9 A side view of a cross-section of another 3D memory device including a vertical transistor, according to some aspects of this disclosure, is shown.

[0022] Figures 10A-10M The present disclosure illustrates a manufacturing process for forming a 3D memory device including vertical transistors, based on some aspects of this disclosure.

[0023] Figures 11A-11I The present disclosure illustrates a manufacturing process for forming another 3D memory device, including vertical transistors, according to some aspects of this disclosure.

[0024] Figures 12A-12H The present disclosure illustrates a manufacturing process for forming another 3D memory device, including vertical transistors, according to some aspects of this disclosure.

[0025] Figures 13A-13H The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure.

[0026] Figures 14A-14E The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure.

[0027] Figures 15A-15D The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure.

[0028] Figure 16 A plan view of another array of memory cells, each including a vertical transistor, in a memory device according to some aspects of this disclosure is shown.

[0029] Figure 17 A side view of a cross-section of another 3D memory device including a vertical transistor, according to some aspects of this disclosure, is shown.

[0030] Figure 18 A perspective view of a vertical transistor array according to some aspects of this disclosure is shown.

[0031] Figures 19A-19M The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure.

[0032] Figure 20 A plan view of another array of memory cells, each including a vertical transistor, in a memory device according to some aspects of this disclosure is shown.

[0033] Figure 21 A side view of a cross-section of another 3D memory device including a vertical transistor, according to some aspects of this disclosure, is shown.

[0034] Figures 22A-22M The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure.

[0035] Figure 23 A flowchart is shown of a method for forming a 3D memory device including vertical transistors, according to some aspects of this disclosure.

[0036] Figure 24 A flowchart is shown of a method for forming memory cell arrays, each comprising vertical transistors, according to some aspects of this disclosure.

[0037] Figure 25 A flowchart is shown of a method for forming another array of memory cells, each comprising a vertical transistor, according to some aspects of this disclosure.

[0038] Figure 26 A flowchart is shown of a method for forming another array of memory cells, each comprising a vertical transistor, according to some aspects of this disclosure.

[0039] Figure 27 A block diagram of an exemplary system having a memory device is shown, according to some aspects of this disclosure.

[0040] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0041] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, and in a manner not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0042] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0043] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without an intermediate feature or layer therebetween (i.e., directly on) the same.

[0044] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (or more) other elements or features as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0045] As used herein, the term "substrate" refers to a material on which subsequent layers of material are added. This substrate itself may be patterned. The material added on top of the substrate may be patterned, or it may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0046] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0047] Transistors are used as switches or selection devices in memory cells of some memory devices, such as DRAM, PCM, and ferroelectric DRAM (FRAM). However, planar transistors commonly used in existing memory cells typically have a horizontal structure, with word lines buried in the substrate and bit lines above the substrate. This increases the area occupied by the transistor because the source and drain of the planar transistor are laterally positioned at different locations. The design of planar transistors also complicates the arrangement of interconnect structures coupled to the memory cells (e.g., word lines and bit lines), for example, by limiting the spacing of word lines and / or bit lines, thus increasing manufacturing complexity and reducing yield. Furthermore, since the bit lines and memory cells (e.g., capacitors or PCM elements) are arranged on the same side of the planar transistor (above the substrate), the bit line process margin is limited by the memory cell, and the coupling capacitance between the bit lines and the memory cells (e.g., capacitors) increases. Planar transistors may also suffer from high leakage currents as the saturation drain current increases, which is undesirable for the performance of the memory device.

[0048] On the other hand, memory cell arrays and the peripheral circuitry used to control them are typically arranged side-by-side in the same plane. As the number of memory cells increases, the dimensions of components in the memory cell array (e.g., transistors, word lines, and / or bit lines) need to be continuously reduced to maintain the same chip size in order to avoid significantly degrading the efficiency of the memory cell array.

[0049] To address one or more of the aforementioned problems, this disclosure describes a solution in which vertical transistors replace conventional planar transistors as switching and selection devices in memory cell arrays of memory devices (e.g., DRAM, PCM, and FRAM). Compared to planar transistors, vertically arranged transistors (i.e., with drain and source overlapping in a planar diagram) can reduce transistor area and simplify the layout of interconnect structures, such as metal wiring word lines and bit lines, which can reduce manufacturing complexity and improve yield. For example, the spacing between word lines and / or bit lines can be reduced for ease of manufacturing. The vertical structure of the transistors also allows bit lines and memory cells (e.g., capacitors) to be arranged vertically on opposite sides of the transistor (e.g., one above the transistor and one below), thereby increasing the process margin of the bit lines and reducing the coupling capacitance between the bit lines and the memory cells.

[0050] Consistent with the scope of this disclosure, according to some aspects of this disclosure, memory cell arrays with vertical transistors and peripheral circuitry of the memory cell arrays can be formed on different wafers and bonded together face-to-face. Therefore, the thermal budget for manufacturing the memory cell arrays does not affect the manufacturing of the peripheral circuitry. Compared to side-by-side arrangements, stacked memory cell arrays and peripheral circuitry can also reduce chip size, thereby improving array efficiency. In some embodiments, bonding techniques are used to stack more than one memory cell array on top of each other to further increase array efficiency. In some embodiments, due to the vertically arranged transistors, word lines and bit lines are positioned close to the bonding interface, allowing the vertically arranged transistors to be coupled to the peripheral circuitry via a large number (e.g., millions) of parallel bonding contacts across the bonding interface. This enables direct, short-distance (e.g., micrometer-scale) electrical connections between the memory cell array and the peripheral circuitry to increase the throughput and input / output (I / O) speed of the memory device.

[0051] In some embodiments, the vertical transistors disclosed herein include multi-gate transistors (e.g., gate-all-around (GAA) transistors, tri-gate transistors, or dual-gate transistors). Multi-gate transistors can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off-state, the leakage current of multi-gate transistors can also be significantly reduced because the channel is fully depleted. Therefore, using multi-gate transistors instead of planar transistors can achieve much better speed (saturation drain current) / leakage current performance.

[0052] In some implementations, the vertical transistors disclosed herein comprise single-gate transistors (also referred to as single-sided gate transistors) arranged in a mirror-symmetric manner with respect to adjacent transistors in the bit-line direction, since multi-gate transistors (e.g., dual-gate transistors) are isolated using trench isolation extending along the word line direction. Therefore, the memory cell density in the bit-line direction can be significantly increased (e.g., doubled) without overcomplicating the fabrication process compared to processes such as self-aligned double patterning (SADP). Furthermore, the mirror-symmetric single-gate transistor offers a larger process window for word line, bit line, and transistor pitch reduction compared to conventional planar transistors or multi-gate vertical transistors (e.g., those with dual-sided or full-ring gates).

[0053] Figure 1A A schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. The 3D memory device 100 represents an example of a bonded chip. Components of the 3D memory device 100 (e.g., memory cell array and peripheral circuitry) may be formed separately on different substrates and then bonded to form a bonded chip. The 3D memory device 100 may include a first semiconductor structure 102 including peripheral circuitry for the memory cell array. The 3D memory device 100 may also include a second semiconductor structure 104 including the memory cell array. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some embodiments, the peripheral circuitry in the first semiconductor structure 102 utilizes complementary metal-oxide-semiconductor (CMOS) technology, for example, which may be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0054] like Figure 1AAs shown, the 3D memory device 100 may further include a second semiconductor structure 104, which includes an array (memory cell array) of memory cells that can use transistors as switching and selection devices. In some embodiments, the memory cell array includes a DRAM cell array. For ease of description, a DRAM cell array may be used as an example for describing the memory cell array in this disclosure. However, it should be understood that the memory cell array is not limited to a DRAM cell array and may include any other suitable type of memory cell array that can use transistors as switching and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, an FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name just a few examples, or any combination thereof.

[0055] The second semiconductor structure 104 may be a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells. In some embodiments, each DRAM cell includes a capacitor for storing data bits as positive or negative charge and one or more transistors (also called transfer transistors) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor-capacitor (ITIC) cell. Since transistors always leak a small amount of charge, capacitors will discharge slowly, causing the information stored therein to be depleted. Thus, according to some embodiments, the DRAM cell must be refreshed, for example, by peripheral circuitry in the first semiconductor structure 102 to retain the data.

[0056] like Figure 1A As shown, the 3D memory device 100 also includes a portion perpendicularly positioned between the first semiconductor structure 102 and the second semiconductor structure 104 (in the vertical direction, for example, Figure 1AThe bonding interface 106 (in the z-direction) is used. As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 can be manufactured separately (and in some embodiments in parallel), such that the thermal budget for manufacturing one of the semiconductor structures 102 and 104 does not limit the process for manufacturing the other semiconductor structure. Furthermore, a large number of interconnects (e.g., bonding contacts) can be formed through the bonding interface 106 to provide direct, short-distance (e.g., micrometer-scale) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, instead of long-distance (e.g., millimeter- or centimeter-scale) chip-to-chip data buses on a circuit board (e.g., a printed circuit board, PCB), thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array in the second semiconductor structure 104 and the peripheral circuitry in the first semiconductor structure 102 can be performed via interconnects (e.g., bonding contacts) through the bonding interface 106. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, the chip size can be reduced and the memory cell density can be increased.

[0057] It should be understood that the relative positions of the stacked first semiconductor structure 102 and the second semiconductor structure 104 are not restricted. Figure 1B A schematic cross-sectional view of another exemplary 3D memory device 101 according to some embodiments is shown. Figure 1A Unlike the 3D memory device 100, in the 3D memory device 100, a second semiconductor structure 104 including a memory cell array is located above a first semiconductor structure 102 including peripheral circuitry. Figure 1B In the 3D memory device 101, a first semiconductor structure 102 including peripheral circuitry is positioned above a second semiconductor structure 104 including an array of memory cells. However, according to some embodiments, a bonding interface 106 is vertically formed between the first semiconductor structure 102 and the second semiconductor structure 104 in the 3D memory device 101, and the first semiconductor structure 102 and the second semiconductor structure 104 are vertically joined by bonding (e.g., hybrid bonding). Hybrid bonding (also referred to as "metal / dielectric hybrid bonding") is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-metal (e.g., copper-copper) bonding and dielectric-dielectric (e.g., silicon oxide-silicon oxide) bonding. Data transfer between the memory cell array in the second semiconductor structure 104 and the peripheral circuitry in the first semiconductor structure 102 can be performed via interconnects (e.g., bonding contacts) through the bonding interface 106.

[0058] Notice, Figure 1A and Figure 1B The x, y, and z axes are included to further illustrate the spatial relationships of components in 3D memory devices 100 and 101. The substrate of the 3D memory device includes two lateral surfaces extending laterally in the xy plane: a top surface on the front side of the wafer, on which semiconductor devices may be formed, and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, when the substrate is positioned in the lowest plane of the 3D memory device in the z-direction (a direction perpendicular to the xy plane, e.g., the thickness direction of the substrate), the z-direction relative to the substrate of the 3D memory device determines whether one component (e.g., a layer or device) of the 3D memory device is “on,” “above,” or “below” another component (e.g., a layer or device). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0059] Figure 2 A schematic diagram of a memory device 200, including peripheral circuitry and arrays of memory cells, each having a vertical transistor, according to some aspects of this disclosure, is shown. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. 3D memory devices 100 and 101 may be examples of memory devices 200 in which the memory cell array 201 and peripheral circuitry 202 may be respectively included in a second semiconductor structure 104 and a first semiconductor structure 102. The memory cell array 201 may be any suitable memory cell array, wherein each memory cell 208 includes a vertical transistor 210 and a memory cell 212 coupled to the vertical transistor 210. In some embodiments, the memory cell array 201 is a DRAM cell array, and the memory cell 212 is a capacitor for storing charge as binary information stored by the respective DRAM cell. In some embodiments, the memory cell array 201 is a PCM cell array, and the storage cell 212 is a PCM element (e.g., including chalcogenide alloys) used to store binary information of the corresponding PCM cell based on the different resistivities of the PCM element in the amorphous and crystalline phases. In some embodiments, the memory cell array 201 is an FRAM cell array, and the storage cell 212 is a ferroelectric capacitor used to store binary information of the corresponding FRAM cell based on the switching between two polarization states of the ferroelectric material under an external electric field.

[0060] like Figure 2As shown, memory cells 208 can be arranged in a two-dimensional (2D) array having rows and columns. Memory device 200 may include word lines 204 coupling peripheral circuitry 202 to the memory cell array 201 for controlling the switching of vertical transistors 210 in the memory cells 208 located in a row, and bit lines 206 coupling peripheral circuitry 202 to the memory cell array 201 for sending data to and / or receiving data from the memory cells 208 located in a column. That is, each word line 204 is coupled to a memory cell 208 in a corresponding row, and each bit line is coupled to a memory cell 208 in a corresponding column.

[0061] Consistent with the scope of this disclosure, a vertical transistor 210, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), can replace a conventional planar transistor as the transfer transistor for memory cell 208 to reduce the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity, as described in detail below. Figure 2 As shown, in some embodiments, unlike planar transistors in which an active region is formed in a substrate, the vertical transistor 210 includes a semiconductor body 214 extending vertically (in the z-direction) above a substrate (not shown). That is, the semiconductor body 214 may extend above the top surface of the substrate to expose not only the top surface of the semiconductor body 214 but also one or more side surfaces of the semiconductor body 214. Figure 2 As shown, for example, the semiconductor body 214 may have a cubic shape to expose its four sides. It should be understood that the semiconductor body 214 may have any suitable 3D shape, such as a polyhedral or cylindrical shape. That is, the cross-section of the semiconductor body 214 in a planar view (e.g., in the xy plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular (or elliptical) shape, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, for a semiconductor body having a circular or elliptical cross-section in a planar view, the semiconductor body may still be considered to have multiple sides, such that the gate structure contacts more than one side of the semiconductor body. As described below regarding the manufacturing process, the semiconductor body 214 may be formed from a substrate (e.g., by etching or epitaxy) and therefore have the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0062] like Figure 2As shown, the vertical transistor 210 may further include a gate structure 216 that contacts one or more sides of the semiconductor body 214, i.e., in one or more planes on one or more side surfaces of the active region(s). That is, the active region of the vertical transistor 210 (i.e., the semiconductor body 214) may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate dielectric 218 over one or more sides of the semiconductor body 214, for example, such as... Figure 2 The gate structure 216 is shown to contact the four side surfaces of the semiconductor body 214. The gate structure 216 may also include a gate electrode 220 on and in contact with the gate dielectric 218. The gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 218 may include silicon oxide, i.e., a gate oxide. The gate electrode 220 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 220 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 220 includes multiple conductive layers, such as a W layer over a TiN layer. It should be understood that in some examples, the gate electrode 220 and the word line 204 may be a continuous conductive structure. That is, the gate electrode 220 can be regarded as part of the word line 204 forming the gate structure 216, or the word line 204 can be regarded as an extension of the gate electrode 220 to couple to the peripheral circuit 202.

[0063] like Figure 2 As shown, the vertical transistor 210 may further include a pair of source and drain electrodes (S / D, doped regions, also referred to as source and drain electrodes) formed respectively at two ends of the semiconductor body 214 in the vertical direction (z-direction). The source and drain electrodes may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain electrodes may be separated in the vertical direction (z-direction) by a gate structure 216. That is, the gate structure 216 is formed vertically between the source and drain electrodes. As a result, when the gate voltage applied to the gate electrode 220 of the gate structure 216 is higher than the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be formed vertically between the source and drain electrodes in the semiconductor body 214. That is, according to some embodiments, each channel of the vertical transistor 210 is also formed in the vertical direction along which the semiconductor body 214 extends.

[0064] In some implementations, such as Figure 2As shown, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 can be connected to more than one side of the semiconductor body 214 (e.g., Figure 2 The four sides of the semiconductor body 214 are contacted to form more than one gate, allowing more than one channel to be formed between the source and drain during operation. That is, unlike planar transistors that only include a single planar gate (and create a single planar channel), the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214 enable the formation of more than one gate. Figure 2 The vertical transistor 210 shown may include multiple vertical gates on multiple sides of the semiconductor body 214. As a result, compared to planar transistors, Figure 2 The vertical transistor 210 shown can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off-state, the leakage current (Ileakage) of the vertical transistor 210 is reduced because the channel is fully depleted. off The size can also be significantly reduced. As described in detail below, multi-gate vertical transistors can include dual-gate vertical transistors (e.g., dual-side-gate vertical transistors), tri-gate vertical transistors (e.g., tri-side-gate vertical transistors), and GAA vertical transistors.

[0065] It should be understood that, although the vertical transistor 210 in Figure 2 While shown as a multi-gate transistor, the vertical transistor disclosed herein may also include a single-gate transistor as described in detail below. That is, for example, for the purpose of increasing transistor and memory cell density, the gate structure 216 may contact a single side of the semiconductor body 214. It should also be understood that although the gate dielectric 218 is shown separated from other gate dielectrics of adjacent vertical transistors (not shown) (i.e., a separated structure), the gate dielectric 218 may be part of a continuous dielectric layer of multiple gate dielectrics having vertical transistors.

[0066] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), the active region (e.g., the semiconductor body (e.g., a fin)) extends laterally (in the xy plane), and the source and drain are located at different positions in the same lateral plane (xy plane). Conversely, according to some embodiments, in the vertical transistor 210, the semiconductor body 214 extends vertically (in the z-direction), and the source and drain are located in different lateral planes. In some embodiments, the source and drain are formed at two ends of the semiconductor body 214 in the vertical direction (z-direction), thus overlapping in a planar view. As a result, the area occupied by the vertical transistor 210 (in the xy plane) can be reduced compared to planar transistors and lateral multi-gate transistors. Furthermore, the metal wiring coupled to the vertical transistor 210 can also be simplified because the interconnects can be wired in different planes. For example, bit line 206 and memory cell 212 can be formed on opposite sides of the vertical transistor 210. In one example, bit line 206 may be coupled to a source or drain at the upper end of semiconductor body 214, while memory cell 212 may be coupled to another source or drain at the lower end of semiconductor body 214.

[0067] like Figure 2 As shown, memory cell 212 can be coupled to the source or drain of vertical transistor 210. Memory cell 212 can include any device capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM and FRAM cells and PCM elements for PCM cells. In some embodiments, vertical transistor 210 controls the selection and / or state switching of the corresponding memory cell 212 coupled to vertical transistor 210. Figure 3 In some embodiments shown, each memory cell 208 includes a transistor 304 (e.g., using...). Figure 2 The vertical transistor 210 in the embodiment) and capacitor 306 (e.g., Figure 2 DRAM cell 302 (example of memory cell 212 in the example). The gate of transistor 304 (e.g., corresponding to gate electrode 220) can be coupled to word line 204, one of the source and drain of transistor 304 can be coupled to bit line 206, the other of the source and drain of transistor 304 can be coupled to one electrode of capacitor 306, and the other electrode of capacitor 306 can be coupled to ground. Figure 4 In some embodiments shown, each memory cell 208 includes a transistor 404 (e.g., using...). Figure 2 Vertical transistor 210 is implemented in the middle) and PCM element 406 (e.g., Figure 2(Example of memory cell 212) PCM cell 402. The gate of transistor 404 (e.g., corresponding to gate electrode 220) may be coupled to word line 204, one of the source and drain of transistor 404 may be coupled to ground, the other of the source and drain of transistor 404 may be coupled to one electrode of PCM element 406, and the other electrode of PCM element 406 may be coupled to bit line 206.

[0068] Peripheral circuitry 202 can be coupled to memory cell array 201 via bit lines 206, word lines 204, and any other suitable metal wiring. As described above, peripheral circuitry 202 can include any suitable circuitry for facilitating operation of memory cell array 201 by applying voltage and / or current signals to each memory cell 208 via word lines 204 and bit lines 206, and sensing voltage and / or current signals from each memory cell 208. Peripheral circuitry 202 can include various types of peripheral circuitry formed using CMOS technology.

[0069] According to some aspects of this disclosure, the vertical transistors of the memory cells in a memory device (e.g., memory device 200) are multi-gate transistors, and the gate dielectrics of the vertical transistors in the word line direction are discrete. For example, Figure 5 A plan view is shown of an array of memory cells 502, each including a vertical transistor, in a memory device 500 according to some aspects of this disclosure. (See diagram below.) Figure 5 As shown, the memory device 500 may include multiple word lines 504, each extending in a first lateral direction (x-direction, referred to as the word line direction). The memory device 500 may also include multiple bit lines 506, each extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. It should be understood that... Figure 5 The memory device 500 is not shown in a cross-section in the same transverse plane, and word lines 504 and bit lines 506 may be formed in different transverse planes to facilitate wiring as described in detail below.

[0070] Memory cells 502 may be formed at the intersection of word lines 504 and bit lines 506. In some embodiments, each memory cell 502 includes a vertical transistor having a semiconductor body 508 and a gate structure 510 (e.g., Figure 2 The vertical transistor 210 in the semiconductor body 508 may extend in a vertical direction (z-direction, not shown) perpendicular to the first and second lateral directions. The vertical transistor may be a multi-gate transistor, wherein the gate structure 510 is adjacent to multiple sides of the semiconductor body 508 (wherein the active region forming the channel) (e.g., Figure 5 All four sides of the surface are in contact. Figure 5As shown, the vertical transistor is a GAA transistor, wherein the gate structure 510 is completely external to the semiconductor body 508 in a plan view. That is, according to some embodiments, the gate structure 510 is external to (e.g., surrounds and contacts) all four sides (having a rectangular or square cross-section) of the semiconductor body 508 in a plan view. The gate structure 510 may include a gate dielectric 512 completely external to the semiconductor body 508 in a plan view, and a gate electrode 514 completely external to the gate dielectric 512. In some embodiments, the gate dielectric 512 is laterally located between the gate electrode 514 and the semiconductor body 508 in the bit line direction and word line direction. As mentioned above, the gate electrode 514 may be a portion of the word line 504, and the word line 504 may be an extension of the gate electrode 514.

[0071] like Figure 5 As shown, the gate electrodes 514 of adjacent vertical transistors in the word line direction (x direction) are continuous, for example, they are portions of a continuous conductive layer having gate electrodes 514 and 504. Conversely, the gate dielectrics 512 of adjacent vertical transistors in the word line direction are separate, for example, they are not portions of a continuous dielectric layer having gate dielectrics 512.

[0072] Figure 6A A side view of a cross-section of a 3D memory device 600 including vertical transistors according to some aspects of this disclosure is shown. The 3D memory device 600 may be an example of a memory device 500 including multi-gate vertical transistors, wherein the gate structure is completely external to the semiconductor body in the plan view, such as a GAA vertical transistor. It should be understood that... Figure 6A This is for illustrative purposes only and does not necessarily need to reflect the actual device structure (e.g., interconnects). As mentioned above regarding... Figure 1A An example of the described 3D memory device 100 is a bonded chip comprising a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 106 between them. Figure 6A As shown, the first semiconductor structure 102 may include a substrate 610, which may include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0073] The first semiconductor structure 102 may include peripheral circuitry 612 on substrate 610. In some embodiments, peripheral circuitry 612 includes a plurality of transistors 614 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 614) may also be formed on or in substrate 610.

[0074] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 616 above the peripheral circuitry 612 for transmitting electrical signals to and from the peripheral circuitry 612. The interconnect layer 616 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and vertical interconnect access (VIA) contacts. As used herein, the term “interconnect” can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 616 may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which interconnects and via contacts can be formed. That is, the interconnect layer 616 may include interconnects and via contacts in multiple ILD layers. In some embodiments, the peripheral circuitry 612 is coupled to each other via interconnects in the interconnect layer 616. The interconnects in interconnect layer 616 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0075] like Figure 6A As shown, the first semiconductor structure 102 may further include a bonding layer 618 at the bonding interface 106 and above the interconnect layer 616 and the peripheral circuitry 612. The bonding layer 618 may include a plurality of bonding contacts 619 and a dielectric material electrically isolating the bonding contacts 619. The bonding contacts 619 may include a conductive material, such as Cu. The remaining region of the bonding layer 618 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 619 in the bonding layer 618 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as Figure 6AAs shown, the second semiconductor structure 104 may also include a bonding layer 620 at the bonding interface 106 and above the bonding layer 618 of the first semiconductor structure 102. The bonding layer 620 may include a plurality of bonding contacts 621 and a dielectric material electrically isolating the bonding contacts 621. The bonding contacts 621 may include a conductive material, such as Cu. The remaining region of the bonding layer 620 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 621 in the bonding layer 620 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 621 contact the bonding contacts 619 at the bonding interface 106.

[0076] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), the bonding interface 106 is disposed between the bonding layers 620 and 618. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is the location where the bonding layers 620 and 618 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness, comprising the top surface of the bonding layer 618 of the first semiconductor structure 102 and the bottom surface of the bonding layer 620 of the second semiconductor structure 104.

[0077] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 622, which includes bit lines 623 above the bonding layer 620 for transmitting electrical signals. The interconnect layer 622 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 622 also include local interconnects, such as bit lines 623 (e.g., Figure 5Examples of bit lines 506, bit line contacts 625 (which may be omitted in some examples), and word line contacts 627 are shown. Interconnect layer 622 may also include one or more ILD layers in which interconnects and via contacts may be formed. Interconnects in interconnect layer 622 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, peripheral circuitry 612 includes a word line driver / line decoder coupled to word line contacts 627 in interconnect layer 622 via bonding contacts 621 and 619 in bonding layers 620 and 618 and interconnect layer 616. In some implementations, peripheral circuitry 612 includes a bit line driver / column decoder that is coupled to bit lines 623 and bit line contacts 625 in interconnect layer 622 via bonding contacts 621 and 619 in bonding layers 620 and 618 and interconnect layer 616.

[0078] In some embodiments, the second semiconductor structure 104 includes a DRAM device, wherein the memory cells are DRAM cells 624 (e.g., Figure 5 An array of memory cells 502 (as in the example) is provided above the interconnect layer 622 and the bonding layer 620. That is, the interconnect layer 622, including bit lines 623, can be disposed between the bonding layer 620 and the array of DRAM cells 624. It should be understood that... Figure 6A The cross-section of the 3D memory device 600 can be cut along the bit line direction (y direction), and a bit line 623 extending laterally in the y direction in the interconnect layer 622 can be coupled to a row of DRAM cells 624.

[0079] Each DRAM cell 624 may include a vertical transistor 626 (e.g., Figure 2 (Example of vertical transistor 210 in the example) and capacitor 628 coupled to vertical transistor 626 (e.g., Figure 2 (Example of memory cell 212 in the example). DRAM cell 624 can be a 1T1C cell consisting of a transistor and a capacitor. It should be understood that DRAM cell 624 can be any suitable construction, such as a 2T1C cell, a 3T1C cell, etc.

[0080] The vertical transistor 626 may be a MOSFET for switching a corresponding DRAM cell 624. In some embodiments, the vertical transistor 626 includes a vertically (in the z-direction) extending semiconductor body 630 (i.e., an active region in which multiple channels may be formed) and a gate structure 636 contacting multiple sides of the semiconductor body 630. As described above, such as in a GAA vertical transistor, the semiconductor body 630 may have a cubic or cylindrical shape, and the gate structure 636 may be completely external to the semiconductor body 630 in a planar view, for example, as... Figure 5 As shown. According to some embodiments, the gate structure 636 includes a gate electrode 634 and a gate dielectric 632 laterally disposed between the gate electrode 634 and the semiconductor body 630. For example, for a semiconductor body 630 having a cylindrical shape, the semiconductor body 630, the gate dielectric 632, and the gate electrode 634 may be arranged radially from the center of the vertical transistor 626 in this order. In some embodiments, the gate dielectric 632 surrounds and contacts the semiconductor body 630, and the gate electrode 634 surrounds and contacts the gate dielectric 632.

[0081] like Figure 6A As shown, in some embodiments, the semiconductor body 630 has two ends (an upper end and a lower end) in the vertical direction (z-direction), and the two ends extend beyond the gate structure 636 into the ILD layer in the vertical direction (z-direction), respectively. That is, the semiconductor body 630 may have a larger vertical dimension (e.g., depth) (e.g., in the z-direction) than the vertical dimension of the gate structure 636, and neither the upper nor lower end of the semiconductor body 630 is flush with the corresponding end of the gate structure 636. Therefore, short circuits between the bit line 623 and the word line / gate electrode 634 or between the word line / gate electrode 634 and the capacitor 628 can be avoided. In some embodiments, the two ILD layers into which the semiconductor body 630 extends (e.g., the ILD layer perpendicularly between the bit line contact 625 and the word line 634, and the ILD layer perpendicularly between the word line 634 and the capacitor 628) comprise the same dielectric material, such as silicon oxide. The vertical transistor 626 may also include a source and a drain (both referred to as 638) respectively disposed at two ends (upper and lower ends) of the semiconductor body 630 in the vertical direction (z-direction). In some embodiments, one of the source and drain 638 (e.g., in...) Figure 6A At the upper end of the middle) it is coupled to capacitor 628, and another of the source and drain 638 (e.g., in the upper end of the middle) ... Figure 6A At the lower end of the line, it is coupled to bit line 623 (e.g., via bit line contact 625 or directly).

[0082] In some embodiments, the semiconductor body 630 comprises a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 630 may comprise monocrystalline silicon. The source and drain 638 may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain 638 and the bit line contact 625 or the first electrode 642 to reduce contact resistance. In some embodiments, the gate dielectric 632 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), or any combination thereof. In some embodiments, the gate electrode 634 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some implementations, the gate electrode 634 includes multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 636 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 632 comprises silicon oxide and the gate electrode 634 comprises doped polysilicon. In another example, the gate structure 636 may be a high-k metal gate (HKMG), wherein the gate dielectric 632 comprises a high-k dielectric and the gate electrode 634 comprises metal.

[0083] As described above, since the gate electrode 634 can be a portion of the word line or as part of the word line in the word line direction (e.g., Figure 5 Extending in the x-direction (in the middle), therefore although in Figure 6A Not directly shown, but the second semiconductor structure 104 of the 3D memory device 600 may also include multiple word lines, each extending in the word line direction (x direction) (e.g., Figure 5 An example of word line 504 (also referred to as 634) is shown. Each word line 634 can be coupled to a row of DRAM cells 624. That is, bit lines 623 and word lines 634 can extend in two perpendicular lateral directions, and the semiconductor body 630 of the vertical transistor 626 can extend in a vertical direction perpendicular to the two lateral directions along which the bit lines 623 and word lines 634 extend. According to some embodiments, word lines 634 are in contact with word line contacts 627. In some embodiments, word lines 634 comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, word lines 634 comprise multiple conductive layers, such as a W layer over a TiN layer.

[0084] like Figure 6A As shown, according to some embodiments, the vertical transistor 626 extends vertically through and contacts the word line 634, and the source or drain 638 at its lower end contacts the bit line contact 625 or directly contacts the bit line 623. Therefore, due to the vertical arrangement of the vertical transistor 626, the word line 634 and the bit line 623 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 634 and the bit line 623. In some embodiments, the bit line 623 is vertically disposed between the bonding layer 620 and the word line 634, and the word line 634 is vertically disposed between the bit line 623 and the capacitor 628. The word line 634 can be coupled to the peripheral circuitry 612 in the first semiconductor structure 102 via the word line contact 627 in the interconnect layer 622, the bonding contacts 621 and 619 in the bonding layers 620 and 618, and the interconnects in the interconnect layer 616. Similarly, bit lines 623 in interconnect layer 622 can be coupled to peripheral circuits 612 in the first semiconductor structure 102 via bonding contacts 621 and 619 in bonding layers 620 and 618 and interconnects in interconnect layer 616.

[0085] In some embodiments, the second semiconductor structure 104 further includes a plurality of air gaps 640, each laterally disposed between adjacent word lines 634. Each air gap 640 may be a trench extending parallel to the word line 634 in the word line direction (e.g., the x-direction) to separate the vertical transistors 626 of adjacent rows. As described below regarding the manufacturing process, the air gaps 640 can be formed because the spacing between the word lines 634 (and the rows of DRAM cells 624) in the bit line direction (e.g., the y-direction) is relatively small. On the other hand, the relatively large dielectric constant of the air in the air gaps 640 (e.g., about 4 times the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the word lines 634 (and the rows of DRAM cells 624).

[0086] like Figure 6AAs shown, in some embodiments, capacitor 628 includes a first electrode 642 above and in contact with the source or drain 638 of vertical transistor 626 (e.g., the upper end of semiconductor body 630). Capacitor 628 may also include a capacitor dielectric 644 above and in contact with the first electrode 642, and a second electrode 646 above and in contact with the capacitor dielectric 644. That is, capacitor 628 may be a vertical capacitor, wherein electrodes 642 and 646 and capacitor dielectric 644 are stacked vertically (in the z-direction), and capacitor dielectric 644 may be sandwiched between electrodes 642 and 646. In some embodiments, each first electrode 642 is coupled to the source or drain 638 of a corresponding vertical transistor 626 in the same DRAM cell, while all second electrodes 646 are portions of a common plate coupled to ground (e.g., common ground). Figure 6A As shown, the second semiconductor structure 104 may further include capacitor contacts 647 that contact a common plate with the second electrode 646 for coupling the second electrode 646 of the capacitor 628 to the peripheral circuit 612 or directly to ground. In some embodiments, the ILD layer forming the capacitor 628 has the same dielectric material, such as silicon oxide, as the two ILD layers extending therefrom in the semiconductor body 630.

[0087] It should be understood that the structure and construction of capacitor 628 are not limited to... Figure 6A Examples are provided, and any suitable structure and construction may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-planar capacitors. In some embodiments, capacitor dielectric 644 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 628 may be a ferroelectric capacitor used in FRAM cells, and capacitor dielectric 644 may be replaced by a ferroelectric layer having a ferroelectric material (e.g., lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT)). In some embodiments, electrodes 642 and 646 comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0088] like Figure 6AAs shown, according to some embodiments, the vertical transistor 626 extends vertically through and contacts the word line 634. The source or drain 638 of the vertical transistor 626 at its lower end contacts the bit line contact 625 or directly contacts the bit line 623, and the source or drain 638 of the vertical transistor 626 at its upper end contacts the electrode 642 of the capacitor 628. That is, the bit line 623 and the capacitor 628 can be arranged in different planes in the vertical direction and are vertically coupled to opposite ends of the vertical transistor 626 of the DRAM cell 624 due to the vertical arrangement of the vertical transistor 626. In some embodiments, the bit line 623 and the capacitor 628 are arranged on opposite sides of the vertical transistor 626 in the vertical direction. Compared to conventional DRAM cells where the bit line and capacitor are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 623 and reduces the coupling capacitance between the bit line 623 and the capacitor 628.

[0089] like Figure 6A As shown, in some embodiments, the vertical transistor 626 is vertically disposed between the capacitor 628 and the bonding interface 106. That is, the vertical transistor 626 can be arranged closer to the peripheral circuitry 612 and the bonding interface 106 of the first semiconductor structure 102 than the capacitor 628. According to some embodiments, since the bit line 623 and the capacitor 628 are coupled to opposite ends of the vertical transistor 626 as described above, the bit line 623 (as part of the interconnect layer 622) is vertically disposed between the vertical transistor 626 and the bonding interface 106. As a result, the interconnect layer 622, including the bit line 623, can be arranged close to the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0090] In some embodiments, the second semiconductor structure 104 further includes a substrate 648 disposed above the DRAM cell 624. As described below regarding the manufacturing process, the substrate 648 may be a portion of a carrier wafer. It should be understood that in some examples, the substrate 648 may not be included in the second semiconductor structure 104.

[0091] like Figure 6AAs shown, the second semiconductor structure 104 may further include a pad-out interconnect layer 650 above the substrate 648 and the DRAM cell 624. The pad-out interconnect layer 650 may include interconnects in one or more ILD layers, such as contact pads 654. The pad-out interconnect layer 650 and the interconnect layer 622 may be formed on opposite sides of the DRAM cell 624. According to some embodiments, a capacitor 628 is vertically disposed between the vertical transistor 626 and the pad-out interconnect layer 650. In some embodiments, for example for pad-out purposes, the interconnects in the pad-out interconnect layer 650 may transmit electrical signals between the 3D memory device 600 and external circuitry. In some embodiments, the second semiconductor structure 104 may also include one or more contacts 652 extending through portions of the substrate 648 and the pad-out interconnect layer 650 to couple the pad-out interconnect layer 650 to the DRAM cell 624 and the interconnect layer 622. As a result, peripheral circuitry 612 can be coupled to DRAM cell 624 via interconnect layers 616 and 622 and bonding layers 620 and 618, and peripheral circuitry 612 and DRAM cell 624 can be coupled to external circuitry via contact 652 and pads leading out of interconnect layer 650. Contact pads 654 and contact 652 can include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, contact pad 654 can include Al, and contact 652 can include W. In some embodiments, contact 652 includes a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the via from substrate 648. Depending on the thickness of substrate 648, contact 652 can be an interlayer via (ILV) with a submicron depth (e.g., between 10 nm and 1 μm), or a through substrate via (TSV) with a micron or tens of micron depth (e.g., between 1 μm and 100 μm).

[0092] It should be understood that the pad leads of 3D memory devices are not limited to those from, for example... Figure 6A The second semiconductor structure 104 shown has DRAM cells 624 and can be derived from the first semiconductor structure 102 having peripheral circuitry 612. For example, as... Figure 6BAs shown, the 3D memory device 601 may include a pad-out interconnect layer 650 in a first semiconductor structure 102. The pad-out interconnect layer 650 may be disposed above and in contact with a substrate 610 of the first semiconductor structure 102 on which transistors 614 with peripheral circuitry 612 are formed. In some embodiments, the first semiconductor structure 102 further includes one or more contacts 653 extending vertically through the substrate 610. In some embodiments, the contacts 653 couple interconnects in interconnect layers 616 of the first semiconductor structure 102 to contact pads 654 in the pad-out interconnect layer 650 for electrical connection through the substrate 610. The contacts 653 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contacts 653 may include W. In some embodiments, the contacts 653 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the substrate 610. It should be understood that in some examples, for example with... Figure 6A Compared to substrate 610, Figure 6B The substrate 610 can be a thinned substrate. Depending on the thickness of the substrate 610, the contact 653 can be an ILV with a submicron depth (e.g., between 10 nm and 1 μm) or a TSV with a micron or tens of micron depth (e.g., between 1 μm and 100 μm). It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 600 and 601 are not repeated. Pad leads from the first semiconductor structure 102, including peripheral circuitry 612, can reduce the interconnect distance between the contact pad 654 and the peripheral circuitry 612, thereby reducing parasitic capacitance from the interconnect and improving the electrical performance of the 3D memory device 601.

[0093] It should also be understood that the relative vertical position between the semiconductor body and the corresponding gate structure and word line is not limited to Figure 6A The example shown illustrates that the upper and lower ends of the semiconductor body 630 extend beyond the gate structure 636 (and word line 634), respectively, depending on the various manufacturing processes described in detail below. For example, as... Figure 6CAs shown, the 3D memory device 603 may include vertical transistors 626, each having a semiconductor body 630 and a gate structure 636, and one end of the semiconductor body 630 in the vertical direction (z-direction) may be flush with the gate structure 636. In some embodiments, the upper or lower end of the semiconductor body 630 that contacts the first electrode 642 of the capacitor 628 is flush with the corresponding end of the gate structure 636 and the word line 634. That is, according to some embodiments, one of the upper and lower ends of the semiconductor body 630 that contacts the capacitor 628 does not extend beyond the corresponding end of the gate structure 636 and the word line 634. In some embodiments, such as Figure 6C As shown, the other end of the semiconductor body 630 that contacts the bit line contact 625 in the vertical direction still extends beyond the corresponding ends of the gate structure 636 and the word line 634 into the ILD layer, which is perpendicular between the bit line contact 625 and the word line 634. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 600 and 603 are not repeated.

[0094] It should also be understood that the dielectric material of the ILD layer extending into the semiconductor body is not limited to... Figure 6A The example shown includes an ILD layer comprising silicon oxide, for example, the same material as the ILD layer in which capacitor 628 is formed, depending on various manufacturing processes described in detail below. For example, as... Figure 6D As shown, the 3D memory device 605 may include two ILD layers 660 and 662 extending therein from a semiconductor body 630. According to some embodiments, ILD layer 660 is perpendicularly positioned between a bit line contact 625 and a word line 634, and ILD layer 662 is perpendicularly positioned between the word line 634 and a first electrode 642 of a capacitor 628. ILD layers 660 and 662 may include a dielectric material different from the dielectric material of the ILD layer in which the capacitor 628 is formed. In some embodiments, ILD layers 660 and 662 comprise silicon nitride, while the ILD layer of the capacitor 628 comprises silicon oxide. Figure 6D As shown, in some embodiments, one end of the semiconductor body 630 that contacts the capacitor 628 in the vertical direction (z-direction) is flush with the corresponding end of the ILD layer 662. In some embodiments, the air gap 640 extends vertically through the ILD layer 662 to separate the ILD layer 662, but does not extend further into the ILD layer 660, i.e., it is stopped by the ILD layer 660. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 600 and 605 are not repeated.

[0095] It should also be understood that the air gaps between word lines can be partially or completely filled with dielectric material. For example, such as... Figure 6E As shown, memory device 607 may not include an air gap between adjacent word lines 634 (e.g., Figure 6A The air gap 640 in the memory device 600 is not shown. Conversely, the memory device 607 may include dielectric wall structures 641 (e.g., filled with a dielectric, such as silicon oxide) formed between adjacent word lines 634. It should be understood that in some examples (not shown), the air gap 640 may still exist between the word lines 634, but with a smaller vertical dimension (depth) compared to the word lines 634. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 600 and 607 are not repeated.

[0096] It should also be understood that more than one DRAM cell array can be stacked on top of each other to vertically and proportionally increase the number of DRAM cells. For example, as Figure 7 As shown, the memory device 700 may further include a third semiconductor structure 702 having an array of DRAM cells 624 stacked on top of the second semiconductor structure 104 and the first semiconductor structure 102. According to some embodiments, the third semiconductor structure 702 and the second semiconductor structure 104 are bonded at another bonding interface 704 therebetween. The third semiconductor structure 702 and the second semiconductor structure 104 may have the same array of DRAM cells 624 and interconnect layer 622, and therefore, for ease of description, the details of the DRAM cells 624 and interconnect layer 622 in the third semiconductor structure 702 will not be repeated.

[0097] According to some embodiments, the third semiconductor structure 702 and the second semiconductor structure 104 can be bonded face-to-face, such that at least some components (e.g., DRAM cells 624) in the third semiconductor structure 702 and the second semiconductor structure 104 can be symmetrical about the bonding interface 704. The bonding interface 704 can be formed vertically between the DRAM cells 624 in the third semiconductor structure 702 and the DRAM cells 624 in the second semiconductor structure 104. Figure 7As shown, in some embodiments, the capacitor 628 in the second semiconductor structure 104 is vertically disposed between the bonding interface 704 and the vertical transistor 626 in the second semiconductor structure 104, and the capacitor 628 in the third semiconductor structure 702 is vertically disposed between the bonding interface 704 and the vertical transistor 626 in the third semiconductor structure 702. That is, the capacitor 628 in the second semiconductor structure 104 and the capacitor 628 in the third semiconductor structure 702 can be disposed on opposite sides of the bonding interface 704. In some embodiments, the second electrode 646 of the capacitor 628 in the third semiconductor structure 702 is in contact with the second electrode 646 of the capacitor 628 in the second semiconductor structure 104 at the bonding interface 704.

[0098] In some embodiments, the 3D memory device 700 includes additional interconnects that couple DRAM cells 624 in a third semiconductor structure 702 across bonding interfaces 704 and 106 to peripheral circuitry 612. These additional interconnects, for example, couple word lines 634 in the third semiconductor structure 702 to word line contacts 734 of the peripheral circuitry 612 in the first semiconductor structure 102. Figure 7 As shown, in contrast to the first semiconductor structure 102 or the second semiconductor structure 104, the third semiconductor structure 702 may include a pad-out interconnect layer 650. In some embodiments, a vertical transistor 626 in the third semiconductor structure 702 is vertically disposed between a capacitor 628 in the third semiconductor structure 702 and the pad-out interconnect layer 650. It should be understood that, for ease of description, details (e.g., materials, manufacturing processes, functions, etc.) of the same components in both 3D memory devices 600 and 700 are not repeated.

[0099] It should be understood that Figure 7 The architecture of the multiple memory cell arrays shown is not limited to the design of DRAM cell 624, and can be applied to any suitable memory cell disclosed herein. It should also be understood that various designs of the memory cells disclosed herein can be used... Figure 7 The architecture of the multiple memory cell arrays shown is mixed. For example, the second semiconductor structure 104 and the third semiconductor structure 702 may include different designs of the memory cells disclosed herein.

[0100] It should also be understood that memory cell arrays are not limited to Figure 5 , Figures 6A-6D and Figure 7 The vertical transistor shown is an example of a GAA transistor, but it could be any other suitable multi-gate vertical transistor. For example, Figure 8A plan view is shown of an array of other memory cells 802, each including a vertical transistor, in a memory device 800 according to some aspects of this disclosure. Figure 8 As shown, the memory device 800 may include multiple word lines 804 extending in a first lateral direction (x-direction, referred to as the word line direction). The memory device 800 may also include multiple bit lines 806 extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. It should be understood that... Figure 8 The memory device 800 is not shown in a cross-section in the same transverse plane, and word lines 804 and bit lines 806 may be formed in different transverse planes to facilitate wiring, as described in detail below.

[0101] Memory cells 802 may be formed at the intersection of word lines 804 and bit lines 806. In some embodiments, each memory cell 802 includes a vertical transistor having a semiconductor body 808 and a gate structure 810 (e.g., Figure 2 (Vertical transistor 210 in the middle). Figure 8 The vertical transistor of the memory cell 802 may be an example of a three-gate vertical transistor (e.g., a three-side gate vertical transistor). The semiconductor body 808 may extend in a vertical direction (z-direction, not shown) perpendicular to the first lateral direction and the second lateral direction. The gate structure 810 may be connected to multiple sides of the semiconductor body 808 (where the active region forming the channel) (e.g., Figure 8 It is in contact with three of the four sides. That is, with Figure 5 Unlike the GAA vertical transistor in memory cell 502, in the plan view, the gate structure 810 of the vertical transistor in memory cell 802 is partially external to the semiconductor body 808. That is, according to some embodiments, in the plan view, the gate structure 810 externalizes (e.g., surrounds and contacts) three of the four sides (with a rectangular or square cross-section) of the semiconductor body 808. According to some embodiments, the gate structure 810 does not surround and contact at least one side of the semiconductor body 808. The gate structure 810 may include a gate dielectric 812 that is partially or completely external to the semiconductor body 808 in the plan view, and a gate electrode 814 that is partially external to the gate dielectric 812. Therefore, a vertical transistor with a gate structure 810 can be considered as a "tri-gate" vertical transistor, wherein the gate structure 810 contacts two opposite sides of the semiconductor body 808 in the word line direction (x direction) and contacts one side of the semiconductor body 808 in the bit line direction (y direction). As described above, the gate electrode 814 can be a portion of the word line 804, and the word line 804 can be an extension of the gate electrode 814. For example, as Figure 8As shown, one edge of each word line 804 can be formed to align with the same side of each semiconductor body 808, such that the gate electrode 814 does not need to extend to that side of the semiconductor body 808 to form a GAA transistor. By arranging the semiconductor body 808 of the memory cell 802 to align with one side of the word line 804, the spacing of the word lines 804 and / or the spacing of the memory cells 802 in the bit line direction (y direction) can be further increased to reduce manufacturing complexity and increase yield.

[0102] Similar to Figure 5 The memory device 500 in the middle, such as Figure 8 As shown, the gate electrodes 814 of adjacent vertical transistors in the word line direction (x direction) are continuous, for example, they are portions of a continuous conductive layer having gate electrodes 814 and 804. Conversely, the gate dielectrics 812 of adjacent vertical transistors in the word line direction are separate, for example, they are not portions of a continuous dielectric layer having gate dielectrics 812.

[0103] Figure 9 A side view of a cross-section of a 3D memory device 900 including vertical transistors, according to some aspects of this disclosure, is shown. The 3D memory device 900 may be an example of a memory device 800 including multi-gate vertical transistors, wherein the gate structure is partially external to the semiconductor body in the plan view. The 3D memory device 900 is similar to... Figure 6A The 3D memory device 600 in the example differs from the DRAM cell 624 in its multi-gate vertical transistor structure. It should be understood that, for ease of description, details of identical components (e.g., materials, manufacturing processes, functions, etc.) in both 3D memory devices 600 and 900 are not repeated. Similar to... Figure 6A , Figure 9 The cross-section of the 3D memory device 900 can be cut along the bit line direction (y direction).

[0104] The vertical transistor 926 may be a MOSFET for switching a corresponding DRAM cell 624. In some embodiments, the vertical transistor 926 includes a vertically (in the z-direction) extending semiconductor body 630 (i.e., an active region in which multiple channels may be formed) and a gate structure 936 contacting multiple sides of the semiconductor body 630. The semiconductor body 630 may have a cubic or cylindrical shape, and the gate structure 936 may be partially external to the semiconductor body 630 in a planar view, for example, as shown in the figure. Figure 8 As shown. Figure 9As shown, according to some embodiments, the gate structure 936 does not extend to at least one side of the semiconductor body 630. According to some embodiments, the gate structure 936 includes a gate electrode 934 and a gate dielectric 932 laterally located between the gate electrode 934 and the semiconductor body 630. Figure 9 As shown, according to some embodiments, the gate electrode 934 does not extend to at least one side of the semiconductor body 630. Due to the increased spacing of the word lines 934 in the bit line direction (y direction) and / or the spacing of the DRAM cells 624, the air gap between the word lines 934 can be partially or completely filled with dielectric.

[0105] It should also be understood that the number of gates in a multi-gate transistor can vary, i.e., it is not affected by... Figure 5 Examples of GAA vertical transistors and Figure 8 The three-gate vertical transistor example is a limitation. For example, a multi-gate vertical transistor may also include a dual-gate vertical transistor (also known as a dual-side gate vertical transistor), wherein the gate structure contacts two sides of the semiconductor body, such as two opposite sides in the bit line direction or word line direction.

[0106] It should also be understood that, despite Figures 6A-6D , Figure 7 and Figure 9 The memory cell is described as a capacitor 628, but in some examples, the memory cell may include any other suitable device, such as a PCM element, as described above. Figure 4 As described. For example, the capacitor dielectric 644 of capacitor 628 can be replaced with a phase change material layer (e.g., a chalcogenide alloy) vertically sandwiched between electrodes 642 and 646 to form a PCM element. Furthermore, instead of coupling the source or drain 638 of vertical transistor 626 or 926 to bitline 623, electrodes 642 or 646 of the PCM element can be coupled to bitline 623, while the source or drain 638 of vertical transistor 626 or 926 can be coupled to ground, such as a common ground plane.

[0107] According to some aspects of this disclosure, the vertical transistors of memory cells in a memory device (e.g., memory device 200) are single-gate transistors, and the gate dielectric of the vertical transistors is continuous in the word line direction. For example, Figure 16 A plan view is shown of an array of memory cells 1602, each including a vertical transistor, in a memory device 1600 according to some aspects of this disclosure. (See diagram below.) Figure 16As shown, the memory device 1600 may include multiple word lines 1604, each extending in a first lateral direction (x-direction, referred to as the word line direction). The memory device 1600 may also include multiple bit lines 1606, each extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. It should be understood that... Figure 16 The cross-section of the memory device 1600 in the same transverse plane is not shown, and the word line 1604 and bit line 1606 may be formed in different transverse planes to facilitate wiring, as described in detail below.

[0108] Memory cells 1602 may be formed at the intersection of word lines 1604 and bit lines 1606. In some embodiments, each memory cell 1602 includes a vertical transistor having a semiconductor body 1608 and a gate structure 1610 (e.g., Figure 2 The vertical transistor 210 is shown in the figure. The semiconductor body 1608 may extend in the substrate in a vertical direction (z-direction, not shown) perpendicular to both the first and second lateral directions. The vertical transistor may be a single-gate transistor, wherein the gate structure 1610 is adjacent to a single side of the semiconductor body 1608 (where the active region forming the channel is located). Figure 16 (One of the four sides) contacts. For example... Figure 16 As shown, the vertical transistor is a single-gate transistor, wherein the gate structure 1610 is adjacent to one side of the semiconductor body 1608 (having a rectangular or square cross-section) in the bit line direction (y-direction) in a plan view. According to some embodiments, the gate structure 1610 does not surround or contact the other three sides of the semiconductor body 1608. The gate structure 1610 may include a gate dielectric 1612 adjacent to one side of the semiconductor body 1608 in a plan view, and a gate electrode 1614 in contact with the gate dielectric 1612. In some embodiments, the gate dielectric 1612 is laterally positioned between the gate electrode 1614 and the semiconductor body 1608 in the bit line direction (y-direction). As described above, the gate electrode 1614 may be a portion of the word line 1604, and the word line 1604 may be an extension of the gate electrode 1614. That is, the gate electrodes 1614 of adjacent vertical transistors in the word line direction (x-direction) are continuous, for example, a portion of a continuous conductive layer having gate electrodes 1614 and 1604.

[0109] and Figure 5 and Figure 8 The separate gate dielectrics 512 and 812 in the model are different, such as Figure 16As shown, the gate dielectrics 1612 of adjacent vertical transistors in the word line direction are continuous, for example, a portion of a continuous dielectric layer having gate dielectrics 1612 and extending in the word line direction to abut vertical transistors in the same row on the same side. The gate structure 1610 can therefore be considered as a portion of a continuous structure extending in the word line direction, in which the continuous structure abuts vertical transistors in the same row on the same side.

[0110] like Figure 16 As shown, according to some embodiments, two adjacent vertical transistors (e.g., 1602A and 1602B) of a memory cell in the bit line direction (y-direction) are mirror-symmetrical to each other. As described below regarding the manufacturing process, the semiconductor body 1608 of each pair of two adjacent vertical transistors (e.g., 1602A and 1602B) of the memory cell in the bit line direction (y-direction) can be formed by separating the semiconductor pillars into two pieces using a trench isolation 1616 extending in the word line direction (x-direction) and parallel to the word line 1604. The trench isolation 1616 and the word line 1604 can be arranged in an interleaved manner in the bit line direction. In some embodiments, the trench isolation 1616 is formed in the middle of the semiconductor pillars (not shown) such that the resulting pair of semiconductor bodies 1608 are mirror-symmetrical to each other with respect to the trench isolation 1616, and so are the pairs of vertical transistors having the semiconductor bodies 1608 when the corresponding gate structures 1610 are also mirror-symmetrical to each other with respect to the trench isolation 1616.

[0111] It should be understood that in some examples, trench isolation 1616 extending in the word line direction may not be formed, such that two adjacent semiconductor bodies 1608 separated by corresponding trench isolation 1616 can be merged into a single semiconductor body having two opposing sides in the bit line direction that contact the gate structure 1610. That is, without trench isolation 1616, adjacent single-gate vertical transistors can be merged to form a dual-gate vertical transistor with increased gate control area and lower leakage current. The gate structure of the dual-gate vertical transistor may include... Figure 16 The two mirror-symmetric gate structures 1610 in the combined semiconductor body 1608 allow two sides in the bit-line direction to contact the gate structure in the dual-gate vertical transistor. On the other hand, by using trench isolation 1616 to divide the dual-gate vertical transistor into a single-gate vertical transistor, the number (and cell density) of memory cells 1602 in the bit-line direction can be doubled compared to the dual-gate vertical transistor without unduly complicating the manufacturing process (e.g., compared to using SADP process).

[0112] Figure 17A side view of a cross-section of another 3D memory device 1700 including a vertical transistor, according to some aspects of this disclosure, is shown. The 3D memory device 1700 may be an example of a memory device 1600 including a single-gate vertical transistor, wherein the gate structure is adjacent to a single side of the semiconductor body in the plan view. It should be understood that... Figure 17 This is for illustrative purposes only and does not necessarily need to reflect the actual device structure (e.g., interconnects). As mentioned above... Figure 1A An example of the described 3D memory device 100, 3D memory device 1700 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 106 between them. Figure 17 As shown, the first semiconductor structure 102 may include a substrate 1710, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0113] The first semiconductor structure 102 may include peripheral circuitry 1712 on a substrate 1710. In some embodiments, the peripheral circuitry 1712 includes a plurality of transistors 1714 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 1714) may also be formed on or in the substrate 1710.

[0114] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 1716 above the peripheral circuitry 1712 to transmit electrical signals to and from the peripheral circuitry 1712. The interconnect layer 1716 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and VIA contacts. The interconnect layer 1716 may also include one or more ILD layers, in which interconnects and via contacts may be formed. That is, the interconnect layer 1716 may include interconnects and via contacts in multiple ILD layers. In some embodiments, the peripheral circuitry 1712 is coupled to each other through interconnects in the interconnect layer 1716. The interconnects in the interconnect layer 1716 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0115] like Figure 17As shown, the first semiconductor structure 102 may further include a bonding layer 1718 at the bonding interface 106 and above the interconnect layer 1716 and the peripheral circuitry 1712. The bonding layer 1718 may include a plurality of bonding contacts 1719 and a dielectric material electrically isolating the bonding contacts 1719. The bonding contacts 1719 may include a conductive material, such as Cu. The remaining region of the bonding layer 1718 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 1719 in the bonding layer 1718 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as... Figure 17 As shown, the second semiconductor structure 104 may also include a bonding layer 1720 at the bonding interface 106 and above the bonding layer 1718 of the first semiconductor structure 102. The bonding layer 1720 may include a plurality of bonding contacts 1721 and a dielectric material electrically isolating the bonding contacts 1721. The bonding contacts 1721 may include a conductive material, such as Cu. The remaining region of the bonding layer 1720 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 1721 in the bonding layer 1720 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 1721 contact the bonding contacts 1719 at the bonding interface 106.

[0116] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), the bonding interface 106 is disposed between bonding layers 1720 and 1718. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is the location where bonding layers 1720 and 1718 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness, comprising the top surface of the bonding layer 1718 of the first semiconductor structure 102 and the bottom surface of the bonding layer 1720 of the second semiconductor structure 104.

[0117] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 1722, which includes bit lines 1723 above the bonding layer 1720 for transmitting electrical signals. The interconnect layer 1722 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1722 also include local interconnects, such as bit lines 1723 (e.g., Figure 16Example of bit line 1606 in the example) and word line contacts (not shown). Interconnect layer 1722 may also include one or more ILD layers in which interconnects and via contacts may be formed. Interconnects in interconnect layer 1722 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, peripheral circuitry 1712 includes word line drivers / line decoders coupled to word line contacts in interconnect layer 1722 via bonding contacts 1721 and 1719 in bonding layers 1720 and 1718 and interconnect layer 1716. In some implementations, peripheral circuitry 1712 includes a bitline driver / column decoder coupled to bitline 1723 and bitline contacts (if any) in interconnect layer 1722 via bonding contacts 1721 and 1719 in bonding layers 1720 and 1718 and interconnect layer 1716.

[0118] In some embodiments, the second semiconductor structure 104 includes DRAM devices, wherein the memory cells are in the form of an array of DRAM cells 1724 (e.g., Figure 16 An example of memory cell 1602 is provided above interconnect layer 1722 and bonding layer 1720. That is, interconnect layer 1722, including bit lines 1723, may be disposed between bonding layer 1720 and the array of DRAM cells 1724. It should be understood that Figure 17 The cross-section of the 3D memory device 1700 can be cut along the bit line direction (y direction), and a bit line 1723 in the interconnect layer 1722 extending laterally in the y direction can be coupled to a row of DRAM cells 1724.

[0119] Each DRAM cell 1724 may include a vertical transistor 1726 (e.g., Figure 2 (Example of vertical transistor 210 in the example) and capacitor 1728 coupled to vertical transistor 1726 (e.g., Figure 2 (Example of memory cell 212). DRAM cell 1724 can be a 1T1C cell consisting of a transistor and a capacitor. It should be understood that DRAM cell 1724 can be any suitable construction, such as a 2T1C cell, a 3T1C cell, etc. To better illustrate the vertical transistor 1726, Figure 18 A perspective view of an array of vertical transistors 1726 according to some aspects of this disclosure is shown. The vertical transistors 1726 will be described together with the above description. Figure 17 and Figure 18 .

[0120] The vertical transistor 1726 may be a MOSFET for switching a corresponding DRAM cell 1724. In some embodiments, the vertical transistor 1726 includes a vertically (in the z-direction) extending semiconductor body 1730 (i.e., an active region in which a channel may be formed) and a gate structure 1736 contacting one side of the semiconductor body 1730 in the bit line direction (y-direction). As described above, such as in a single-gate vertical transistor, the semiconductor body 1730 may have a cubic or cylindrical shape, and the gate structure 1736 may be adjacent to a single side of the semiconductor body 1730 in a planar view, for example, as... Figure 17 and Figure 18 As shown. According to some embodiments, the gate structure 1736 includes a gate electrode 1734 and a gate dielectric 1732 laterally positioned between the gate electrode 1734 and the semiconductor body 1730 in the bit line direction. In some embodiments, the gate dielectric 1732 is adjacent to one side of the semiconductor body 1730, and the gate electrode 1734 is adjacent to the gate dielectric 1732.

[0121] like Figure 17 and Figure 18 As shown, in some embodiments, the semiconductor body 1730 has two ends (an upper end and a lower end) in the vertical direction (z direction), and at least one end (e.g., Figure 17 and Figure 18 The lower end of the semiconductor body 1730 extends in the vertical direction (z-direction) beyond the gate dielectric 1732 into the ILD layer. In some embodiments, one end of the semiconductor body 1730 (e.g., Figure 17 and Figure 18 The upper end of the gate dielectric 1732 (e.g., the corresponding end of the gate dielectric 1732) and the corresponding end of the gate dielectric 1732 (e.g., Figure 17 and Figure 18 The upper end of the semiconductor body 1730 is flush with the gate electrode 1734. In some embodiments, the two ends (upper end and lower end) of the semiconductor body 1730 extend in the vertical direction (z direction) beyond the gate electrode 1734 into the ILD layer. That is, the semiconductor body 1730 may have a larger vertical dimension (e.g., depth) (e.g., in the z direction) than the gate electrode 1734, and neither the upper end nor the lower end of the semiconductor body 1730 is flush with the corresponding end of the gate electrode 1734. Therefore, short circuits between the bit line 1723 and the word line / gate electrode 1734 or between the word line / gate electrode 1734 and the capacitor 1728 can be avoided. The vertical transistor 1726 may also include a source and a drain (both referred to as 1738 since their positions can be interchanged) respectively disposed in the vertical direction (z direction) at the two ends (upper end and lower end) of the semiconductor body 1730. In some embodiments, one of the source and drain 1738 (e.g., in the z direction) is flush with the gate electrode 1734. Figure 17 and Figure 18 At the upper end of the middle) it is coupled to capacitor 1728, and another of the source and drain 1738 (e.g., in the upper end of the middle) ... Figure 17 and Figure 18 (At the lower end of the middle) Coupled to line 1723.

[0122] In some embodiments, the semiconductor body 1730 comprises a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 1730 may comprise monocrystalline silicon. The source and drain 1738 may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain 1738 and the bit line 1723 or the first electrode 1742 to reduce contact resistance. In some embodiments, the gate dielectric 1732 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 1734 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the gate electrode 1734 includes multiple conductive layers, such as a W layer above a TiN layer, as shown below. Figure 17 and Figure 18 As shown in the diagram. In one example, the gate structure 1736 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 1732 comprises silicon oxide and the gate electrode 1734 comprises doped polysilicon. In another example, the gate structure 1736 may be an HKMG, wherein the gate dielectric 1732 comprises a high-k dielectric and the gate electrode 1734 comprises metal.

[0123] As described above, since the gate electrode 1734 can be a portion of the word line or as part of the word line in the word line direction (e.g., Figure 18 Extending in the x-direction (as in the example), Figure 18 As shown, the second semiconductor structure 104 of the 3D memory device 1700 may also include multiple word lines, each extending in the word line direction (x direction) (e.g., Figure 16An example of word line 1604 (also referred to as 1734). Each word line 1734 can be coupled to a row of DRAM cells 1724. That is, bit line 1723 and word line 1734 can extend in two perpendicular lateral directions, and the semiconductor body 1730 of the vertical transistor 1726 can extend in a vertical direction perpendicular to the two lateral directions along which the bit line 1723 and word line 1734 extend. According to some embodiments, word line 1734 is in contact with word line contacts (not shown). In some embodiments, word line 1734 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, word line 1734 includes multiple conductive layers, such as a W layer above a TiN layer, as... Figure 17 As shown in the image.

[0124] like Figure 17 and Figure 18 As shown, according to some embodiments, the vertical transistor 1726 extends vertically through and contacts the word line 1734, and the source or drain 1738 of the vertical transistor 1726 at its lower end contacts the bit line 1723 (or contacts the bit line contact, if any). Therefore, due to the vertical arrangement of the vertical transistor 1726, the word line 1734 and the bit line 1723 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 1734 and the bit line 1723. In some embodiments, the bit line 1723 is vertically disposed between the bonding layer 1720 and the word line 1734, and the word line 1734 is vertically disposed between the bit line 1723 and the capacitor 1728. Word line 1734 can be coupled to peripheral circuitry 1712 in the first semiconductor structure 102 via word line contacts (not shown) in interconnect layer 1722, bonding contacts 1721 and 1719 in bonding layers 1720 and 1718, and interconnections in interconnect layer 1716. Similarly, bit line 1723 in interconnect layer 1722 can be coupled to peripheral circuitry 1712 in the first semiconductor structure 102 via bonding contacts 1721 and 1719 in bonding layers 1720 and 1718, and interconnections in interconnect layer 1716.

[0125] As mentioned above Figure 16 The vertical transistors 1726 can be arranged in a mirror-symmetric manner to increase the density of DRAM cells 1724 in the bit line direction (y-direction). For example... Figure 17 As shown, according to some embodiments, two adjacent vertical transistors 1726 in the bit line direction are isolated relative to the trench 1760 (e.g., corresponding to...). Figure 16The trench isolations 1616 in the second semiconductor structure 104 are mirror-symmetric to each other. That is, the second semiconductor structure 104 may include a plurality of trench isolations 1760, each trench isolation 1760 extending parallel to word line 1734 in the word line direction (x-direction) and disposed between semiconductor bodies 1730 of adjacent rows of vertical transistors 1726. In some embodiments, the rows of vertical transistors 1726 separated by the trench isolations 1760 are mirror-symmetric to each other with respect to the trench isolations 1760. The trench isolations 1760 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. It should be understood that the trench isolations 1760 may include air gaps, each laterally disposed between adjacent semiconductor bodies 1730. As described below regarding the manufacturing process, air gaps can be formed because the spacing of the vertical transistors 1726 in the bit line direction (e.g., the y-direction) is relatively small. On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times that of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the isolation effect between the vertical transistors 1726 (and the rows of DRAM cells 1724). Similarly, in some embodiments, air gaps are also formed laterally between the word lines / gate electrodes 1734 in the bit line direction, depending on the spacing of the word line / gate electrodes 1734 in the bit line direction.

[0126] like Figure 17 As shown, in some embodiments, capacitor 1728 includes a first electrode 1742 above and in contact with the source or drain 1738 of vertical transistor 1726 (e.g., the upper end of semiconductor body 1730). Capacitor 1728 may also include a capacitor dielectric 1744 above and in contact with the first electrode 1742, and a second electrode 1746 above and in contact with the capacitor dielectric 1744. That is, capacitor 1728 may be a vertical capacitor, wherein electrodes 1742 and 1746 and capacitor dielectric 1744 are stacked vertically (in the z-direction), and capacitor dielectric 1744 may be sandwiched between electrodes 1742 and 1746. In some embodiments, each first electrode 1742 is coupled to the source or drain 1738 of a corresponding vertical transistor 1726 in the same DRAM cell, while all second electrodes 1746 are portions of a common plate (e.g., common ground) coupled to ground. Figure 17As shown, the second semiconductor structure 104 may further include capacitor contacts 1747 that contact a common plate of the second electrode 1746 for coupling the second electrode 1746 of the capacitor 1728 to a peripheral circuit 1712 or directly to ground. In some embodiments, the ILD layer forming the capacitor 1728 has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 1730 extends.

[0127] It should be understood that the structure and construction of capacitor 1728 are not limited to... Figure 17 Examples are provided, and any suitable structure and construction may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-planar capacitors. In some embodiments, capacitor dielectric 1744 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 1728 may be a ferroelectric capacitor used in FRAM cells, and capacitor dielectric 1744 may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, electrodes 1742 and 1746 comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0128] like Figure 17 As shown, according to some embodiments, the vertical transistor 1726 extends vertically through and contacts the word line 1734. The source or drain 1738 of the vertical transistor 1726 at its lower end contacts the bit line 1723, and the source or drain 1738 of the vertical transistor 1726 at its upper end contacts the electrode 1742 of the capacitor 1728. That is, due to the vertical arrangement of the vertical transistor 1726, the bit line 1723 and the capacitor 1728 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 1726 of the DRAM cell 1724. In some embodiments, the bit line 1723 and the capacitor 1728 are arranged on opposite sides of the vertical transistor 1726 in the vertical direction. Compared to conventional DRAM cells where the bit line and capacitor are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 1723 and reduces the coupling capacitance between the bit line 1723 and the capacitor 1728.

[0129] like Figure 17As shown, in some embodiments, the vertical transistor 1726 is vertically disposed between the capacitor 1728 and the bonding interface 106. That is, the vertical transistor 1726 can be arranged closer to the peripheral circuitry 1712 and the bonding interface 106 of the first semiconductor structure 102 than the capacitor 1728. Since the bit line 1723 and the capacitor 1728 are coupled to opposite ends of the vertical transistor 1726, as described above, according to some embodiments, the bit line 1723 (as part of the interconnect layer 1722) is vertically disposed between the vertical transistor 1726 and the bonding interface 106. As a result, the interconnect layer 1722, including the bit line 1723, can be arranged close to the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0130] In some embodiments, the second semiconductor structure 104 further includes a substrate 1748 disposed above the DRAM cell 1724. As described below with respect to the manufacturing process, the substrate 1748 may be a portion of a carrier wafer. It should be understood that in some examples, the substrate 1748 may not be included in the second semiconductor structure 104.

[0131] like Figure 17As shown, the second semiconductor structure 104 may further include a pad-out interconnect layer 1750 above the substrate 1748 and the DRAM cell 1724. The pad-out interconnect layer 1750 may include interconnects in one or more ILD layers, such as contact pads 1754. The pad-out interconnect layer 1750 and the interconnect layer 1722 may be formed on opposite sides of the DRAM cell 1724. According to some embodiments, a capacitor 1728 is vertically disposed between the vertical transistor 1726 and the pad-out interconnect layer 1750. In some embodiments, for example for pad-out purposes, the interconnects in the pad-out interconnect layer 1750 may transmit electrical signals between the 3D memory device 1700 and external circuitry. In some embodiments, the second semiconductor structure 104 may also include one or more contacts 1752 extending through a portion of the pad-out interconnect layer 1750 and the substrate 1748 to couple the pad-out interconnect layer 1750 to the DRAM cell 1724 and the interconnect layer 1722. As a result, peripheral circuitry 1712 can be coupled to DRAM cell 1724 via interconnect layers 1716 and 1722 and bonding layers 1720 and 1718, and peripheral circuitry 1712 and DRAM cell 1724 can be coupled to external circuitry via contact 1752 and pads leading out from interconnect layer 1750. Contact pads 1754 and contact 1752 can include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, contact pad 1754 can include Al, and contact 1752 can include W. In some embodiments, contact 1752 includes a via surrounded by a dielectric spacer (e.g., having silicon oxide) to electrically isolate the via from substrate 1748. Depending on the thickness of substrate 1748, contact 1752 can be an ILV with a submicron depth (e.g., between 10 nm and 1 μm) or a TSV with a micron or tens of micron depth (e.g., between 1 μm and 100 μm).

[0132] Although not shown, it should be understood that the pad leads of 3D memory devices are not limited to those from... Figure 17 The second semiconductor structure 104 shown has DRAM cells 1724 and can be used in conjunction with the above-mentioned... Figure 6B A similar approach is derived from a first semiconductor structure 102 having peripheral circuitry 1712. Although not shown, it should be understood that the air gaps between word lines 1734 and / or between semiconductor bodies 1730 can be configured similarly to those described above. Figure 6E The dielectric is partially or completely filled in a similar manner. Although not shown, it should be understood that an array of more than one DRAM cell 1724 can be configured in accordance with the above description. Figure 7 The similar arrangements are stacked on top of each other to vertically and proportionally increase the number of DRAM cells 1724.

[0133] As mentioned above, in some examples, it may not be formed in Figure 16 The trench isolation 1616 extending in the word line direction allows two adjacent semiconductor bodies 1608 separated by the respective trench isolation 1616 to be merged into a single semiconductor body having two opposing sides in contact with the gate structure 1610 in the bit line direction. That is, without the trench isolation 1616, adjacent single-gate vertical transistors can be merged to form a dual-gate vertical transistor (e.g., a dual-side gate vertical transistor) with increased gate control area and lower leakage current. For example, Figure 20 A plan view is shown of an array of individual memory cells 2002, each including a vertical transistor, in a memory device 2000 according to some aspects of this disclosure. (See diagram below.) Figure 20 As shown, the memory device 2000 may include multiple word lines 2004 extending in a first lateral direction (x-direction, referred to as the word line direction). The memory device 2000 may also include multiple bit lines 2006 extending in a second lateral direction (y-direction, referred to as the bit line direction) perpendicular to the first lateral direction. It should be understood that... Figure 20 The memory device 2000 is not shown in a cross-section in the same horizontal plane, and the word line 2004 and bit line 2006 may be formed in different horizontal planes to facilitate wiring, as described in detail below.

[0134] Memory cell 2002 may be formed at the intersection of word line 2004 and bit line 2006. In some embodiments, each memory cell 2002 includes a vertical transistor having a semiconductor body 2008 and a gate structure 2010 (e.g., Figure 2 The vertical transistor 210 is shown in the figure. The semiconductor body 2008 may extend in the substrate in a vertical direction (z-direction, not shown) perpendicular to both the first and second lateral directions. The vertical transistor may be a dual-gate transistor, wherein the gate structure 2010 is adjacent to two sides of the semiconductor body 2008 (where the active region forming the channel is located), e.g., Figure 20 Two of the four sides of the object are in contact. For example... Figure 20As shown, the vertical transistor is a dual-gate transistor, wherein the gate structure 2010 is adjacent to two opposite sides of the semiconductor body 1608 (having a rectangular or square cross-section) in the bit line direction (y-direction) of the plan view. According to some embodiments, the gate structure 2010 does not surround or contact the other two sides of the semiconductor body 2008 in the word line direction (x-direction). That is, the gate structure 2010 may be partially external to the semiconductor body 2008 in the plan view. The gate structure 2010 may include a gate dielectric 2012 adjacent to two opposite sides of the semiconductor body 2008 in the plan view, and a gate electrode 2014 in contact with the gate dielectric 2012. In some embodiments, the gate dielectric 2012 is laterally positioned between the gate electrode 2014 and the semiconductor body 2008 in the bit line direction (y-direction). As described above, the gate electrode 2014 may be a portion of the word line 2004, and the word line 2004 may be an extension of the gate electrode 2014. That is, the gate electrodes 1614 of adjacent vertical transistors in the word line direction (x direction) are continuous, for example, a portion of a continuous conductive layer having gate electrodes 1614 and 1604.

[0135] and Figure 5 and Figure 8 The separate gate dielectrics 512 and 812 in the model are different, such as Figure 20 As shown, the gate dielectrics 2012 of adjacent vertical transistors in the word line direction are continuous, for example, a portion of a continuous dielectric layer having gate dielectrics 2012 and extending in the word line direction. The gate structure 2010 can therefore be considered as a portion of a continuous structure extending in the word line direction, in which the continuous structure intersects with the vertical transistors in the same row.

[0136] Figure 21 A side view of a cross-section of another 3D memory device 2100 including vertical transistors, according to some aspects of this disclosure, is shown. The 3D memory device 2100 may be an example of a memory device 2000 including dual-gate vertical transistors, wherein the gate structure is adjacent to two sides of the semiconductor body in the plan view. It should be understood that... Figure 21 This is for illustrative purposes only and does not necessarily need to reflect the actual device structure (e.g., interconnects). As mentioned above... Figure 1A An example of the described 3D memory device 100 is a bonded chip comprising a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 106 between them. Figure 21As shown, the first semiconductor structure 102 may include a substrate 2110, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0137] The first semiconductor structure 102 may include peripheral circuitry 2112 on substrate 2110. In some embodiments, peripheral circuitry 2112 includes a plurality of transistors 2114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 2114) may also be formed on or in substrate 2110.

[0138] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 2116 above the peripheral circuitry 2112 for transmitting electrical signals to and from the peripheral circuitry 2112. The interconnect layer 2116 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and VIA contacts. The interconnect layer 1716 may also include one or more ILD layers, in which interconnects and via contacts may be formed. That is, the interconnect layer 2116 may include interconnects and via contacts in multiple ILD layers. In some embodiments, the peripheral circuitry 2112 is coupled to each other via interconnects in the interconnect layer 2116. The interconnects in the interconnect layer 2116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0139] like Figure 21 As shown, the first semiconductor structure 102 may further include a bonding layer 2118 at the bonding interface 106 and above the interconnect layer 2116 and the peripheral circuitry 2112. The bonding layer 2118 may include a plurality of bonding contacts 2119 and a dielectric material electrically isolating the bonding contacts 2119. The bonding contacts 2119 may include a conductive material, such as Cu. The remaining region of the bonding layer 2118 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 2119 in the bonding layer 2118 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as... Figure 21As shown, the second semiconductor structure 104 may further include a bonding layer 2120 at the bonding interface 106 and above the bonding layer 2118 of the first semiconductor structure 102. The bonding layer 2120 may include a plurality of bonding contacts 2121 and a dielectric material electrically isolating the bonding contacts 2121. The bonding contacts 2121 may include a conductive material, such as Cu. The remaining region of the bonding layer 2120 may be formed of a dielectric material (e.g., silicon oxide). The bonding contacts 2121 in the bonding layer 2120 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 2121 contact the bonding contacts 2119 at the bonding interface 106.

[0140] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), the bonding interface 106 is disposed between bonding layers 2120 and 2118. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is the location where bonding layers 2120 and 2118 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness, comprising the top surface of the bonding layer 2118 of the first semiconductor structure 102 and the bottom surface of the bonding layer 2120 of the second semiconductor structure 104.

[0141] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 2122, which includes bit lines 2123 above the bonding layer 2120 for transmitting electrical signals. The interconnect layer 2122 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 2122 also include local interconnects, such as bit lines 2123 (e.g., Figure 20Example of bit line 2006 in the example) and word line contacts (not shown). Interconnect layer 2122 may also include one or more ILD layers, in which interconnects and via contacts may be formed. Interconnects in interconnect layer 2122 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, peripheral circuitry 2112 includes word line drivers / line decoders coupled to word line contacts in interconnect layer 2122 via bonding contacts 2121 and 2119 in bonding layers 2120 and 2118 and interconnect layer 2116. In some implementations, peripheral circuitry 2112 includes a bitline driver / column decoder coupled to bitline 2123 and bitline contacts (if any) in interconnect layer 2122 via bonding contacts 2121 and 2119 in bonding layers 2120 and 2118 and interconnect layer 2116.

[0142] In some embodiments, the second semiconductor structure 104 includes a DRAM device, wherein the memory cells are DRAM cells 2124 (e.g., Figure 20 An array of memory cells 2002 (as in the example) is provided above the interconnect layer 2122 and the bonding layer 2120. That is, the interconnect layer 2122, including bit lines 2123, can be disposed between the bonding layer 2120 and the array of DRAM cells 2124. It should be understood that... Figure 21 The cross-section of the 3D memory device 2100 can be cut along the bit line direction (y direction), and a bit line 2123 in the interconnect layer 2122 extending laterally in the y direction can be coupled to a row of DRAM cells 2124.

[0143] Each DRAM cell 2124 may include a vertical transistor 2126 (e.g., Figure 2 (Example of vertical transistor 210) and capacitor 2128 coupled to vertical transistor 2126 (e.g., Figure 2 (Example of memory cell 212). DRAM cell 2124 can be a 1T1C cell consisting of a transistor and a capacitor. It should be understood that DRAM cell 2124 can be any suitable construction, such as a 2T1C cell, a 3T1C cell, etc.

[0144] The vertical transistor 2126 may be a MOSFET for switching a corresponding DRAM cell 2124. In some embodiments, the vertical transistor 2126 includes a vertically (in the z-direction) extending semiconductor body 2130 (i.e., an active region in which a channel may be formed) and a gate structure 2136 contacting two opposing sides of the semiconductor body 2130 in the bit line direction (y-direction). As described above, such as in a dual-gate vertical transistor, the semiconductor body 2130 may have a cubic or cylindrical shape, and the gate structure 2136 may be adjacent to two sides of the semiconductor body 2130 in a plan view, for example, as... Figure 21 As shown. According to some embodiments, the gate structure 2136 includes a gate electrode 2134 and a gate dielectric 2132 laterally located between the gate electrode 2134 and the semiconductor body 2130 in the bit line direction. In some embodiments, the gate dielectric 2132 is adjacent to two sides of the semiconductor body 2130, and the gate electrode 2134 is adjacent to the gate dielectric 2132.

[0145] like Figure 21 As shown, in some embodiments, the semiconductor body 2130 has two ends (an upper end and a lower end) in the vertical direction (z direction), and at least one end (e.g., Figure 21 The lower end of the semiconductor body 2130 extends in the vertical direction (z-direction) beyond the gate dielectric 2132 into the ILD layer. In some embodiments, one end of the semiconductor body 2130 (e.g., Figure 21 The upper end of the gate dielectric 2132 and the corresponding end of the gate dielectric 2132 (e.g., Figure 21 The upper and lower ends of the semiconductor body 2130 are flush with each other. In some embodiments, the two ends (upper and lower) of the semiconductor body 2130 extend beyond the gate electrode 2134 into the ILD layer in the vertical direction (z direction). That is, the semiconductor body 2130 may have a larger vertical dimension (e.g., depth) (e.g., in the z direction) than the vertical dimension of the gate electrode 2134, and neither the upper nor lower end of the semiconductor body 2130 is flush with the corresponding end of the gate electrode 2134. Therefore, short circuits between the bit line 2123 and the word line / gate electrode 2134 or between the word line / gate electrode 2134 and the capacitor 2128 can be avoided. The vertical transistor 2126 may also include a source and a drain (both referred to as 2138 since their positions can be interchanged) respectively disposed in the vertical direction (z direction) at the two ends (upper and lower) of the semiconductor body 2130. In some embodiments, one of the source and drain 2138 (e.g., in the z direction) is flush with the upper end of the gate electrode 2134. Figure 21 At the upper end of the middle) it is coupled to capacitor 2128, and another of the source and drain 2138 (e.g., in the upper end of the middle) ... Figure 21 At the lower end of the line, the coupling line is 2123.

[0146] In some embodiments, the semiconductor body 2130 comprises a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 2130 may comprise monocrystalline silicon. The source and drain electrodes 2138 may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain electrodes 2138 and the bit line 2123 or the first electrode 2142 to reduce contact resistance. In some embodiments, the gate dielectric 2132 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 2134 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some implementations, the gate electrode 2134 includes multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 2136 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 2132 comprises silicon oxide and the gate electrode 2134 comprises doped polysilicon. In another example, the gate structure 2136 may be an HKMG, wherein the gate dielectric 2132 comprises a high-k dielectric and the gate electrode 2134 comprises metal.

[0147] As described above, since the gate electrode 2134 can be a portion of a word line or extend as a word line in the word line direction, the second semiconductor structure 104 of the 3D memory device 2100 can also include multiple word lines, each extending in the word line direction (e.g., Figure 20 An example of word line 2004 (also referred to as 2134) is shown. Each word line 2134 can be coupled to a row of DRAM cells 2124. That is, bit lines 2123 and word lines 2134 can extend in two perpendicular lateral directions, and the semiconductor body 2130 of the vertical transistor 2126 can extend in a vertical direction perpendicular to the two lateral directions along which the bit lines 2123 and word lines 2134 extend. According to some embodiments, word lines 2134 are in contact with word line contacts (not shown). In some embodiments, word lines 2134 comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, word lines 2134 comprise multiple conductive layers, such as a W layer over a TiN layer.

[0148] like Figure 21As shown, according to some embodiments, the vertical transistor 2126 extends vertically through and contacts the word line 2134, and the source or drain 2138 of the vertical transistor 2126 at its lower end contacts the bit line 2123 (or bit line contact, if any). Therefore, due to the vertical arrangement of the vertical transistor 2126, the word line 2134 and the bit line 2123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 2134 and the bit line 2123. In some embodiments, the bit line 2123 is vertically disposed between the bonding layer 2120 and the word line 2134, and the word line 2134 is vertically disposed between the bit line 2123 and the capacitor 2128. Word line 2134 can be coupled to peripheral circuitry 2112 in the first semiconductor structure 102 via word line contacts in interconnect layer 2122, bonding contacts 2121 and 2119 in bonding layers 2120 and 2118, and interconnections in interconnect layer 2116. Similarly, bit line 2123 in interconnect layer 2122 can be coupled to peripheral circuitry 2112 in the first semiconductor structure 102 via bonding contacts 2121 and 2119 in bonding layers 2120 and 2118, and interconnections in interconnect layer 2116.

[0149] In some embodiments, the second semiconductor structure 104 further includes a plurality of air gaps 2140, each laterally disposed between adjacent word lines 2134. Each air gap 2140 may be a trench extending parallel to the word line 2134 in the word line direction (e.g., the x-direction) to separate vertical transistors 2126 in adjacent rows. As described below regarding the manufacturing process, air gaps 2140 can be formed because the spacing of word lines 2134 (and rows of DRAM cells 2124) in the bit line direction (e.g., the y-direction) is relatively small. On the other hand, the relatively large dielectric constant of air in the air gaps 2140 (e.g., about 4 times the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between word lines 2134 (and rows of DRAM cells 2124).

[0150] like Figure 21As shown, in some embodiments, capacitor 2128 includes a first electrode 2142 above and in contact with the source or drain 2138 of vertical transistor 2126 (e.g., the upper end of semiconductor body 2130). Capacitor 2128 may also include a capacitor dielectric 2144 above and in contact with the first electrode 2142, and a second electrode 2146 above and in contact with the capacitor dielectric 2144. That is, capacitor 2128 may be a vertical capacitor, wherein electrodes 2142 and 2146 and capacitor dielectric 2144 are stacked vertically (in the z-direction), and capacitor dielectric 2144 may be sandwiched between electrodes 2142 and 2146. In some embodiments, each first electrode 2142 is coupled to the source or drain 2138 of a corresponding vertical transistor 2126 in the same DRAM cell, while all second electrodes 2146 are portions of a common plate (e.g., common ground) coupled to ground. Figure 21 As shown, the second semiconductor structure 104 may further include capacitor contacts 2147 that are in contact with a common plate of the second electrode 2146 for coupling the second electrode 2146 of the capacitor 2128 to a peripheral circuit 2112 or directly to ground. In some embodiments, the ILD layer forming the capacitor 2128 has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 2130 extends.

[0151] It should be understood that the structure and construction of capacitor 2128 are not limited to... Figure 21 Examples are provided, and any suitable structure and construction may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-planar capacitors. In some embodiments, capacitor dielectric 2144 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 2128 may be a ferroelectric capacitor used in FRAM cells, and capacitor dielectric 2144 may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, electrodes 2142 and 2146 comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0152] like Figure 21As shown, according to some embodiments, the vertical transistor 2126 extends vertically through and contacts the word line 2134. The source or drain 2138 of the vertical transistor 2126 at its lower end contacts the bit line 2123 directly or via a bit line contact, and the source or drain 2138 of the vertical transistor 2126 at its upper end contacts the electrode 2142 of the capacitor 2128. That is, due to the vertical arrangement of the vertical transistor 2126, the bit line 2123 and the capacitor 2128 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 2126 of the DRAM cell 2124. In some embodiments, the bit line 2123 and the capacitor 2128 are arranged on opposite sides of the vertical transistor 2126 in the vertical direction. Compared to conventional DRAM cells where the bit line and capacitor are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 2123 and reduces the coupling capacitance between the bit line 2123 and the capacitor 2128.

[0153] like Figure 21 As shown, in some embodiments, the vertical transistor 2126 is vertically disposed between the capacitor 2128 and the bonding interface 106. That is, the vertical transistor 2126 can be arranged closer to the bonding interface 106 and the peripheral circuit 2112 of the first semiconductor structure 102 than the capacitor 2128. As described above, according to some embodiments, since the bit line 2123 and the capacitor 2128 are coupled to opposite ends of the vertical transistor 2126, the bit line 2123 (as part of the interconnect layer 2122) is vertically disposed between the vertical transistor 2126 and the bonding interface 106. As a result, the interconnect layer 2122 including the bit line 2123 can be arranged close to the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0154] In some embodiments, the second semiconductor structure 104 further includes a substrate 2148 disposed above the DRAM cell 2124. As described below regarding the manufacturing process, the substrate 2148 may be a portion of a carrier wafer. It should be understood that in some examples, the substrate 2148 may not be included in the second semiconductor structure 104.

[0155] like Figure 21As shown, the second semiconductor structure 104 may further include a pad-out interconnect layer 2150 above the substrate 2148 and the DRAM cell 2124. The pad-out interconnect layer 2150 may include interconnects in one or more ILD layers, such as contact pads 2154. The pad-out interconnect layer 2150 and the interconnect layer 2122 may be formed on opposite sides of the DRAM cell 2124. According to some embodiments, a capacitor 2128 is vertically disposed between the vertical transistor 2126 and the pad-out interconnect layer 2150. In some embodiments, for example for pad-out purposes, the interconnects in the pad-out interconnect layer 2150 may transmit electrical signals between the 3D memory device 2100 and external circuitry. In some embodiments, the second semiconductor structure 104 may also include one or more contacts 2152 extending through the substrate 2148 and portions of the pad-out interconnect layer 2150 to couple the pad-out interconnect layer 2150 to the DRAM cell 2124 and the interconnect layer 2122. As a result, peripheral circuitry 2112 can be coupled to DRAM cell 2124 via interconnect layers 2116 and 2122 and bonding layers 2120 and 2118, and peripheral circuitry 2112 and DRAM cell 2124 can be coupled to external circuitry via contact 2152 and pads leading out of interconnect layer 2150. Contact pads 2154 and contact 2152 can comprise conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, contact pad 2154 can comprise Al, and contact 2152 can comprise W. In some embodiments, contact 2152 includes vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from substrate 2148. Depending on the thickness of substrate 2148, contact 2152 can be an ILV with a submicron depth (e.g., between 10 nm and 1 μm) or a TSV with a micron or tens of micron depth (e.g., between 1 μm and 100 μm).

[0156] Although not shown, it should be understood that the pad leads of 3D memory devices are not limited to those shown. Figure 21 The diagram shows a second semiconductor structure 104 having DRAM cells 2124, and can be used in conjunction with the above regarding... Figure 6B A similar approach is derived from a first semiconductor structure 102 having peripheral circuitry 2112. Although not shown, it should be understood that the air gap between word lines 2134 can be configured similarly to the above-mentioned... Figure 6E The dielectric is partially or completely filled in a similar manner. Although not shown, it should be understood that an array of more than one DRAM cell 2124 can be configured in accordance with the above description. Figure 7 The similar arrangements are stacked on top of each other to vertically and proportionally increase the number of DRAM cells 2124.

[0157] Figure 27 A block diagram of a system 2700 having a memory device according to some aspects of this disclosure is shown. System 2700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 27 As shown, system 2700 may include host 2708 and memory system 2702 having one or more memory devices 2704 and memory controller 2706. Host 2708 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 2708 may be configured to send data to or receive data from memory device 2704.

[0158] Memory device 2704 can be any memory device disclosed herein, such as 3D memory devices 100 and 101, memory devices 200, 500, 800, 1600 and 2000, and 3D memory devices 600, 601, 603, 605, 607, 700, 900, 1700 and 2100. In some embodiments, memory device 2704 includes an array of memory cells, each memory cell including a vertical transistor, as described in detail above.

[0159] According to some embodiments, memory controller 2706 is coupled to memory device 2704 and host 2708 and is configured to control memory device 2704. Memory controller 2706 can manage data stored in memory device 2704 and communicate with host 2708. Memory controller 2706 can be configured to control the operation of memory device 2704, such as read, write, and refresh operations. Memory controller 2706 can also be configured to manage various functions regarding data stored or to be stored in memory device 2704, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, memory controller 2706 is also configured to determine the maximum memory capacity that the computer system can use, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Any other suitable functions can also be performed by memory controller 2706. Memory controller 2706 can communicate with external devices (e.g., host 2708) according to a specific communication protocol. For example, the memory controller 2706 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0160] Figures 10A-10M The present disclosure illustrates a manufacturing process for forming a 3D memory device including vertical transistors, based on some aspects of this disclosure. Figures 11A-11I The present disclosure illustrates a manufacturing process for forming another 3D memory device, including vertical transistors, according to some aspects of this disclosure. Figures 12A-12H The present disclosure illustrates a manufacturing process for forming another 3D memory device, including vertical transistors, according to some aspects of this disclosure. Figures 13A-13H The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure. Figures 14A-14EThe present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure. Figures 15A-15D The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure. Figures 19A-19M The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure. Figures 22A-22M The present disclosure illustrates a manufacturing process for forming another 3D memory device including vertical transistors, based on some aspects of this disclosure. Figure 23 A flowchart of a method 2300 for forming a 3D memory device including vertical transistors, according to some aspects of this disclosure, is shown. Figures 10A-10M Examples of 3D memory devices depicted include Figure 6A and Figure 6B The 3D memory devices 600 and 601 are depicted in the figure. Figures 11A-11I Examples of 3D memory devices depicted include Figure 9 The 3D memory device 900 is depicted in the image. Figures 12A-12H Examples of 3D memory devices depicted include Figure 6C The 3D memory device 603 is depicted in the figure. Figures 13A-13H Examples of 3D memory devices depicted include Figure 6D The 3D memory device 605 is depicted in the figure. Figures 14A-14E and 15A- Figure 15D Examples of 3D memory devices depicted include Figure 7 The 3D memory device 700 is depicted in the figure. Figures 19A-19M Examples of 3D memory devices depicted include Figure 17 The 3D memory device 1700 is depicted in the figure. Figure 22A-22M Examples of 3D memory devices depicted include Figure 21 The 3D memory device 2100 depicted in the image will be described together. Figures 10A-10M , Figures 11A-11I , Figures 12A-12H , Figures 13A-13H , Figures 14A-14E , Figures 15A-15D , Figures 19A-19M , Figures 22A-22M and Figure 23 It should be understood that the operations shown in method 2300 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 23 The different execution orders shown.

[0161] In some implementations, a first semiconductor structure including peripheral circuitry is formed. For example... Figure 10Lor Figure 19L The depicted structure forms a first semiconductor structure including peripheral circuitry. In some embodiments, a second semiconductor structure is formed including a first memory cell array and multiple bit lines coupled to the memory cells. Each memory cell may include a vertical transistor and a memory cell coupled to the vertical transistor. A corresponding bit line and a corresponding memory cell are perpendicularly coupled to opposite ends of each memory cell in the memory cell. Figure 10L , Figure 11I , Figure 12H , Figure 13H , Figure 19L or Figure 22L The depicted structure forms a second semiconductor structure comprising an array of DRAM cells, each DRAM cell including a vertical transistor and a capacitor coupled to the vertical transistor. The second semiconductor structure also includes multiple bit lines coupled to the memory cells, with a corresponding bit line and a corresponding memory cell perpendicularly coupled to opposite ends of each memory cell. In some embodiments, the first and second semiconductor structures are bonded face-to-face, such that the first memory cell array is coupled to peripheral circuitry via the bonding interface. Figure 10L and Figure 10M , Figure 19L or Figure 22L The first and second semiconductor structures are bonded face-to-face, allowing the DRAM cell array to be coupled to the peripheral circuitry via the bonding interface.

[0162] refer to Figure 23 Method 2300 begins at operation 2302, wherein a peripheral circuit is formed on a first substrate. The first substrate may include a silicon substrate. In some embodiments, an interconnect layer is formed over the peripheral circuit. The interconnect layer may include multiple interconnects in one or more ILD layers.

[0163] like Figure 10L As shown, a plurality of transistors 1042 are formed on a silicon substrate 1038. The transistors 1042 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1038 by ion implantation and / or thermal diffusion, and these doped regions serve, for example, as the source and drain of the transistors 1042. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1038 by wet / dry etching and thin film deposition. Peripheral circuitry 1040 can be formed on the silicon substrate 1038 for the transistors 1042.

[0164] like Figure 10L As shown, an interconnect layer 1044 can be formed over a peripheral circuit 1040 having a transistor 1042. The interconnect layer 1044 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the peripheral circuit 1040. In some embodiments, the interconnect layer 1044 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1044 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 10L The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1044.

[0165] Method 2300 proceeds to operation 2304, such as... Figure 23 As shown, a first bonding layer is formed above the peripheral circuitry (and interconnect layer). The first bonding layer may include first bonding contacts. Figure 10L As shown, a bonding layer 1046 is formed over interconnect layer 1044 and peripheral circuitry 1040. Bonding layer 1046 may include a plurality of bonding contacts 1047 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of interconnect layer 1044 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, bonding contacts 1047 that penetrate the dielectric layer and contact the interconnects in interconnect layer 1044 can be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0166] Method 2300 proceeds to operation 2306, such as... Figure 23As shown, an array of memory cells is formed on a second substrate, each memory cell including a vertical transistor and a memory cell. The second substrate may include a carrier substrate. The memory cell may include a capacitor or a PCM element. In some embodiments, the capacitor is formed as a vertical transistor coupled to the corresponding memory cell.

[0167] For example, Figure 24 A flowchart is shown of a method 2400 for forming memory cell arrays, each comprising vertical transistors, according to some aspects of this disclosure. Figure 24 At operation 2402, a stack of dielectric layers is formed on the substrate. In some embodiments, to form the stack of dielectric layers, three layers having a first dielectric, a second dielectric, and a third dielectric are subsequently deposited on the substrate. The first dielectric may include silicon oxide, and the second dielectric may include silicon nitride. The layer having the second dielectric may serve as a sacrificial layer vertically sandwiched between the two layers having the first dielectric. The sacrificial layer can be removed by selective etching relative to the two layers having the first dielectric, and the sacrificial layer can be replaced with a conductive layer in subsequent processes.

[0168] like Figure 10A As shown, a stack of silicon oxide layer 1004, silicon nitride layer 1006, and silicon oxide layer 1008 is formed on silicon substrate 1002. To form the dielectric stack, silicon oxide, silicon nitride, and silicon oxide are subsequently deposited onto silicon substrate 1002 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, silicon oxide layer 1004 is formed by oxidizing the top portion of silicon substrate 1002 using dry oxidation and / or wet oxidation (e.g., in-situ steam generation (ISSG) oxidation process). In some embodiments, the thickness of silicon oxide layer 1004 (e.g., ISSG silicon oxide) is less than the thickness of silicon oxide layer 1008 (e.g., CVD silicon oxide). Figure 10A A side view of a cross-section along the y-direction (bitline direction, e.g., in the CC plane) is shown. Figure 10A Planar views of the cross-section in the top portion of the structure and in the xy plane (e.g., in the AA plane passing through the silicon nitride layer 1006). Figure 10A (In the bottom part). Figures 10B-10G The same drawing layout was also used in the middle.

[0169] exist Figure 24At operation 2404, a semiconductor body is formed from a stack extending vertically through the dielectric layer from the substrate. In some embodiments, to form the semiconductor body, an opening extending through the dielectric layer of the stack is etched to expose a portion of the substrate, and the semiconductor body is epitaxially grown from the exposed portion of the substrate in the opening.

[0170] like Figure 10B As shown, an array of openings 1010 is formed, each opening extending perpendicularly (in the z-direction) through the stack of silicon oxide layer 1008, silicon nitride layer 1006, and silicon oxide layer 1004 to reach silicon substrate 1002. As a result, portions of silicon substrate 1002 can be exposed from the openings 1010. In some embodiments, for example based on word line and bit line designs, a photolithography process is performed to pattern the array of openings 1010 using an etch mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes (e.g., reactive ion etching (RIE)) are performed to etch the openings 1010 through silicon oxide layer 1008, silicon nitride layer 1006, and silicon oxide layer 1004 until stopped by silicon substrate 1002.

[0171] like Figure 10C As shown, an array of semiconductor bodies 1012 is formed in the opening 1010. The semiconductor bodies 1012 can be epitaxially grown from the corresponding exposed portions of the silicon substrate 1002 in the respective openings 1010. The fabrication process for epitaxially growing the semiconductor bodies 1012 can include, but is not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combination thereof. Epitaxy can proceed upwards (towards the positive z-direction) from the exposed portions of the silicon substrate 1002 in the openings 1010. The semiconductor bodies 1012 can therefore have the same material as the silicon substrate 1002, i.e., single-crystal silicon. Depending on the shape of the opening 1010, the semiconductor bodies 1012 can have the same shape as the opening 1010, such as a cubic or cylindrical shape. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor bodies 1012 that extend beyond the top surface of the silicon oxide layer 1008. As a result, according to some embodiments, an array of semiconductor bodies 1012 (e.g., single-crystal silicon bodies) is thus formed, extending vertically (in the z-direction) from the silicon substrate 1002 through a stack of silicon oxide layers 1008, silicon nitride layers 1006 and silicon oxide layers 1004.

[0172] exist Figure 24At operation 2406, a dielectric layer in the stack of dielectric layers is removed to expose a portion of the semiconductor body. In some embodiments, to remove a dielectric layer in the stack of dielectric layers, a trench is etched through at least a portion of the stack of dielectric layers to expose a layer having a second dielectric, and the layer having the second dielectric (e.g., a sacrificial layer) is etched away via the trench. In some embodiments, trenches are etched between adjacent rows of semiconductor bodies without contacting any sidewalls of the semiconductor bodies.

[0173] like Figure 10D As shown, a plurality of trenches 1014 (slot openings) are formed to expose a silicon nitride layer 1006. Each trench 1014 extends laterally along the word line direction (x-direction) and vertically through at least a silicon oxide layer 1008 and a silicon nitride layer 1006. As a result, portions of the silicon nitride layer 1006 can be exposed from the trenches 1014. In some embodiments, such as based on the word line (word line trench) design, a photolithography process is performed to pattern the trenches 1014 using an etch mask (e.g., a photoresist mask). Figure 10D As shown, trench 1014 is patterned to form between adjacent rows of semiconductor bodies 1012 without contacting any side of the semiconductor bodies 1012, such that the semiconductor bodies 1012 are not exposed from any of their sides. In one example, trench 1014 is patterned to form in the middle between adjacent rows of semiconductor bodies 1012, i.e., two adjacent rows of semiconductor bodies 1012 with the same distance. In some embodiments, one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch trench 1014 through silicon oxide layer 1008, silicon nitride layer 1006, and silicon oxide layer 1004 until it is stopped by silicon substrate 1002. It should be understood that in some examples, etching of trench 1014 may not continue to the silicon substrate 1002, but may stop at silicon oxide layer 1004, as long as silicon nitride layer 1006 is exposed from trench 1014.

[0174] like Figure 10E As shown, the silicon nitride layer 1006 (as shown) is removed. Figure 10DAs shown in the diagram, this exposes a portion of the adjacent silicon nitride layer 1006 of the semiconductor body 1012. In some embodiments, the silicon nitride layer 1006 is etched away via trench 1014. For example, a wet etchant comprising phosphoric acid can be applied through trench 1014 to selectively wet etch the silicon nitride layer 1006 without etching the silicon oxide layers 1004 and 1008, as well as the semiconductor body 1012 and the silicon substrate 1002. As a result, a lateral groove 1016 can be formed vertically between the silicon oxide layers 1004 and 1008, thereby exposing a portion of the semiconductor body 1012. As shown in the plan view, all sides of each semiconductor body 1012 can be exposed from the lateral groove 1016.

[0175] exist Figure 24 At operation 2408, a gate structure is formed that contacts multiple sides of the exposed portion of the semiconductor body. In some embodiments, to form the gate structure, a gate dielectric is formed on the exposed portion of the semiconductor body, a conductive layer is deposited on the gate dielectric, and the conductive layer is patterned to form a gate electrode on the gate dielectric.

[0176] like Figure 10F As shown, a gate dielectric 1018 is formed over the exposed portion of each semiconductor body 1012, i.e., surrounding and contacting all sides of the exposed portion of the semiconductor body 1012. As shown in the plan view, the gate dielectric 1018 may be completely external to the respective semiconductor body 1012. In some embodiments, wet oxidation and / or dry oxidation processes (e.g., ISSG) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 1012 (e.g., single-crystal silicon) as the gate dielectric 1018. In some embodiments, the gate dielectric 1018 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 1012 through trenches 1014 and lateral recesses 1016 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) without filling the lateral recesses 1016 and trenches 1014.

[0177] like Figure 10G As shown, through the groove 1014 in the transverse groove 1016 ( Figure 10FA conductive layer 1020 is formed over the gate dielectric 1018 (shown). In some embodiments, the conductive layer 1020 is formed by depositing a conductive material (e.g., a metal or metal compound (e.g., TiN)) over the gate dielectric 1018 through trench 1014 to fill the lateral trench 1016 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to fill the trench 1016. In one example, the deposition of the conductive layer 1020 is controlled to not fill the trench 1014. It should be understood that in some examples, the deposition of the conductive layer 1020 may also fill the trench 1014. Therefore, a planarization process (e.g., CMP) can be performed to remove excess conductive layer 1020 on the top surface of the silicon oxide layer 1008, and the conductive layer 1020 can be patterned to form a gate electrode over the respective gate dielectric. For example, the trench 1014 filled with the conductive layer 1020 can also be patterned and etched to separate the conductive layer 1020 between the semiconductor body 1012 and the gate dielectric 1018 in adjacent rows. As described above, for example, based on word lines (word line trenches), a photolithography process can be performed to pattern the trenches 1014 using an etch mask (e.g., a photoresist mask).

[0178] As a result, the patterned conductive layer 1020 can become word lines, each extending in the word line direction (x direction) and separated by adjacent trenches 1014, and the portion of the patterned conductive layer 1020 above the gate dielectric 1018 (e.g., completely external to the corresponding gate dielectric 1018 in a planar view) can become a gate electrode. This allows the formation of gate structures, each including a corresponding gate dielectric 1018 above an exposed portion of the semiconductor body 1012 and a corresponding gate electrode (i.e., a portion of the conductive layer 1020) above the gate dielectric 1018. Figure 10G As shown, according to some embodiments, since the conductive layer 1020 remains on all sides of the semiconductor body 1012 (and the gate dielectric 1018 thereon) during patterning of the conductive layer 1020 (etching trench 1014), the gate structure contacts all sides of the semiconductor body 1012. As shown in the plan view, the gate structure (having the gate dielectric 1018 and the gate electrode) can be completely external to the corresponding semiconductor body 1012, and all sides of each semiconductor body 1012 can be surrounded and contacted by the corresponding gate structure. Figure 10G and Figure 10A A comparison was made, based on some implementation methods. Figure 10A The silicon nitride layer 1006 (sacrificial layer) in the middle is ultimately made by Figure 10G The conductive layer 1020 is replaced.

[0179] exist Figure 24At operation 2410, the first end of the semiconductor body, far from the substrate, is doped. For example... Figure 10G As shown, the exposed upper end of each semiconductor body 1012 (i.e., one of the two ends of the semiconductor body 1012 that is away from the silicon substrate 1002 in the vertical direction (z-direction)) is doped to form a source / drain 1021. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 to form the source / drain 1021. In some embodiments, a silicide layer is formed on the source / drain 1021 by performing a silicide process at the exposed upper end of the semiconductor body 1012.

[0180] exist Figure 24 At operation 2412, a memory cell is formed in contact with a semiconductor substrate (e.g., its doped first end). The memory cell may include a capacitor or a PCM element. In some embodiments, to form a memory cell that is a capacitor, a first electrode is formed on the doped first end of the semiconductor substrate, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0181] like Figure 10H As shown, for example, one or more ILD layers are formed on the top surface of the silicon oxide layer 1008 by depositing a dielectric using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). It should be understood that in some examples where the ILD layer comprises silicon oxide (the same material as the silicon oxide layer 1008), the boundary and interface between the ILD layer and the silicon oxide layer 1008 may become indistinguishable after deposition. This depends on the lateral dimensions of the trench 1014 (e.g., ...). Figure 10G As shown, when the ILD layer is formed, trench 1014 may not be completely filled by a dielectric (e.g., silicon oxide), and thus become an air gap 1022 between adjacent word lines (patterned conductive layer 1020). It should be understood that in some examples, when the lateral dimension of trench 1014 is large enough, the dielectric can completely fill trench 1014 during ILD layer formation, thereby eliminating air gap 1022.

[0182] like Figure 10HAs shown, a first electrode 1024, a capacitor dielectric 1026, and a second electrode 1028 are subsequently formed in the ILD layer to form a capacitor in contact with the semiconductor body 1012. In some embodiments, each first electrode 1024 is formed on the corresponding source / drain 1021 (i.e., the doped upper end of the corresponding semiconductor body 1012) by patterning and etching electrode holes aligned with the corresponding source / drain 1021 using photolithography and etching processes, and by depositing conductive material to fill the electrode holes using a thin-film deposition process. Similarly, in some embodiments, the second electrode 1028 is formed on the capacitor dielectric 1026 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 1026 using photolithography and etching processes, and by depositing conductive material to fill the electrode holes using a thin-film deposition process.

[0183] exist Figure 24 At operation 2414, the substrate is removed to expose the second end of the semiconductor body opposite the first end. For example... Figure 10I As shown, a carrier substrate 1030 (also known as a processing substrate) is bonded to the front side of a silicon substrate 1002, and a device is formed on the front side of the silicon substrate 1002 using any suitable bonding process (e.g., anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1002 is above the carrier substrate 1030.

[0184] like Figure 10J As shown, the silicon substrate 1002 is removed ( Figure 10I (As shown) to expose the undoped upper end of the semiconductor body 1012 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1002 until the upper end of the silicon oxide layer 1004 and the semiconductor body 1012 are removed.

[0185] exist Figure 24 At operation 2416, the exposed second end of the doped semiconductor body. For example... Figure 10J As shown, the exposed upper end of each semiconductor body 1012 (i.e., one of the two ends of the semiconductor body 1012 that is away from the carrier substrate 1030 in the vertical direction (z-direction)) is doped to form another source / drain 1023. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 to form the source / drain 1023. In some embodiments, a silicide layer is formed on the source / drain 1023 by performing a silicide process at the exposed upper end of the semiconductor body 1012. As a result, as Figure 10JAs shown, according to some embodiments, a vertical transistor is thus formed having a semiconductor body 1012, source / drain electrodes 1021 and 1023, a gate dielectric 1018, and a gate electrode (a portion of the conductive layer 1020). As described above, as... Figure 10J As shown, according to some embodiments, capacitors each having a first electrode 1024 and a second electrode 1028 and a capacitor dielectric 1026 are thus formed, and DRAM cells 1080 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are thus formed.

[0186] Return to reference Figure 23 Method 2300 proceeds to operation 2308, such as... Figure 23 As shown, an interconnect layer including bit lines is formed above the memory cell array. Figure 10K As shown, an interconnect layer 1032 can be formed above the DRAM cell 1080. The interconnect layer 1032 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1080. In some embodiments, the interconnect layer 1032 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1032 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1004 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 10K The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1032.

[0187] like Figure 24 As shown, at operation 2418, bit lines are formed on the doped second end in order to form an interconnect layer. Figure 10K As shown, trenches aligned with the corresponding source / drain 1023 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin-film deposition processes to fill the trenches, forming bit lines 1034 on the source / drain 1023. As a result, bit lines 1034 and capacitors having electrodes 1024 and 1028 and capacitor dielectric 1026 can be formed on opposite sides of the semiconductor body 1012 and coupled to opposite ends of the semiconductor body 1012. It should be understood that additional local interconnects, such as word line contacts 1039, capacitor contacts 1083, and bit line contacts 1041, can also be formed similarly.

[0188] Method 2300 proceeds to operation 2310, such as... Figure 23As shown, a second bonding layer is formed above the memory cell array and the interconnect layer. The second bonding layer may include second bonding contacts. Figure 10K As shown, a bonding layer 1036 is formed over the interconnect layer 1032 and the DRAM cell 1080. The bonding layer 1036 may include a plurality of bonding contacts 1037 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of the interconnect layer 1032 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts 1037 that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1032. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0189] Method 2300 proceeds to operation 2312, such as... Figure 23 As shown, a first semiconductor structure and a second semiconductor structure are bonded face-to-face, such that a first memory cell array is coupled to peripheral circuitry via the bonding interface. Bonding may include hybrid bonding. In some embodiments, after bonding, the first bonding contacts and the second bonding contacts make contact at the bonding interface. In some embodiments, the second semiconductor structure is positioned above the first semiconductor structure after bonding. In some embodiments, the first semiconductor structure is positioned above the second semiconductor structure after bonding.

[0190] like Figure 10L As shown, the carrier substrate 1030 and the components formed thereon (e.g., DRAM cell 1080) are flipped upside down. Figure 10M As shown, the downward-facing bonding layer 1036 is bonded to the upward-facing bonding layer 1046 (i.e., face-to-face), thereby forming a bonding interface 1050. In some embodiments, a processing technique, such as plasma treatment, wet processing, and / or heat treatment, is applied to the bonding surfaces prior to bonding. Although Figure 10L and Figure 10MNot shown, but the silicon substrate 1038 and components formed thereon (e.g., peripheral circuitry 1040) can be flipped upside down, and the downward-facing bonding layer 1046 can be bonded to the upward-facing bonding layer 1036 (i.e., face-to-face), thereby forming a bonding interface 1050. After bonding, the bonding contacts 1037 in the bonding layer 1036 and the bonding contacts 1047 in the bonding layer 1046 are aligned and in contact with each other, so that the DRAM cell 1080 can be electrically connected to the peripheral circuitry 1040 via the bonding interface 1050. It is understood that in the bonded chip, the DRAM cell 1080 can be above or below the peripheral circuitry 1040. However, after bonding, the bonding interface 1050 can be formed vertically between the peripheral circuitry 1040 and the DRAM cell 1080.

[0191] Method 2300 proceeds to operation 2314, such as... Figure 23 As shown, an interconnect layer is formed on the back side of the first semiconductor structure or the second semiconductor structure, with pads leading out. Figure 10M As shown, a pad-out interconnect layer 1052 is formed on the back side of a carrier substrate 1030. The pad-out interconnect layer 1052 may include interconnects formed in one or more ILD layers, such as pad contacts 1054. The pad contacts 1054 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding, contacts 1056 extending vertically through the carrier substrate 1030 are formed, for example, by wet / dry etching processes followed by deposition of conductive material. Contacts 1056 may contact interconnects in the pad-out interconnect layer 1052. It should be understood that in some examples, the carrier substrate 1030 may be thinned or removed, for example, using planarization processes and / or etching processes, after bonding and before the formation of the pad-out interconnect layer 1052 and contacts 1056.

[0192] Although not shown, it should be understood that in some examples, the pad-out interconnect layer 1052 may be formed on the back side of the silicon substrate 1038, and the contacts 1056 may be formed to extend vertically through the silicon substrate 1038. The silicon substrate 1038 may be thinned, for example, using planarization and / or etching processes, prior to the formation of the pad-out interconnect layer 1052 and the contacts 1056.

[0193] As mentioned above, Figures 10A-10M The fabrication process for forming a DRAM array with vertically oriented transistors is shown, where the gate structure contacts all sides of the semiconductor body, i.e., a GAA transistor. In such... Figures 11A-11IIn some of the embodiments shown, a DRAM array with vertical transistors is formed with a relatively large word line pitch and reduced manufacturing complexity by changing the layout of the word line trenches, wherein the gate structure contacts some sides (e.g., three of the four sides) of the semiconductor body.

[0194] like Figure 11A As shown, a stack of silicon oxide layer 1104, silicon nitride layer 1106, and silicon oxide layer 1108 is formed on silicon substrate 1102. To form the dielectric stack, silicon oxide, silicon nitride, and silicon oxide are subsequently deposited onto silicon substrate 1102 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, silicon oxide layer 1104 is formed by oxidizing the top portion of silicon substrate 1102 using dry oxidation and / or wet oxidation (e.g., ISSG oxidation process). In some embodiments, the thickness of silicon oxide layer 1104 (e.g., ISSG silicon oxide) is less than the thickness of silicon oxide layer 1108 (e.g., CVD silicon oxide). Besides... Figure 11A Outside the side view of the cross-section along the y-direction (e.g., the bit line direction) shown in the top portion, Figure 11A The bottom portion also shows a plan view of the cross-section in the xy plane passing through the silicon nitride layer 1106. Figures 11B-11E The same drawing layout was also used in the middle.

[0195] like Figure 11B As shown, an array of semiconductor bodies 1112 is formed, each semiconductor body 1112 extending vertically through a stack of silicon oxide layer 1108, silicon nitride layer 1106, and silicon oxide layer 1104. The semiconductor bodies 1112 can be epitaxially grown from corresponding exposed portions of a silicon substrate 1102 in corresponding openings (not shown). The fabrication process for epitaxially growing the semiconductor bodies 1112 can include, but is not limited to, VPE, LPE, MPE, or any combination thereof. Epitaxy can proceed upwards (towards the positive z-direction) from the exposed portions of the silicon substrate 1102 in the openings. The semiconductor bodies 1112 can therefore have the same material as the silicon substrate 1102, i.e., monocrystalline silicon. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor bodies 1112 extending beyond the top surface of the silicon oxide layer 1108. As a result, according to some embodiments, an array of semiconductor bodies 1112 (e.g., single-crystal silicon bodies) is thus formed, extending vertically (in the z-direction) from the silicon substrate 1102 through a stack of silicon oxide layers 1108, silicon nitride layers 1106 and silicon oxide layers 1104.

[0196] In some implementations, in Figure 24At operation 2406, a portion of a dielectric layer in the stack of dielectric layers is removed to expose a portion of the semiconductor body. In some embodiments, to remove a dielectric layer in the stack of dielectric layers, a trench is etched through at least a portion of the stack of dielectric layers to expose a layer having a second dielectric, and the layer having the second dielectric (e.g., a sacrificial layer) is etched away via the trench. In some embodiments, the trench is etched to align with a side of the semiconductor body to expose the semiconductor body from that side.

[0197] like Figure 11C As shown, a plurality of trenches 1114 (slot openings) are formed to expose the silicon nitride layer 1106. Each trench 1114 extends laterally along the word line direction (x-direction) and vertically through at least the silicon oxide layer 1108 and the silicon nitride layer 1106. As a result, portions of the silicon nitride layer 1106 can be exposed from the trenches 1114. In some embodiments, for example, based on the design of the word lines (word line trenches), a photolithography process is performed to pattern the trenches 1114 using an etch mask (e.g., a photoresist mask). Figure 11C As shown, according to some embodiments, trench 1114 is patterned to form between adjacent rows of semiconductor bodies 1112 and aligned with one side of the semiconductor body 1112 to expose the semiconductor body 1112 from that side. That is, trench 1114 may be patterned to contact one side of the semiconductor body 1112, such that the semiconductor body 1112 is exposed from that side. In some embodiments, one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch trench 1114 through silicon oxide layer 1108, silicon nitride layer 1106, and silicon oxide layer 1104 until it is stopped by silicon substrate 1102. It should be understood that in some examples, etching of trench 1114 may not continue to the silicon substrate 1102, but may stop at silicon oxide layer 1104, as long as silicon nitride layer 1106 is exposed from trench 1114.

[0198] like Figure 11D As shown, the silicon nitride layer 1106 is removed. Figure 11C (As shown) to expose a portion of the adjacent silicon nitride layer 1106 of the semiconductor body 1112. In some embodiments, the silicon nitride layer 1106 is etched away via trench 1114. For example, the silicon nitride layer 1106 can be selectively wet-etched by applying a wet etchant including phosphoric acid through trench 1114, without etching the silicon oxide layers 1104 and 1108, as well as the semiconductor body 1112 and the silicon substrate 1102. As a result, a lateral groove 1116 can be formed vertically between the silicon oxide layers 1104 and 1108, thereby exposing a portion of the semiconductor body 1112.

[0199] like Figure 11DAs shown, a gate dielectric 1118 is formed over the exposed portion of each semiconductor body 1112, i.e., surrounding and contacting all sides of the exposed portion of the semiconductor body 1112. As shown in the plan view, the gate dielectric 1118 may be completely external to the respective semiconductor body 1112. In some embodiments, wet oxidation and / or dry oxidation processes (e.g., ISSG) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 1112 (e.g., single-crystal silicon) as the gate dielectric 1118. In some embodiments, the gate dielectric 1118 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 1112 through trenches 1114 and lateral recesses 1116 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) without filling the lateral recesses 1116 and trenches 1114.

[0200] and Figure 10F The difference lies in Figure 10F Because all sides of the semiconductor body 1112 are surrounded by lateral grooves 1016 with the same vertical dimension, the gate dielectric 1118 has a consistent vertical dimension (thickness in the z-direction). Figure 11D In this context, because one side of the semiconductor body 1112 aligns with and contacts a trench 1114 having a vertical dimension larger than that of the lateral groove 1116, a portion of the gate dielectric 1118 formed on that side of the semiconductor body 1112 (referred to as the extended gate dielectric portion 1119) can have a larger vertical dimension than the remaining portion of the gate dielectric 1118 formed on the other sides of the semiconductor body 1112 that contact the lateral groove 1116, such as... Figure 11D The side view is shown.

[0201] like Figure 11E As shown, the conductive layer 1120 is formed in the transverse groove 1116 that passes through the trench 1114 (e.g. Figure 11DThe conductive layer 1120 is formed over the gate dielectric 1118 (as shown), but not over the extended gate dielectric portion 1119. In some embodiments, a conductive material (e.g., a metal or metal compound (e.g., TiN)) is deposited over the gate dielectric 1118 through trench 1114 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to fill the lateral trench 1116. In one example, the deposition of the conductive layer 1120 is controlled to not fill the trench 1114 (and not over the extended gate dielectric portion 1119). It should be understood that in some examples, the deposition of the conductive layer 1120 may also fill the trench 1114. Therefore, a planarization process (e.g., CMP) can be performed to remove excess conductive layer 1120 over the top surface of the silicon oxide layer 1108, and the conductive layer 1120 can be patterned to form the gate electrode only over the gate dielectric 1118 and not over the extended gate dielectric portion 1119. For example, trenches 1114 filled with conductive layer 1120 can be patterned and etched in the same way to separate the conductive layer 1120 between the semiconductor body 1112 and the gate dielectric 1118 in adjacent rows. As described above, for example, based on word line (word line trench) design, a photolithography process can be performed to pattern trenches 1114 using an etching mask (e.g., a photoresist mask).

[0202] As a result, the patterned conductive layer 1120 can become word lines, each word line extending in the word line direction (x direction) and separated by adjacent trenches 1114, and the portion of the patterned conductive layer 1120 above the gate dielectric 1118 but not above the extended gate dielectric portion 1119 can become a gate electrode. This allows the formation of gate structures, each gate structure including a corresponding gate dielectric 1118 above the exposed portion of the semiconductor body 1112 and a corresponding gate electrode (i.e., a portion of the conductive layer 1120) above the gate dielectric 1118. Figure 11E As shown, according to some embodiments, since the conductive layer 1120 is only retained on some sides of the semiconductor body 1012 (and the gate dielectric 1018 thereon) when the conductive layer 1120 is patterned (etched trench 1114), the gate structure contacts some, but not all, sides of the semiconductor body 1012. As shown in the plan view, the gate structure (having the gate dielectric 1118 and the gate electrode) can be partially external to the corresponding semiconductor body 1112, and not all sides of each semiconductor body 1112 can be surrounded and contacted by the corresponding gate structure. Figure 10G Compared to the spacing of the 1020 character lines in the example, Figure 11E The spacing of the 1120 character lines can be increased to reduce manufacturing complexity.

[0203] like Figure 11E As shown, the exposed upper end of each semiconductor body 1112 (i.e., one of the two ends of the semiconductor body 1112 that is away from the silicon substrate 1102 in the vertical direction (z-direction)) is doped to form a source / drain 1121. In some embodiments, an implantation process and / or a thermal diffusion process are performed to dope a P-type dopant or an N-type dopant onto the exposed upper end of the semiconductor body 1112 to form a source / drain 1021.

[0204] like Figure 11F As shown, for example, a dielectric is deposited on the top surface of the silicon oxide layer 1108 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) to form one or more ILD layers. It should be understood that in some examples where the ILD layer comprises silicon oxide (the same material as the silicon oxide layer 1108), the boundary and interface between the ILD layer and the silicon oxide layer 1108 may become indistinguishable after deposition. This is because trench 1114 (compared to trench 1014) Figure 11E The relatively large lateral dimensions (as a result of the larger spacing of word lines 1120) of the trench 1114, when the ILD layer is formed, allow the trench 1114 to be completely or at least partially filled with a dielectric (e.g., silicon oxide), and thus eliminate or at least reduce the air gap 1022 between adjacent word lines (patterned conductive layer 1120).

[0205] like Figure 11F As shown, a first electrode 1124, a capacitor dielectric 1126, and a second electrode 1128 are subsequently formed in the ILD layer to form a capacitor in contact with the semiconductor body 1112. In some embodiments, each first electrode 1124 is formed on the corresponding source / drain 1121 (i.e., the doped upper end of the corresponding semiconductor body 1112) by patterning and etching electrode holes aligned with the corresponding source / drain 1121 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process. Similarly, in some embodiments, the second electrode 1128 is formed on the capacitor dielectric 1126 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 1126 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process.

[0206] like Figure 11G As shown, a carrier substrate 1130 (also known as a processing substrate) is bonded to the front side of a silicon substrate 1102, and a device is formed on the front side of the silicon substrate 1102 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1102 is above the carrier substrate 1130.

[0207] like Figure 11H As shown, the silicon substrate 1102 is removed ( Figure 11G As shown), to expose the undoped upper end of the semiconductor body 1112 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1102 until the upper end of the semiconductor body 1112 is covered by the silicon oxide layer 1104 and the silicon body 1112.

[0208] like Figure 11H As shown, the exposed upper end of each semiconductor body 1112 (i.e., one of the two ends of the semiconductor body 1112 that is away from the carrier substrate 1130 in the vertical direction (z-direction)) is doped to form another source / drain 1123. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1112 to form the source / drain 1123. As a result, as Figure 11H As shown, according to some embodiments, a multi-gate vertical transistor is thus formed having a semiconductor body 1112, source / drain electrodes 1121 and 1123, a gate dielectric 1118 (excluding the extended gate dielectric portion 1119), and a gate electrode (a portion of the conductive layer 1120). As described above, as... Figure 11H As shown, according to some embodiments, capacitors each having a first electrode 1124 and a second electrode 1128 and a capacitor dielectric 1126 are thus formed, and DRAM cells 1180 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are thus formed.

[0209] like Figure 11I As shown, an interconnect layer 1132 can be formed above the DRAM cell 1180. The interconnect layer 1132 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers to form an electrical connection with the DRAM cell 1180. In some embodiments, the interconnect layer 1132 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1132 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1104 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 11I The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1132. For example... Figure 11IAs shown, trenches aligned with the corresponding source / drain 1123 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin film deposition processes to fill the trenches, forming bit lines 1134 on the source / drain 1123.

[0210] like Figure 11I As shown, a bonding layer 1136 is formed over interconnect layer 1132 and DRAM cell 1180. Bonding layer 1136 may include a plurality of bonding contacts 1137 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of interconnect layer 1132 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts 1137 that penetrate the dielectric layer and contact the interconnects in interconnect layer 1132. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0211] As mentioned above, Figures 10A-10M A fabrication process for forming a DRAM cell array from a three-layer dielectric stack is illustrated, the three-layer dielectric stack having a sacrificial layer (e.g., silicon nitride layer 1006) sandwiched between two dielectric layers (e.g., silicon oxide layers 1004 and 1008). It should be understood that in other examples, the construction of the dielectric stack forming the DRAM cell array can be varied, resulting in DRAM cells with different structures, for example in... Figure 6C and Figure 6D In the 3D memory devices 603 and 605. In such Figures 12A-12H In some of the embodiments shown, the DRAM cell array is formed by a two-layer dielectric stack having a sacrificial layer on the dielectric layer.

[0212] exist Figure 24 At operation 2402, a stack of dielectric layers is formed on the substrate. In some embodiments, to form the stack of dielectric layers, two layers having a first dielectric and a second dielectric, respectively, are subsequently deposited on the substrate. The first dielectric may include silicon oxide, and the second dielectric may include silicon nitride. The layer having the second dielectric can be used as a sacrificial layer on the layer having the first dielectric. The sacrificial layer can be removed by selective etching relative to the other layer having the first dielectric, and the sacrificial layer can be replaced with a conductive layer in subsequent processes.

[0213] like Figure 12AAs shown, a stack of silicon oxide layer 1204 and silicon nitride layer 1206 is formed on silicon substrate 1202. To form the dielectric stack, silicon oxide and silicon nitride are subsequently deposited onto silicon substrate 1202 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, the top portion of silicon substrate 1202 is oxidized using dry oxidation and / or wet oxidation (e.g., in-situ vapor generation (ISSG) oxidation process) to form silicon oxide layer 1204.

[0214] like Figure 12B As shown, an array of semiconductor bodies 1212 is formed, each semiconductor body 1212 extending vertically through a stack of silicon nitride layers 1206 and silicon oxide layers 1204. The semiconductor bodies 1212 can be epitaxially grown from corresponding exposed portions of a silicon substrate 1202 in corresponding openings (not shown). The fabrication process for epitaxially growing the semiconductor bodies 1212 can include, but is not limited to, VPE, LPE, MPE, or any combination thereof. Epitaxy can proceed upwards (towards the positive z-direction) from the exposed portions of the silicon substrate 1202 in the openings. The semiconductor bodies 1212 can therefore have the same material as the silicon substrate 1202, i.e., monocrystalline silicon. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor bodies 1212 extending beyond the top surface of the silicon nitride layer 1206. As a result, according to some embodiments, an array of semiconductor bodies 1212 (e.g., monocrystalline silicon bodies) extending vertically (in the z-direction) through a stack of silicon nitride layers 1206 and silicon oxide layers 1204 from the silicon substrate 1202 is thus formed.

[0215] like Figure 12C As shown, a plurality of trenches 1214 (slot openings) are formed to expose a silicon nitride layer 1206. Each trench 1214 extends laterally along the word line direction (x-direction) and vertically through at least the silicon nitride layer 1206. As a result, portions of the silicon nitride layer 1206 can be exposed from the trenches 1214. In some embodiments, for example based on a word line (word line trench) design, a photolithography process is performed to pattern the trenches 1214 using an etching mask (e.g., a photoresist mask). In some embodiments, one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 1214 through the silicon nitride layer 1206 and the silicon oxide layer 1204 until stopped by the silicon substrate 1202. It should be understood that in some examples, the etching of the trenches 1214 may not reach the silicon substrate 1202 and may stop at the silicon oxide layer 1204, as long as the silicon nitride layer 1206 is exposed from the trenches 1214.

[0216] like Figure 12D As shown, the silicon nitride layer 1206 is removed. Figure 12CAs shown), to expose a portion of the adjacent silicon nitride layer 1206 of the semiconductor body 1212. In some embodiments, the silicon nitride layer 1206 is etched away via trench 1214. For example, a wet etchant comprising phosphoric acid can be applied through trench 1214 to selectively wet etch the silicon nitride layer 1206 without etching the silicon oxide layer 1204, the semiconductor body 1212, and the silicon substrate 1202. As a result, a lateral groove 1216 is formed to expose a portion of the semiconductor body 1212. It should be understood that in some examples, the top surface of the silicon nitride layer 1206 can be exposed, so that trench 1214 is not required to remove the silicon nitride layer 1206. Dry etching and / or wet etching processes can be applied directly to the silicon nitride layer 1206 to remove the silicon nitride layer 1206 (i.e., from...). Figure 12B Directly to Figure 12D Without going through Figure 12C ).

[0217] like Figure 12D As shown, the gate dielectric 1218 is formed over the exposed portion of each semiconductor body 1212, i.e., surrounding and contacting all sides of the exposed portion of the semiconductor body 1212. In some embodiments, wet oxidation and / or dry oxidation processes (e.g., ISSG) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 1212 (e.g., single-crystal silicon) as the gate dielectric 1218. In some embodiments, the gate dielectric 1218 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 1212 through trenches 1214 and lateral recesses 1216 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) without filling the lateral recesses 1216 and trenches 1214. Since the silicon oxide layer 1008 is omitted, the upper end of the gate dielectric 1218 can be flush with the upper end of the semiconductor body 1212, as shown. Figure 12D As shown, while Figure 10F The upper end of the gate dielectric 1018 is below the upper end of the semiconductor body 1012.

[0218] like Figure 12E As shown, through the groove 1214 in the transverse groove 1216 ( Figure 12DA conductive layer 1220 is formed over the gate dielectric 1218 (shown). In some embodiments, the conductive layer 1220 is formed by depositing a conductive material (e.g., a metal or metal compound (e.g., TiN)) over the gate dielectric 1218 through trench 1214 to fill the lateral trench 1216 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to fill the trench 1216. In one example, the deposition of the conductive layer 1220 is controlled to not fill the trench 1214. It should be understood that in some examples, the deposition of the conductive layer 1220 may also fill the trench 1214. Therefore, a planarization process (e.g., CMP) can be performed to remove excess conductive layer 1220 to expose the upper end of the semiconductor body 1212, and the conductive layer 1220 can be patterned to form a gate electrode over the respective gate dielectric. For example, trenches 1214 filled with conductive layer 1220 can be patterned and etched in the same way to separate the conductive layer 1220 between the semiconductor body 1212 and the gate dielectric 1218 in adjacent rows. As described above, for example based on a word line (word line trench) design, a photolithography process can be performed to pattern the trenches 1214 using an etching mask (e.g., a photoresist mask). Since the silicon oxide layer 1008 is omitted, the top surface of the conductive layer 1220 (including the gate electrode and word line) can be flush with the upper end of the semiconductor body 1212, such as... Figure 12E As shown, while Figure 10G The top surface of the Chinese character line 1020 is below the upper end of the semiconductor body 1012.

[0219] As a result, the patterned conductive layer 1220 can become word lines, each word line extending in the word line direction (x direction) and separated by adjacent trenches 1214, and the portion of the patterned conductive layer 1220 above the gate dielectric 1218 (e.g., completely external to the corresponding gate dielectric 1218 in a planar view) can become a gate electrode. This allows the formation of gate structures, each gate structure including a corresponding gate dielectric 1218 on the exposed portion of the semiconductor body 1212 and a corresponding gate electrode (i.e., a portion of the conductive layer 1220) on the gate dielectric 1218. Figure 12E and Figure 12A A comparison was made, based on some implementation methods. Figure 12A The silicon nitride layer 1206 (sacrificial layer) in the middle was eventually... Figure 12E The conductive layer 1220 is replaced.

[0220] like Figure 12EAs shown, the exposed upper portion of each semiconductor body 1212 (i.e., one of the two ends of the semiconductor body 1212 that is away from the silicon substrate 1202 in the vertical direction (z-direction)) is doped to form a source / drain 1221. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper portion of the semiconductor body 1212 to form the source / drain 1221.

[0221] like Figure 12F As shown, for example, a dielectric is deposited on the top surface of the conductive layer 1220 by means of one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) to form one or more ILD layers. Depending on the lateral dimensions of the trench 1214 (e.g., ...), Figure 12E As shown, when the ILD layer is formed, trench 1214 may not be completely filled with a dielectric (e.g., silicon oxide), and thus become an air gap 1222 between adjacent word lines (patterned conductive layer 1220). It should be understood that in some examples, when the lateral dimension of trench 1214 is large enough, the dielectric can completely fill trench 1214 during ILD layer formation, thereby eliminating air gap 1222.

[0222] like Figure 12F As shown, a first electrode 1224, a capacitor dielectric 1226, and a second electrode 1228 are subsequently formed in the ILD layer to form a capacitor in contact with the semiconductor body 1212. In some embodiments, each first electrode 1224 is formed on the corresponding source / drain 1221 (i.e., the doped upper end of the corresponding semiconductor body 1212) by patterning and etching electrode holes aligned with the corresponding source / drain 1221 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process. Similarly, in some embodiments, the second electrode 1228 is formed on the capacitor dielectric 1226 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 1226 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process.

[0223] like Figure 12G As shown, a carrier substrate (also known as a processing substrate) 1230 is bonded to the front side of a silicon substrate 1202, and a device is formed on the front side of the silicon substrate 1202 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1202 is above the carrier substrate 1230.

[0224] like Figure 12G As shown, the silicon substrate 1202 is removed ( Figure 12F(As shown) to expose the undoped upper end of the semiconductor body 1212 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1202 until the upper end of the silicon oxide layer 1204 and the semiconductor body 1212 are removed.

[0225] like Figure 12G As shown, the exposed upper end of each semiconductor body 1212 (i.e., one of the two ends of the semiconductor body 1212 away from the carrier substrate 1230 in the vertical direction (z-direction)) is doped to form another source / drain 1223. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1212 to form the source / drain 1223. As a result, as Figure 12G As shown, according to some embodiments, a multi-gate vertical transistor is thus formed having a semiconductor body 1212, source / drain electrodes 1221 and 1223, a gate dielectric 1218, and a gate electrode (a portion of the conductive layer 1220). As described above, as... Figure 12G As shown, according to some embodiments, capacitors each having a first electrode 1224 and a second electrode 1228 and a capacitor dielectric 1226 are thus formed, and DRAM cells 1280 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are thus formed.

[0226] like Figure 12H As shown, an interconnect layer 1232 can be formed above the DRAM cell 1280. The interconnect layer 1232 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1280. In some embodiments, the interconnect layer 1232 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1232 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1204 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 12H The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1232. For example... Figure 12H As shown, trenches aligned with the corresponding source / drain 1223 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin film deposition processes to fill the trenches, forming bit lines 1234 on the source / drain 1223.

[0227] like Figure 12H As shown, a bonding layer 1236 is formed over the interconnect layer 1232 and the DRAM cell 1280. The bonding layer 1236 may include a plurality of bonding contacts 1237 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of the interconnect layer 1232 by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts 1237 that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1232. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0228] In such Figures 13A-13H In some embodiments shown, the DRAM cell array is formed by a four-layer dielectric stack having a sacrificial layer (e.g., silicon oxide layer) sandwiched between two dielectric layers (e.g., silicon nitride layers) on a pad layer (e.g., silicon oxide layer).

[0229] exist Figure 24 At operation 2402, a stack of dielectric layers is formed on the substrate. In some embodiments, to form the stack of dielectric layers, four layers having a first dielectric, a second dielectric, a third dielectric, and a second dielectric are subsequently deposited on the substrate. The second dielectric may include silicon nitride, and the third dielectric may include silicon oxide. The layer having the third dielectric can be used as a sacrificial layer vertically sandwiched between the two layers having the second dielectric. The sacrificial layer can be removed by selective etching relative to the other layer having the second dielectric, and the sacrificial layer can be replaced with a conductive layer in subsequent processes.

[0230] like Figure 13A As shown, a stack of silicon oxide layer 1304, silicon nitride layer 1306, silicon oxide layer 1308, and silicon nitride layer 1309 is formed on silicon substrate 1302. To form the dielectric stack, silicon oxide and silicon nitride are subsequently deposited onto silicon substrate 1302 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, the top portion of silicon substrate 1302 is oxidized using dry oxidation and / or wet oxidation (e.g., ISSG oxidation process) to form silicon oxide layer 1304 (pad layer). In some embodiments, the thickness of silicon oxide layer 1304 (e.g., ISSG silicon oxide) is less than the thickness of silicon oxide layer 1308 (e.g., CVD silicon oxide).

[0231] like Figure 13B As shown, an array of semiconductor bodies 1312 is formed, each semiconductor body 1312 extending vertically through a stack of silicon oxide layer 1304, silicon nitride layer 1306, silicon oxide layer 1308, and silicon nitride layer 1309. The semiconductor bodies 1312 can be epitaxially grown from corresponding exposed portions of a silicon substrate 1302 in corresponding openings (not shown). The fabrication process for epitaxially growing the semiconductor bodies 1312 can include, but is not limited to, VPE, LPE, MPE, or any combination thereof. Epitaxy can proceed upwards (towards the positive z-direction) from the exposed portions of the silicon substrate 1302 in the openings. The semiconductor bodies 1312 can therefore have the same material as the silicon substrate 1302, i.e., monocrystalline silicon. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess portions of the semiconductor bodies 1312 extending beyond the top surface of the silicon nitride layer 1309. As a result, according to some embodiments, an array of semiconductor bodies 1312 (e.g., single-crystal silicon bodies) is thus formed, extending vertically (in the z-direction) from the silicon substrate 1302 through a stack of silicon oxide layers 1304, silicon nitride layers 1306, silicon oxide layers 1308, and silicon nitride layers 1309.

[0232] exist Figure 24 At operation 2406, a portion of a dielectric layer in the stack of dielectric layers is removed to expose a portion of the semiconductor body. In some embodiments, to remove a dielectric layer in the stack of dielectric layers, a trench is etched through at least a portion of the stack of dielectric layers to expose a layer having a third dielectric, and the layer having the third dielectric (e.g., a sacrificial layer) is etched away via the trench.

[0233] like Figure 13C As shown, a plurality of trenches 1314 (slot openings) are formed to expose the silicon oxide layer 1308. Each trench 1314 extends laterally along the word line direction (x-direction) and vertically through at least the silicon nitride layer 1309 and the silicon oxide layer 1308. As a result, portions of the silicon oxide layer 1308 can be exposed from the trenches 1314. In some embodiments, for example based on the word line (word line trench) design, a photolithography process is performed to pattern the trenches 1314 using an etch mask (e.g., a photoresist mask). In some embodiments, one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 1314 through the silicon nitride layer 1309 and the silicon oxide layer 1308 until stopped by the silicon nitride layer 1306. It should be understood that in some examples, the etching of the trenches 1314 may further penetrate into the silicon nitride layer 1306 but not into the silicon oxide layer 1304.

[0234] like Figure 13D As shown, the silicon oxide layer 1308 is removed. Figure 13C(As shown), to expose a portion of the adjacent silicon oxide layer 1308 of the semiconductor body 1312. In some embodiments, the silicon oxide layer 1308 is etched away via trench 1314. For example, a wet etchant comprising hydrofluoric acid can be applied through trench 1314 to selectively wet etch the silicon oxide layer 1308 without etching the silicon nitride layers 1309 and 1306 and the semiconductor body 1312. As a result, a lateral groove 1316 can be formed to expose a portion of the semiconductor body 1312.

[0235] like Figure 13E As shown, the gate dielectric 1318 is formed over the exposed portion of each semiconductor body 1312, i.e., surrounding and contacting all sides of the exposed portion of the semiconductor body 1312. In some embodiments, wet oxidation and / or dry oxidation processes (e.g., ISSG) are performed to form a native oxide (e.g., silicon oxide) as the gate dielectric 1318 on the semiconductor body 1312 (e.g., single-crystal silicon). In some embodiments, the gate dielectric 1318 is formed by depositing a dielectric layer (e.g., silicon oxide) over the exposed portion of the semiconductor body 1312 through trenches 1314 and lateral recesses 1316 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) without filling the lateral recesses 1316 and trenches 1314. Due to the presence of the silicon nitride layer 1309, in Figure 13E The upper end of the gate dielectric 1318 may be below the upper end of the semiconductor body 1312.

[0236] like Figure 13F As shown, through the groove 1314 in the transverse groove 1316 (as shown) Figure 13EA conductive layer 1320 is formed over the gate dielectric 1318 (shown). In some embodiments, the conductive layer 1320 is formed by depositing a conductive material (e.g., a metal or metal compound (e.g., TiN)) over the gate dielectric 1318 through trench 1314 to fill the lateral trench 1316 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to fill the trench 1316. In one example, the deposition of the conductive layer 1320 is controlled to not fill the trench 1314. It should be understood that in some examples, the deposition of the conductive layer 1320 may also fill the trench 1314. Therefore, a planarization process (e.g., CMP) can be performed to remove excess conductive layer 1320 to expose the upper end of the semiconductor body 1312, and the conductive layer 1320 can be patterned to form a gate electrode over the respective gate dielectric. For example, trenches 1314 filled with conductive layer 1320 can be patterned and etched in the same way to separate the conductive layer 1320 between the semiconductor body 1312 and the gate dielectric 1318 in adjacent rows. As described above, for example based on word line (word line trench) designs, photolithography processes can be performed to pattern trenches 1314 using an etching mask (e.g., a photoresist mask). Due to the presence of silicon nitride layer 1309, in Figure 13F The top surface of the intermediate conductive layer 1320 (including the gate electrode and word line) may be below the upper end of the semiconductor body 1312.

[0237] As a result, the patterned conductive layer 1320 can serve as word lines, each extending in the word line direction (x-direction) and separated by adjacent trenches 1314, and the portion of the patterned conductive layer 1320 above the gate dielectric 1318 (e.g., completely external to the corresponding gate dielectric 1318 in a planar view) can serve as a gate electrode. This allows the formation of gate structures, each including a corresponding gate dielectric 1318 on the exposed portion of the semiconductor body 1312 and a corresponding gate electrode (i.e., a portion of the conductive layer 1320) on the gate dielectric 1318. Figure 13F and Figure 13A A comparison was made, based on some implementation methods. Figure 13A The silicon oxide layer 1308 (sacrificial layer) in the middle is ultimately made by Figure 13F The conductive layer 1320 is replaced.

[0238] like Figure 13FAs shown, the exposed upper portion of each semiconductor body 1312 (i.e., one of the two ends of the semiconductor body 1312 away from the silicon substrate 1302 in the vertical direction (z-direction)) is doped to form a source / drain 1321. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper portion of the semiconductor body 1312 to form the source / drain 1321.

[0239] like Figure 13G As shown, for example, one or more ILD layers are formed on the top surface of the silicon nitride layer 1309 by depositing a dielectric using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Depending on the lateral dimensions of the trench 1314 (e.g., ...), Figure 13F As shown, when the ILD layer is formed, trench 1314 may not be completely filled by a dielectric (e.g., silicon oxide), and thus become an air gap 1322 between adjacent word lines (patterned conductive layer 1320). It should be understood that in some examples, when the lateral dimension of trench 1314 is large enough, the dielectric can completely fill trench 1314 during the formation of the ILD layer, thereby eliminating air gap 1322.

[0240] like Figure 13G As shown, a first electrode 1324, a capacitor dielectric 1326, and a second electrode 1328 are subsequently formed in the ILD layer to form a capacitor in contact with the semiconductor body 1312. In some embodiments, each first electrode 1324 is formed on the corresponding source / drain 1321 (i.e., the doped upper end of the corresponding semiconductor body 1312) by patterning and etching electrode holes aligned with the corresponding source / drain 1321 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process. Similarly, in some embodiments, the second electrode 1328 is formed on the capacitor dielectric 1326 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 1326 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin film deposition process.

[0241] like Figure 13H As shown, a carrier substrate 1330 (also known as a processing substrate) is bonded to the front side of a silicon substrate 1302, and a device is formed on the front side of the silicon substrate 1302 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1302 is above the carrier substrate 1330.

[0242] like Figure 13H As shown, the silicon substrate 1302 is removed ( Figure 13G(As shown) to expose the undoped upper end of the semiconductor body 1312 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1302 until the upper end of the silicon oxide layer 1304 and the semiconductor body 1312 are removed.

[0243] like Figure 13H As shown, the exposed upper end of each semiconductor body 1312 (i.e., one of the two ends of the semiconductor body 1312 away from the carrier substrate 1330 in the vertical direction (z-direction)) is doped to form another source / drain 1323. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1312 to form the source / drain 1323. As a result, as Figure 13H As shown, according to some embodiments, a vertical transistor is thus formed having a semiconductor body 1312, source / drain electrodes 1321 and 1323, a gate dielectric 1318, and a gate electrode (a portion of the conductive layer 1320). Figure 13H As shown, according to some embodiments, as described above, capacitors each having a first electrode 1324 and a second electrode 1328 and a capacitor dielectric 1326 are also formed therefrom, and DRAM cells 1380 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are formed therefrom.

[0244] like Figure 13H As shown, an interconnect layer 1332 can be formed above the DRAM cell 1380. The interconnect layer 1332 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1380. In some embodiments, the interconnect layer 1332 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1332 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1304 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 13H The ILD layer and interconnects shown can be collectively referred to as interconnect layer 1332. For example... Figure 13H As shown, trenches aligned with the corresponding source / drain 1323 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin film deposition processes to fill the trenches, forming bit lines 1334 on the source / drain 1323.

[0245] like Figure 13H As shown, a bonding layer 1336 is formed over the interconnect layer 1332 and the DRAM cell 1380. The bonding layer 1336 may include a plurality of bonding contacts 1337 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of the interconnect layer 1332 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts 1337 that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1332. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0246] A third semiconductor structure comprising a second array of memory cells can be formed. Each memory cell may also include a vertical transistor and a memory cell coupled to the vertical transistor. The second and third semiconductor structures may be bonded face-to-face. In some embodiments, the second and third semiconductor structures are bonded before the first and second semiconductor structures are bonded. For example, as... Figure 23 As shown, the second semiconductor structure and the third semiconductor structure can be bonded before operation 2312 (e.g., between operation 2306 and operation 2308).

[0247] like Figure 14A As shown, any suitable manufacturing process disclosed herein (e.g., in) Figures 10A-10H Two semiconductor structures 1000 and 1400 are formed individually (e.g., in parallel). For ease of description, the manufacturing process for forming semiconductor structure 1400 is not repeated, and the manufacturing process for forming semiconductor structure 1400 is the same as that for forming semiconductor structure 1000. Therefore, the two semiconductor structures 1000 and 1400 can have the same devices in them.

[0248] like Figure 14A As shown, the semiconductor structure 1400 is flipped vertically. (As...) Figure 14BAs shown, a bonding interface 1402 is formed by bonding the downward-facing semiconductor structure 1400 to the upward-facing semiconductor structure 1000 (i.e., face-to-face bonding) using any suitable substrate / wafer bonding process, including, for example, hybrid bonding (as described in detail above), anodic bonding, and fusion (direct) bonding. In one example, fusion bonding can be performed between silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide layers using pressure and heat. In another example, anodic bonding can be performed between silicon oxide (in ionomer glass) and silicon layers using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 1402. For example, a silicon oxide layer can be formed on the top surfaces of semiconductor structures 1000 and 1400 to allow for fusion-bonded SiO2-SiO2 bonding. In some embodiments, the second electrode 1028 of semiconductor structure 1400 is in contact with the second electrode 1028 of semiconductor structure 1000 at bonding interface 1402, and can therefore be regarded as a common electrode (e.g., a common ground plane) for both semiconductor structures 1000 and 1400.

[0249] like Figure 14B As shown, the silicon substrate 1002 (on top of the semiconductor structure 1000 after bonding) has the semiconductor structure 1400 removed. Figure 14A As shown), to expose the undoped upper end of the semiconductor body 1012 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1002 of the semiconductor structure 1400 until the upper end of the semiconductor body 1012 of the semiconductor structure 1400 is removed by the silicon oxide layer 1004.

[0250] like Figure 14B As shown, the exposed upper end of each semiconductor body 1012 of the doped semiconductor structure 1400 (i.e., one of the two ends of the semiconductor body 1012 that is away from the semiconductor structure 1000 in the vertical direction (z-direction)) forms another source / drain 1023. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 of the semiconductor structure 1400 to form the source / drain 1023. As a result, as Figure 14B As shown, according to some embodiments, a multi-gate vertical transistor having a semiconductor body 1012, source / drain electrodes 1021 and 1023, a gate dielectric 1018, and a gate electrode (a portion of the conductive layer 1020) is thus formed in the semiconductor structure 1400. As described above, Figure 14BAs shown, according to some embodiments, capacitors each having a first electrode 1024 and a second electrode 1028 and a capacitor dielectric 1026 are also formed, and DRAM cells 1080 of semiconductor structure 1400 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are formed.

[0251] like Figure 14C As shown, an interconnect layer 1032 can be formed above the DRAM cell 1080. The interconnect layer 1032 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1080. In some embodiments, the interconnect layer 1032 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1032 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing processes forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1004 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 14C The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1032.

[0252] like Figure 14D As shown, a carrier substrate 1030 (also referred to as a processing substrate) is bonded to the front side of the semiconductor structure 1400, and a device is formed on the front side of the semiconductor structure 1400 using any suitable bonding process (e.g., anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the semiconductor structure 1000 is positioned above the carrier substrate 1030. Figure 14D (Not shown in the image).

[0253] like Figure 14D As shown, the silicon substrate 1002 of the semiconductor structure 1000 is removed. Figure 14C As shown), to expose the undoped upper end of the semiconductor body 1012 of the semiconductor structure 1000 (used as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1002 of the semiconductor structure 1000 until the silicon oxide layer 1004 and the upper end of the semiconductor body 1012 of the semiconductor structure 1000 are removed.

[0254] like Figure 14DAs shown, the exposed upper end of each semiconductor body 1012 of the doped semiconductor structure 1000 (i.e., one of the two ends of the semiconductor body 1012 that is away from the semiconductor structure 1400 in the vertical direction (z-direction)) forms another source / drain 1023. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 of the semiconductor structure 1000 to form the source / drain 1023. As a result, as Figure 14D As shown, according to some embodiments, a vertical transistor having a semiconductor body 1012, source / drain electrodes 1021 and 1023, a gate dielectric 1018, and a gate electrode (a portion of the conductive layer 1020) is thus formed in the semiconductor structure 1000. As described above, as... Figure 14D As shown, according to some embodiments, capacitors each having a first electrode 1024 and a second electrode 1028 and a capacitor dielectric 1026 are also formed, and DRAM cells 1080 of semiconductor structure 1000 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are formed.

[0255] like Figure 14E As shown, an interconnect layer 1032 can be formed over the DRAM cell 1080 in the semiconductor structure 1000. The interconnect layer 1032 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1080 in the semiconductor structure 1000. In some embodiments, the interconnect layer 1032 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1032 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1004 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 14E The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1032.

[0256] like Figure 14EAs shown, a bonding layer 1036 is formed over the interconnect layer 1032 and the DRAM cell 1080 in the semiconductor structure 1000. The bonding layer 1036 may include a plurality of bonding contacts 1037 surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of the interconnect layer 1032 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be first patterned using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts 1037 that penetrate the dielectric layer and contact the interconnects in the interconnect layer 1032. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer before depositing the conductor.

[0257] Then, Figure 14E The bonding structure shown can be bonded to a semiconductor structure, including peripheral circuitry, in a face-to-face manner, as described above regarding... Figure 23 Operation 2312 and Figure 10L and Figure 10M As described in detail.

[0258] In some implementations, the second and third semiconductor structures are bonded after the first and second semiconductor structures are bonded. For example, as... Figure 23 As shown, the second semiconductor structure and the third semiconductor structure can be bonded after operation 2312 (e.g., between operation 2312 and operation 2314).

[0259] like Figure 15A As shown, in Figure 10L Following the manufacturing process shown, the bonded semiconductor structure 1500 is formed by removing the carrier substrate 1030. Any suitable manufacturing process disclosed herein (e.g., in...) can be used. Figures 10A-10H Semiconductor structure 1000 is formed individually (e.g., in parallel). For ease of description, the manufacturing processes for forming semiconductor structures 1000 and 1500 will not be repeated.

[0260] like Figure 15A As shown, the semiconductor structure 1000 is flipped vertically. (As...) Figure 15BAs shown, the downward-facing semiconductor structure 1000 is bonded to the upward-facing semiconductor structure 1500 (i.e., bonded face-to-face) using any suitable substrate / wafer bonding process, including, for example, hybrid bonding (as described in detail above), anodic bonding, and fusion (direct) bonding, thereby forming a bonding interface 1502. In one example, fusion bonding can be performed between silicon and silicon, silicon and silicon oxide, or silicon oxide and silicon oxide layers using pressure and heat. In another example, anodic bonding can be performed between silicon oxide (in ionomer glass) and silicon layers using voltage, pressure, and heat. It should be understood that, depending on the bonding process, a dielectric layer (e.g., a silicon oxide layer) can be formed on one or both sides of the bonding interface 1502. For example, a silicon oxide layer can be formed on the top surfaces of semiconductor structures 1000 and 1500 to allow for fusion-bonded SiO2-SiO2 bonding. In some embodiments, the second electrode 1028 of the semiconductor structure 1000 is in contact with the second electrode 1028 of the semiconductor structure 1500 at the bonding interface 1502, and can therefore be regarded as a common electrode (e.g., a common ground plane) for both semiconductor structures 1000 and 1500.

[0261] like Figure 15C As shown, the silicon substrate 1002 (on top of semiconductor structure 1500 after bonding) with semiconductor structure 1000 removed Figure 15B As shown), to expose the undoped upper end of the semiconductor body 1012 (which serves as the lower end before flipping). In some embodiments, a planarization process (e.g., CMP) and / or an etching process are performed to remove the silicon substrate 1002 of the semiconductor structure 1000 until the silicon oxide layer 1004 and the upper end of the semiconductor body 1012 of the semiconductor structure 1000 are removed.

[0262] like Figure 15C As shown, the exposed upper end of each semiconductor body 1012 of the doped semiconductor structure 1000 (i.e., one of the two ends of the semiconductor body 1012 that is away from the semiconductor structure 1500 in the vertical direction (z-direction)) forms another source / drain 1023. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1012 of the semiconductor structure 1000 to form the source / drain 1023. As a result, as Figure 15C As shown, according to some embodiments, a multi-gate vertical transistor having a semiconductor body 1012, source / drain electrodes 1021 and 1023, a gate dielectric 1018, and a gate electrode (a portion of the conductive layer 1020) is thus formed in the semiconductor structure 1000. As described above, as... Figure 15CAs shown, according to some embodiments, capacitors each having a first electrode 1024 and a second electrode 1028 and a capacitor dielectric 1026 are also formed, and DRAM cells 1080 of semiconductor structure 1400 each having a multi-gate vertical transistor and a capacitor coupled to the multi-gate vertical transistor are formed.

[0263] like Figure 15D As shown, an interconnect layer 1032 can be formed over the DRAM cell 1080 in the semiconductor structure 1000. The interconnect layer 1032 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1080. In some embodiments, the interconnect layer 1032 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1032 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited on the silicon oxide layer 1004 by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 15D The ILD layer and interconnect shown can be collectively referred to as interconnect layer 1032.

[0264] Then, as mentioned above... Figure 23 Operation 2314 and Figure 10M A detailed description is available at [website name]. Figure 15D The bonding structure shown in the figure has pads forming an interconnect layer.

[0265] Method 2300 can also be used through Figures 19A-19M The manufacturing process described in Figure 22 is implemented to form Figure 17 The 3D memory device 1700 depicted here has a single-gate vertical transistor instead of a multi-gate vertical transistor. (Reference) Figure 23 Method 2300 begins at operation 2302, wherein a peripheral circuit is formed on a first substrate. The first substrate may include a silicon substrate. In some embodiments, an interconnect layer is formed over the peripheral circuit. The interconnect layer may include multiple interconnects in one or more ILD layers.

[0266] like Figure 19LAs shown, a plurality of transistors 1948 are formed on a silicon substrate 1944. The transistors 1948 can be formed using a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 1944 by ion implantation and / or thermal diffusion, and these doped regions serve as, for example, the source and drain of the transistors 1948. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 1944 by wet / dry etching and thin film deposition. Peripheral circuitry 1946 can be formed on the silicon substrate 1944 for the transistors 1948.

[0267] like Figure 19L As shown, an interconnect layer 1950 can be formed over a peripheral circuit 1946 having a transistor 1948. The interconnect layer 1950 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the peripheral circuit 1946. In some embodiments, the interconnect layer 1950 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1950 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 19L The ILD layer and interconnect shown can be collectively referred to as the Interconnect Layer 1950.

[0268] Method 2300 proceeds to operation 2304, such as... Figure 23 As shown, a first bonding layer is formed above the peripheral circuitry (and interconnect layer). The first bonding layer may include first bonding contacts. Figure 19L As shown, a bonding layer 1952 is formed over interconnect layer 1950 and peripheral circuitry 1946. Bonding layer 1952 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of interconnect layer 1950 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be patterned first using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts that penetrate the dielectric layer and contact the interconnects in interconnect layer 1950. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0269] Method 2300 proceeds to operation 2306, such as... Figure 23 As shown, an array of memory cells, each comprising a vertical transistor and a memory cell, is formed on a second substrate. The second substrate may include a carrier substrate. The memory cell may include a capacitor or a PCM element. In some embodiments, the capacitor is formed as a vertical transistor coupled to the respective memory cell.

[0270] For example, Figure 25 A flowchart illustrating a method 2500 for forming another array of memory cells, each comprising a vertical transistor, according to some aspects of this disclosure is shown. Figure 25 At operation 2502, a semiconductor pillar extending vertically in the substrate is formed. The substrate may be a silicon substrate. In some embodiments, to form the semiconductor pillar, the substrate is etched in a first lateral direction to form a plurality of first trenches, a dielectric is deposited to fill the first trenches to form second trench isolation, and the substrate and second trench isolation are etched in a second lateral direction to form a plurality of second trenches and a semiconductor pillar surrounded by the second trenches and second trench isolation. In some embodiments, a dielectric is deposited to partially fill the second trenches.

[0271] like Figure 19A As shown, a plurality of parallel trenches 1904 are formed in the y-direction (e.g., the bit line direction) to form a plurality of parallel semiconductor walls 1905 in the y-direction. In some embodiments, such as based on the bit line design, a photolithography process is performed to pattern the trenches 1904 and semiconductor walls 1905 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 1904 in the silicon substrate 1902. Thus, semiconductor walls 1905 extending vertically in the silicon substrate 1902 can be formed. The bottom of the semiconductor walls 1905 may be below the top surface of the silicon substrate 1902. Since the semiconductor walls 1905 are formed by etching the silicon substrate 1902, the semiconductor walls 1905 can have the same material as the silicon substrate 1902, such as single-crystal silicon. Figure 19A A side view of a cross section along the x-direction (word line direction, e.g., in the BB plane) is shown. Figure 19A Plan view of the cross-section in the top part) and in the xy plane (e.g., in the AA plane passing through semiconductor wall 1905). Figure 19A (In the bottom part). Figure 19B The same drawing layout was also used in the middle.

[0272] like Figure 19BAs shown, trench isolation 1908 (e.g., STI) is formed in trench 1904. In some embodiments, a dielectric (e.g., silicon oxide) is deposited using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to completely fill trench 1904. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric deposited beyond the top surface of the silicon substrate 1902. As a result, parallel semiconductor walls 1905 can be separated by trench isolation 1908.

[0273] like Figure 19C As shown, a plurality of parallel trenches 1910 are formed in the x-direction (e.g., word line direction) to form an array of semiconductor pillars 1906, each extending vertically in the silicon substrate 1902. In some embodiments, such as based on word line design, a photolithography process is performed to pattern the trenches 1910 perpendicular to the trench isolation 1908 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) are performed on the silicon substrate 1902 and the trench isolation 1908 to etch the trenches 1910 in the silicon substrate 1902. As a result, semiconductor walls 1905 ( Figure 19B The semiconductor pillars (as shown) can be cut by trench 1910 to form an array of semiconductor pillars 1906, each extending vertically in the silicon substrate 1902. The bottom of the semiconductor pillars 1906 may be below the top surface of the silicon substrate 1902. Since the semiconductor pillars 1906 are formed by etching the silicon substrate 1902, the semiconductor pillars 1906 may have the same material as the silicon substrate 1902, such as single-crystal silicon. Figure 19C A side view of a cross-section along the y-direction (bitline direction, e.g., in the CC plane) is shown. Figure 19C Plan view of the cross-section in the top part) and in the xy plane (e.g., in the AA plane passing through semiconductor pillar 1906). Figure 19C (In the bottom part). Figures 19C-19G The same drawing layout was also used in the middle.

[0274] like Figure 19CAs shown, a dielectric layer 1912 is formed at the bottom of trench 1910, for example, by depositing a dielectric (e.g., silicon oxide) to partially fill trench 1910 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Deposition conditions (e.g., deposition rate and / or time) can be controlled to control the thickness of the dielectric layer 1912 and avoid completely filling trench 1910. As a result, the bottom surface of trench 1910 can be raised above the bottom surface of semiconductor pillar 1906. As shown in the plan view, two opposite sides of semiconductor pillar 1906 in the y-direction are exposed through trench 1910, and another two opposite sides of semiconductor pillar 1906 in the x-direction are in contact with trench isolation 1908. That is, semiconductor pillar 1906 is surrounded by trench 1910 and trench isolation 1908.

[0275] exist Figure 25 At operation 2504, a gate structure is formed that contacts the opposite side of the semiconductor pillar. In some embodiments, to form the gate structure, a gate dielectric is formed on the opposite side of the semiconductor pillar, and a gate electrode is formed on the gate dielectric. In some embodiments, to form the gate electrode, a conductive layer is deposited on the gate dielectric, and the conductive layer is etched back.

[0276] like Figure 19D As shown, a gate dielectric 1914 is formed over two opposite sides of the semiconductor pillar 1906 exposed from the trench 1910 in the bit line direction (y-direction). As shown in the plan view, the gate dielectric 1914 may be a portion of a continuous dielectric layer formed over the sidewalls of each row of semiconductor pillars 1906 and trench isolation 1908. In some embodiments, the gate dielectric 1914 is formed by depositing a dielectric layer (e.g., silicon oxide) over the sidewalls of the trench 1910 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) without completely filling the trench 1910. It should be understood that in some examples, the gate dielectric 1914 may not be a portion of a continuous dielectric layer. For example, wet oxidation and / or dry oxidation processes (e.g., in-situ vapor generation (ISSG) oxidation) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor pillar 1906 (e.g., single-crystal silicon) as the gate dielectric 1914.

[0277] like Figure 19DAs shown, a conductive layer 1916 is formed over a gate dielectric 1914 in trench 1910. In some embodiments, the conductive layer 1916 is formed by depositing one or more conductive materials (e.g., metals and / or metal compounds (e.g., W and TiN)) over the gate dielectric 1914 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to partially fill trench 1910. For example, a TiN layer and a W layer may be deposited sequentially to form the conductive layer 1916. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of the silicon substrate 1902.

[0278] like Figure 19E As shown, in some embodiments, the conductive layer 1916 is etched back using, for example, dry etching and / or wet etching (e.g., RIE) to form a recess, such that the upper end of the conductive layer 1916 is below the top surface of the semiconductor pillar 1906. In some embodiments, since the gate dielectric 1914 is not etched back, the upper end of the conductive layer 1916 is also below the upper end of the gate dielectric 1914, which is flush with the top surface of the semiconductor pillar 1906. As a result, the etched-back conductive layer 1916 can become word lines extending in the word line direction (x direction), and the portion of the etched-back conductive layer 1916 facing the semiconductor pillar 1906 can become a gate electrode. This allows the formation of gate structures, each including a corresponding gate dielectric 1914 on the exposed side of the semiconductor pillar 1906 and a corresponding gate electrode (i.e., a portion of the conductive layer 1916) on the gate dielectric 1914. In some embodiments, as... Figure 19E As shown, a dielectric layer 1918 is formed in the remaining space of trench 1910 and in the recess (not shown) created by etching back conductive layer 1916, for example, by depositing a dielectric (e.g., silicon oxide) using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). It should be understood that air gaps may be formed in dielectric layer 1918 depending on the word line spacing (i.e., the size of trench 1910).

[0279] exist Figure 25 At operation 2506, a first trench isolation extending vertically through the semiconductor pillar is formed to separate the semiconductor pillar into semiconductor bodies, each semiconductor body contacting a corresponding gate structure in the gate structure. In some embodiments, to form the first trench, the semiconductor pillar is etched in a second lateral direction to form a third trench, and a dielectric is deposited to fill the third trench.

[0280] like Figure 19FAs shown, a plurality of parallel trenches 1922 are formed in the x-direction (e.g., word line direction) to form an array of semiconductor bodies 1920, each extending vertically in the silicon substrate 1902. In some embodiments, a photolithography process is performed to pattern the trenches 1922 on the semiconductor pillars 1906 using an etching mask (e.g., a photoresist mask and / or a hard mask). Figure 19E As shown in the plan view, one or more dry etching and / or wet etching processes (e.g., RIE) are performed on the semiconductor pillars 1906 and trench isolation 1908 to etch the trenches 1922. The etching can be controlled such that the bottom of the trench 1922 is flush with or below the bottom surface of the semiconductor pillars 1906. As a result, each semiconductor pillar 1906 can be separated into two semiconductor bodies 1920 in the y-direction by a corresponding trench 1922. Since the semiconductor bodies 1920 are formed by etching the silicon substrate 1902, the semiconductor bodies 1920 can have the same material as the silicon substrate 1902, such as monocrystalline silicon. As shown in the plan view, each semiconductor body 1920 can contact a gate structure having a gate dielectric 1914 and a gate electrode 1916 on one side of the semiconductor body 1920 in the y-direction. The opposite sides of the semiconductor bodies 1920 can be exposed through the trench 1922. In some implementations, the two semiconductor bodies 1920 and their two gate structures are arranged in a mirror symmetry by forming a trench 1922 across the middle of the respective semiconductor pillars 1906.

[0281] like Figure 19G As shown, for example, a dielectric (e.g., silicon oxide) is deposited to fill trench 1922 by using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof), in trench 1922 ( Figure 19F Trench isolation 1926 is formed in the (shown) layer. A planarization process can be performed to remove excess dielectric above the top surface of the silicon substrate 1902. It should be understood that air gaps can be formed in the trench isolation 1926 depending on the spacing of the semiconductor bodies 1920 (i.e., the size of the trench 1922). As shown in the plan view, parallel trench isolations 1926, each extending in the x-direction, can form an array of semiconductor bodies 1920, wherein a single side contactes a gate structure having a gate dielectric 1914 and a gate electrode 1916.

[0282] exist Figure 25 At operation 2508, the first end of the doped semiconductor substrate is located away from the substrate. For example... Figure 19GAs shown, the exposed upper portion of each semiconductor body 1920 (i.e., one of the two ends of the semiconductor body 1920 away from the silicon substrate 1902 in the vertical direction (z-direction)) is doped to form a source / drain 1924. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper portion of the semiconductor body 1920 to form the source / drain 1924. In some embodiments, a silicide layer is formed on the source / drain 1924 by performing a silicide process at the exposed upper portion of the semiconductor body 1920.

[0283] exist Figure 25 At operation 2510, a memory cell is formed in contact with a semiconductor substrate (e.g., its doped first end). The memory cell may include a capacitor or a PCM element. In some embodiments, to form a memory cell that is a capacitor, a first electrode is formed on the doped first end of the semiconductor substrate, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0284] like Figure 19H As shown, for example, one or more ILD layers are formed on the top surface of a silicon substrate 1902 by depositing a dielectric material using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). A first electrode 1928, a capacitor dielectric 1930, and a second electrode 1932 are then formed in the ILD layers to form a capacitor in contact with the semiconductor body 1920. In some embodiments, each first electrode 1928 is formed on the respective source / drain 1924 (i.e., the doped upper end of the respective semiconductor body 1920) by patterning and etching electrode holes aligned with the respective source / drain 1924 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin-film deposition process. Similarly, in some embodiments, the second electrode 1932 is formed on the capacitor dielectric 1930 by patterning and etching electrode holes aligned with the respective capacitor dielectric 1930 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin-film deposition process.

[0285] exist Figure 25 At operation 2512, the substrate is thinned to expose the second end of the semiconductor body opposite the first end. For example... Figure 19I As shown, a carrier substrate 1934 (also known as a processing substrate) is bonded to the front side of a silicon substrate 1902, and a device is formed on the front side of the silicon substrate 1902 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped so that the silicon substrate 1902 is above the carrier substrate 1934.

[0286] like Figure 19J As shown, silicon substrate 1902 ( Figure 19I The thin silicon substrate 1902 is thinned to expose the undoped upper portion of the semiconductor body 1920 (which serves as the lower portion before flipping). In some embodiments, a planarization process (e.g., CMP) and / or etching process is performed on the thin silicon substrate 1902 until it is stopped by the upper portion of the dielectric layer 1918 and the semiconductor body 1920.

[0287] exist Figure 25 At operation 2514, the exposed second end of the doped semiconductor body. For example... Figure 19J As shown, the exposed upper end of each semiconductor body 1920 (i.e., one of the two ends of the semiconductor body 1920 away from the carrier substrate 1934 in the vertical direction (z-direction)) is doped to form another source / drain 1936. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 1920 to form the source / drain 1936. In some embodiments, a silicide layer is formed on the source / drain 1936 by performing a silicide process at the exposed upper end of the semiconductor body 1920. As a result, as Figure 19J As shown, according to some embodiments, a vertical transistor is thus formed having a semiconductor body 1920, source / drain electrodes 1924 and 1936, a gate dielectric 1914, and a gate electrode (a portion of the conductive layer 1916). As described above, as Figure 19J As shown, according to some embodiments, capacitors each having a first electrode 1928 and a second electrode 1932 and a capacitor dielectric 1930 are thus formed, and DRAM cells 1980 each having a single-gate vertical transistor and a capacitor coupled to the single-gate vertical transistor are thus formed.

[0288] Return to reference Figure 23 Method 2300 proceeds to operation 2308, such as... Figure 23 As shown, an interconnect layer including bit lines is formed above the memory cell array. Figure 19KAs shown, an interconnect layer 1940 can be formed above the DRAM cell 1980. The interconnect layer 1940 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 1980. In some embodiments, the interconnect layer 1940 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 1940 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 19K The ILD layer and interconnect shown can be collectively referred to as Interconnect Layer 1940.

[0289] like Figure 25 As shown, at operation 2516, bit lines are formed on the doped second end in order to form an interconnect layer. Figure 19K As shown, trenches aligned with the corresponding source / drain 1936 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin-film deposition processes to fill the trenches, forming bit lines 1938 on the source / drain 1936. As a result, bit lines 1938 and capacitors having electrodes 1928 and 1932 and a capacitor dielectric 1930 can be formed on opposite sides of the semiconductor body 1920 and coupled to opposite ends of the semiconductor body 1920. It should be understood that additional local interconnects, such as word line contacts, capacitor contacts, and bit line contacts, can also be formed similarly.

[0290] Method 2300 proceeds to operation 2310, such as... Figure 23 As shown, a second bonding layer is formed above the memory cell array and the interconnect layer. The second bonding layer may include second bonding contacts. Figure 19KAs shown, a bonding layer 1942 is formed over interconnect layer 1940 and DRAM cell 1980. Bonding layer 1942 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of interconnect layer 1940 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be patterned first using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts that penetrate the dielectric layer and contact the interconnects in interconnect layer 1940. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0291] Method 2300 proceeds to operation 2312, such as... Figure 23 As shown, the first semiconductor structure and the second semiconductor structure are bonded face-to-face, such that the first memory cell array is coupled to peripheral circuitry via the bonding interface. Bonding may include hybrid bonding. In some embodiments, after bonding, the first bonding contact and the second bonding contact contact at the bonding interface. In some embodiments, the second semiconductor structure is positioned above the first semiconductor structure after bonding. In some embodiments, the first semiconductor structure is positioned above the second semiconductor structure after bonding.

[0292] like Figure 19L As shown, the carrier substrate 1934 and the components formed thereon (e.g., DRAM cell 1980) are flipped upside down. Figure 19L As shown, the downward-facing bonding layer 1942 is bonded to the upward-facing bonding layer 1952 (i.e., face-to-face), thereby forming a bonding interface 1954. In some embodiments, a processing technique, such as plasma treatment, wet treatment, and / or heat treatment, is applied to the bonding surfaces prior to bonding. Although Figure 19L Not shown, but the silicon substrate 1944 and the components formed thereon (e.g., peripheral circuitry 1946) can be flipped upside down, and the downward-facing bonding layer 1952 can be bonded to the upward-facing bonding layer 1942 (i.e., face-to-face), thereby forming a bonding interface 1954. After bonding, the bonding contacts in the bonding layer 1942 and the bonding contacts in the bonding layer 1952 are aligned and in contact with each other, so that the DRAM cell 1980 can be electrically connected to the peripheral circuitry 1946 via the bonding interface 1954. It should be understood that in the bonded chip, the DRAM cell 1980 can be above or below the peripheral circuitry 1946. However, after bonding, the bonding interface 1954 can be formed vertically between the peripheral circuitry 1946 and the DRAM cell 1980.

[0293] Method 2300 proceeds to operation 2314, such as... Figure 23 As shown, an interconnect layer is formed on the back side of the first semiconductor structure or the second semiconductor structure, with pads leading out. Figure 19M As shown, a pad-out interconnect layer 1956 is formed on the back side of a carrier substrate 1934. The pad-out interconnect layer 1956 may include interconnects formed in one or more ILD layers, such as pad contacts 1958. The pad contacts 1958 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, after bonding, conductive material is subsequently deposited, for example by a wet / dry etching process, to form contacts 1960 extending vertically through the carrier substrate 1934. Contacts 1960 may contact the interconnects in the pad-out interconnect layer 1956. It should be understood that in some examples, the carrier substrate 1934 may be thinned or removed, for example using planarization processes and / or etching processes, after bonding and before the formation of the pad-out interconnect layer 1956 and contacts 1960.

[0294] Although not shown, it should be understood that in some examples, a pad-out interconnect layer 1956 may be formed on the back side of the silicon substrate 1944, and contacts 1960 may be formed to extend vertically through the silicon substrate 1944. Before forming the pad-out interconnect layer 1956 and contacts 1960, the silicon substrate 1944 may be thinned, for example, using planarization and / or etching processes. Although not shown, it should also be understood that in some examples, [the following applies to...] Figures 14A-14E and Figures 15A-15D The described manufacturing process is for bonding to components including those mentioned above. Figure 19A-19M An array of another DRAM cell 1980 is formed in another semiconductor structure of the semiconductor structure of the described DRAM cell 1980.

[0295] Method 2300 can also be used through Figures 22A-22M and Figure 26 The manufacturing process described herein is implemented to form Figure 21 The 3D memory device 2100 depicted here has dual-gate vertical transistors instead of a single-gate vertical transistor. (Reference) Figure 23 Method 2300 begins at operation 2302, wherein a peripheral circuit is formed on a first substrate. The first substrate may include a silicon substrate. In some embodiments, an interconnect layer is formed over the peripheral circuit. The interconnect layer may include multiple interconnects in one or more ILD layers.

[0296] like Figure 22LAs shown, a plurality of transistors 2248 are formed on a silicon substrate 2244. The transistors 2248 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 2244 by ion implantation and / or thermal diffusion, and the doped regions serve, for example, as the source and drain of the transistors 2248. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 2244 by wet / dry etching and thin film deposition. Peripheral circuitry 2246 can be formed on the silicon substrate 2244 for the transistors 2248.

[0297] like Figure 22L As shown, an interconnect layer 2250 can be formed over a peripheral circuit 2246 having a transistor 2248. The interconnect layer 2250 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the peripheral circuit 2246. In some embodiments, the interconnect layer 2250 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 2250 may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Figure 22L The ILD layer and interconnect shown can be collectively referred to as interconnect layer 2250.

[0298] Method 2300 proceeds to operation 2304, such as... Figure 23 As shown, a first bonding layer is formed above the peripheral circuitry (and interconnect layer). The first bonding layer may include first bonding contacts. Figure 22L As shown, a bonding layer 2252 is formed over interconnect layer 2250 and peripheral circuitry 2246. Bonding layer 2252 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of interconnect layer 2250 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be patterned first using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts that penetrate the dielectric layer and contact the interconnects in interconnect layer 2250. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0299] Method 2300 proceeds to operation 2306, such as... Figure 23 As shown, an array of memory cells, each comprising a vertical transistor and a memory cell, is formed on a second substrate. The second substrate may include a carrier substrate. The memory cell may include a capacitor or a PCM element. In some embodiments, the capacitor is formed as a vertical transistor coupled to the respective memory cell.

[0300] For example, Figure 26 A flowchart of a method 2600 for forming another array of memory cells, each comprising a vertical transistor, according to some aspects of this disclosure is shown. Figure 26 At operation 2602, a semiconductor body extending vertically in the substrate is formed. The substrate may be an SOI substrate, comprising a processing layer, a buried oxide layer, and a device layer. In some embodiments, to form the semiconductor body, the processing layer is etched in a first lateral direction to form a first trench, and in a second lateral direction to form a second trench, such that two opposite sides of the semiconductor body are exposed by the second trench. In some embodiments, a dielectric is deposited to partially fill the second trench.

[0301] like Figure 22A As shown, a plurality of parallel trenches 2204 are formed in the y-direction (e.g., the bit line direction) to form a plurality of parallel semiconductor walls 2205 in the y-direction. In some embodiments, such as based on the bit line design, a photolithography process is performed to pattern the trenches 2204 and semiconductor walls 2205 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 1904 in the SOI substrate 2201. Thus, semiconductor walls 1905 extending vertically in the SOI substrate 2201 can be formed. Figure 22A As shown, the SOI substrate 2201 may include a processing layer 2202, a buried oxide layer 2203 on the processing layer 2202, and a device layer 2209 on the buried oxide layer 2203. In some embodiments, the buried oxide layer 2203 comprises silicon oxide, and the device layer 2209 comprises monocrystalline silicon. In some embodiments, to form the trench 2204, the device layer 2209 is etched using RIE, stopping at the buried oxide layer 2203. That is, the buried oxide layer 2203 can be used as an etch stop layer. It should be understood that in some examples, the device layer 2209 may not be part of the SOI substrate, but may be transferred from another silicon substrate (not shown, e.g., an SOI substrate) and bonded to the buried oxide layer 2203. It should also be understood that in some examples, the SOI substrate 2201 may be replaced by a silicon substrate, for example... Figure 19AIn the silicon substrate 1902; the etching of the trench 2204 can be stopped without being stopped by the buried oxide layer 2203, but by controlling the etching rate and / or duration, for example, as Figure 19A As shown

[0302] However, the bottom of the semiconductor wall 2205 may be below the top surface of the SOI substrate 2201. Since the semiconductor wall 2205 is formed by etching the device layer 2209 of the SOI substrate 2201, the semiconductor wall 2205 may have the same material as the device layer 2209 of the SOI substrate 2201, such as single-crystal silicon. Figure 22A A side view of a cross section along the x-direction (word line direction, e.g., in the BB plane) is shown. Figure 22A Plan view of the cross-section in the top part) and in the xy plane (e.g., in the AA plane passing through semiconductor wall 2205). Figure 22A (in the bottom part).

[0303] like Figure 22B As shown, a plurality of parallel trenches 2210 are formed in the x-direction (e.g., word line direction) to form an array of semiconductor bodies 2206 that each extends vertically in the SOI substrate 2201. In some embodiments, such as based on word line design, a photolithography process is performed to pattern the trenches 2210 perpendicular to the trenches 2204 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) are performed to etch the trenches 2210 in the device layer 2209 of the SOI substrate 2201. As a result, semiconductor walls 2205 (such as...) Figure 22A (As shown) can be cut by trench 2210 to form an array of semiconductor bodies 2206, each extending vertically in the SOI substrate 2201. The bottom of the semiconductor bodies 2206 may be below the top surface of the SOI substrate 2201. Since the semiconductor bodies 2206 are formed by etching the device layer 2209 of the SOI substrate 2201, the semiconductor bodies 2206 may have the same material as the device layer 2209 of the SOI substrate 2201, such as single-crystal silicon. Figure 22B A side view of a cross-section along the y-direction (bitline direction, e.g., in the CC plane) is shown. Figure 22B Plan view of the cross-section in the top portion of the semiconductor body 2206 (e.g., in the AA plane passing through the semiconductor body 2206) and in the xy plane (e.g., in the AA plane passing through the semiconductor body 2206). Figure 22B (In the bottom part). Figures 22C-22G The same drawing layout was also used in the middle.

[0304] It should be understood that, in some examples, instead of two consecutive processes, trenches 2204 and 2210 can be formed in the same process. For example, the same photolithography process can be used to pattern trenches 2204 and 2210, followed by the same etching process. It should also be understood that, in some examples, trench 2210 can be formed in the word line direction before trench 2204 is formed in the bit line direction. However, after forming trenches 2204 and 2210, a semiconductor body 2206 can be formed, and all four sides of the semiconductor body 2206 can be exposed through trenches 2204 and 2210. In some embodiments, two opposite sides of the semiconductor body 2206 in the word line direction are exposed through trench 2204, and two opposite sides of the semiconductor body 2206 in the bit line direction are exposed through trench 2210, as shown in the plan view. That is, the semiconductor body 2206 can be surrounded by trenches 2204 and 2210.

[0305] like Figure 22C As shown, for example, a dielectric layer 2212 is formed at the bottom of trench 2210 (and in some examples, trench 2204) by depositing a dielectric (e.g., silicon oxide) to partially fill trench 2210 using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Deposition conditions (e.g., deposition rate and / or time) can be controlled to control the thickness of the dielectric layer 2212 and avoid completely filling trench 2210. As a result, the bottom surface of trench 2210 can be raised above the bottom surface of semiconductor body 2206.

[0306] exist Figure 26 At operation 2604, a gate structure is formed that contacts the opposite side of the semiconductor body. In some embodiments, to form the gate structure, a gate dielectric is formed on the opposite side of the semiconductor body, and a gate electrode is formed on the gate dielectric. In some embodiments, to form the gate electrode, a conductive layer is deposited on the gate dielectric, and the conductive layer is etched back.

[0307] like Figure 22DAs shown, a gate dielectric 2214 is formed over two opposite sides of the semiconductor body 2206 exposed from trench 2210 in the bit line direction (y-direction). As shown in the plan view, the gate dielectric 2214 may be a portion of a continuous dielectric layer formed over the sidewalls of each row of semiconductor bodies 2206. In some embodiments, the gate dielectric 2214 is formed by depositing a dielectric layer (e.g., silicon oxide) over the sidewalls and top surface of the semiconductor body 2206 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) without completely filling the trench 2210. It should be understood that in some examples, the gate dielectric 2214 may not be a portion of a continuous dielectric layer. For example, wet oxidation and / or dry oxidation processes (e.g., ISSG oxidation) are performed to form a native oxide (e.g., silicon oxide) on the semiconductor body 2206 (e.g., single-crystal silicon) as the gate dielectric 2214.

[0308] like Figure 22D As shown, a conductive layer 2216 is formed over the gate dielectric 2214. In some embodiments, the conductive layer 2216 is formed by depositing one or more conductive materials (e.g., metals and / or metal compounds (e.g., W and TiN)) over the gate dielectric 2214 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof) to partially fill the trench 2210. For example, layers of TiN and W may be deposited sequentially to form the conductive layer 2216. As shown in the side view, the conductive layer 2216 may be a continuous layer in the bit line direction, as the conductive material may be deposited over the top surface of the semiconductor body 2206 and the bottom surface of the trench 2210.

[0309] like Figure 22E As shown, in some embodiments, a portion of the conductive layer 2216 at the bottom surface of trench 2210 is removed to separate the continuous conductive layer 2216 into discrete wafers in the bit line direction, for example, by using dry etching and / or dry etching (e.g., RIE) to form a notch 2211 on the bottom surface of trench 2210. In some embodiments, a portion of the conductive layer 2216 at the top surface of semiconductor body 2206 is also removed by the same etching process to expose the gate dielectric 2214 at the top surface of semiconductor body 2206.

[0310] like Figure 22F As shown, in some embodiments, a dielectric (e.g., silicon oxide) is deposited to fill trench 2210, for example, by using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) to form trench isolation 2218 (e.g.) in trench 2210. Figure 22EAs shown in the planar view. Planarization processes (e.g., CMP and / or etching processes) can be performed to remove excess dielectric above the top surface of the semiconductor body 2206. In some embodiments, the planarization process also removes a portion of the gate dielectric 2214 above the top surface of the semiconductor body 2206 to expose the top surface of the semiconductor body 2206. It should be understood that, depending on the spacing of the semiconductor bodies 2206 (i.e., the size of the trench 2210), an air gap can be formed in the trench isolation 2218. As shown in the planar view, dielectric deposition can also fill the remaining space in the trench 2204 ( Figure 22E As shown in the diagram, isolation 2219 is formed between adjacent semiconductor bodies 2206 in the word line direction (e.g., in the same row).

[0311] like Figure 22G As shown, in some embodiments, the conductive layer 2216 is etched back using, for example, dry etching and / or wet etching (e.g., RIE) to form a recess such that the upper end of the conductive layer 2216 is below the top surface of the semiconductor body 2206. In some embodiments, since the gate dielectric 2214 is not etched back, the upper end of the conductive layer 2216 is also below the upper end of the gate dielectric 2214, which is flush with the top surface of the semiconductor body 2206. As a result, the etched-back conductive layer 2216 can become word lines extending in the word line direction (x direction), and the portion of the etched-back conductive layer 2216 facing the semiconductor body 2206 can become the gate electrode. This allows the formation of gate structures, each including a corresponding gate dielectric 2214 on two exposed opposing sides (in the bit line direction) of the semiconductor body 2206 and a corresponding gate electrode (i.e., a portion of the conductive layer 2216) on the gate dielectric 2214.

[0312] exist Figure 26 At operation 2606, the first end of the doped semiconductor substrate is located away from the substrate. For example... Figure 22G As shown, the exposed upper end (top surface) of each semiconductor body 2206 (i.e., one of the two ends of the semiconductor body 2206 away from the processing layer 2202 of the SOI substrate 2201 in the vertical direction (z-direction)) is doped to form a source / drain 2224. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 2206 to form the source / drain 2224. In some embodiments, a silicide layer is formed on the source / drain 2224 by performing a silicide process at the exposed upper end of the semiconductor body 2206.

[0313] exist Figure 26At operation 2608, a memory cell is formed in contact with a semiconductor substrate (e.g., its doped first end). The memory cell may include a capacitor or a PCM element. In some embodiments, to form a memory cell that is a capacitor, a first electrode is formed on the doped first end of the semiconductor substrate, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0314] like Figure 22H As shown, one or more ILD layers are formed on the top surface of a semiconductor body 2206, for example, by depositing a dielectric material using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). A first electrode 2228, a capacitor dielectric 2230, and a second electrode 2232 are then formed in the ILD layers to form a capacitor in contact with the semiconductor body 2206. In some embodiments, each first electrode 2228 is formed on the corresponding source / drain 2224 (i.e., the doped upper end of the corresponding semiconductor body 2206) by patterning and etching electrode holes aligned with the corresponding source / drain 2224 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin-film deposition process. Similarly, in some embodiments, the second electrode 2232 is formed on the capacitor dielectric 2230 by patterning and etching electrode holes aligned with the corresponding capacitor dielectric 2230 using photolithography and etching processes and depositing conductive material to fill the electrode holes using a thin-film deposition process.

[0315] exist Figure 26 At operation 2610, the substrate is thinned to expose the second end of the semiconductor body opposite the first end. As shown in FIG22, a carrier substrate 2234 (also referred to as a processing substrate) is bonded to the front side of the SOI substrate 2201, and a device is formed on the front side of the SOI substrate 2201 using any suitable bonding process (e.g., anodic bonding, fused bonding, transfer bonding, adhesive bonding, and eutectic bonding). The bonded structure can then be flipped over so that the processing layer 2202 of the SOI substrate 2201 is above the carrier substrate 2234.

[0316] like Figure 22J As shown, the SOI substrate 2201 is thinned to expose the undoped upper portion of the semiconductor body 2206 (which serves as the lower portion before flipping). In some embodiments, planarization processes (e.g., CMP) and / or etching processes are performed to remove the processing layer 2202 and the buried oxide layer 2203 (e.g., ...) of the SOI substrate 2201. Figure 22G (as shown), until it is stopped at the upper end of the semiconductor body 2206.

[0317] exist Figure 26At operation 2612, the exposed second end of the doped semiconductor body. For example... Figure 22J As shown, the exposed upper end of each semiconductor body 2206 (i.e., one of the two ends of the semiconductor body 2206 away from the carrier substrate 2234 in the vertical direction (z-direction)) is doped to form another source / drain 2236. In some embodiments, implantation and / or thermal diffusion processes are performed to dope P-type or N-type dopant onto the exposed upper end of the semiconductor body 2206 to form the source / drain 2236. In some embodiments, a silicide layer is formed on the source / drain 2236 by performing a silicide process at the exposed upper end of the semiconductor body 2206. As a result, as Figure 22J As shown, according to some embodiments, a vertical transistor is thus formed having a semiconductor body 2206, source / drain electrodes 2224 and 2236, a gate dielectric 2214, and a gate electrode (a portion of the conductive layer 2216). As described above, as Figure 22J As shown, according to some embodiments, capacitors each having a first electrode 2228 and a second electrode 2232 and a capacitor dielectric 2230 are thus formed, and DRAM cells 2280 each having a dual-gate vertical transistor and a capacitor coupled to the dual-gate vertical transistor are thus formed.

[0318] Return to reference Figure 23 Method 2300 proceeds to operation 2308, such as... Figure 23 As shown, an interconnect layer including bit lines is formed above the memory cell array. Figure 22K As shown, an interconnect layer 2240 can be formed above the DRAM cell 2280. The interconnect layer 2240 may include MEOL interconnects and / or BEOL interconnects in a plurality of ILD layers for electrical connection to the DRAM cell 2280. In some embodiments, the interconnect layer 2240 includes a plurality of ILD layers and interconnects formed therein using a variety of processes. For example, the interconnects in the interconnect layer 2240 may include conductive materials deposited by one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof). The manufacturing process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited using one or more thin-film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Figure 22K The ILD layer and interconnect shown can be collectively referred to as interconnect layer 2240.

[0319] like Figure 26 As shown, at operation 2614, bit lines are formed on the doped second end in order to form an interconnect layer. Figure 22KAs shown, trenches aligned with the corresponding source / drain 2236 can be patterned and etched using photolithography and etching processes, and conductive material can be deposited using thin-film deposition processes to fill the trenches, forming bit lines 2238 on the source / drain 2236. As a result, bit lines 2238 and capacitors having electrodes 2228 and 2232 and a capacitor dielectric 2230 can be formed on opposite sides of the semiconductor body 2206 and coupled to opposite ends of the semiconductor body 2206. It should be understood that additional local interconnects, such as word line contacts, capacitor contacts, and bit line contacts, can also be formed similarly.

[0320] Method 2300 proceeds to operation 2310, such as... Figure 23 As shown, a second bonding layer is formed above the memory cell array and the interconnect layer. The second bonding layer may include second bonding contacts. Figure 22K As shown, a bonding layer 2242 is formed over interconnect layer 2240 and DRAM cell 2280. Bonding layer 2242 may include a plurality of bonding contacts surrounded by a dielectric. In some embodiments, a dielectric layer (e.g., an ILD layer) is deposited on the top surface of interconnect layer 2240 using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). Then, contact holes through the dielectric layer can be patterned first using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) to form bonding contacts that penetrate the dielectric layer and contact the interconnects in interconnect layer 2240. The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer prior to depositing the conductor.

[0321] Method 2300 proceeds to operation 2312, such as... Figure 23 As shown, the first semiconductor structure and the second semiconductor structure are bonded face-to-face, such that the first memory cell array is coupled to peripheral circuitry via the bonding interface. Bonding may include hybrid bonding. In some embodiments, after bonding, the first bonding contact and the second bonding contact contact at the bonding interface. In some embodiments, the second semiconductor structure is positioned above the first semiconductor structure after bonding. In some embodiments, the first semiconductor structure is positioned above the second semiconductor structure after bonding.

[0322] like Figure 22L As shown, the carrier substrate 2234 and the components formed thereon (e.g., DRAM cell 2280) are flipped upside down. Figure 22LAs shown, the downward-facing bonding layer 2242 is bonded to the upward-facing bonding layer 2252 (i.e., bonded face-to-face), thereby forming a bonding interface 2254. In some embodiments, a processing technique, such as plasma treatment, wet treatment, and / or heat treatment, is applied to the bonding surfaces prior to bonding. Although in Figure 22L Not shown, but the silicon substrate 2244 and the components formed thereon (e.g., peripheral circuitry 2246) can be flipped ups...

Claims

1. A three-dimensional (3D) memory device, comprising: A first semiconductor structure, the first semiconductor structure including peripheral circuitry; A second semiconductor structure, the second semiconductor structure comprising: An array of memory cells, each memory cell comprising a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor; and Multiple bit lines are coupled to the memory cell and each extends in a second direction perpendicular to the first direction. The vertical transistor includes a semiconductor body extending in the first direction and a gate structure contacting two opposite sides of the semiconductor body in the second direction; and A corresponding bit line and a corresponding memory cell in the bit lines are coupled to opposite ends of each memory cell in the memory cell in the first direction; and A bonding interface is located in the first direction between the first semiconductor structure and the second semiconductor structure, wherein the memory cell array is coupled to the peripheral circuit via the bonding interface, and wherein the bit line is disposed between the vertical transistor and the bonding interface.

2. The 3D memory device according to claim 1, wherein, The vertical transistor is a dual-gate transistor, wherein the gate structure is partially external to the semiconductor body in a plan view.

3. The 3D memory device according to claim 1 or 2, wherein, The gate structure includes a gate electrode and a gate dielectric between the gate electrode and the semiconductor body in the second direction.

4. The 3D memory device according to claim 1 or 2, wherein, The second semiconductor structure also includes multiple word lines, each extending upward in a third direction perpendicular to the first direction and the second direction.

5. The 3D memory device according to claim 4, wherein, The gate dielectrics of two adjacent vertical transistors in the third direction of the vertical transistor are continuous.

6. The 3D memory device according to claim 1 or 2, wherein, The vertical transistor further includes a source and a drain respectively disposed at two ends of the semiconductor body in the first direction.

7. The 3D memory device according to claim 6, wherein, One of the source and drain of the vertical transistor is coupled to the memory cell in the corresponding memory cell.

8. The 3D memory device according to claim 7, wherein, The source and drain of the vertical transistor are coupled to the corresponding bit line.

9. The 3D memory device according to claim 1 or 2, wherein, The second semiconductor structure further includes a pad-out interconnect layer; and The storage cell is disposed between the vertical transistor and the pad-out interconnect layer.

10. The 3D memory device according to claim 1 or 2, wherein, The first semiconductor structure further includes a pad-out interconnect layer; and The peripheral circuitry is disposed between the bonding interface and the interconnect layer with the pads.

11. A memory system, comprising: A memory device configured to store data, and comprising: A first semiconductor structure, the first semiconductor structure including peripheral circuitry; A second semiconductor structure, the second semiconductor structure comprising: An array of memory cells, each memory cell comprising a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor; and Multiple bit lines are coupled to the memory cell and each extends in a second direction perpendicular to the first direction. The vertical transistor includes a semiconductor body extending in the first direction and a gate structure contacting two opposite sides of the semiconductor body in the second direction; and A corresponding bit line and a corresponding memory cell in the bit lines are coupled to opposite ends of each memory cell in the memory cell in the first direction; and A bonding interface is located in the first direction between the first semiconductor structure and the second semiconductor structure, wherein the memory cell array is coupled to the peripheral circuit via the bonding interface, and wherein the bit line is disposed between the vertical transistor and the bonding interface; and A memory controller coupled to the memory device and configured to control the memory cell array via the peripheral circuitry and the bit lines.

12. The memory system of claim 11, further comprising a host coupled to the memory controller and configured to send the data to or receive the data from the memory device.

13. The memory system according to claim 11 or 12, wherein, The memory unit includes at least a dynamic random access memory (DRAM) unit, a phase change memory (PCM) unit, or a ferroelectric RAM (FRAM) unit.

14. A method for forming a three-dimensional (3D) memory device, comprising: Forming a first semiconductor structure including peripheral circuitry; Forming a second semiconductor structure includes: Forming a memory cell array, each memory cell comprising a vertical transistor extending in a first direction and a memory cell coupled to the vertical transistor; and Multiple bit lines are formed, which are coupled to the memory cell and each extends in a second direction perpendicular to the first direction. The vertical transistor includes a semiconductor body extending in the first direction and a gate structure contacting two opposite sides of the semiconductor body in the second direction; and A corresponding bit line and a corresponding memory cell in the bit lines are coupled to opposite ends of each memory cell in the memory cell in the first direction; and The first semiconductor structure and the second semiconductor structure are bonded face-to-face, such that the memory cell array is coupled to the peripheral circuit through the bonding interface, and the bit line is positioned between the vertical transistor and the bonding interface.

15. The method of claim 14, further comprising, after the bonding, forming a pad-out interconnect layer on the back side of the first semiconductor structure or the second semiconductor structure.

16. The method according to claim 14 or 15, wherein, The bonding includes hybrid bonding.

17. The method according to claim 14 or 15, wherein, Forming the memory cell array includes: A vertically extending semiconductor body is formed in the substrate; A gate structure is formed that contacts two opposite sides of the semiconductor body; and A memory cell is formed in contact with the semiconductor body.

18. The method according to claim 17, wherein, The substrate includes a silicon-on-insulator (SOI) substrate, which includes a processing layer, a buried oxide layer, and a device layer. and The semiconductor body comprises: The processing layer is etched in the first lateral direction to form a first trench; as well as The processing layer is etched in the second lateral direction to form a second trench, such that the two opposite sides of the semiconductor body are exposed by the second trench.

19. The method according to claim 18, wherein, Forming the semiconductor body also includes depositing a dielectric to partially fill the second trench.

20. The method of claim 17, wherein, Forming the gate structure includes: A gate dielectric is formed on the two opposite sides of the semiconductor body; and A gate electrode is formed on the gate dielectric.

21. The method according to claim 20, wherein, Forming the gate electrode includes: A conductive layer is deposited on the gate dielectric; and The conductive layer is etched back.

22. The method according to claim 17, wherein, Forming the memory cell array includes: Doping the first end of the semiconductor body away from the substrate before forming the memory cell; After forming the memory cell, the substrate is thinned to expose a second end of the semiconductor body opposite the first end; and The exposed second end of the doped semiconductor body.

23. The method according to claim 22, wherein, The storage unit comprises: A first electrode is formed on the doped first end of the semiconductor body; A capacitor dielectric is formed on the first electrode; and A second electrode is formed on the capacitor dielectric.

24. The method according to claim 22, wherein, Forming the bit line includes forming a corresponding bit line on the doped second end of the semiconductor body.

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