Artificial intelligence storage system

Abstract

This invention relates to an artificial intelligence storage system. A string comprises multiple sets of transistor pairs connected in parallel between a source line and a bit line, with each set containing a pair of source-interconnected storage transistors. The sources of both storage transistors in each set are connected to the source line, and the drains of both storage transistors are connected to the bit line. Multiple strings are mapped to multiple weight value carriers of a neural network. The input data for each set of transistor pairs in each string is refreshed periodically. In consecutively numbered sets of transistor pairs, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the adjacent numbered transistor pairs of that set are locked for one refresh cycle during the periodic refresh of the input data, and unlocked after the locking ends to begin the next round of input data refresh.

Description

Technical Field

[0001] This invention primarily relates to the field of data storage technology, and more specifically, to an artificial intelligence storage system that combines artificial intelligence technology with storage technology in the field of data storage and computing. Background Technology

[0002] Artificial intelligence (AI) is gradually becoming widespread in various electronic products. In-memory computing (IMC), which combines AI with storage, is a relatively new direction in AI. While it utilizes storage media for computation, the media model still requires further exploration. Flash memory, as a crucial medium for IMC, allows for the independent operation of its internal cells as discrete electronic devices. Furthermore, it enables the integration of flash memory cells and processors onto the same chip, offering flexibility that perfectly suits the needs of various electronic products with AI capabilities, especially edge computing. As an IMC technology, the key challenge lies in building high-cell-density storage systems that can accurately achieve high-precision neural network calculations. Summary of the Invention

[0003] This application relates to an artificial intelligence storage system (or storage device or storage apparatus), comprising: Multiple strings are arranged in parallel; each string is configured with a source line and a bit line. A single string contains multiple pairs of transistors connected in parallel between the source line and the bit line. Each pair of transistors contains a pair of memory transistors with source interconnection. The sources of the two memory transistors in each pair are connected to the source line and the drains of the two memory transistors are connected to the bit line. Multiple strings are mapped to multiple columns of weight value carriers of a neural network. The weight value represented by each memory transistor is adjusted by the threshold voltage of each memory transistor. Each pair of transistors in each string is assigned a number in sequence. The input data sent to each string by the neural network is input to the gate of each storage transistor in the string in the form of pulse signals. The output data of the neural network at the string is obtained by collecting the source line charge of the string. The input data of each pair of transistors in each string is refreshed periodically. In a pair of transistors with consecutive numbers, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the other transistor pairs with adjacent numbers in the pair of transistors will be locked for one refresh cycle during the periodic refresh of the input data. After the locking is completed, they will be unlocked to enter the next round of input data refresh.

[0004] In the aforementioned artificial intelligence storage system, the other transistors are adjacent transistor pairs numbered before the array of transistor pairs, or adjacent transistor pairs numbered after the array of transistor pairs, or adjacent transistor pairs numbered before and after the array of transistor pairs.

[0005] In the aforementioned artificial intelligence storage system, for a neural network mapped from multiple strings, each storage transistor adjusts the size of the input data for each storage transistor by changing the pulse width of the pulse signal input to its gate.

[0006] In the aforementioned artificial intelligence storage system, during the latching period of a refresh cycle, the gates of other transistor pairs with adjacent numbering in the array transistor pair are clamped at the level corresponding to the ineffective pulse that is opposite to the effective pulse.

[0007] In the aforementioned artificial intelligence storage system, during the period when the other transistor pairs of adjacent numbered array transistor pairs are latched up for a refresh cycle, their threshold voltages are modulated to a state that is larger than the threshold voltage during the unlocking period.

[0008] In the aforementioned artificial intelligence storage system, during the period when the array of transistor pairs is locked for a refresh cycle, the weight values ​​of other adjacent numbered transistor pairs are adjusted to a lower state than the weight values ​​during the unlocking period.

[0009] In the aforementioned artificial intelligence storage system, during the latching period of a refresh cycle, the total charge output by other adjacent numbered transistor pairs of the array transistor pair to the source line of the corresponding string is clamped to a lower value than the total charge output by the array transistor pair to the source line of the corresponding string.

[0010] In the aforementioned artificial intelligence storage system, each of the multiple parallel strings defines its own array of transistor pairs, and the numbering segment of the transistor pairs in any string is the same as the numbering segment of the transistor pairs in other dissimilar strings. This array of transistor pairs can also be defined or referred to as a specified array of transistor pairs.

[0011] This application relates to an artificial intelligence storage system (or storage device or storage apparatus), comprising: Multiple strings are arranged in parallel; each string is configured with a source line and a bit line. A single string contains multiple pairs of transistors connected in parallel between the source line and the bit line. Each pair of transistors contains a pair of memory transistors with source interconnection. The sources of the two memory transistors in each pair are connected to the source line and the drains of the two memory transistors are connected to the bit line. Multiple strings are mapped to multiple weight value carriers of a neural network. The weight represented by each memory transistor is adjusted by the threshold voltage of each memory transistor. Each pair of transistors in each string is assigned a number in sequence. The input data sent to each string by the neural network is input to the gate of each storage transistor in the string in the form of pulse signals. The output data of the neural network at the string is obtained by collecting the source line charge of the string. The input data of each pair of transistors in each string is refreshed periodically. In the array of consecutively numbered transistor pairs, if the difference between the effective pulse duration of the previous cycle and the effective pulse duration of the next cycle of any storage transistor in the array exceeds a predetermined value, then the other transistor pairs with adjacent numbers in the array will clamp their gates to an ineffective pulse during the periodic refresh of the input data, interrupting one refresh cycle. After the interruption, the gate potential clamping is released to enter the next round of input data refresh.

[0012] In the aforementioned artificial intelligence storage system, each of the multiple parallel strings defines its own array of transistor pairs. The numbering segment of the array of transistor pairs in any string is the same as the numbering segment of the array of transistor pairs in other dissimilar strings. As a result, the weight level of the array of transistor pairs in each string takes precedence over the weight level of the remaining transistor pairs in the entire weight matrix of the neural network.

[0013] In the aforementioned artificial intelligence storage system, the other transistors are adjacent transistor pairs numbered before the array of transistor pairs, or adjacent transistor pairs numbered after the array of transistor pairs, or adjacent transistor pairs numbered before and after the array of transistor pairs.

[0014] In the aforementioned artificial intelligence storage system, for a neural network mapped from multiple strings, each storage transistor adjusts the size of the input data for each storage transistor by changing the pulse width of the pulse signal input to its gate.

[0015] In the aforementioned AI-powered storage system, during the latching period of a refresh cycle, the total charge output by the other transistor pairs to the source lines of the corresponding string is clamped to a lower level than the total charge output by the array of transistor pairs to the source lines of the corresponding string. This array of transistor pairs can also be defined or referred to as a designated array of transistor pairs.

[0016] This application also relates to an in-memory computing method for artificial intelligence, including: It provides multiple parallel strings, each configured with a source line and a bit line; A single string contains multiple pairs of transistors connected in parallel between the source line and the bit line, and each pair of transistors contains a pair of source-interconnected memory transistors. The sources of the two memory transistors in each pair of transistors are connected to the source line of the single string, and the drains of the two memory transistors are connected to the bit line of the single string. Multiple strings are mapped to multiple columns of weight value carriers of a neural network. The weight value represented by each memory transistor is adjusted by the threshold voltage of each memory transistor. Each pair of transistors in each string is assigned a number in sequence. Strings are used to perform operations on input data and produce output data for the neural network. The input data sent to each string is transmitted to the gate of each storage transistor in the string in the form of pulse signals. The output data of the neural network at the string is obtained by collecting the source line charge of the string. The input data of each pair of transistors in each string is refreshed periodically. In consecutively numbered pairs of transistors, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the other transistor pairs with adjacent numbers in the pair of transistors are locked for one refresh cycle during the periodic refresh of the input data. After the locking is completed, they are unlocked to enter the next round of input data refresh.

[0017] In the aforementioned in-memory computing method for artificial intelligence, the other transistors are either adjacent transistor pairs numbered before the array of transistor pairs, or adjacent transistor pairs numbered after the array of transistor pairs, or adjacent transistor pairs numbered before and after the array of transistor pairs.

[0018] The aforementioned in-memory computing method for artificial intelligence targets a neural network mapped from multiple strings. Each storage transistor adjusts the size of its input data by changing the pulse width of the pulse signal input to its gate.

[0019] In the aforementioned in-memory computing method for artificial intelligence, during the latching period of a refresh cycle, the gates of the other transistor pairs are clamped at the level corresponding to the ineffective pulse that is opposite to the effective pulse.

[0020] In the aforementioned in-memory computing method for artificial intelligence, the threshold voltages of the other transistor pairs are modulated to a state that is larger than the threshold voltages during the unlocking period during a latching refresh cycle.

[0021] In the aforementioned in-memory computing method for artificial intelligence, the weight values ​​of the other transistor pairs are adjusted to a lower state than the weight values ​​during the unlocking period, during which the transistor pairs are locked for a refresh cycle.

[0022] In the aforementioned in-memory computing method for artificial intelligence, during the period when the other transistor pairs are locked for a refresh cycle, the total charge output by them to the source lines of the corresponding string is clamped to a level lower than the total charge output by the array of transistor pairs to the source lines of the corresponding string.

[0023] The aforementioned in-memory computing method for artificial intelligence defines a transistor array pair in each of several parallel strings. The numbering segment of the transistor array pair in any string is the same as the numbering segment of the transistor array pair in other dissimilar strings. This transistor array pair can also be defined or referred to as a specified transistor array pair.

[0024] The implementation basis of the artificial intelligence storage system in this application is a memory with storage transistors. The memory can be based on flash memory such as NOR-FLASH. The flash memory with computing capabilities is converted into flash memory cells. When the memory cells are discrete components, they can cooperate with an external processor to coordinate the processor to perform neural network acceleration calculations. The advantage of memory cells as discrete components is that they can flexibly expand the matrix size, for example, by expanding in two-dimensional planes similar to chips or in three-dimensional vertical directions to adapt to the required computing scale. In addition, non-discrete flash memory can also be integrated with the processor into a single multi-functional integrated chip. These adaptability of the memory provide easily cut or expandable neural network weight matrices for artificial intelligence in storage computing functions. Using common-source transistor pairs as basic controlled unit cells to operate the computing process, the source current is easily affected by unwanted charges at high cell densities. This application takes into account both the high computing power requirements brought about by high cell density and the problem of miscalculation caused by negative charges. Attached Figure Description

[0025] To make the objectives, features, and advantages described above more easily understood, the following detailed description of specific embodiments is provided in conjunction with the accompanying drawings. After reading the following description and referring to the accompanying drawings, the features and advantages of this application will become apparent.

[0026] Figure 1 It consists of multiple parallel strings, each of which is configured with a source line and a bit line.

[0027] Figure 2 A single string consists of multiple pairs of transistors connected in parallel between the source line and the bit line.

[0028] Figure 3 The input data of each pair of transistors in each string is refreshed periodically.

[0029] Figure 4 Some of the storage transistors are latched up during the periodic refresh of the input data.

[0030] Figure 5This means that the total amount of charge output from the source line by a portion of the storage transistor is clamped. Detailed Implementation

[0031] The technical solutions disclosed in this application will be clearly and completely described below with reference to specific embodiments. However, the described embodiments are only the embodiments used for description and illustration in this application and not all of the embodiments.

[0032] See Figure 1 This application will now be explained based on the illustrated NOR flash memory array. The principle involves forming a floating gate, capable of storing charges such as electrons, between the source (S) and drain (D) of the storage transistor and on the semiconductor in the current conduction path. The floating gate is encased within a silicon oxide insulator. Above the floating gate is a select / control gate that controls the conduction current between the source and drain. The charges, such as electrons, in the floating gate do not disappear when power is lost, making flash memory a non-volatile memory. A write operation involves applying a positive voltage to the control gate, causing charges, such as electrons, to pass through the insulating layer into the floating gate. An erase operation is the opposite; applying a positive voltage to the substrate causes electrons to be extracted from the floating gate, thus erasing the data. Data operations in flash memory are prior art and will not be described separately here.

[0033] See Figure 1 In the multiple parallel strings, the first string is configured with source line S1 and bit line B1, the second string is configured with source line S2 and bit line B2, and the third string is also configured with source line S3 and bit line B3 (not shown). Other strings not shown will not be detailed here. We will use the first string as an example for explanation, and the other strings can be deduced similarly.

[0034] See Figure 1 The first string comprises transistor pairs T11 and T12, transistor pairs T13 and T14, transistor pairs T15 and T16, and transistor pairs T17 and T18. All other transistor pairs in this first string (not shown) are connected in parallel. The drain of each memory transistor in this first string is coupled to bit line B1, and the source of each memory transistor in this first string is coupled to source line S1. Further details regarding the other transistor pairs in the first string are omitted.

[0035] See Figure 1See the first pair of transistors: In the first pair of transistors T11 and T12, the drain of transistor T12 is coupled to the bit line B1 of the string, and the source of transistor T12 is coupled to the source line S1 of the string; the drain of transistor T11 is coupled to the bit line B1 of the string, and the source of transistor T11 is coupled to the source line S1 of the string. Based on the requirements for manufacturing high-density transistor cells, the first pair of transistors T11 and T12 can share a source. This can be achieved by designing them to share the same source doping region during transistor manufacturing. Another important factor in arranging transistor pairs is that when transistors or strings of transistors are mapped to the weights of a neural network, it becomes difficult to control the weight matrix once the neural network becomes very large. This is because each transistor affects the charge and current on the source line. Negative currents or charges can easily cause large errors in the output of the neural network. Folding a large number of transistors into pairs makes them easier to control, as will be explained later.

[0036] See Figure 1 See the second pair of transistors: In the second pair of transistors T13 and T14, the drain of transistor T14 is coupled to the bit line B1 of the string, and the source of transistor T14 is coupled to the source line S1 of the string; the drain of transistor T13 is coupled to the bit line B1 of the string, and the source of transistor T13 is coupled to the source line S1 of the string. Similar to what was mentioned earlier, the second pair of transistors T13 and T14 here can also share a common source.

[0037] See Figure 1 See the third transistor pair: In the third transistor pair T15 and T16, the drain of transistor T16 is coupled to the bit line B1 of the string, and the source of transistor T16 is coupled to the source line S1 of the string; the drain of transistor T15 is coupled to the bit line B1 of the string, and the source of transistor T15 is coupled to the source line S1 of the string. Similar to what was mentioned earlier, the third transistor pair T15 and T16 here can also share a common source.

[0038] See Figure 1 See the fourth transistor pair: In the fourth transistor pair T17 and T18, the drain of transistor T18 is coupled to the bit line B1 of the string, and the source of transistor T18 is coupled to the source line S1 of the string; the drain of transistor T17 is coupled to the bit line B1 of the string, and the source of transistor T17 is coupled to the source line S1 of the string. Similar to what was mentioned earlier, the fourth transistor pair T17 and T18 here can also share a common source.

[0039] See Figure 1For the first string, all storage transistors in the first to fourth or more transistor pairs are connected in parallel, and are all connected in parallel between bit line B1 and source line S1. Therefore, the multiple transistor pairs contained in a string are configured to be connected in parallel, and the drain of each storage transistor in the string is coupled to the bit line of the string, and the source of each storage transistor in the string is coupled to the source line of the string.

[0040] See Figure 1 In an optional embodiment, the artificial intelligence storage system includes multiple strings arranged in parallel, each string also having a source line and a bit line; a single string contains multiple pairs of transistors connected in parallel between the source line and the bit line, and each pair of transistors contains a pair of source-interconnected storage transistors, the sources of the two storage transistors in each pair of transistors being connected to the source line of the single string and the drains of the two storage transistors being connected to the bit line of the single string.

[0041] See Figure 1 For example, the first string contains multiple sets of transistor pairs connected in parallel between the source line S1 and the bit line B1, and each set of transistor pairs contains a pair of source-interconnected memory transistors: such as the first to fourth sets of transistor pairs connected in parallel, and the first set of transistor pairs containing a pair of source-interconnected memory transistors T11 and T12, the second set of transistor pairs connected in parallel with the first set of transistor pairs containing a pair of source-interconnected memory transistors T13 and T14, the third set of transistor pairs connected in parallel with the first set of transistor pairs containing a pair of source-interconnected memory transistors T15 and T16, the fourth set of transistor pairs connected in parallel with the first set of transistor pairs containing a pair of source-interconnected memory transistors T17 and T18, and so on.

[0042] See Figure 1 In the first transistor pair of the first string, the sources of the two storage transistors T11 and T12 are both connected to the same source line S1 of the first string, and the drains of the two storage transistors T11 and T12 are both connected to the same bit line B1 of the first string. Similarly, in the second transistor pair, the sources of the two storage transistors T13 and T14 are both connected to the same source line S1 of the first string, and the drains of the two storage transistors T13 and T14 are both connected to the same bit line B1 of the first string. The second and fourth transistor pairs follow the same procedure and will not be described further.

[0043] See Figure 1The first string containing source line S1 and bit line B1, the second string containing source line S2 and bit line B2, and the third, fourth, and other strings (not shown) are collectively mapped to multiple columns of weight values ​​for the neural network. The first string is mapped to the first column of weight values ​​for the neural network, the second string to the second column, and so on. Thus, multiple strings are mapped to multiple columns of weight values ​​for the neural network. Furthermore, the weight value represented by each storage transistor is adjusted by the threshold voltage of each storage transistor, which will be further explained below.

[0044] See Figure 1 Each pair of transistors in each string is assigned a number sequentially. Taking the first string as an example, transistor pairs T11 and T12 are assigned a number, either 1 or N1, and transistor pairs T13 and T14 are also assigned a number, either 2 or N2. Similarly, transistor pairs T15 and T16 are assigned a number, either 3 or N3, and transistor pairs T17 and T18 are assigned a number, either 4 or N4.

[0045] See Figure 1 Assume the second string contains transistors T21 through T28. Taking this second string as an example, transistors T21 and T22 are sequentially assigned a number (either 1 or N1), and transistors T23 and T24 are sequentially assigned a number (either 2 or N2). Similarly, transistors T25 and T26 are sequentially assigned a number (either 3 or N3), and transistors T27 and T28 are sequentially assigned a number (either 4 or N4).

[0046] See Figure 2 In an optional embodiment, the input data of the neural network to each string is input as pulse signals to the gates of each storage transistor in the string, and the output data of the neural network at the string is obtained by collecting the source line charge of the string. Taking the first string as an example: the input data of the neural network to the first string is input as pulse signals to the gates of each storage transistor T11 to T18 in the first string, and the output data of the neural network at the first string is obtained by collecting the source line charge, i.e., the S1 charge, of the first string. Taking transistors T21-T28, etc. (not shown) in the second string as another example: the input data of the neural network to the second string is input as pulse signals to the gates of each storage transistor T21 to T28 in the second string, and the output data of the neural network at the second string is obtained by collecting the source line charge, i.e., the S2 charge, of the second string.

[0047] See Figure 2 In an optional embodiment, the input data of each pair of transistors in each string is refreshed periodically. For example, the input data of each pair of transistors T11-T12, T13-T14, T15-T16, T17-T18, etc., in the first string is refreshed periodically. Taking transistor pairs T13-T14 and T15-T16 as an example, the data refresh is explained. In the two adjacent refresh cycles shown in the figure, storage transistors T13 and T14 input data once in cycle Tim1, and in the next adjacent cycle, storage transistors T13 and T14 input data again in cycle Tim2. Again, in these two adjacent refresh cycles, storage transistors T15 and T16 input data once in cycle Tim1, and in the next adjacent cycle, storage transistors T15 and T16 input data again in cycle Tim2. Besides the two adjacent refresh cycles shown, there are many more data refresh cycles not all shown in the figure.

[0048] See Figure 2 In an optional embodiment, the input data fed to each string by the neural network is fed to the gate of each storage transistor in the string in the form of a pulse signal. For example, the input data fed to the first string is fed to the gate of each storage transistor in the first string in the form of a pulse signal. Storage transistors T13-T14 and T15-T16 are used as examples to illustrate the input data being fed to the first string in the form of a pulse signal.

[0049] See Figure 2 In an optional embodiment, input data to storage transistor T13 is input as a pulse signal to the gate of storage transistor T13, for example, G3; input data to storage transistor T14 is input as a pulse signal to the gate of storage transistor T14, for example, G4; input data to storage transistor T15 is input as a pulse signal to the gate of storage transistor T15, for example, G5; and input data to storage transistor T16 is input as a pulse signal to the gate of storage transistor T16, for example, G6. The same applies to other storage transistors. Typically, the width of the effective pulse of the pulse signal, such as the width of the high level, determines the size of the input data. Typically, the ineffective pulse of the pulse signal, such as the low level, often determines the off-time of the storage transistor.

[0050] See Figure 3In an optional embodiment, the size of the input data of the storage transistor T13 is adjusted by changing the pulse width of the pulse signal input to the gate, such as G3. In the figure, the wider the pulse width received by the gate G3 in Tim1, the larger the input data input to the storage transistor T13 in Tim1, and vice versa. Figure 3 The pulse width received by the middle gate G3 is compared to Figure 2 The pulse width is much wider, so the input data is more... Figure 2 It should also be bigger.

[0051] See Figure 3 In an optional embodiment, the size of the input data of the storage transistor T14 is adjusted by changing the pulse width of the pulse signal input to the gate, such as G4. In the figure, the wider the pulse width received by the gate G4 in Tim2, the larger the input data input to the storage transistor T14 in Tim2, and vice versa. Figure 3 The pulse width received by the middle gate G4 is compared to Figure 2 The pulse width is much wider, so the input data is more... Figure 2 It should also be bigger.

[0052] See Figure 3 In an optional embodiment, the size of the input data of the storage transistor T15 is adjusted by changing the pulse width of the pulse signal input to the gate, such as G5. In the figure, the wider the pulse width received by the gate G5 in Tim2, the larger the input data input to the storage transistor T15 in Tim2, and vice versa. Figure 3 The pulse width received by the middle gate G5 is compared to Figure 2 The pulse width is much wider, so the input data is more... Figure 2 It should also be bigger.

[0053] See Figure 3 In an optional embodiment, the size of the input data of the storage transistor T16 is adjusted by changing the pulse width of the pulse signal input to the gate, such as G6. In the figure, the wider the pulse width received by the gate G6 in Tim1, the larger the input data input to the storage transistor T16 in Tim1, and vice versa. Figure 3 The pulse width received by the middle gate G6 is compared to Figure 2 The pulse width is much wider, so the input data is more... Figure 2It should also be bigger.

[0054] See Figure 4 The input data of each pair of transistors in each string is refreshed periodically: In a pair of transistors with consecutive numbers, if the difference between the effective pulse duration of the previous cycle and the effective pulse duration of the next cycle of any storage transistor in the pair exceeds a predetermined value, then the other transistor pairs with adjacent numbers in the pair will be locked for one refresh cycle, for example, skip one cycle, during the periodic refresh of the input data, and will be unlocked after the locking is completed to enter the next round of input data refresh.

[0055] See Figure 4 In the first string, transistor group N1, whose input data for transistors T11 and T12 is known, needs to be refreshed periodically. Similarly, transistor group N2, whose input data for transistors T13 and T14 is refreshed periodically. The same applies to transistor group N3, whose input data for transistors T15 and T16 is refreshed periodically. Similarly, transistor group N4, whose input data for transistors T17 and T18 is refreshed periodically. Regarding consecutively numbered transistor pairs: Note that consecutively numbered transistor pairs here means that the numbering is not interrupted, for example, N1-N4 is consecutive and N2-N3 is consecutive; however, if one or more numbers in between are not included, it is not considered consecutive. For example, N1-N2 and N4 are clearly no longer consecutive because N3 is not included. Since N2 is not included in the calculation, N3-N4 and N1 are clearly no longer considered consecutive.

[0056] See Figure 4A sequence of consecutive transistor pairs is defined as consecutively numbered arrays of transistors. For example, the second and third transistor pairs are two consecutive pairs numbered N2-N3; similarly, the second to fourth transistor pairs are three consecutive pairs numbered N2-N4. We will use the second and third transistor pairs as an example. In many applications of neural networks, high-priority processing regions of the weight matrix are involved. Consecutive arrays of transistors can be considered high-priority processing regions within the entire weight matrix. For instance, in deep learning, image processing, and machine vision, the Region of Interest (ROI) can be mapped to the corresponding weights of consecutively numbered arrays of transistors within the entire weight matrix. The role of consecutively numbered arrays of transistors is not limited to this. For example, in matrix filling scenarios, the weight values ​​corresponding to consecutively numbered arrays of transistors can also be considered elements at valid positions rather than missing elements. This example is an important application of neural networks in accelerating computation.

[0057] See Figure 4 The transistor-string is mapped to a series of weights in the neural network, and the weights are determined by the threshold voltage V of the storage transistor. TH To adjust. Multiple strings arranged in parallel can form multiple weight carriers, and neural networks are typically configured with multiple weights. For memory transistors, the gate controls whether the memory transistor is turned on or off, while the floating gate stores charge. Since a memory transistor maps to a weight carrier in a neural network, the high degree of adjustment of the charge storage scale provides flexibility for weight programming, which requires significant variations in neural network configuration. Threshold voltage V TH The adjustments are described below.

[0058] See Figure 4 The string can use gates G1-GN as inputs and source line S1 as output. Figure 1 Flash memory is considered the physical carrier for implementing weights in neural networks. To illustrate the specific implementation process, a matrix Max with N elements (N storage transistors) can be designed to associate with the flash memory. The gates G1-GN of each storage transistor in a single string serve as an input example; other strings not shown can be deduced similarly. N=8 is the embodiment shown in the figure, but in actual production, N far exceeds the example of 8; the specific value here is not a limitation.

[0059] See Figure 4The inputs to gates G1-GN are represented by the vector Max_in = [I1*t1, I2*t2, ..., IN*tn]. For ease of representation, the input values ​​of gate G1 are mapped to I1*t1 = X1, the input values ​​of gate G2 are mapped to I2*t2 = X2, and similarly, the input values ​​of gate G3 are mapped to I3*t3 = X3, and the input values ​​of gate GN are mapped to IN*tn = X1. N The output current or sink current obtained from the source line of the string is IS1. The current of T1N is injected into the source line S1 in pulse form for a time of tn, that is, the current IN is injected during the time period tn. The current of T11 is injected into the source line S1 in pulse form for a time of t1, that is, the current I1 is injected during the time period t1. The current of T12 is injected into the source line S1 in pulse form for a time of t2, that is, the current I2 is injected during the time period t2. The current of T13 is similarly injected into the source line S1 in pulse form for a time of t3, that is, the current I3 is injected during the time period t3. A pulse signal is applied to the gate or word line, and the effective width of the pulse is time t, which is also the effective pulse duration. The t of each transistor can be the same or different.

[0060] See Figure 4 The output of source line S1 is represented by the vector Max_out=[QIS1]. For ease of expression, the output of the source line needs to be mapped to Y1. QIS1 is the charge or quantity gained by source line S1 under the current IS1 condition. Assuming there are multiple strings, such as the Mth string, QISM is the charge or quantity gained by source line SM under the current ISM condition. For example, IS1 charges the unshown capacitor of the source line to gain charge, and ISM charges the capacitor at the source line SM to gain charge. The currents of the strings from the first storage transistor to the Nth transistor T11-T1N are I1 to IN respectively. Due to the current collection characteristics of the source line, the total current IS1 on source line S1 is the sum of I1 to IN. M=1 and M=2 are examples as shown in the figure, but in actual production, M is much larger than the example of 2. The specific values ​​shown here do not constitute a limitation.

[0061] See Figure 4 This example uses vector-matrix multiplication to demonstrate the general operation process involving arrays. The principle of vector-matrix representation of flash memory performing local data processing in a neural network is roughly as follows. Combined with... Figures 1 to 3 .

[0062] See Figure 4 Predetermine X1 to X NY1 represents the input layer of the neural network (the input is a pulse signal delivered from the control gate of each storage transistor in each string), and Y2 represents the relative output layer of the neural network (the output data at the source line of the string is extracted by collecting the charge of the source line of the storage transistor in each string). Thus, the flash memory completes a complete vector operation from the input layer to the output layer. This is significantly different from the operation of a traditional von Neumann computer, because this operation only requires measuring the charge of each source line S1 (or other SMs). Individual multiplications and additions do not need to be performed individually, and the final result can be fully represented from the charge of the source line S1 (or other SMs) at once, hence the term analog computation. Von Neumann performs multiplications and additions individually, which cannot be performed all at once. If multiple strings are arranged side-by-side, the matrix Max is multi-row and multi-column instead of a single row, and the output is also multi-row instead of a single row. For example, in this case, the relative output layer of the neural network in the figure is Y1 to Y2. N In other words, multiple strings are used to represent multiple output layers.

[0063] See Figure 4 For matrix Max, the gate of the first storage transistor in the string is connected to G1, the gate of the second storage transistor in the string is connected to G2, and the gate of the Nth storage transistor in the string is connected to GN. The transistors in the string are mapped to weights T11-T1N in the weight matrix, denoted as W. 11 W 12 W 13 、......W 1N The transistors in the first string are labeled T11-T18 and their respective weights are W. 11 W 12 W 13 ...W 18 Therefore, each storage transistor is configured with a corresponding weight value that contributes to the matrix Max participating in the neural network.

[0064] See Figure 4 This explains the relationship between the current, threshold voltage, and applied voltage of a storage transistor. The transistor threshold voltage is V. TH The process parameter K=μCW / L, which is related to the manufacturing process, belongs to the existing technology of transistors. For example, W / L in the parameter is the aspect ratio of the transistor. For memory transistors with a given fabrication process and size, the process parameter K is almost a constant. The voltage V between the gate and source... GS and the voltage V between the drain and source of the transistor DS It can satisfy K(V) GS -V TH V DS=I. When a transistor operates in the linear or bipolar junction region, I is the current flowing between the drain and source of the transistor. In this paper, the current I of a single transistor is multiplied, and the output currents I of a single-row transistor are accumulated (such as the sum of I1 to IN in a string), which is equivalent to matrix multiplication and accumulation calculation.

[0065] See Figure 4 The string contains bit line B1 and source line S1: the current I1 of the first transistor can be calculated and denoted as K(V). GS11 -V TH11 V DS11 =I1. Following the same current formula, the current I2 of the second transistor can be calculated and written as K(V). GS12 -V TH12 V DS12 =I2, Nth transistor current K (V) GS1N -V TH1N V DS1N =IN. The voltage between the gate and source of the first transistor is V. GS11 The voltage between the drain and source is V. DS11 Threshold voltage is V TH11 The voltage between the gate and source of the second transistor is V. GS12 The voltage between the drain and source is V. DS12 Threshold voltage is V TH12 The voltage between the gate and source of the Nth transistor is V. GS1N and the drain-source voltage is V DS1N Threshold voltage is V TH1N The current characteristics of the storage transistors in other strings are similar to those in T11-T1N, and will not be repeated here. The weight of each storage transistor can be adjusted by its respective threshold voltage. If the transistors in the same column share a common bit line and a common source line, the voltage between their respective drain and source can be the same, such as allowing V... DS11 and V DS12 and V DS1N They can be the same.

[0066] See Figure 4For bit line B1 and source line S1 in the string: the source currents of the first to Nth transistors all flow to the common source line S1 of that column of transistors. The charge on source line S1 is QIS1. The charge can be integrated with the currents I1 to IN using a known capacitor (note the non-parasitic capacitance). For example, a capacitor of known capacitance can be placed on the source line to charge source line S1 with the currents I1 to IN, and the charge is QIS1. For example, in the example shown in the figure, a capacitor can be placed on source line S1 (the same applies to other source lines SM). The figure is only for illustration; in practice, capacitors are often placed on source lines S1 to SM and combined with operational amplifiers. For example, a known capacitor is connected to the positive input of the operational amplifier, and the negative input of the operational amplifier can be connected to the reference ground. Then, a signal such as the output voltage value is provided at the output of the operational amplifier, that is, the charge is converted into a sampleable voltage value. Sampling can be performed using existing techniques.

[0067] See Figure 4 For the bit line B1 and source line S1 of the string: This indicates the location of the first transistor if W is defined. 11 With K(V) GS11 -V TH11 V DS11 To ensure a proportional or equal relationship, the charge flowing through the first transistor and onto the common source line S1 of the transistors in that column can be expressed as Q11 = I1 * t1. At the location of the second transistor, if W is defined... 12 With K(V) GS12 -V TH12 V DS12 To ensure a proportional or equal relationship, the charge flowing through the second transistor and onto the common source line S1 of the same column of transistors can be expressed as Q12 = I2 * t2. And at the location of the third transistor, if W is defined... 13 With K(V) GS13 -V TH13 V DS13 To ensure a proportional or equal relationship, the charge flowing through the third transistor and onto the common source line S1 of that column of transistors can be expressed as Q13 = I3 * t3. And if W is defined at the location of the Nth transistor... 1N With K(V) GS1N -V TH1N V DS1N To ensure a proportional or equal relationship, the amount of charge flowing through the Nth transistor and towards the common source line S1 of that column of transistors is expressed as Q1N = IN * tn. QIS1 is the sum of Q11 to Q1N.

[0068] See Figure 4For bit line B1 and source line S1 in the string: the charge QIS1 on source line S1 can be expressed as charge addition after conversion (Y1=QIS1 can also be defined in Max_out=[QIS1]). This is precisely the source current convergence characteristic of the transistors in the string, which is equivalent to the multiplication and accumulation calculation algorithm of vector matrix multiplication. It meets the high-speed computing requirements of artificial intelligence for matrix operations, so the parallel arrangement of multiple strings can be equivalent to an accelerator.

[0069] See Figure 4 The diagram illustrates a basic example of a single string. In reality, multiple strings similar to the diagram can be combined to form a series of parallel strings. This involves configuring multiple parallel strings for a neural network, and adjusting the input data size for each memory transistor by changing the pulse width of the pulse signal input to its gate. This has been described previously. Figure 5 This will be further explained. If multiple strings are arranged side-by-side, the matrix Max is multi-row and multi-column rather than a single row, and the output Max_out is also multi-row rather than a single row. For example, the source S1 at the first string can provide an output Y1 based on the charge acquisition amount. Assuming the second string is arranged, the source S2 at the second string can provide an output Y2 based on the charge acquisition amount. Assuming the third string is arranged, the source S3 at the third string can provide an output Y3 based on the charge acquisition amount. Let the Mth string be arranged, then the source SM at the Mth string can provide an output Y based on the charge acquisition amount. M By analogy, Y1 to Y... M Even more strings of output can be combined together to form a multi-line output Max_out=[Y1, Y2, Y3...Y M The output vector of , ...].

[0070] See Figure 4 If a capacitor is connected at source line S1, and the capacitor collects the charge or electrical quantity at source line S1, and the magnitude of the charge is exactly QIS1 as mentioned earlier, this is considered the output of the string containing source line S1. For the output data of a single string, the output data of the neural network at that single string is obtained by collecting the output charge on the source line corresponding to that single string. The output data of the neural network at the first string is obtained by collecting the output charge on source line S1 of the first string, and the output data of the neural network at the second string is obtained by collecting the output charge on source line S2 of the second string. Assuming there are M strings, the output data of the neural network at the Mth string is obtained by collecting the output charge on source line SM of the Mth string; that is, collecting QIS1, QIS2, ... QISM, etc.

[0071] See Figure 4As illustrated in the previous example, the input data of each pair of transistors in each string is refreshed periodically. For example, the input data of each pair of transistors T11-T12, T13-T14, T15-T16, T17-T18, etc., in the first string is refreshed periodically. In consecutively numbered arrays of transistor pairs: taking the second and third sets of transistor pairs as examples (i.e., N2-N3) consecutively numbered pairs T12-T14 and T12-T16, if the difference dif between the effective pulse duration t_1 of the previous cycle Tim1 and the effective pulse duration t_2 of the next cycle Tim2 exceeds a predetermined value for any storage transistor in this array (i.e., N2-N3), other adjacent transistor pairs such as T11-T12 and T17-T18 are locked for one refresh cycle during the periodic refresh of the input data. For example, they can be locked in the next cycle Tim2 or the following cycle Tim3. If the input data refresh rate is low, it can be locked directly in the next cycle, Tim2. Alternatively, if the input data refresh rate is high, it can be locked in the cycle following Tim3, the cycle after Tim2. Figure 2 The narrow pulse width is assumed to be the effective pulse duration t_1 of the previous cycle Tim1. Due to variations in the effective pulse duration, Figure 3 The wide pulse width is assumed to be the effective pulse duration t_2 of the next cycle Tim2. Taking the storage transistor T16 as an example, Figure 4Narrow pulse widths are shaded, while the difference between a wide pulse and a narrow pulse width is represented by the value dif. If the difference dif between the effective pulse duration t_2 of the next cycle Tim2 and the effective pulse duration t_1 of the previous cycle Tim1 is greater than a predetermined value, then the adjacent transistor pairs T11-T12 will be latched for one refresh cycle, or the adjacent transistor pairs T17-T18 will be latched for one refresh cycle, or simultaneously, both adjacent transistor pairs T11-T12 and T17-T18 will be latched for one refresh cycle. Defined as an array of transistor pairs (numbered N2-N3), if the difference between the effective pulse duration of any storage transistor such as T13, T14, or T15 in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then other adjacent transistor pairs in that array, such as T11-T12 and T17-T18, will be latched for one refresh cycle. That is, except for T16, if the difference between the effective pulse duration of the previous cycle and the effective pulse duration of the next cycle in any of the predefined or selected array transistor pairs (numbered N2-N3) exceeds a predetermined value, then the other transistor pairs with adjacent numbers in that array transistor pair will be locked for one refresh cycle during the periodic refresh of the input data. The predetermined value can be given in advance based on experience. The predetermined value can also be obtained by multiplying the cycle by a preset ratio, for example, the predetermined value can be equal to the result of multiplying the cycle by a preset ratio (such as the range rg1 to rg2). For example, rg1 = 1 / 5 to rg2 = 1 / 2. The predetermined value can also be fixed as a fixed ratio of the cycle, for example, fixed as one-quarter of the cycle; then the larger the cycle, the larger the predetermined value, and vice versa.

[0072] See Figure 4As mentioned above, storage transistors T11-T12 need to be latched for one refresh cycle. This can be done in the following cycle (Tim2) or in the cycle immediately following (Tim3). However, it's important to note that storage transistors T11-T12 must be unlocked after being locked to allow for the next round of input data refresh, thus ensuring the operation of the neural network. If storage transistors T11-T12 are latched in the following cycle (Tim2), they should be unlocked in the next cycle (Tim3). If they are latched in the next cycle (Tim3), they should be unlocked in the following cycle (Tim4). After unlocking, the input data to storage transistors T11-T12 is still sent to the corresponding gates G1-G2. In summary, within consecutively numbered array transistor pairs: if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration of the next cycle exceeds a predetermined value, then the other adjacent numbered transistor pairs in that array transistor pair will lock for one refresh cycle during the periodic refresh of input data, and will unlock after locking to enter the next round of input data refresh. The adjacent numbered transistor pairs of the array transistor pairs (N2-N3) are defined as T17-T18 in addition to the aforementioned storage transistors T11-T12. The locking and unlocking principles of T17-T18 are the same as those of storage transistors T11-T12, and will not be repeated here. Of course, in addition to T11-T12 and T17-T18 performing the locking and unlocking tasks individually, these two adjacent numbered transistor pairs can also perform the locking and unlocking tasks simultaneously. If the overall weight matrix of the neural network is large, then in a preferred embodiment, if the two groups of adjacent numbered transistors T11-T12 and T17-T18 simultaneously perform the latching and unlocking tasks, it can accelerate the computation of the neural network. If the overall weight matrix of the neural network is small, then in a preferred embodiment, if the two groups of adjacent numbered transistors T11-T12 and T17-T18 perform the latching and unlocking tasks respectively, it can provide the neural network with more refined and accurate computational results.

[0073] See Figure 2Let's illustrate with an example. Suppose some elements or pixels in a grayscale image pix1 are mapped to weight values ​​corresponding to defined array transistor pairs (numbered N2-N3), and some elements or pixels in another grayscale image pix2 are also mapped to these weight values ​​corresponding to defined array transistor pairs (numbered N2-N3). In the field of machine vision, the defined array transistor pairs (numbered N2-N3) can represent visual regions of elements or pixels with higher grayscale values, while other transistor pairs with adjacent numbers (such as N1 or N4) can be classified as visual regions of elements or pixels with lower or even zero grayscale values. For example, to enable artificial intelligence to obtain inference results more quickly, the defined array transistor pairs (numbered N2-N3) are key elements or pixels that need more attention and preferential processing. As another example, the overlapping region ov of grayscale images pix1 and pix2 can be considered a region of interest (ROI) in image processing to focus on core information processing and simplify and reduce computational load. It is evident that the scheme involving consecutively numbered array transistor pairs has broad applicability in artificial intelligence applications.

[0074] See Figure 4Using common-source transistor pairs as controlled unit cells to operate neural networks significantly increases transistor density per unit chip or wafer area. Furthermore, it folds massive numbers of transistors into pairs, facilitating source current handling, weight programming management, and transistor manufacturing. For example, a common-source transistor means that a pair of transistors only needs to draw current from a common source. During weight programming, only a suitable voltage needs to be provided to the same common source, and programming voltages need to be provided at the gates of each pair of transistors to simultaneously assign weights to both transistors. In transistor manufacturing, a single doped region can be used for the common source. This brings numerous advantages to the production and manufacturing of the physical carrier of the neural network (chip), weight programming, and computational processes, including rapid current and charge flow and high-speed sampling. A higher density of neural network transistors per unit chip or wafer area translates to greater computing power. However, a common concern with semiconductor chips is the presence of parasitic capacitors at the source, drain, and gate of transistors. Parasitic capacitance superimposed on the source line or actively added capacitance is almost unavoidable. Meanwhile, at high cell densities, the source current is easily affected by unwanted charges. The larger the neural network, the greater the impact of unwanted charges on the source current. For example, with high computing power or high clock frequency, the faster the data refresh, the more charge can accumulate on the source lines. Typically, the charge formed on the source lines by the local storage transistors in a neural network in the previous cycle has not yet dissipated under high computing power or high clock frequency conditions, while the input data of the many storage transistors in the neural network is fed in in the next cycle. Considering the huge number of strings of neural networks and the number of transistors in the strings, if even a small amount of current charge from the previous cycle remains in the storage transistors, the string output will be incorrect. However, the electronic or computing devices carrying the neural network will not recognize this as an error because it is hidden. Even if the next cycle can tolerate or ignore this error, over several cycles, this error will accumulate and eventually exceed the tolerance or negligibility limit within certain finite cycles, manifesting as an accumulated error. The solution mentioned in this paper aims to solve this hidden problem that is difficult to detect and may even accumulate over several cycles before causing errors. One root cause of this problem is that the string output data is obtained by collecting the source line charges of the string. However, the source lines are highly sensitive to various unwanted negative charges (such as hysteresis charges). The erroneous accumulation of hysteresis charges over cycle can easily cause the neural network to exhibit activation behavior similar to an activation function, equivalent to certain computational results or output results being accidentally and incorrectly activated. This undoubtedly limits the learning ability of the neural network or provides incorrect indications.

[0075] See Figure 4In summary, the input data of each pair of transistors in each string is refreshed periodically. In consecutively numbered pairs of transistors, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the other transistor pairs with adjacent numbers in that pair are locked for one refresh cycle (i.e., skip one cycle) during the periodic refresh of the input data. After the locking is completed, the locked other transistor pairs are unlocked, allowing the next round of input data refresh to begin. This prevents the charge formed on the source line by the input data of the other transistor pairs with adjacent numbers in that pair from lagging behind in the charge formed on the same source line by the input data of the next cycle. For example, this prevents the charge formed on the S1 source line by the Tim1 input data of the adjacent N1 / N4 transistor pairs T11-T12 and T17-T18 in the N2-N3 pair from lagging behind in the charge formed on the same source line S1 by the Tim2 input data of the next cycle. This application aims to avoid the periodic accumulation of hysteresis charges in neural networks and to prevent charge hysteresis from exceeding tolerable or negligible limits within certain finite periods, thus resulting in accumulated errors. Larger neural networks have more strings and more parallel transistor pairs within a single string, making the source current more susceptible to negative charges at high cell densities. This application balances the high computational demands of high cell density with the solution to calculation errors caused by negative charges, not only building a high-cell-density storage system but also achieving high-precision computation of the neural network. This trade-off allows for the sacrifice of current charges in non-critical areas in exchange for high-precision computation of current charges in critical areas. Neural network applications receive input signals and generate output signals, involving activation functions. Different types of activation functions can almost all produce a step function effect on the result, which is a factor to consider.

[0076] See Figure 4 The adjacent transistor pairs of the array transistor pair (numbered N2-N3), besides the aforementioned storage transistors T11-T12, include T17-T18. The latching and unlocking principles of T17-T18 after latching are the same as those of storage transistors T11-T12. Then, the other adjacent transistor pairs of this array transistor pair (numbered N2-N3) are the adjacent transistor pairs numbered before this array transistor pair, such as T11-T12. They are numbered N1, and the first group of transistor pairs here has the number N1 before this array transistor pair (numbered N2-N3), with N1 preceding N2-N3.

[0077] See Figure 4For example, the other transistor pairs with adjacent numbers to the transistor pair in the array (numbered N2-N3) are adjacent transistor pairs such as T17-T18 that are numbered after the transistor pair in the array. They are numbered N4, and the fourth transistor pair here is numbered N4 after the transistor pair in the array (numbered N2-N3). N4 is later than N2-N3.

[0078] See Figure 4 For example, other transistor pairs with adjacent numbers in the same transistor array (N2-N3) include adjacent transistor pairs numbered before the current transistor array, such as T11-T12, which are numbered N1, and the first group of transistor pairs here has N1 before the current transistor array (N2-N3). This also includes cases where the transistor pairs are numbered after the current transistor array. For another example, other transistor pairs with adjacent numbers in the same transistor array (N2-N3) include adjacent transistor pairs numbered after the current transistor array, such as T17-T18, which are numbered N4, and the fourth group of transistor pairs here has N4 after the current transistor array (N2-N3).

[0079] See Figure 4 The other transistor pairs with adjacent numbers in the array of transistor pairs can be: adjacent transistor pairs numbered before the array of transistor pairs, adjacent transistor pairs numbered after the array of transistor pairs, adjacent transistor pairs numbered before the array of transistor pairs, and adjacent transistor pairs numbered after the array of transistor pairs.

[0080] See Figure 4 For a neural network mapped from multiple strings (e.g., the first string, the second string, up to the Mth string), each storage transistor, such as T11-T18, adjusts the size of its input data by changing the pulse width of the pulse signal input to its gates G1-G8. For example, storage transistor T11 adjusts its input data size by changing the pulse width of the pulse signal input to its gate G1. Generally, the wider the pulse width, i.e., the longer the high-level duration, the larger the input data; conversely, the narrower the pulse width, i.e., the shorter the high-level duration, the smaller the input data. Similarly, storage transistor T16 adjusts its input data size by changing the pulse width of the pulse signal input to its gate G6. The wider the pulse width, i.e., the longer the high-level duration, received by gate G6, the larger the input data for storage transistor T16; conversely, the narrower the pulse width, i.e., the shorter the high-level duration, the smaller the input data for storage transistor T16.

[0081] See Figure 4As mentioned earlier, storage transistors T11-T12 need to be latched for one refresh cycle. This latching can be done in the following cycle (Tim2) or in the cycle immediately following (Tim3). However, it's important to note that storage transistors T11-T12 must be unlocked after latching to allow for the next round of input data refresh, thus ensuring normal operation. During the latching period of one refresh cycle, the gates G1-G2 of adjacent storage transistors T11-T12 are clamped to the level corresponding to an ineffective pulse that is opposite to the effective pulse. For example, gates G1-G2 may be clamped to the level corresponding to an ineffective pulse (low level) that is opposite to the effective pulse (high level) (such as the low level of the system, like zero potential or reference ground potential).

[0082] See Figure 4 As mentioned earlier, storage transistors T17-T18 need to be latched for one refresh cycle. This latching can be done in the following cycle (Tim2) or in the cycle immediately following (Tim3). However, it's important to note that storage transistors T17-T18 must be unlocked after latching to allow for the next round of input data refresh, thus ensuring normal operation. During the latching period of one refresh cycle, the gates G7-G8 of adjacent storage transistors T17-T18 are clamped to the level corresponding to an ineffective pulse that is opposite to the effective pulse. For example, gates G7-G8 may be clamped to the level corresponding to an ineffective pulse that is opposite to the effective pulse (high level), i.e., a low level (such as zero potential or reference ground potential, etc.).

[0083] See Figure 4 As previously mentioned, storage transistors T11-T12 need to be latched for one refresh cycle. This latching can be done in the next cycle (Tim2) or in the cycle immediately following Tim3. However, it's important to note that storage transistors T11-T12 must be unlocked after the latching process to allow for the next round of input data refresh and ensure normal operation. During the latching period of one refresh cycle, the threshold voltages (V) of adjacent storage transistors T11-T12 in this transistor pair... TH The voltage is modulated to a state higher than the threshold voltage during unlocking. The threshold voltages (V) of storage transistors T11-T12 are... THThe value during the latch-up period is set to be greater than the value during the unlock-up period. During the latch-up period, the threshold voltage or floating gate charge of the storage transistors T11-T12 is modulated to a higher state than the threshold voltage or floating gate charge during the unlock-up period.

[0084] See Figure 4 As previously mentioned, storage transistors T17-T18 need to be latched for one refresh cycle. This latching can be done in the following cycle (Tim2) or in the cycle immediately following (Tim3). However, it's important to note that storage transistors T17-T18 must be unlocked after the latching process to allow for the next round of input data refresh and ensure normal operation. During the latching period of one refresh cycle, the threshold voltages (V) of adjacent storage transistors T17-T18 in this transistor pair... TH The voltage is modulated to a state higher than the threshold voltage during unlocking. Storage transistors T17-T18 have their threshold voltages (V...) TH The value during the latch-up period is set to be greater than the value during the unlock-up period. During the latch-up period, the threshold voltage or floating gate charge of the storage transistors T17-T18 is modulated to a higher state than the threshold voltage or floating gate charge during the unlock-up period.

[0085] See Figure 5 As previously mentioned, storage transistors T11-T12 need to be latched for one refresh cycle. This latching can be done in the following cycle (Tim2) or in the cycle immediately following (Tim3). However, note that storage transistors T11-T12 are unlocked after the latching process to allow for the next round of input data refresh, thus ensuring normal operation. During the latching period of one refresh cycle, the weight values ​​of adjacent storage transistors T11-T12 are adjusted to a lower state than their weight values ​​during the unlocking period. See also... Figures 2 to 4 .

[0086] See Figure 5As previously mentioned, storage transistors T17-T18 need to be latched for one refresh cycle. This latching can be done in the following cycle (Tim2) or in the cycle immediately following (Tim3). However, note that storage transistors T17-T18 are unlocked after the latching process to allow for the next round of input data refresh, thus ensuring normal operation. During the latching period of one refresh cycle, the weight values ​​of adjacent storage transistors T17-T18 are adjusted to a lower state than their weight values ​​during the unlocking period. See also... Figures 2 to 4 .

[0087] See Figure 5 In summary, for consecutively numbered array transistor pairs, during a lock-up period of one refresh cycle, the gates of adjacent numbered transistor pairs are clamped to the level corresponding to the inactive pulse, which is opposite to the active pulse. During the lock-up period of one refresh cycle, the total charge output by adjacent numbered transistor pairs to the source line S1 of the corresponding string is clamped to a level lower than the total charge output by the array transistor pair to the source line of the corresponding string. This prevents adjacent numbered transistor pairs from accumulating or integrating charge on the source line S1 cycle by cycle.

[0088] See Figure 5 For example, in the second and third consecutive transistor pairs numbered N2-N3, the gates of adjacent transistor pairs T11-T12 and T17-T18 are clamped to the level corresponding to the ineffective pulse, which is opposite to the effective pulse, during a latched refresh cycle. During the latched refresh cycle, the total charge output by transistor pairs T11-T12 and T17-T18 to the source line S1 of the first string is clamped to a lower level than the total charge output by transistor pairs T13-T14 and T15-T16 to the source line S1 of the first string. This prevents other adjacent transistor pairs T11-T12 and T17-T18 from accumulating or integrating charge (or charge) to their respective source lines S1 on a cycle-by-cycle basis.

[0089] See Figure 5In summary, for consecutively numbered array transistor pairs, during a lock-up refresh cycle, the threshold voltages of adjacent numbered transistor pairs are modulated to be higher than their threshold voltages during the unlock period. During a lock-up refresh cycle, the total charge output by these adjacent numbered transistor pairs to the source line S1 of the corresponding string is clamped to a level lower than the total charge output by the array transistor pair to the source line of the corresponding string. This prevents adjacent numbered transistor pairs from accumulating or integrating charge on the source line S1 cycle by cycle.

[0090] See Figure 5 For example, in the second and third consecutive transistor pairs numbered N2-N3, the threshold voltages of adjacent transistor pairs T11-T12 and T17-T18 are modulated to a higher value during a locked refresh cycle than during an unlocked refresh cycle. During a locked refresh cycle, the total charge output by transistor pairs T11-T12 and T17-T18 to the source line S1 of the first string is clamped to a lower value than the total charge output by transistor pairs T13-T14 and T15-T16 to the source line S1 of the first string. This prevents other adjacent transistor pairs (T11-T12 and T17-T18) from accumulating or integrating charge (or charge) to their respective source lines S1 on a cycle-by-cycle basis.

[0091] See Figure 5 In summary, for consecutively numbered array transistor pairs, during a lock-up period of one refresh cycle, the weight values ​​of adjacent numbered transistor pairs are adjusted to a lower value than during the unlock period. During a lock-up period of one refresh cycle, the total charge output by adjacent numbered transistor pairs to the source line S1 of the corresponding string is clamped to a lower value than the total charge output by the array transistor pair to the source line of the corresponding string. This prevents adjacent numbered transistor pairs from accumulating or integrating charge on the source line S1 cycle by cycle.

[0092] See Figure 5For example, in the second and third consecutive transistor pairs numbered N2-N3, the weight values ​​of adjacent transistor pairs T11-T12 and T17-T18 are adjusted to a lower state than their weight values ​​during the unlocking period when the transistor pairs T11-T12 and T17-T18 are locked for one refresh cycle. During the lockout of one refresh cycle, the total charge output by transistor pairs T11-T12 and T17-T18 to the source line S1 of the first string is clamped to a lower level than the total charge output by transistor pairs T13-T14 and T15-T16 to the source line S1 of the first string. This prevents other adjacent transistor pairs T11-T12 and T17-T18 from accumulating or integrating charge (or charge) on the corresponding source line S1 on a cycle-by-cycle basis.

[0093] See Figure 5 In an optional embodiment, during the latching period of a refresh cycle, the gates of other transistor pairs with adjacent numbering in the array transistor pair are clamped to the level corresponding to an ineffective pulse opposite to the effective pulse. During the latching period of a refresh cycle, the total charge output by these other transistor pairs to the source lines of their respective strings is clamped to a lower level than the total charge output by the array transistor pair to the source lines of the respective strings. Thus, during the latching period of a refresh cycle, the integration of charge on the source lines cycle by cycle is avoided; in particular, the integration of charge on the source lines cycle by cycle by other transistor pairs with adjacent numbering in the array transistor pair is avoided.

[0094] See Figure 5 In an optional embodiment, the threshold voltages of adjacent transistor pairs of the array transistor pair are modulated to be higher than the threshold voltages during the unlocking period during a refresh cycle. During the latching period, the total charge output by these other transistor pairs to the source lines of their respective strings is clamped to a lower level than the total charge output by the array transistor pair to the source lines of the respective strings. This latching period serves to prevent cycle-by-cycle integration of charge to the source lines; particularly, it prevents cycle-by-cycle integration of charge to the source lines by adjacent transistor pairs of the array transistor pair.

[0095] See Figure 5In an optional embodiment, during the latching period of a refresh cycle, the weight values ​​of adjacent numbered transistor pairs in the array are adjusted to a lower state than their weight values ​​during the unlocking period. Meanwhile, during the latching period of a refresh cycle, the total charge output by the other transistor pairs to the source lines of their respective strings is clamped to a lower level than the total charge output by the array of transistor pairs to the source lines of their respective strings. This latching period serves to prevent cycle-by-cycle integration of charge on the source lines; in particular, it prevents cycle-by-cycle integration of charge on the source lines by other adjacent numbered transistor pairs in the array of transistor pairs.

[0096] See Figure 1 In an optional embodiment, in a plurality of parallel different strings, each string defines the array of transistor pairs, and the numbering segment of the array of transistors in any string is the same as the numbering segment of the array of transistors in other dissimilar strings. For example, in a plurality of parallel first to Mth strings, each string defines the array of transistor pairs. The first string defines the array of transistor pairs, such as the second and third transistor pairs numbered N2-N3. The second string defines the array of transistor pairs, such as the second and third transistor pairs numbered N2-N3. The Mth string defines the array of transistor pairs, such as the second and third transistor pairs numbered N2-N3. The numbering segment of the array of transistors (the second and third transistor pairs) in the first string is the same as the numbering segment of the array of transistors (the second and third transistor pairs) in other dissimilar second strings, and the numbering segment is N2-N3. The numbering segment of the transistor array in the second string (the second and third transistor pairs) is the same as the numbering segment of the transistor array in the Mth string (the second and third transistor pairs), and the numbering segment is N2-N3. That is, the numbering segment (e.g., N2-N3) of the transistor array in any string is the same as the numbering segment (e.g., N2-N3) of the transistor array in other different strings. Taking T13-T14 and T15-T16 as examples of the aforementioned transistor array pairs for illustration, each string defines such transistor array pairs.

[0097] See Figure 1 In an optional embodiment, in the first to the Mth parallel strings, each string defines an array of transistor pairs T13-T14 and T15-T16 numbered N2-N3. Moreover, the numbering segment N2-N3 of the array of transistors in any string (i.e., T13-T14 and T15-T16) is the same as the numbering segment N2-N3 of the array of transistors in other different strings (i.e., T13-T14 and T15-T16).

[0098] See Figure 5In an optional embodiment, an artificial intelligence storage system includes: multiple parallel strings, each string being configured with a source line and a bit line; a single string containing multiple pairs of transistors connected in parallel between the source line and the bit line, each pair of transistors containing a pair of source-interconnected storage transistors; the sources of the two storage transistors in each pair of transistors being connected to the source line and the drains of the two storage transistors being connected to the bit line; the multiple strings being mapped to multiple columns of weight value carriers of a neural network; the weight represented by each storage transistor being adjusted by the threshold voltage of each storage transistor; and each pair of transistors in each string being sequentially assigned a number.

[0099] See Figure 5 In an optional embodiment, the input data of the neural network to each string is input to the gate of each storage transistor in the string in the form of a pulse signal, and the output data of the neural network at the string is obtained by collecting the source line charge of the string. The input data of each pair of transistors in each string is refreshed periodically. In the array of consecutively numbered transistor pairs, if the difference between the effective pulse duration of the previous cycle and the effective pulse duration of the next cycle of any storage transistor in the array exceeds a predetermined value, then the other transistor pairs with adjacent numbers in the array will clamp their gates to an ineffective pulse during the periodic refresh of the input data, interrupting one refresh cycle. After the interruption, the gate potential clamping is released to enter the next round of input data refresh.

[0100] See Figure 5 In an optional embodiment, for example, if the input data of each pair of transistors in the first string is refreshed periodically, and in consecutive array transistor pairs such as T13-T14 and T15-T16 numbered N2-N3, when the difference dif between the effective pulse duration of the previous cycle Tim1 and the effective pulse duration of the next cycle Tim2 in any storage transistor such as T16 exceeds a predetermined value, then during the periodic refresh of the input data, the gates G1-G2 and / or G7-G8 of the other transistor pairs such as T11-T12 and T17-T18 with adjacent numbers such as N1 and / or N4 are clamped to an ineffective pulse such as a low level, interrupting one refresh cycle. After the interruption, the gate potential clamping is released, allowing the next round of input data refresh to begin. Releasing the potential clamping of gates G1-G2 and / or G7-G8 means that they are not clamped but controlled according to the normal input data of the neural network. The advantage of this embodiment over other embodiments described above is that it is simpler to control; the purpose can be achieved by manipulating the gate potential.

[0101] See Figure 5In an optional embodiment, in multiple parallel strings, each string defines its own array of transistor pairs, and the numbering segment of the array of transistor pairs in any string is the same as the numbering segment of the array of transistor pairs in other dissimilar strings. Therefore, the weight level of the array of transistor pairs in each string is prioritized over or higher than the weight level of the remaining transistor pairs in the entire weight matrix of the neural network. Here, "remaining transistor pairs" refers to all other transistor pairs in each string besides its own array of transistor pairs.

[0102] See Figure 5 In an optional embodiment, in the first to Mth parallel strings, each string defines a pair of transistors T13-T14 and T15-T16 numbered N2-N3. The numbering segment N2-N3 of the transistor pair T13-T14 and T15-T16 in any string is the same as the numbering segment N2-N3 of the transistor pair T13-T14 and T15-T16 in other different strings. The weight level of the transistors T13-T14 and T15-T16 in each of the first to Mth strings is prioritized or higher than the weight level of the remaining transistor pairs in the entire weight matrix of the neural network. Note that the entire weight matrix of the neural network is a matrix composed of all the weight values ​​corresponding to all stored transistors in the first to Mth strings. For example, all weight values ​​of all storage transistors T11-T1N in the first string are part of the entire weight matrix. Similarly, all weight values ​​of all storage transistors T11-T1N in the second string are also part of the entire weight matrix. Furthermore, all weight values ​​of all storage transistors T11-T1N in the Mth string are also part of the entire weight matrix. The remaining transistor pairs include all other transistor pairs in the first string except for the specified array transistor pairs T13-T14 and T15-T16, all other transistor pairs in the second string except for the specified array transistor pairs T13-T14 and T15-T16, all other transistor pairs in the Mth string except for the specified array transistor pairs T13-T14 and T15-T16, and so on.

[0103] See Figure 5 In an optional embodiment, the weight level of the specified array transistor pairs such as T13-T14 and T15-T16 in the first to Mth strings takes precedence over the weight levels of the remaining transistor pairs in the entire weight matrix of the neural network. Figure 4In the first string, the weight value of the specified transistor pair (e.g., T13-T14, T15-T16) can be denoted as wei1. The weight values ​​of the remaining transistor pairs (T11-T12, excluding the specified pair) in the first string are denoted as wei2, and the weight values ​​of the remaining transistor pairs (T17-T18, excluding the specified pair) are denoted as wei3. Clearly, in the first string, weight value wei1 has a higher priority than wei2 and wei3. The second and Mth strings also follow this pattern; their weight priorities are not elaborated further.

[0104] See Figure 5 In an optional embodiment, the weights of the specified transistor pairs (N2-N3) in the first to Mth strings take precedence over the weights of the remaining transistor pairs (N1 and N4) in the entire weight matrix of the neural network. This means that in the entire weight matrix of the first to Mth strings, the anchored region (N2-N3) is more critical to the data being processed under the current conditions or state than the remaining regions (N1 and N4). Note that the anchored region is dynamic, not static.

[0105] See Figure 5 In summary, the input data of each pair of transistors in each string is refreshed periodically. In consecutively numbered pairs of transistors, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the other transistor pairs with adjacent numbers in that pair are locked for one refresh cycle (i.e., skip one cycle) during the periodic refresh of the input data. After the locking period ends, the locked transistor pairs are unlocked, allowing the next round of input data refresh to begin. This is to prevent the charge formed on the source line by the input data of the other transistor pairs with adjacent numbers in that pair from being delayed in the charge formed on the same source line by the input data of the next cycle. During this one-refresh-cycle locking period, it also prevents the other transistor pairs with adjacent numbers in that pair from integrating the charge on the source line cycle by cycle, thereby preventing the accumulated charge from having an equivalent activation effect on the output data of the corresponding string. This effectively prevents the output of the neural network from being erroneously activated without an activation function being implemented.

[0106] The foregoing description and accompanying drawings have provided typical embodiments of specific structures for specific implementations. The above-described invention presents preferred embodiments, but these are not intended to be limiting. Various changes and modifications will undoubtedly be apparent to those skilled in the art after reading the foregoing description. Therefore, the appended claims should be considered to cover all changes and modifications that encompass the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should be considered to still fall within the intent and scope of the invention.

Claims

1. An artificial intelligence storage system, characterized in that, include: Multiple strings are arranged in parallel; each string is configured with a source line and a bit line. A single string contains multiple pairs of transistors connected in parallel between the source line and the bit line. Each pair of transistors contains a pair of memory transistors with source interconnection. The sources of the two memory transistors in each pair are connected to the source line and the drains of the two memory transistors are connected to the bit line. Multiple strings are mapped to multiple columns of weight value carriers of a neural network. The weight value represented by each memory transistor is adjusted by the threshold voltage of each memory transistor. Each pair of transistors in each string is assigned a number in sequence. The input data sent to each string by the neural network is input to the gate of each storage transistor in the string in the form of pulse signals. The output data of the neural network at the string is obtained by collecting the source line charge of the string. The input data of each pair of transistors in each string is refreshed periodically. In a pair of transistors with consecutive numbers, if the difference between the effective pulse duration of any storage transistor in the previous cycle and the effective pulse duration in the next cycle exceeds a predetermined value, then the other transistor pairs with adjacent numbers in the pair of transistors will be locked for one refresh cycle during the periodic refresh of the input data. After the locking is completed, they will be unlocked to enter the next round of input data refresh.

2. The artificial intelligence storage system according to claim 1, characterized in that: The other transistors are adjacent transistor pairs numbered before the transistor pair in the array, or adjacent transistor pairs numbered after the transistor pair in the array, or adjacent transistor pairs numbered before and after the transistor pair in the array.

3. The artificial intelligence storage system according to claim 1, characterized in that: For a neural network composed of multiple strings, each storage transistor adjusts the size of the input data by changing the pulse width of the pulse signal input to its gate.

4. The artificial intelligence storage system according to claim 1, characterized in that: During the latching period of one refresh cycle, the gates of the other transistor pairs are clamped to the level corresponding to the ineffective pulse that is opposite to the effective pulse.

5. The artificial intelligence storage system according to claim 1, characterized in that: During the latching period of a refresh cycle, the threshold voltages of the other transistor pairs are modulated to be larger than the threshold voltages during the unlocking period.

6. The artificial intelligence storage system according to claim 1, characterized in that: During the latching period of a refresh cycle, the weight values ​​of the other transistor pairs are adjusted to a lower state than the weight values ​​during the unlocking period.

7. The artificial intelligence storage system according to any one of claims 4-6, characterized in that: During the latching period of a refresh cycle, the total charge output by the other transistor pairs to the source lines of the corresponding string is clamped to a level lower than the total charge output by the array of transistor pairs to the source lines of the corresponding string.

8. The artificial intelligence storage system according to claim 1, characterized in that: In multiple parallel strings, each string defines the array of transistor pairs, and the numbering segment of the array of transistor pairs in any string is the same as the numbering segment of the array of transistor pairs in other different strings.

9. An artificial intelligence storage system, characterized in that, include: Multiple strings are arranged in parallel; each string is configured with a source line and a bit line. A single string contains multiple pairs of transistors connected in parallel between the source line and the bit line. Each pair of transistors contains a pair of memory transistors with source interconnection. The sources of the two memory transistors in each pair are connected to the source line and the drains of the two memory transistors are connected to the bit line. Multiple strings are mapped to multiple weight value carriers of a neural network. The weight represented by each memory transistor is adjusted by the threshold voltage of each memory transistor. Each pair of transistors in each string is assigned a number in sequence. The input data sent to each string by the neural network is input to the gate of each storage transistor in the string in the form of pulse signals. The output data of the neural network at the string is obtained by collecting the source line charge of the string. The input data of each pair of transistors in each string is refreshed periodically. In the array of consecutively numbered transistor pairs, if the difference between the effective pulse duration of the previous cycle and the effective pulse duration of the next cycle of any storage transistor in the array exceeds a predetermined value, then the other transistor pairs with adjacent numbers in the array will clamp their gates to an ineffective pulse during the periodic refresh of the input data, interrupting one refresh cycle. After the interruption, the gate potential clamping is released to enter the next round of input data refresh.

10. The artificial intelligence storage system according to claim 9, characterized in that: In multiple parallel strings, each string defines its own array of transistor pairs. The numbering segment of the array of transistor pairs in any string is the same as the numbering segment of the array of transistor pairs in other dissimilar strings. Therefore, the weight level of the array of transistor pairs in each string takes precedence over the weight level of the remaining transistor pairs in the entire weight matrix of the neural network.

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