Semiconductor device and method of manufacturing the same, power device

Abstract

The application provides a semiconductor device and a preparation method thereof and a power device. The method comprises the following steps: providing a substrate with a gate trench; forming a dielectric layer, the dielectric layer comprising a first dielectric layer, a second dielectric layer and a third dielectric layer, the material of the second dielectric layer being silicon nitride, and the dielectric layer enclosing the first filling area in the gate trench; forming a first mask layer with a mask opening, the mask opening at least exposing the first filling area and one sidewall thereof; taking the first mask layer as a mask, removing the dielectric layer on one sidewall of the first filling area to expose the wall surface of the gate trench opposite to one sidewall of the first filling area; and removing the first mask layer; removing the second dielectric layer and the third dielectric layer on the other sidewall of the first filling area; forming a fourth dielectric layer covering the inner wall of the gate trench, the fourth dielectric layer and the remaining first dielectric layer constituting a gate dielectric layer; and forming a gate electrode. The application can reduce the preparation process of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and a power device. Background Technology

[0002] Shielded Gate Trench FETs (SGT FETs) offer optimized high-voltage, high-speed, and low-loss performance for power MOSFETs and are widely used in high-efficiency, high-frequency power conversion applications. In these applications, power devices need to simultaneously possess high conduction performance and high reliability (wide safe operating area, SOA).

[0003] In related technologies, in order to balance the wide safe operating area (SOA) and the zero temperature coefficient (ZTC) of a shielded gate field-effect transistor, the thickness difference of the gate dielectric layer on both sides of the same cell is usually adjusted to form an asymmetric threshold voltage distribution. In this way, ZTC optimization and SOA expansion can be achieved synergistically.

[0004] However, the fabrication process of the gate dielectric layer in current shielded gate field-effect transistors (SGTs) is relatively complex, which can easily lead to the accumulation of process errors in semiconductor devices and reduce their performance. Summary of the Invention

[0005] In view of the above problems, this application provides a semiconductor device and its fabrication method, as well as a power device, which can simplify the complexity of the gate dielectric layer fabrication process and improve the performance of the semiconductor device.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, comprising:

[0008] A substrate is provided, and the substrate is patterned to form gate trenches in the substrate;

[0009] A dielectric layer is formed, which at least covers the inner wall of the gate trench. The dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked together. The second dielectric layer is made of silicon nitride. The dielectric layer encloses a first filling region within the gate trench.

[0010] A first mask layer is formed, the first mask layer is disposed on the substrate, and the first mask layer also has a mask opening, the mask opening exposing at least the first filling area and one sidewall of the first filling area;

[0011] Using the first mask layer as a mask, the dielectric layer located on one sidewall of the first filling region is removed to expose the wall surface of the gate trench opposite to one sidewall of the first filling region; and the first mask layer is removed.

[0012] Remove the second and third dielectric layers located on the other sidewall of the first filling area;

[0013] A fourth dielectric layer is formed, which covers the inner wall of the gate trench, and the fourth dielectric layer and the remaining first dielectric layer constitute the gate dielectric layer;

[0014] A gate is formed, wherein the gate is disposed within a second filling region enclosed by the gate dielectric layer.

[0015] In one possible implementation, the step of removing the second and third dielectric layers located on the other sidewall of the first filling region includes:

[0016] Perform a first etching process, using the second dielectric layer as an etching stop layer, to remove the third dielectric layer located on the other sidewall of the first filling region;

[0017] A second etching process is performed, using the first dielectric layer as an etching stop layer, to remove the second dielectric layer located on the other sidewall of the first filling region, while retaining the first dielectric layer located on the other sidewall of the first filling region.

[0018] In one possible implementation, after the step of forming the dielectric layer and before the step of forming the first mask layer, the fabrication method further includes:

[0019] A shielding gate is formed, the shielding gate being located within the second filling region enclosed by the dielectric layer in the gate trench, and the top surface of the shielding gate being lower than the top surface of the substrate;

[0020] An insulating layer is formed, the insulating layer being disposed on the shielding grid, and the top surface of the insulating layer being lower than the top surface of the substrate.

[0021] In one possible implementation, the substrate includes a cell region and a terminal region adjacent to the cell region;

[0022] The number of gate trenches is multiple, and the gate trenches are arranged at intervals along a first direction within the substrate, wherein each gate trench spans the cell region and the terminal region.

[0023] In one possible implementation, the step of providing the substrate includes:

[0024] A second mask layer and a photoresist layer are formed on the substrate in a stacked manner;

[0025] The photoresist layer is patterned, and the second mask layer and the substrate are patterned using the photoresist layer as a mask to form a gate trench in the substrate;

[0026] Remove the photoresist layer and a portion of the thickness of the second mask layer.

[0027] In one possible implementation, the step of forming the shielding barrier includes:

[0028] A shielding gate material is formed, which fills the second filling area enclosed by the gate trench in the dielectric layer and covers the top surface of the dielectric layer;

[0029] A portion of the shielding barrier material is removed to form an intermediate layer, the top surface of which is lower than the dielectric layer;

[0030] A third mask layer is formed, which is disposed on the dielectric layer and covers the terminal area;

[0031] Using the third mask layer as a mask, a third etching process is performed to remove the intermediate layer located on the cell region, so that the remaining intermediate layer forms a shielding gate.

[0032] In one possible implementation, the step of forming the insulating layer includes:

[0033] An insulating material layer is formed, which is disposed on the shielding grid and covers the dielectric layer;

[0034] Remove the insulating material layer and the dielectric layer located on the substrate;

[0035] Using the first mask layer as a mask, a portion of the insulating material layer within the cell is removed, and the remaining insulating material layer constitutes the insulating layer.

[0036] Secondly, embodiments of this application provide a semiconductor device, including:

[0037] A substrate having gate trenches therein;

[0038] A gate, wherein the gate is disposed within the gate trench;

[0039] A gate dielectric layer is disposed in the gate trench and surrounds the gate, wherein, in the extension direction perpendicular to the gate trench, the gate dielectric layer on one side of the gate includes a first dielectric layer and a fourth dielectric layer stacked thereon, and the gate dielectric layer on the other side of the gate includes a fourth dielectric layer.

[0040] In one possible implementation, the semiconductor device further includes a shielding gate and an insulating layer;

[0041] The shielding gate is located within the gate trench and below the gate;

[0042] The insulating layer is disposed between the shielding gate and the gate.

[0043] Thirdly, embodiments of this application provide a power device, including the semiconductor device described in the second aspect.

[0044] In the semiconductor devices and their fabrication methods and power devices provided in the embodiments of this application, by improving the dielectric layer, it is not necessary to form a mask layer when forming the fourth dielectric layer. This reduces the number of mask plates, saves on the design and manufacturing costs of the mask plates, shortens the operation time of the photolithography process, and reduces the equipment occupation and maintenance costs of the photolithography machine. This compresses the overall process cost from both material and labor time perspectives.

[0045] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that the semiconductor devices and their preparation methods and power devices provided by the embodiments of this application can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0047] Figure 1 A process flow diagram of the method for fabricating a semiconductor device provided in the embodiments of this application;

[0048] Figure 2 A schematic diagram of a substrate provided in the method for fabricating a semiconductor device according to an embodiment of this application;

[0049] Figure 3 A schematic diagram illustrating the formation of a gate trench in a method for fabricating a semiconductor device according to an embodiment of this application;

[0050] Figure 4A schematic diagram of a second mask layer with a portion of its thickness removed in a method for fabricating a semiconductor device according to an embodiment of this application;

[0051] Figure 5 This is a schematic diagram illustrating the formation of a dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0052] Figure 6 This is a schematic diagram illustrating the formation of a shielding gate material in a method for fabricating a semiconductor device according to an embodiment of this application.

[0053] Figure 7 This is a schematic diagram of the removal of a portion of the thickness of the shielding gate material in the fabrication method of the semiconductor device provided in this application embodiment. Figure 1 ;

[0054] Figure 8 This is a schematic diagram of the removal of a portion of the thickness of the shielding gate material in the fabrication method of the semiconductor device provided in this application embodiment. Figure 2 ;

[0055] Figure 9 This is a schematic diagram illustrating the formation of a shielding gate in a method for fabricating a semiconductor device according to an embodiment of this application.

[0056] Figure 10 A schematic diagram illustrating the formation of an insulating material layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0057] Figure 11 A schematic diagram of removing a portion of the thickness of the insulating material layer in the method for fabricating the semiconductor device provided in the embodiments of this application;

[0058] Figure 12 A schematic diagram illustrating the formation of a first mask layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0059] Figure 13 A schematic diagram illustrating the removal of the insulating layer and part of the dielectric layer in the fabrication method of the semiconductor device provided in this application embodiment;

[0060] Figure 14 A schematic diagram of a portion of the film layer on the other sidewall of the first filled region in the method for fabricating the semiconductor device provided in the embodiments of this application;

[0061] Figure 15 This is a schematic diagram illustrating the formation of a gate dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0062] Figure 16 This is a schematic diagram of the formation of a gate in a method for fabricating a semiconductor device provided in an embodiment of this application.

[0063] Figure label:

[0064] 10: Substrate; 11: Cell region; 12: Termination region; 13: Gate trench; 14: First filling region; 15: Second filling region;

[0065] 20: Second sub-mask layer; 21: First sub-mask layer; 22: Second sub-mask layer;

[0066] 30: Photoresist layer;

[0067] 40: Dielectric layer; 41: First dielectric layer; 42: Second dielectric layer; 43: Third dielectric layer;

[0068] 50: Shielding grid; 51: Shielding grid material; 52: Intermediate layer; 53: Third filling area;

[0069] 60: Insulating layer; 61: Insulating material layer;

[0070] 70: First mask layer; 71: Mask opening;

[0071] 80: Fourth dielectric layer;

[0072] 90: Gate dielectric layer;

[0073] 100: Gate;

[0074] 110: Field oxide layer;

[0075] 120: Third mask layer.

[0076] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0077] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0078] In related technologies, an etching process is first required to remove the material layer located within the gate trench. Then, a first thermal oxidation process is performed to form a thin gate dielectric layer within the gate trench. Next, a mask layer is formed to expose the gate trench, and an etching process is performed to remove the thin gate dielectric layer on one sidewall of the gate trench. Then, a second mask layer is formed to cover the thin gate dielectric layer, and a thermal oxidation process is performed to expose the other sidewall of the gate trench, forming a thicker gate dielectric layer. This increases the number of thermal oxidation processes and mask layer layers.

[0079] To address the aforementioned technical problems, this application provides a semiconductor device and its fabrication method, as well as a power device. By improving the dielectric layer, a mask layer can be eliminated when forming the fourth dielectric layer, reducing the number of mask plates and saving on mask design and manufacturing costs. This also shortens the operation time of the photolithography process, reduces the equipment occupancy and maintenance costs of the photolithography machine, and compresses the overall process cost from both material and labor perspectives.

[0080] Furthermore, the gate dielectric layer on one side of the gate is composed of a fourth dielectric layer, and the gate dielectric layer on the other side of the gate is composed of a first dielectric layer and a fourth dielectric layer stacked together. This allows gate dielectric layers of different thicknesses to be formed on both sides of the gate. In this way, an asymmetric gate dielectric thickness is naturally formed in the same gate trench, so that the channel regions on both sides of the gate have different threshold voltages Vth. This enables zoned control of the conduction capability within the same cell, which is beneficial to optimizing the overall current distribution of the device and suppressing local current concentration.

[0081] Furthermore, under high temperature, high current and switching transient conditions, the side with a thicker gate dielectric layer has a higher threshold voltage, which can automatically receive and shunt the current, forming a self-current equalization effect inside the cell, effectively suppressing the generation of hot spots and the risk of thermal runaway, and significantly improving the thermal stability and wide safe operating area (SOA) range of the device.

[0082] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0083] Please refer to Figure 1 This application provides a method for fabricating a semiconductor device, comprising the following steps:

[0084] Step S100: Provide a substrate and pattern the substrate to form a gate trench in the substrate.

[0085] Please refer to Figure 2 The substrate 10 serves as a support component for a semiconductor device, supporting other components disposed thereon. The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. It should be noted that the substrate 10 can be a single-layer structure or a multilayer structure. For example, the substrate 10 includes a substrate and an epitaxial layer disposed on the substrate.

[0086] In some embodiments, the step of patterning the substrate 10 may further include:

[0087] A second mask layer 20 and a photoresist layer 30 are stacked on a substrate 10. It should be noted that the second mask layer 20 may include at least two sub-mask layers. Exemplarily, the mask layer 20 includes a first sub-mask layer 21 and a second sub-mask layer 22. The first sub-mask layer 21 is disposed on the substrate 10, and the second sub-mask layer 22 is disposed on the side of the first sub-mask layer 21 facing away from the substrate 10. In some embodiments of this application, both the first sub-mask layer 21 and the second sub-mask layer 22 can be made of silicon oxide. The first sub-mask layer 21, which is connected to the substrate 10, can be prepared by a first thermal oxidation process. This ensures that the first sub-mask layer 21 has high purity and quality, and makes the top surface of the first sub-mask layer 21 as flat as possible, improving the interface flatness of the first sub-mask layer 21.

[0088] Next, a second sub-mask layer 22 of a certain thickness is formed on the first sub-mask layer 21 through a deposition process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0089] Next, a photoresist layer 30 of a certain thickness is formed on the second sub-mask layer 22 by coating.

[0090] Next, please continue to refer to Figure 2 and Figure 3 A photoresist layer 30 is patterned, and a second mask layer 20 and a substrate 10 are patterned using the photoresist layer 30 as a mask to form a gate trench 13 in the substrate 10. The depth direction of the gate trench 13 extends in a direction perpendicular to the substrate 10.

[0091] In some embodiments, the substrate 10 includes adjacent cell regions 11 and terminal regions 12. The cell regions 11 are the main functional regions in a semiconductor device and typically contain multiple repeating unit structures or cells. The terminal regions 12 are regions located around the cell regions 11 and are typically used to support and protect the normal operation of the cell regions 11.

[0092] The number of gate trenches 13 is multiple, and the gate trenches 13 are arranged at intervals in the substrate 10 along the first direction, wherein each gate trench 13 spans the cell region 11 and the terminal region 12.

[0093] The extension direction of the gate trench 13 can be tilted relative to the horizontal direction, and Figure 3 The cross-sectional lines can be parallel to the horizontal direction to allow multiple gate trenches to be displayed on the cross-sectional view. That is, the first direction intersects the extension direction of the gate trench 13. Figure 3 It is a sectional view along the first direction.

[0094] In this embodiment, a portion of the gate trench 13 is located within the cell region 11, and a portion is located within the termination region 12. Figure 3 For example, from right to left, we cut out a section of the first, second and third gate trenches in cell region 11, and a section of the fourth gate trench in terminal region 12.

[0095] Next, please refer to Figure 4 The photoresist layer 30 and a portion of the thickness of the second mask layer 20 are removed. Exemplarily, the photoresist layer 30 and a portion of the thickness of the second sub-mask layer 22 are removed. This removal can be performed by a cleaning process and an etching process, or by a cleaning process and a chemical mechanical polishing process.

[0096] Step S200: Form a dielectric layer, which at least covers the inner wall of the gate trench. The dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked together. The second dielectric layer is made of silicon nitride. The dielectric layer encloses a first filling region within the gate trench. It should be understood that the following embodiments are described in detail using multiple gate trenches 13 as an example.

[0097] In some embodiments, the step of forming the dielectric layer may further include: Please refer to Figure 5 For example, a second thermal oxidation process is performed to form a first dielectric layer 41, which covers the inner walls of the plurality of gate trenches 13 and the top surface of the substrate 10 (such as a second mask layer 20 located on the top surface of the substrate 10). The material of the first dielectric layer 41 is silicon oxide.

[0098] Next, a first deposition process is performed to form a second dielectric layer 42, which covers the first dielectric layer 41. The material of the second dielectric layer 42 is silicon nitride.

[0099] Next, a second deposition process is performed to form a third dielectric layer 43, which covers the second dielectric layer 42. The material of the third dielectric layer 43 is silicon oxide, so that the dielectric layer 40 has an "ONO" structure. The dielectric layer 40 encloses a first filling region 14 within the gate trench 13.

[0100] With this setup, the different materials of the first dielectric layer 41, the third dielectric layer 43, and the second dielectric layer 42 can be used to change the etching selectivity in subsequent processes, selectively removing some film layers to reduce the number of photomasks used and reduce the number of steps in the semiconductor device fabrication process.

[0101] In some embodiments, before performing step S200 and step S300, the method for fabricating a semiconductor device further includes: forming a shielding gate, wherein the shielding gate is located within a second filling region enclosed by the dielectric layer in the gate trench, and the top surface of the shielding gate is lower than the top surface of the substrate.

[0102] Please refer to Figure 6 After step S200 is completed, a shielding gate material 51 can be formed by chemical vapor deposition. The shielding gate material 51 fills the first filling region 14 formed by the dielectric layer 40 in the gate trench 13, extends to the outside of the first filling region 14, and covers the top surface of the dielectric layer 40.

[0103] Next, please refer to Figure 7 A chemical mechanical polishing (CMP) process is performed to planarize the top surface of the shielding grid material 51, thereby removing part of the thickness of the shielding grid material 51 so that the remaining top surface of the shielding grid material 51 is flush with the top surface of the dielectric layer 40.

[0104] Next, please refer to Figure 8 The etching process is performed to remove part of the thickness of the shielding gate material 51 to form an intermediate layer 52, wherein the top surface of the intermediate layer 52 is lower than the top surface of the dielectric layer 40, so that the intermediate layer 52 and the dielectric layer 40 enclose to form a third filling area 53.

[0105] Next, please refer to Figure 9 A third mask layer 120 is formed, which is disposed on the dielectric layer 40 and covers the terminal region 12. Alternatively, the third mask layer 120 is projected orthogonally onto the substrate 10 and covers the terminal region 12.

[0106] In this step, the third mask layer 120 also fills the third fill area 53 to protect the intermediate layer 52 located in the terminal area 12.

[0107] Continue to refer to Figure 9 Using the third mask layer 120 as a mask, a third etching process is performed to remove the intermediate layer 52 located on the cell region 11, so that the remaining intermediate layer 52 forms a shielding gate 50.

[0108] In this embodiment, by taking advantage of the different materials of the dielectric layer 40 and the intermediate layer 52, the etching selectivity of the third etching process can be adjusted to remove part of the thickness of the intermediate layer 52 without damaging the dielectric layer 40 as much as possible, so as to form the shielding gate 50.

[0109] After the shielding grid 50 is formed, an insulating layer 60 is then formed. The insulating layer 60 is disposed on the shielding grid 50, and the top surface of the insulating layer 60 is lower than the top surface of the substrate 10.

[0110] In some embodiments, the step of forming the insulating layer 60 may further include:

[0111] Please refer to Figure 10 A deposition process is performed to form an insulating material layer 61, which is disposed on the shielding gate 50, extends to the outside of the gate trench 13, and covers the top surface of the dielectric layer 40.

[0112] Next, please refer to Figure 11 A chemical mechanical polishing process is performed to remove the insulating material layer 61 and the dielectric layer 40 located on the substrate 10, so that the remaining insulating material layer 61 and dielectric layer 40 are flush with the top surface of the substrate 10.

[0113] It should be noted that when a second mask layer 20 is also provided on the substrate 10, this step also removes the second mask layer 20 simultaneously.

[0114] Step S300: Form a first mask layer, the first mask layer is disposed on the substrate, and the first mask layer also has a mask opening, the mask opening exposing at least a first filling area and one sidewall of the first filling area.

[0115] Please refer to Figure 12 A first mask layer 70 can be formed on the substrate 10 and the first mask layer 70 can be patterned to form a mask opening 71 in the first mask layer 70.

[0116] The mask opening 71 exposes at least the first filling region 14 and one sidewall located within the first filling region 14. Exemplarily, when the first filling region 14 contains an insulating material layer 61, the mask opening 71 exposes the insulating material layer 61 and a dielectric layer 40 located on one side of the insulating material layer 61 in a first direction. Alternatively, in the first direction, the first filling region 14 has a first sidewall and a second sidewall disposed opposite to each other, so as to... Figure 5 Taking the orientation shown as an example, the first sidewall can be the right sidewall of the first filling area 14, and the second sidewall can be the left sidewall of the first filling area 14. At this time, the mask opening 71 can expose the first sidewall but not the second sidewall. In this way, the first sidewall constitutes one sidewall of the first filling area 14, and the second sidewall constitutes the other sidewall of the first filling area 14.

[0117] In step S400: using the first mask layer as a mask, remove the dielectric layer located on one sidewall of the first filling region to expose the wall surface of the gate trench opposite to one sidewall of the first filling region; and remove the first mask layer.

[0118] In some embodiments, when the first filling region 14 has an insulating material layer 61, step S400 may further include the following steps:

[0119] Please refer to Figure 13 Using the first mask layer 70 as a mask, a portion of the thickness of the insulating material layer 61 located in the first filling region 14 and a portion of the thickness of the dielectric layer 40 located on a sidewall of the first filling region 14 are simultaneously removed, so that the remaining insulating material layer 61 constitutes the insulating layer 60 and exposes the wall surface of the gate trench 13 opposite to a sidewall of the first filling region 14.

[0120] Afterwards, a cleaning or ashing process is performed to remove the first mask layer 70.

[0121] Step S500: Remove the second and third dielectric layers located on the other sidewall of the first filling area.

[0122] In some embodiments, the step of removing the second dielectric layer 42 and the third dielectric layer 43 located on another sidewall of the first filling region 14 includes:

[0123] Please refer to Figure 14 The first etching process is performed, using the second dielectric layer 42 as the etching stop layer, to remove the third dielectric layer 43 located on the other sidewall of the first filling area 14.

[0124] A second etching process is performed, using the first dielectric layer 41 as an etching stop layer, to remove the second dielectric layer 42 located on the other sidewall of the first filling region, while retaining the first dielectric layer 41 located on the other sidewall of the first filling region 14.

[0125] This setup allows for the use of different materials in the dielectric layer 40, and the different materials of the first dielectric layer 41, the second dielectric layer 42, and the third dielectric layer 43. By adjusting the etching selectivity ratio of the first and second etching processes, the second dielectric layer 42 and the third dielectric layer 43 can be selectively removed. This setup reduces the number of photomasks, saving on the design and manufacturing costs of photomasks, and shortening the operation time of the photolithography process. It also reduces the equipment occupancy and maintenance costs of the photolithography machine, thus compressing the overall process cost from both material and labor perspectives.

[0126] Step S600: Form a fourth dielectric layer, which covers the inner wall of the gate trench. The fourth dielectric layer and the remaining first dielectric layer constitute the gate dielectric layer.

[0127] Please refer to Figure 15 In some embodiments, a deposition process may be performed to form a fourth dielectric layer on the inner wall of the gate trench 13, the fourth dielectric layer being made of silicon oxide.

[0128] In other embodiments, a third thermal oxidation process may be performed to form a fourth dielectric layer on the inner wall of the gate trench 13, the fourth dielectric layer being made of silicon oxide.

[0129] With this configuration, the fourth dielectric layer and the retained first dielectric layer 41 constitute the gate dielectric layer 90; thus, the gate dielectric layer 90 on one side wall of the gate trench 13 is the fourth dielectric layer, and the film layer on the other side wall of the gate trench 13 is the stacked first dielectric layer 41 and the fourth dielectric layer, so that the film layers on the two side walls of the gate trench 13 have different thicknesses.

[0130] Step S700: Form a gate, which is disposed within the second filling region enclosed by the gate dielectric layer.

[0131] In some examples, please refer to Figure 16 A deposition process is performed to form a gate material layer. The gate material layer fills the second filling region 15 surrounded by the gate dielectric layer 90, extends to the outside of the second filling region 15, and covers the substrate 10.

[0132] Subsequently, a chemical mechanical polishing (CMP) process is performed to remove a portion of the gate material layer, so that the remaining gate material layer constitutes gate 100.

[0133] With this configuration, the gate dielectric layer 90 on one side of the gate 100 is composed of a fourth dielectric layer, while the gate dielectric layer 90 on the other side of the gate 100 is composed of a first dielectric layer and a fourth dielectric layer stacked together. This allows gate dielectric layers 90 of different thicknesses to be formed on both sides of the gate 100. This naturally creates an asymmetric gate dielectric thickness within the same gate trench, resulting in differentiated threshold voltages Vth in the channel regions on both sides of the gate. This enables zoned control of the conduction capability within the same cell, which is beneficial for optimizing the overall current distribution of the device and suppressing local current concentration. Furthermore, under high temperature, high current, and switching transient conditions, the thicker side of the gate dielectric layer 90, due to its higher threshold voltage, can automatically receive and shunt current, forming a self-current sharing effect within the cell. This effectively suppresses hot spot generation and the risk of thermal runaway, significantly improving the thermal stability and the DC safe operating area (SOA) range of the device.

[0134] In related technologies, an etching process is first required to remove the material layer located within the gate trench. Then, a first thermal oxidation process is performed to form a thin gate dielectric layer within the gate trench. Next, a mask layer is formed to expose the gate trench, and an etching process is performed to remove the thin gate dielectric layer on one sidewall of the gate trench. Then, a second mask layer is formed to cover the thin gate dielectric layer, and a thermal oxidation process is performed to expose the other sidewall of the gate trench, forming a thicker gate dielectric layer. This increases the number of thermal oxidation processes and mask layer layers.

[0135] In the above-mentioned semiconductor device fabrication process, by improving the film layer of dielectric layer 40, it is not necessary to form a mask layer when forming the fourth dielectric layer. This reduces the number of mask plates, saves on mask design and manufacturing costs, shortens the operation time of the photolithography process, and reduces the equipment occupation and maintenance costs of the photolithography machine. Overall process costs are compressed from both material and labor time perspectives.

[0136] It should be noted that the dielectric layer 40 retained in the gate trench 13 constitutes the field oxide layer 110, which surrounds the outer periphery of the shielding gate 50.

[0137] This application provides a semiconductor device, which is prepared by the semiconductor device preparation method described in any of the above embodiments.

[0138] Please continue to refer to this. Figure 16 Semiconductor devices include:

[0139] The substrate 10 has a gate trench 13 extending in a direction perpendicular to the substrate 10. It should be noted that there can be multiple gate trenches 13, which are arranged at intervals along a first direction.

[0140] A gate 100 is disposed within a gate trench 13. Specifically, in the extension direction perpendicular to the gate trench 13, a gate dielectric layer 90 on one side of the gate 100 includes a first dielectric layer and a fourth dielectric layer stacked together, and a gate dielectric layer 90 on the other side of the gate 100 includes a fourth dielectric layer.

[0141] In this way, an asymmetric gate dielectric thickness is naturally formed within the same gate trench, resulting in differentiated threshold voltages Vth in the channel regions on both sides of the gate. This enables zoned control of the conduction capability within the same cell, which is beneficial for optimizing the overall current distribution of the device and suppressing local current concentration. Furthermore, under high temperature, high current, and switching transient conditions, the thicker side of the gate dielectric layer 90 has a higher threshold voltage and can automatically accept and shunt current, forming a self-current sharing effect within the cell. This effectively suppresses hot spot generation and the risk of thermal runaway, significantly improving the thermal stability and DC safe operating area (SOA) range of the device.

[0142] In some possible implementations, the semiconductor device further includes a shielding gate 50 and an insulating layer 60. The shielding gate 50 is located in the gate trench 13 and below the gate 100. The insulating layer 60 is disposed between the shielding gate 50 and the gate 100 to isolate the shielding gate 50 from the gate 100 and prevent electrical connection between them. The insulating layer 60 is made of silicon nitride.

[0143] It should be noted that the semiconductor device also includes a field oxide layer 110, which is disposed within the gate trench 13 and surrounds the shielding gate 50. The field oxide layer 110 includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked together, wherein the second dielectric layer is made of silicon nitride. It should be noted that the field oxide layer 110 is a remnant of the aforementioned dielectric layers.

[0144] The embodiments of this application reduce gate-drain capacitance, decrease Miller effect, and improve switching oscillation and switching losses by shielding the high-voltage coupling between the gate and the drain.

[0145] This application provides a power device, including the semiconductor device described in any of the above embodiments. The power device provided in this application can be applied to discrete devices, AC-DC converters, or temperature sensors.

[0146] It should be noted that the beneficial effects of the power device provided in this application embodiment are the same as the beneficial effects of the semiconductor device provided in the above embodiment, and will not be elaborated further in this embodiment.

[0147] This application also provides a chip, including the semiconductor device described in any of the above embodiments. In some embodiments, the chip may be a memory power device such as dynamic random access memory (DRAM) or static random access memory (SRAM), an image sensing power device, or a processing power device.

[0148] Since the chip may include the semiconductor device provided in the third aspect of the present application, the chip has the specific structure, materials and beneficial effects of the semiconductor device, which will not be described in detail here.

[0149] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0150] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, and the substrate is patterned to form gate trenches in the substrate; A dielectric layer is formed, which at least covers the inner wall of the gate trench. The dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked together. The second dielectric layer is made of silicon nitride. The dielectric layer encloses a first filling region within the gate trench. A first mask layer is formed, the first mask layer is disposed on the substrate, and the first mask layer also has a mask opening, the mask opening exposing at least the first filling area and one sidewall of the first filling area; Using the first mask layer as a mask, the dielectric layer located on one sidewall of the first filling region is removed to expose the wall surface of the gate trench opposite to one sidewall of the first filling region; and the first mask layer is removed. Remove the second and third dielectric layers located on the other sidewall of the first filling area; A fourth dielectric layer is formed, which covers the inner wall of the gate trench, and the fourth dielectric layer and the remaining first dielectric layer constitute the gate dielectric layer; A gate is formed, wherein the gate is disposed within a second filling region enclosed by the gate dielectric layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of removing the second and third dielectric layers located on the other sidewall of the first filling area includes: Perform a first etching process, using the second dielectric layer as an etching stop layer, to remove the third dielectric layer located on the other sidewall of the first filling region; A second etching process is performed, using the first dielectric layer as an etching stop layer, to remove the second dielectric layer located on the other sidewall of the first filling region, while retaining the first dielectric layer located on the other sidewall of the first filling region.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After the step of forming the dielectric layer and before the step of forming the first mask layer, the fabrication method further includes: A shielding gate is formed, the shielding gate being located within the second filling region enclosed by the dielectric layer in the gate trench, and the top surface of the shielding gate being lower than the top surface of the substrate; An insulating layer is formed, the insulating layer being disposed on the shielding grid, and the top surface of the insulating layer being lower than the top surface of the substrate.

4. The method for fabricating a semiconductor device according to any one of claims 1-3, characterized in that, The substrate includes a cell region and a terminal region adjacent to the cell region; The number of gate trenches is multiple, and the gate trenches are arranged at intervals along a first direction within the substrate, wherein each gate trench spans the cell region and the terminal region.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The steps for providing the substrate include: A second mask layer and a photoresist layer are formed on the substrate in a stacked manner; The photoresist layer is patterned, and the second mask layer and the substrate are patterned using the photoresist layer as a mask to form a gate trench in the substrate; Remove the photoresist layer and a portion of the thickness of the second mask layer.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The step of forming the shielding barrier includes: A shielding gate material is formed, which fills the second filling area enclosed by the gate trench in the dielectric layer and covers the top surface of the dielectric layer; A portion of the shielding barrier material is removed to form an intermediate layer, the top surface of which is lower than the dielectric layer; A third mask layer is formed, which is disposed on the dielectric layer and covers the terminal area; Using the third mask layer as a mask, a third etching process is performed to remove the intermediate layer located on the cell region, so that the remaining intermediate layer forms a shielding gate.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The steps for forming an insulating layer include: An insulating material layer is formed, which is disposed on the shielding grid and covers the dielectric layer; Remove the insulating material layer and the dielectric layer located on the substrate; Using the first mask layer as a mask, a portion of the insulating material layer within the cell is removed, and the remaining insulating material layer constitutes the insulating layer.

8. A semiconductor device, characterized in that, include: A substrate having gate trenches therein; A gate, wherein the gate is disposed within the gate trench; A gate dielectric layer is disposed in the gate trench and surrounds the gate, wherein, in the extension direction perpendicular to the gate trench, the gate dielectric layer on one side of the gate includes a first dielectric layer and a fourth dielectric layer stacked thereon, and the gate dielectric layer on the other side of the gate includes a fourth dielectric layer.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a shielding gate and an insulating layer; The shielding gate is located within the gate trench and below the gate; The insulating layer is disposed between the shielding gate and the gate.

10. A power device, characterized in that, Includes the semiconductor device described in claim 8 or claim 9.

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