Display panel and display device
By setting up a flip-chip film and flexible circuit board in the OLED panel, and using a grid-like power bus and a ring VSS bus, the uneven display and burn-in risk caused by increased power line voltage drop are solved, achieving the effect of narrow bezel design and reduced production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-19
- Publication Date
- 2026-03-13
AI Technical Summary
As the amount of chip-on-film (COF) decreases, the number of power line input ports for OLED panels decreases, leading to a larger voltage drop. This increases the risk of uneven screen display and burn-in, making it difficult to achieve narrow bezel designs and reduce production costs.
A flip-chip film and a flexible circuit board are set in the bonding area of the display panel and connected to the power bus through the first and second connection line groups to increase the number of power input lines. A grid-like power bus structure and a ring VSS bus are adopted to distribute current and optimize the wiring area.
It improves the uniformity of power signals, reduces power consumption, avoids the risk of panel burn-in, and achieves an ultra-narrow bezel design, thereby improving display uniformity and reliability.
Smart Images
Figure CN121665858A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology
[0002] With the continuous development of display technology, organic light-emitting diode (OLED) displays... OLED (Optical Display Panel) panels are becoming increasingly popular with users. To reduce the bezel of OLED panels, a chip-on-film (COF) membrane can be used to connect the driver chip on the back of the OLED panel to the display device on the OLED panel.
[0003] To reduce the manufacturing cost of COF-type OLED panels, the number of COFs on the OLED panel can be reduced. However, as the number of COFs decreases, the number of power line input ports on the OLED panel decreases, resulting in a larger voltage drop on the power lines. This can easily cause uneven screen display and increase the risk of burn-in. Summary of the Invention
[0004] This application provides a display panel and a display device that improves the uniformity of power signals throughout the display area, thereby improving the display uniformity of the display panel. At the same time, it can reduce the power consumption of the entire display panel and avoid the risk of panel burn-out caused by excessively high local power signals.
[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, including a display area and a non-display area disposed around the display area, the non-display area including a bonding area located on one side of the display area and a wiring area located between the display area and the bonding area; the display panel includes: At least one power line located in the display area; The flip-chip film and at least one flexible circuit board are located in the bonding region; The wiring area includes at least one power bus, at least one first connection group, and at least one second connection group; both the first connection group and the second connection group include at least one power connection line. The flip-chip film is electrically connected to the power line via at least one first connection line group and the power bus in sequence, and the flexible circuit board is electrically connected to the power line via at least one second connection line group and the power bus in sequence. Furthermore, the flip-chip film and the flexible circuit board are both located on the same side of the power bus away from the display area.
[0006] Optionally, at least some of the power connection wires in the second connection wire group are wider than the power connection wires in the first connection wire group.
[0007] Optionally, the power line includes a first power line, the power bus includes a first power bus; the first connection line group includes at least one first power connection line, and the second connection line group includes at least one second power connection line. The flip-chip film is electrically connected to the first power line in sequence via the first power connection line and the first power bus, and the flexible circuit board is electrically connected to the first power line in sequence via the second power connection line and the first power bus.
[0008] Optionally, the first power bus is arranged in a grid pattern, and the ends of the first power connection line and the second power connection line away from the bonding area are electrically connected to the side of the first power bus near the bonding area, and the first power connection line and the second power connection line are arranged on the same layer.
[0009] Optionally, the first power bus extends along a first direction, the first power connection line and the second power connection line extend along a second direction, and the first direction and the second direction are perpendicular to each other.
[0010] Optionally, the power line further includes a second power line, the power bus further includes a second power bus, and the first power line and the second power line are configured to be connected to different voltages; the first connection line group further includes at least one third power connection line, and the second connection line group further includes at least one fourth power connection line. The flip-chip film is electrically connected to the second power line in sequence via the third power connection line, the second power bus, and the flexible circuit board is electrically connected to the second power line in sequence via the fourth power connection line, the second power bus, and the second power line.
[0011] Optionally, the second power bus is disposed in a manner that at least partially overlaps with the first power bus in the thickness direction of the display panel; The second power bus extends along the first direction, the third power connection line and the fourth power connection line are arranged on the same layer and extend along the second direction, and the first direction and the second direction are perpendicular to each other.
[0012] Optionally, the power bus further includes a third power bus extending around the display area, and the second power bus and the third power bus are configured to access the same voltage; The first connection line group further includes at least one fifth power connection line, and the second connection line group further includes at least one sixth power connection line; the flip-chip film is electrically connected to the second power line in sequence through the fifth power connection line and the third power bus, and the flexible circuit board is electrically connected to the second power line in sequence through the sixth power connection line and the third power bus.
[0013] Optionally, the third power connection line, the fourth power connection line, the fifth power connection line, and the sixth power connection line are arranged on the same layer.
[0014] Optionally, in the wiring area, the third power bus is located on the side of the first power bus near the bonding area, the third power bus extends along a first direction, the fifth power connection line and the sixth power connection line extend along a second direction, and the first direction and the second direction are perpendicular to each other; The third power bus has a first opening and a second opening at positions corresponding to the first connection line group and the second connection line group, respectively; the first power connection line and the third power connection line in the same first connection line group are located between two adjacent fifth power connection lines and pass through the first opening in the direction towards the display area, and the second power connection line and the fourth power connection line in the same second connection line group are located between two adjacent sixth power connection lines and pass through the second opening in the direction towards the display area.
[0015] Optionally, the display panel further includes a driving transistor and a light-emitting device located in the display area, the light-emitting device including an anode and a cathode; the first power line is electrically connected to the first electrode of the driving transistor, the second electrode of the driving transistor is electrically connected to the anode of the light-emitting device, and the second power line is electrically connected to the cathode of the light-emitting device.
[0016] Optionally, at least a portion of the power supply connection lines in the first connection line group and the second connection line group are disposed on the same layer as the first electrode and the second electrode of the driving transistor.
[0017] Optionally, the number of flexible circuit boards is even, and the multiple flexible circuit boards are symmetrically distributed on opposite sides of the flip-chip film.
[0018] According to a second aspect of this application, a display device is provided, the display device comprising the display panel described above.
[0019] In the display panel and display device of this application, by simultaneously setting a flip-chip film and a flexible circuit board in the bonding area of the display panel, and correspondingly, providing a first connecting line group and a second connecting line group in the wiring area of the display panel, which are electrically connected to the flip-chip film and the flexible circuit board respectively, and electrically connected to the power lines in the display area through the power bus in the wiring area, thereby realizing the transmission of power signals; this setting effectively increases the number of power input lines in the non-display area, thereby distributing the power signals to multiple lines, which helps to reduce the voltage drop on the power lines in the display area, thereby improving the uniformity of the power signals in the entire display area, thus improving the display uniformity of the display panel, and at the same time, reducing the power consumption of the entire display panel and avoiding the risk of panel burn-out caused by excessive local power signals.
[0020] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0022] Figure 1 This is a top view schematic diagram of an exemplary integrated circuit driven display panel; Figure 2 This is a top view schematic diagram of an exemplary flip-chip thin-film driven display panel; Figure 3 This is a top view of a display panel provided in an embodiment of this application; Figure 4 yes Figure 3 Enlarged schematic diagram of part P in the middle; Figure 5 yes Figure 3 Enlarged schematic diagram of the Q section; Figure 6 This is a circuit diagram of a driving circuit unit provided in an embodiment of this application; Figure 7 This is a partial cross-sectional structural diagram of a display panel provided in an embodiment of this application; Figure 8 This is a partial cross-sectional structural diagram of a display device provided in an embodiment of this application.
[0023] Explanation of reference numerals in the attached figures: 1. Display panel; 2. Power cord; 2a. First power cord; 2b. Second power cord; 3. Chip-coated film; 4. Flexible circuit board; 5. Power bus; 5a. First power bus; 5b. Second power bus; 5c. Third power bus; 6. First connecting wire group; 7. Second connecting wire group; 8. Power connection line; 8a. First power connection line; 8b. Second power connection line; 8c. Third power connection line; 8d. Fourth power connection line; 8e. Fifth power connection line; 8f. Sixth power connection line; 9. First power trunk line; 10. First power branch line; 11. First opening; 12. Second opening; 13. Reset line; 13a. First reset line; 13b. Second reset line; 14. Reset bus; 14a. First reset bus; 14b. Second reset bus; 5. First reset connection line; 16. Second reset connection line; 17. Third opening; 18. Driving transistor; 19. Light-emitting device; 20. Anode; 21. Cathode; 22. Driving circuit unit; 23. Array substrate; 24. Substrate layer; 25. Active layer; 26. First insulating layer; 27. First gate layer; 28. Second insulating layer; 29. Second gate layer; 30. Third insulating layer; 31. First source / drain electrode layer; 32. First passivation layer; 33. First planarization layer; 34. Second source / drain electrode layer; 35. Second planarization layer; 36. First gate; 37. Second gate; 38. Source; 39. Drain; 40. Pixel definition layer; 41. Organic functional layer; 42. Pixel opening; 43. Display device; 44. Housing; 45. Protective layer; 46. Connecting electrode; AA, Display area; NAA, Non-display area; BA, Bonding area; FA, Wiring area; X, First direction; Y, Second direction. Detailed Implementation
[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0025] Figure 1 This is a top view schematic diagram of an exemplary integrated circuit (IC) driven display panel. (Right) Figure 1 It can be seen that multiple (e.g., two) IC chips are bonded to the lower bezel of the display panel to provide drive signals to the display area AA. Figure 1In the display panel shown, the number of VDD and VSS input lines from the two IC chips on the bottom bezel are both 10. This helps improve the voltage uniformity of the VDD and VSS signal lines in the display area AA, avoiding increased power consumption, uneven display, and the risk of burn-in caused by excessive voltage drop (IR drop). However, Figure 1 In the display panel shown, the bottom bezel of the display panel is relatively wide because the IC chip needs to be bonded to it, which is not conducive to achieving a narrow bezel design.
[0026] It should be noted that the number of incoming lines mentioned in the embodiments of this application refers to the number of signal transmission channels.
[0027] To achieve a narrow bezel design, IC chips are typically integrated and packaged on a flexible thin film, allowing the IC chip to be bent to the back of the screen, thus achieving an ultra-narrow bezel design. The technology for integrating and packaging IC chips on a flexible thin film is called chip-on-film (COF) technology. Figure 2 This is a top view schematic diagram of an exemplary flip-chip thin-film driven display panel.
[0028] To reduce the production cost and power consumption of display panels and improve production efficiency, the number of COFs can be reduced. Figure 2 The display panel shown is driven by a single COF. Since the total length of the COF and the port size on the COF are fixed, that is, the total number of input ports on the COF is fixed, the number of input ports allocated to the VDD and VSS signals is limited. This results in a significant reduction in the number of VDD and VSS input lines of the entire display panel, which in turn leads to an increase in the voltage drop of VDD and / or VSS. This causes the voltage uniformity of the VDD and / or VSS signal lines in the display area AA to deteriorate, resulting in problems such as increased power consumption, uneven display, and increased risk of burn-in.
[0029] It's important to note that voltage drop refers to the voltage loss caused by factors such as line resistance during current transmission. Due to the reduced number of COFs (Chip-on-Flush) connections, the number of input ports for VDD and VSS decreases, requiring each channel to carry a larger current. This exacerbates resistance losses, resulting in a significant increase in the voltage drop across VDD and / or VSS. Increased voltage drop leads to poorer consistency in the power supply voltage across different areas of the screen. This can cause variations in screen brightness and color across different areas, such as localized dark areas or color differences. Furthermore, a large and uneven voltage drop increases energy loss on the lines, and localized areas may overheat due to concentrated current and excessive power. Over time, this increases the risk of burning out internal screen components (such as the driver circuitry and display panel).
[0030] To address the aforementioned issues, this application adds a flexible circuit board, such as a flexible printed circuit (FPC), while maintaining the same number of COFs. The flexible circuit board has VDD and VSS input ports, thereby increasing the number of VDD and VSS inputs and reducing the voltage drop of VDD and VSS. This solves the problems of high power consumption, uneven display, and increased risk of burn-in caused by excessive VDD and VSS voltage drops. Furthermore, this application optimizes the wiring in the display panel's wiring area, which further helps to reduce the voltage drop of VDD and VSS.
[0031] like Figures 3 to 5 As shown, this application embodiment provides a display panel 1, which includes a display area AA and a non-display area NAA surrounding the display area AA. The non-display area NAA includes a bonding area BA located on one side of the display area AA and a wiring area FA located between the display area AA and the bonding area BA.
[0032] Specifically, the display panel 1 includes: at least one power line 2 located in the display area AA; a chip-on-film (COF) 3 and at least one flexible circuit board 4 located in the bonding area BA; and at least one power bus 5, at least one first connection line group 6, and at least one second connection line group 7 located in the wiring area FA. Both the first connection line group 6 and the second connection line group 7 include at least one power connection line 8. The COF 3 is electrically connected to the power line 2 sequentially via the at least one first connection line group 6 and the power bus 5, and the flexible circuit board 4 is electrically connected to the power line 2 sequentially via the at least one second connection line group 7 and the power bus 5. Furthermore, both the COF 3 and the flexible circuit board 4 are located on the same side of the power bus 5 away from the display area AA.
[0033] Understandably, one end of the power connection line 8 in the first connection line group 6 is electrically connected to the corresponding flip-chip film 3, and the other end is electrically connected to the power bus 5; one end of the power connection line 8 in the second connection line group 7 is electrically connected to the corresponding flexible circuit board 4, and the other end is electrically connected to the power bus 5. Therefore, the flip-chip film 3 can be electrically connected to the power line 2 in the display area AA in sequence through the power connection line 8 and the power bus 5 in the first connection line group 6, thereby realizing the transmission of power signals; at the same time, the flexible circuit board 4 can be electrically connected to the power line 2 in the display area AA in sequence through the power connection line 8 and the power bus 5 in the second connection line group 7, thereby realizing the transmission of power signals.
[0034] In some embodiments, the flexible circuit board 4 is selected from flexible printed circuit boards (FPCs), but is not limited thereto.
[0035] In this embodiment, a flexible circuit board 4 is added to the crystal-coated film 3. The crystal-coated film 3 and the flexible circuit board 4 simultaneously provide power signals to the power lines 2 in the display area AA, effectively increasing the number of power input lines in the non-display area NAA. This allows the power signals to be distributed across multiple lines, which helps reduce the voltage drop on the power lines 2 in the display area AA. This, in turn, helps improve the uniformity of the power signals in the entire display area AA, thereby improving the display uniformity of the display panel 1. At the same time, it can avoid the risk of panel burn caused by excessively high local power signals.
[0036] Understandably, the flip-chip film 3 has input ports that are electrically connected one-to-one with the multiple power connection lines 8 in the first connection line group 6, and the flexible circuit board 4 has input ports that are electrically connected one-to-one with the multiple power connection lines 8 in the second connection line group 7. Clearly, the number of input ports for providing power signals in the display panel 1 provided in this embodiment of the application is effectively increased.
[0037] In some embodiments, the non-display area NAA of the display panel 1 includes an upper border area and a lower border area disposed opposite to each other along the second direction Y. The bonding area BA and the wiring area FA are both located in the lower border area of the display panel 1 and are located on the same side of the power bus 5 away from the display area AA.
[0038] In this embodiment, by placing both the flip-chip film 3 and the flexible circuit board 4 on the same side of the display area AA, it is possible to achieve an ultra-narrow bezel design on the bottom bezel while effectively achieving an extremely narrow bezel design on the other three sides.
[0039] In some embodiments, at least a portion of the power connection lines 8 in the second connection line group 7 are wider than the power connection lines 8 in the first connection line group 6. That is, at least a portion of the power connection lines 8 electrically connected to the flexible circuit board 4 are wider than the power connection lines 8 electrically connected to the flip-chip film 3.
[0040] In a preferred embodiment, the width of any power connection line 8 in the second connection line group 7 is greater than the width of any power connection line 8 in the first connection line group 6.
[0041] It should be noted that, due to limitations in manufacturing processes, the total number of input ports on the flip-chip film 3 is fixed. Since the flip-chip film 3 typically also needs to transmit data signals and GOA signals, the width of the input ports used for power signal transmission is limited, resulting in a smaller width of the power connection lines 8 in the first connection group 6 leading from the input ports of the flip-chip film 3. In this case, the voltage uniformity and voltage drop on the power lines 2 are poor. However, this embodiment of the application compensates for the voltage drop of the power signal by increasing the width of the power connection lines 8 in the second connection group 7 leading from the flexible printed circuit board (FPC) 4, thereby reducing the overall voltage drop of the power signal.
[0042] In some embodiments, the flexible circuit board 4 is used only for transmitting power signals, which allows for a greater number of power input ports on the flexible circuit board 4 for transmitting power signals, and / or a greater width of the power input ports, thereby enabling the width of any power connection line 8 in the second connection line group 7 to be greater than the width of any power connection line 8 in the first connection line group 6.
[0043] In some embodiments, the power line 2 includes a first power line 2a, the power bus 5 includes a first power bus 5a, the first connection line group 6 includes at least one first power connection line 8a, and the second connection line group 7 includes at least one second power connection line 8b. The flip-chip film 3 is electrically connected to the first power line 2a in sequence via the first power connection line 8a and the first power bus 5a, and the flexible circuit board 4 is electrically connected to the first power line 2a in sequence via the second power connection line 8b and the first power bus 5a.
[0044] In some embodiments, the first power line 2a is a VDD line, meaning that the first power line 2a is configured to connect to a high-level signal. In this case, the first power bus 5a is a VDD bus, and both the first power connection line 8a and the second power connection line 8b are VDD connection lines.
[0045] Understandably, one end of the first power connection line 8a is electrically connected to the flip-chip film 3, and the other end is electrically connected to the first power bus 5a; one end of the second power connection line 8b is electrically connected to the flexible circuit board 4, and the other end is electrically connected to the first power bus 5a; the first power bus 5a is electrically connected to the first power line 2a.
[0046] In this embodiment, the flexible circuit board 4 and the second connecting line group 7 are provided to increase the number of traces used to transmit the VDD signal, which helps to reduce the voltage drop of the VDD signal and thus improves the uniformity of the VDD signal in the display area AA.
[0047] In some embodiments, the first power bus 5a is arranged in a grid pattern, and the ends of the first power connection line 8a and the second power connection line 8b away from the bonding area BA are electrically connected to the side of the first power bus 5a close to the bonding area BA, and the first power connection line 8a and the second power connection line 8b are arranged on the same layer.
[0048] In other words, the first power connection line 8a is located between the first power bus 5a and the flip-chip film 3, and the second power connection line 8b is located between the first power bus 5a and the flexible circuit board 4.
[0049] It should be noted that the same-layer arrangement described in the embodiments of this application refers to materials that are the same and formed in the same process.
[0050] In this embodiment, the first power bus 5a is configured as a mesh structure, transforming the VDD power supply from a few input points to a multi-point distributed power supply. This significantly shortens the current transmission distance and reduces voltage drops caused by accumulated line resistance. The intersecting lines in the mesh structure form redundant power supply paths. When the current on a certain line is too high, it can be shunted by adjacent lines, preventing excessive local voltage drops and resulting in a more uniform VDD voltage across the entire display panel 1, thereby improving display brightness and color uniformity. Simultaneously, due to the high redundancy of the mesh structure, if a section of the line fails (such as poor contact or breakage), the current can be transmitted through other paths, preventing localized power outages and improving power supply reliability. Furthermore, the distributed current distribution reduces the current load on individual lines, lowering the risk of localized overheating due to current concentration and reducing the risk of component burnout, making it particularly suitable for the high current requirements of high-resolution, high-refresh-rate panels.
[0051] In some embodiments, the first power bus 5a extends along a first direction X, and the first power connection line 8a and the second power connection line 8b extend along a second direction Y, with the first direction X and the second direction Y being perpendicular to each other. The extension directions of the first power connection line 8a and the second power connection line 8b are perpendicular to the extension direction of the first power bus 5a, which helps to simplify the manufacturing process of the power connection line 8a and can reduce the length of the first power connection line 8a and the second power connection line 8b, which helps to further reduce the VDD voltage drop.
[0052] In one specific embodiment, the first power bus 5a includes multiple first power trunk lines 9 extending along the first direction X. The multiple first power trunk lines 9 are spaced apart in the second direction Y, and any two adjacent first power trunk lines 9 are connected by multiple first power branch lines 10 to form a grid-like bus.
[0053] Understandably, the first power connection line 8a and the second power connection line 8b are electrically connected to the first power trunk line 9 on the side of the first power bus 5a near the bonding area BA. This design helps to simplify the wiring in the wiring area FA, reduce the manufacturing difficulty of the first power connection line 8a and the second power connection line 8b, and reduce the length of the first power connection line 8a and the second power connection line 8b, thereby further reducing the VDD voltage drop.
[0054] In some embodiments, the first power connection line 8a, the second power connection line 8b, and the first power bus 5a are arranged on the same layer. This design can simplify the manufacturing process of the power connection line 8, which is beneficial to improving panel manufacturing efficiency and saving panel manufacturing costs.
[0055] In some embodiments, power line 2 further includes a second power line 2b, power bus 5 further includes a second power bus 5b, and the first power line 2a and the second power line 2b are configured to be connected to different voltages. The first connection group 6 further includes at least one third power connection line 8c, and the second connection group 7 further includes at least one fourth power connection line 8d. The flip-chip film 3 is electrically connected to the second power line 2b sequentially via the third power connection line 8c and the second power bus 5b, and the flexible circuit board 4 is electrically connected to the second power line 2b sequentially via the fourth power connection line 8d and the second power bus 5b.
[0056] In some embodiments, the second power line 2b is a VSS line, meaning that the second power line 2b is configured to connect to a low-level signal. In this case, the second power bus 5b is a VSS bus, and both the third power connection line 8c and the fourth power connection line 8d are VSS connection lines.
[0057] Understandably, one end of the third power connection line 8c is electrically connected to the flip-chip film 3, and the other end is electrically connected to the second power bus 5b; one end of the fourth power connection line 8d is electrically connected to the flexible circuit board 4, and the other end is electrically connected to the second power bus 5b; the second power bus 5b is electrically connected to the second power line 2b.
[0058] In this embodiment, the flexible circuit board 4 and the second connecting line group 7 are provided to increase the number of traces used to transmit the VSS signal, which helps to reduce the voltage drop of the VSS signal and thus improves the uniformity of the VSS signal in the display area AA.
[0059] In some embodiments, the second power bus 5b is at least partially overlapped with the first power bus 5a in the thickness direction of the display panel 1; the second power bus 5b extends along the first direction X, the third power connection line 8c and the fourth power connection line 8d are disposed on the same layer and extend along the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.
[0060] Understandably, the first power bus 5a and the second power bus 5b are insulated from each other. By placing the first power bus 5a and the second power bus 5b in different metal layers, the second power bus 5b can be arranged to at least partially overlap with the first power bus 5a in the thickness direction of the display panel 1, and the two can be avoided from being electrically connected.
[0061] In some embodiments, the third power connection line 8c, the fourth power connection line 8d, and the second power bus 5b are arranged on the same layer. This design simplifies the manufacturing process of the power connection line 8, which helps improve panel manufacturing efficiency and save panel manufacturing costs.
[0062] In some embodiments, the first power connection line 8a, the second power connection line 8b, and the first power bus 5a are disposed in the first metal layer, and the third power connection line 8c, the fourth power connection line 8d, and the second power bus 5b are disposed in the second metal layer. An insulating layer is provided between the first metal layer and the second metal layer. This design can effectively prevent the first power bus 5a and the second power bus 5b from being short-circuited, thereby improving the transmission stability of the VDD signal and the VSS signal.
[0063] In other embodiments, the first power connection line 8a, the second power connection line 8b, the third power connection line 8c, and the fourth power connection line 8d are arranged on the same layer, while the first power bus 5a and the second power bus 5b are arranged on different layers. This design can further simplify the manufacturing process of the power connection line 8, which is beneficial to improving panel manufacturing efficiency and saving panel manufacturing costs.
[0064] Specifically, when the first power bus 5a and the second power bus 5b are arranged on different layers, and the first power connection line 8a, the second power connection line 8b, and the first power bus 5a are arranged on the same layer, among the third power connection line 8c and the fourth power connection line 8d, the portion of the connection line that does not coincide with the first power bus 5a in the thickness direction of the display panel 1 is arranged on the same layer as the first power connection line 8a and the second power connection line 8b, and the portion of the connection line that coincides with the first power bus 5a in the thickness direction of the display panel 1 is arranged on the same layer as the first power connection line 8a and the second power connection line 8b. It can be understood that the portion of the connection line that coincides with the first power bus 5a in the thickness direction of the display panel 1 can be considered as a bridging wire.
[0065] In some embodiments, the power bus 5 further includes a third power bus 5c, which extends to surround the display area AA, and the second power bus 5b and the third power bus 5c are configured to receive the same voltage. The first connection line group 6 further includes at least one fifth power connection line 8e, and the second connection line group 7 further includes at least one sixth power connection line 8f. The flip-chip film 3 is electrically connected to the second power line 2b in sequence via the fifth power connection line 8e and the third power bus 5c, and the flexible circuit board 4 is electrically connected to the second power line 2b in sequence via the sixth power connection line 8f and the third power bus 5c.
[0066] Understandably, the third power bus 5c is also the VSS bus, used to transmit the VSS signal. Typically, the VSS bus can also be referred to as the ground bus.
[0067] Specifically, because the non-display area (NAA) of display panel 1 contains a large number of signal lines (such as gate drive signals, data signals, and VDD signals), these lines are susceptible to external electromagnetic interference (such as electromagnetic waves in the environment and radiation from other electronic components) during transmission. A closed VSS bus acts as a grounding shielding ring, which can absorb or block external interference signals, preventing them from intruding into sensitive internal circuits (such as pixel drive transistors and COF), and ensuring the accuracy of signal transmission.
[0068] Furthermore, as a grounding wire, the VSS bus needs to provide a low-impedance return path for the current of the entire display panel 1. A ring-shaped VSS bus located in the non-display area NAA can distribute grounding nodes around the perimeter of the panel, shortening the grounding distance in each area (especially edge pixels) and reducing resistance loss during current return. The ring structure also makes the grounding loop more balanced, avoiding voltage fluctuations caused by poor grounding in localized areas, indirectly improving the uniformity of VDD / VSS voltage and enhancing the consistency of display brightness.
[0069] Furthermore, the non-display area (NAA) of the display panel (especially flexible OLED) 1 is a densely packed area of lines. The ring-shaped VSS bus can serve as a common ground reference point, unifying the voltage reference (0V) of each area and avoiding signal conflicts caused by differences in ground potential between different areas (such as chaotic output signal levels of the driver IC). For large-size panels, the ring-shaped VSS bus can also share some of the grounding current, reducing the load on a single grounding line, reducing localized heating caused by current concentration, and improving the long-term reliability of the panel.
[0070] In addition, the non-display area (NAA) is a transitional area between the panel and external devices (such as driver boards and housings), which is prone to static electricity accumulation. The ring-shaped VSS bus can serve as an electrostatic discharge channel, quickly releasing static charge through grounding and preventing electrostatic discharge from damaging internal precision components.
[0071] Therefore, by setting a ring of third power bus 5c in the non-display area NAA of the display panel 1, the grounding performance can be optimized, the signal anti-interference capability can be enhanced, and the display stability and reliability can be improved.
[0072] In some embodiments, the third power connection line 8c, the fourth power connection line 8d, the fifth power connection line 8e, and the sixth power connection line 8f are arranged on the same layer. This design can simplify the manufacturing process of the power connection lines 8, which is beneficial to improving panel manufacturing efficiency and saving panel manufacturing costs.
[0073] In some embodiments, in the wiring area FA, the third power bus 5c is located on the side of the first power bus 5a near the bonding area BA. The third power bus 5c extends along the first direction X, and the fifth power connection line 8e and the sixth power connection line 8f extend along the second direction Y, with the first direction X and the second direction Y being perpendicular to each other.
[0074] The third power bus 5c has a first opening 11 and a second opening 12 at positions corresponding to the first connection group 6 and the second connection group 7, respectively. The first power connection line 8a and the third power connection line 8c in the same first connection group 6 are located between two adjacent fifth power connection lines 8e and pass through the first opening 11 in the direction of the display area AA. The second power connection line 8b and the fourth power connection line 8d in the same second connection group 7 are located between two adjacent sixth power connection lines 8f and pass through the second opening 12 in the direction of the display area AA.
[0075] Understandably, the first opening 11 and the second opening 12 are designed to avoid the third power bus 5c from intersecting with the first power connection line 8a, the second power connection line 8b, the third power connection line 8c and the fourth power connection line 8d. This avoids crosstalk between different signals and simplifies the manufacturing process of the power connection line 8.
[0076] When the third power bus 5c is arranged on a different layer from the first power connection line 8a, the second power connection line 8b, the third power connection line 8c and the fourth power connection line 8d, the first power connection line 8a and the third power connection line 8c in the same first connection line group 6 are arranged to coincide with the first opening 11 in the thickness direction of the display panel 1, and the second power connection line 8b and the fourth power connection line 8d in the same second connection line group 7 are arranged to coincide with the second opening 12 in the thickness direction of the display panel 1.
[0077] When the third power bus 5c is arranged on the same layer as the first power connection line 8a, the second power connection line 8b, the third power connection line 8c and the fourth power connection line 8d, the first power connection line 8a and the third power connection line 8c in the same first connection line group 6 are located between two adjacent fifth power connection lines 8e and pass through the first opening 11 in the direction of the display area AA. The second power connection line 8b and the fourth power connection line 8d in the same second connection line group 7 are located between two adjacent sixth power connection lines 8f and pass through the second opening 12 in the direction of the display area AA.
[0078] Understandably, in order to ensure that the third power bus 5c is a closed loop structure in the direction surrounding the display area AA, the third power bus 5c needs to be connected in series with the flip-chip film 3 through two oppositely arranged fifth power connection lines 8e at the opening position of the first opening 11, and the third power bus 5c needs to be connected in series with the flexible circuit board 4 through two oppositely arranged sixth power connection lines 8f at the opening position of the second opening 12.
[0079] In some embodiments, the flip-chip film 3 is provided with two first connection line groups 6, and the third power bus 5c is provided with two first openings 11 at the corresponding positions of the flip-chip film 3. At each opening position of the first opening 11, the third power bus 5c needs to be connected in series with the flip-chip film 3 through two oppositely arranged fifth power connection lines 8e. This arrangement increases the number of fifth power connection lines 8e, which is beneficial to further increase the number of VSS input lines, thereby further reducing the VSS voltage drop.
[0080] In some embodiments, the display panel 1 further includes at least one reset line 13 located in the display area AA and a reset bus 14 located in the wiring area FA, and the first connection line group 6 further includes at least one reset connection line. The flip-chip film 3 is electrically connected to the reset line 13 of the display area AA in sequence through the reset connection line and the reset bus 14.
[0081] In some embodiments, the reset line 13 includes a first reset line 13a and a second reset line 13b, the reset bus 14 includes a first reset bus 14a and a second reset bus 14b, and the first connection line group 6 includes at least one first reset connection line 15 and at least one second reset connection line 16. The first reset line 13a is an anode reset line, and the second reset line 13b is a gate reset line. The flip-chip film 3 is electrically connected to the first reset line 13a of the display area AA in sequence through the first reset connection line 15 and the first reset bus 14a, and the flip-chip film 3 is electrically connected to the second reset line 13b of the display area AA in sequence through the second reset connection line 16 and the second reset bus 14b.
[0082] It should be noted that the appendix to this application Figure 3In the display area AA, the first power line 2a, the second power line 2b, the first reset line 13a, and the second reset line 13b are only used to indicate that the display area AA has these signal lines, and are not used to limit the position and number of signal lines.
[0083] In some embodiments, at least one third opening 17 is provided on the first power trunk line 9, at least on the side closest to the bonding area BA, in the first power bus 5a. The third power connection line 8c, the first reset connection line 15, and the second reset connection line 16 are arranged to coincide with the third opening 17 in the thickness direction of the display panel 1. This design can reduce or avoid the cross-sectional area of the first power bus 5a with other signal lines, and avoid crosstalk between different signals.
[0084] In some embodiments, the display panel 1 further includes a VDD bus, a VSS bus, a gate reset bus, and an anode reset bus located in the upper bezel area, for further improving the uniformity of power signals in the entire display panel 1, thereby improving the uniformity of display brightness.
[0085] In some embodiments, the number of flexible circuit boards 4 is an even number; in the first direction X, the multiple flexible circuit boards 4 are symmetrically distributed on opposite sides of the flip-chip film 3. By symmetrically distributing the multiple flexible circuit boards 4 on opposite sides of the flip-chip film 3, the power input lines on both sides can be symmetrically arranged, which is beneficial to improving the uniformity of the power signal of the entire display panel 1, thereby improving the brightness uniformity of the display panel 1.
[0086] In one specific embodiment, there is one flip-chip film 3 and two flexible circuit boards 4. It can be understood that, in the first direction X, the two flexible circuit boards 4 are symmetrically arranged on both sides of the flip-chip film 3.
[0087] Of course, in other embodiments, the number of flexible circuit boards 4 can be 4 or 6 or even more, depending on the size of the display panel 1.
[0088] In other embodiments, the number of flip-chip films 3 may also be multiple. In this case, the multiple flip-chip films 3 are treated as a whole, and in the first direction X, the multiple flexible circuit boards 4 are symmetrically distributed on both sides of the multiple flip-chip films 3.
[0089] It should be noted that the main problem this application aims to solve is the increased VDD and VSS voltage drops caused by a single COF, because when there are many COFs, the VDD and VSS voltage drops usually do not worsen. Of course, this application is also applicable when there are multiple COFs and the problem of worsened VDD and VSS voltage drops exists.
[0090] In one specific implementation, such as Figure 3As shown, there is one flip-chip film 3 and two flexible circuit boards 4. Figure 4 As shown, two first connection line groups 6 are provided between the flip-chip film 3 and the display area AA. Each first connection line group 6 includes two first power connection lines 8a, one third power connection line 8c, and two fifth power connection lines 8e. Figure 5 As shown, each flexible circuit board 4 is provided with a second connection line group 7 between it and the display area AA. The second connection line group 7 includes two second power connection lines 8b, one fourth power connection line 8d, and two sixth power connection lines 8f.
[0091] Therefore, the number of VDD lines leading from the bonding area BA of display panel 1 is 8, and the number of VSS lines leading from the bonding area BA of display panel 1 is 10. Figure 2 Compared to the display panel shown, the display panel 1 provided in this application embodiment has a significantly increased number of VDD and VSS input lines, which can effectively reduce the VDD and VSS voltage drop of the display panel 1.
[0092] In some embodiments, at least one first connection line group 6 electrically connected to the same flip-chip film 3 is symmetrically arranged about a first axis of symmetry L1, which extends along a second direction Y. A plurality of second connection line groups 7 are also symmetrically arranged about the first axis of symmetry L1. This design helps improve the signal uniformity of the entire display panel 1, thereby improving the uniformity of the display brightness of the display panel 1.
[0093] In some embodiments, each second connection line group 7 is symmetrically arranged about a second axis of symmetry, and the second axis of symmetry extends along a second direction Y. This design is beneficial for further improving the signal uniformity of the entire display panel 1, thereby improving the display brightness uniformity of the display panel 1.
[0094] In some embodiments, such as Figure 7 As shown, the display panel 1 also includes a driving transistor 18 and a light-emitting device 19 located in the display area AA. The light-emitting device 19 includes an anode 20 and a cathode 21. A first power line 2a is electrically connected to the first electrode of the driving transistor 18, a second electrode of the driving transistor 18 is electrically connected to the anode 20 of the light-emitting device 19, and a second power line 2b is electrically connected to the cathode 21 of the light-emitting device 19.
[0095] Understandably, when the driving transistor 18 is turned on, the first power line 2a provides a high-level signal to the anode 20 of the light-emitting device 19 through the driving transistor 18, and the second power line 2b provides a low-level signal to the cathode 21 of the light-emitting device 19, thereby driving the light-emitting device 19 to emit light.
[0096] In some embodiments, the light-emitting device 19 is an OLED device, but is not limited thereto.
[0097] In some embodiments, at least a portion of the power connection lines 8 in the first connection line group 6 and the second connection line group 7 are disposed on the same layer as the first electrode and the second electrode of the driving transistor 18.
[0098] In some embodiments, the display panel 1 further includes a plurality of driving circuit units 22 and a plurality of light-emitting devices 19 located in the display area AA. Each driving circuit unit 22 is electrically connected to at least one light-emitting device 19 and is used to drive the light-emitting device 19 to emit light. Each driving circuit unit 22 includes at least one capacitor and a plurality of transistors, one of which is the aforementioned driving transistor 18.
[0099] In some embodiments, the display panel 1 includes an array substrate 23 and a plurality of light-emitting devices 19 disposed on the array substrate 23, and a plurality of driving circuit units 22 disposed in the array substrate 23. Figure 6 As shown, the array substrate 23 also includes a data line Data, a scan line Scan(n), a first reset line VI-ANO, a second reset line VI-Q, a first power line VDD, a second power line VSS, a first reset control line Reset-ANO, a second reset control line Reset-Q, and a light emission control line EM.
[0100] It should be noted that the number of transistors in the driving circuit unit 22 is not limited in the embodiments of this application.
[0101] This application uses a 7T1C driving circuit as an example to illustrate the structure of the driving circuit unit 22.
[0102] like Figure 6 As shown, the driving circuit unit 22 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, and an initialization transistor T4. The gate of the switching transistor T2 is connected to the scan line Scan(n), the first electrode of the switching transistor T2 is connected to the data line Data, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at a first node A. The gate of the compensation transistor T3 is connected to the scan line Scan(n), the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at a second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1 at a third node B. The gate of the initialization transistor T4 is connected to the second reset control line Reset-Q, the first electrode of the initialization transistor T4 is connected to the second reset line VI-Q, and the second electrode of the initialization transistor T4 is connected to the gate of the driving transistor T1 at a second node Q.
[0103] Specifically, such as Figure 6 As shown, the drive circuit unit 22 further includes: The first light-emitting control transistor T5 has its gate connected to the light-emitting control line EM, its first electrode connected to the first power supply line VDD, and its second electrode connected to the first electrode of the driving transistor T1 at the first node A. The second light-emitting control transistor T6 has its gate connected to the light-emitting control line EM, and its first electrode is connected to the second electrode of the driving transistor T1 at the third node B. Reset transistor T7, the gate of reset transistor T7 is connected to the first reset control line Reset-ANO, the first electrode of reset transistor T7 is connected to the first reset line VI-ANO, the second electrode of reset transistor T7 is connected to the second electrode of the second light-emitting control transistor T6 at the fourth node C, and the second electrode of reset transistor T7 is connected to the anode of the light-emitting device OLED at the fourth node C. The storage capacitor Cst has one plate connected to the first power supply line VDD, and the other plate connected to the gate of the driving transistor T1 at the second node Q.
[0104] Specifically, such as Figure 6 As shown, the cathode of the OLED light-emitting device is connected to the second power line VSS.
[0105] It is understood that the first electrode described in the embodiments of this application is the source electrode 38 and the second electrode is the drain electrode 39, and vice versa.
[0106] It should be noted that, Figure 6 The driving circuit unit 22 shown is only an example, and the structure of the driving circuit unit 22 is not limited thereto.
[0107] This application embodiment does not limit the structure and type of the driving transistor T1 in the driving circuit unit 22. For example, this application embodiment... Figure 7 The partial cross-sectional structural schematic diagram of the display panel 1 shown illustrates the structure of the driving transistor 18 in the array substrate 23 and the light-emitting device 19 electrically connected to the driving transistor 18. At the same time, the arrangement positions of the first connecting line group 6 and the second connecting line group 7 are illustrated.
[0108] like Figure 7As shown, the array substrate 23, from bottom to top, includes a substrate layer 24, an active layer 25, a first insulating layer 26, a first gate layer 27, a second insulating layer 28, a second gate layer 29, a third insulating layer 30, a first source / drain electrode layer 31, a first passivation layer 32, a first planarization layer 33, a second source / drain electrode layer 34, and a second planarization layer 35. The first gate layer 27 includes a first gate 36 aligned with the active layer 25, the second gate layer 29 includes a second gate 37 aligned with the first gate 36, the first source / drain electrode layer 31 includes a source 38 and a drain 39 electrically connected to both sides of the active layer 25, and the second source / drain electrode layer 34 includes a connection electrode 46 electrically connected to the drain 39. The active layer 25, the first gate 36, the second gate 37, the source 38, and the drain 39 constitute a transistor. This transistor can be a driving transistor 18 or a light-emitting control transistor (e.g., Figure 6 The transistor T6 in the circuit depends specifically on the structure of the drive circuit unit 22.
[0109] like Figure 7 As shown, the light-emitting device 19 includes an anode 20, a pixel definition layer 40, an organic functional layer 41, and a cathode 21 disposed on the second planarization layer 35 of the array substrate 23. The pixel definition layer 40 has a pixel opening 42, and the organic functional layer 41 is disposed in the pixel opening 42. The anode 20 is electrically connected to the drain 39 of the transistor through a connecting electrode 46, thereby realizing an electrical connection with the driving circuit unit 22.
[0110] Understandably, the anode 20 is electrically connected to the first power line 2a, and the cathode 21 is electrically connected to the second power line 2b.
[0111] In some embodiments, at least a portion of the connecting lines in the first connecting line group 6 and the second connecting line group 7 are located in the first source-drain electrode layer 31. For example, at least the first power connection line 8a and the second power connection line 8b are located in the first source-drain electrode layer 31.
[0112] In some embodiments, both the third power connection line 8c and the fourth power connection line 8d include a main body and a crossover portion. The main body is a region that does not intersect with the power bus 5, and the crossover portion is a region that intersects with the power bus 5. The main body portions of the third power connection line 8c and the fourth power connection line 8d are located on the first source / drain electrode layer 31, and their crossover portions are located on the second gate layer 29 or the second source / drain electrode layer 34.
[0113] In some embodiments, the material of the first source / drain electrode layer 31 is selected from titanium-aluminum alloys, such as Ti / Al / Ti, but is not limited thereto.
[0114] In some embodiments, the materials of the first gate layer 27 and the second gate layer 29 are selected from molybdenum (Mo), but are not limited thereto.
[0115] In some embodiments, the data line Data is located in the first source / drain electrode layer 31 or the second source / drain electrode layer 34, and the scan line Scan(n) is located in the first gate layer 27 or the second gate layer 29. The positions of the first reset line VI-ANO, the second reset line VI-Q, the first power supply line VDD, the second power supply line VSS, the first reset control line Reset-ANO, the second reset control line Reset-Q, and the light emission control line EM are not limited.
[0116] In this embodiment, by simultaneously setting a flip-chip film 3 and a flexible circuit board 4 in the bonding area BA of the display panel 1, the wiring area FA of the display panel 1 is provided with a first connecting line group 6 and a second connecting line group 7 that are electrically connected to the flip-chip film 3 and the flexible circuit board 4, respectively. The first connecting line group 6 and the second connecting line group 7 are electrically connected to the power line 2 in the display area AA through the power bus 5 in the wiring area FA, thereby realizing the transmission of power signals (e.g., VDD and / or VSS signals). This setting effectively increases the number of VDD and / or VSS power input lines in the non-display area NAA, thereby distributing the VDD and / or VSS power signals to multiple lines, which helps to reduce the voltage drop on the VDD and / or VSS power lines 2 in the display area AA, thereby improving the uniformity of the VDD and / or VSS power signals in the entire display area AA, thus improving the display uniformity of the display panel 1. At the same time, it can reduce the power consumption of the entire display panel 1 and avoid the risk of panel burn-out caused by excessive local power signals.
[0117] like Figure 8 As shown, this application embodiment also provides a display device 43, which includes the display panel 1 described in the foregoing embodiment.
[0118] In some embodiments, the display device 43 further includes a housing 44 and a protective layer 45, and the display panel 1 is disposed in the cavity formed by the housing 44 and the protective layer 45.
[0119] In this embodiment, since the display uniformity of the display panel 1 is improved and the power consumption and risk of burn-in are reduced, the display effect, power consumption and service life of the display device 43 containing the display panel 1 are all improved.
[0120] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0121] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0122] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0123] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A display panel, characterized in that, The display panel includes a display area and a non-display area surrounding the display area, the non-display area including a bonding area located on one side of the display area and a wiring area located between the display area and the bonding area; the display panel includes: At least one power line located in the display area; The flip-chip film and at least one flexible circuit board are located in the bonding region; The wiring area includes at least one power bus, at least one first connection group, and at least one second connection group; both the first connection group and the second connection group include at least one power connection line. The flip-chip film is electrically connected to the power line via at least one first connection line group and the power bus in sequence, and the flexible circuit board is electrically connected to the power line via at least one second connection line group and the power bus in sequence. Furthermore, the flip-chip film and the flexible circuit board are both located on the same side of the power bus away from the display area.
2. The display panel according to claim 1, characterized in that, At least some of the power connection wires in the second connection wire group are wider than the power connection wires in the first connection wire group.
3. The display panel according to claim 1, characterized in that, The power line includes a first power line, and the power bus includes a first power bus; the first connection line group includes at least one first power connection line, and the second connection line group includes at least one second power connection line. The flip-chip film is electrically connected to the first power line in sequence via the first power connection line and the first power bus, and the flexible circuit board is electrically connected to the first power line in sequence via the second power connection line and the first power bus.
4. The display panel according to claim 3, characterized in that, The first power bus is arranged in a grid pattern. The ends of the first power connection line and the second power connection line away from the bonding area are electrically connected to the side of the first power bus that is close to the bonding area. The first power connection line and the second power connection line are arranged on the same layer.
5. The display panel according to claim 4, characterized in that, The first power bus extends along a first direction, and the first power connection line and the second power connection line extend along a second direction, with the first direction and the second direction being perpendicular to each other.
6. The display panel according to claim 3, characterized in that, The power line also includes a second power line, the power bus also includes a second power bus, and the first power line and the second power line are configured to be connected to different voltages; the first connection line group also includes at least one third power connection line, and the second connection line group also includes at least one fourth power connection line. The flip-chip film is electrically connected to the second power line in sequence via the third power connection line, the second power bus, and the flexible circuit board is electrically connected to the second power line in sequence via the fourth power connection line, the second power bus, and the second power line.
7. The display panel according to claim 6, characterized in that, The second power bus is at least partially overlapped with the first power bus in the thickness direction of the display panel; the second power bus extends along a first direction, the third power connection line and the fourth power connection line are arranged on the same layer and extend along a second direction, and the first direction and the second direction are perpendicular to each other.
8. The display panel according to claim 6, characterized in that, The power bus also includes a third power bus that extends around the display area, and the second power bus and the third power bus are configured to be connected to the same voltage; The first connection line group further includes at least one fifth power connection line, and the second connection line group further includes at least one sixth power connection line; the flip-chip film is electrically connected to the second power line in sequence through the fifth power connection line and the third power bus, and the flexible circuit board is electrically connected to the second power line in sequence through the sixth power connection line and the third power bus.
9. The display panel according to claim 8, characterized in that, The third power connection line, the fourth power connection line, the fifth power connection line, and the sixth power connection line are arranged on the same layer.
10. The display panel according to claim 8, characterized in that, In the wiring area, the third power bus is located on the side of the first power bus near the bonding area, the third power bus extends along a first direction, the fifth power connection line and the sixth power connection line extend along a second direction, and the first direction and the second direction are perpendicular to each other. The third power bus has a first opening and a second opening at positions corresponding to the first connection line group and the second connection line group, respectively; the first power connection line and the third power connection line in the same first connection line group are located between two adjacent fifth power connection lines and pass through the first opening in the direction towards the display area, and the second power connection line and the fourth power connection line in the same second connection line group are located between two adjacent sixth power connection lines and pass through the second opening in the direction towards the display area.
11. The display panel according to claim 6, characterized in that, The display panel further includes a driving transistor and a light-emitting device located in the display area. The light-emitting device includes an anode and a cathode. The first power line is electrically connected to the first electrode of the driving transistor, the second electrode of the driving transistor is electrically connected to the anode of the light-emitting device, and the second power line is electrically connected to the cathode of the light-emitting device.
12. The display panel according to claim 6, characterized in that, At least a portion of the power supply connection lines in the first connection line group and the second connection line group are disposed on the same layer as the first electrode and the second electrode of the driving transistor.
13. The display panel according to any one of claims 1 to 12, characterized in that, The number of flexible circuit boards is even, and multiple flexible circuit boards are symmetrically distributed on opposite sides of the flip-chip film.
14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.