Memory management method and storage device

Abstract

The present application provides a memory management method and a storage device. The method comprises: based on an operation event, obtaining a selection strategy corresponding to the operation event through a performance mapping table; determining a target virtual block combination from a plurality of candidate virtual block combinations according to the selection strategy; and responding to the operation event using the target virtual block combination. Thus, the performance and / or operation stability of the storage device can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] Some types of storage devices (such as flash memory) support virtual blocks as the basic unit of management for memory modules. Each virtual block can contain multiple physical blocks. Ideally, multiple physical blocks within the same virtual block are distributed across multiple planes of the memory module. By performing multi-plane reads or multi-plane writes on multiple physical blocks within the same virtual block, the access performance of the memory module can be effectively improved.

[0003] However, a common problem in practice is that after a period of use, bad blocks will gradually appear in multiple physical blocks belonging to the same virtual block. In this case, good blocks located in the same or different planes may be used to replace bad blocks in the virtual block to continuously build usable virtual blocks. However, virtual blocks built using different construction methods may have significantly different operational performances due to the different distribution of their physical blocks on one or more planes. Therefore, randomly using reconstructed virtual blocks to operate the memory module may cause the operating performance of the storage device to deviate from expectations. Summary of the Invention

[0004] The present invention provides a memory management method and a storage device, which can effectively improve the above-mentioned problems and thereby improve the performance and / or operational stability of the storage device.

[0005] This invention provides a memory management method, comprising: obtaining a selection strategy for a corresponding operation event through a performance mapping table based on an operation event; determining a target virtual block combination from multiple candidate virtual block combinations according to the selection strategy; and responding to the operation event using the target virtual block combination.

[0006] According to one embodiment of the present invention, when the operation event is a host write event or a data cleanup event, the selection strategy is a first selection strategy; and when the operation event is a system data update event, the selection strategy is a second selection strategy.

[0007] According to an embodiment of the present invention, the first selection strategy includes: sequentially determining the plurality of candidate virtual block combinations as the target virtual block combination in descending order of performance level, wherein the higher the performance level, the fewer normal virtual blocks are in the candidate virtual block combination; the second selection strategy includes: sequentially determining the plurality of candidate virtual block combinations as the target virtual block combination in ascending order of performance level.

[0008] According to an embodiment of the present invention, the first selection strategy further includes: determining a starting candidate virtual block combination as the target virtual block combination, wherein the data processing event includes a delayed processing event, a controlled maintenance event, and a autonomous maintenance event; when the operation event is the host write event or the delayed processing event, determining the candidate virtual block combination corresponding to the first performance level in the performance level descending order as the starting candidate virtual block combination; when the operation event is the controlled maintenance event or the autonomous maintenance event, determining the candidate virtual block combination corresponding to the second performance level in the performance level descending order as the starting candidate virtual block combination.

[0009] According to an embodiment of the present invention, the second selection strategy further includes: determining a starting candidate virtual block combination as the target virtual block combination, and determining the candidate virtual block combination corresponding to the lowest performance level in the performance level ascending order as the starting candidate virtual block combination.

[0010] According to one embodiment of the present invention, the performance mapping table is established based on the target performance, and the performance mapping table is used to record the correspondence between the plurality of candidate virtual block combinations and the plurality of performance levels.

[0011] According to one embodiment of the present invention, the performance mapping table is further used to record the correspondence between the plurality of candidate virtual block combinations and different types of virtual blocks.

[0012] According to one embodiment of the present invention, the different types of virtual blocks span different numbers of planes.

[0013] According to one embodiment of the present invention, the different types of virtual blocks correspond to different operational performance.

[0014] According to an embodiment of the present invention, the plurality of candidate virtual block combinations include a first type of candidate virtual block combination and a second type of candidate virtual block combination. The first type of candidate virtual block combination contains only normal virtual blocks, and the second type of candidate virtual block combination contains the normal virtual blocks and mixed-plane virtual blocks.

[0015] According to one embodiment of the present invention, a plurality of entity blocks in the normal virtual block are located on a first number of planes, and a plurality of entity blocks in the mixed-plane virtual block are located on a second number of planes, wherein the first number is greater than the second number.

[0016] According to one embodiment of the present invention, in the normal virtual block, there are no multiple entity blocks located on the same plane.

[0017] According to one embodiment of the present invention, in the mixed-plane virtual block, there are multiple physical blocks located on the same plane.

[0018] According to one embodiment of the present invention, in different types of combinations of second-class candidate virtual blocks, the ratio of the number of normal virtual blocks to the number of mixed-plane virtual blocks is different.

[0019] This invention also provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute a memory management method.

[0020] Based on the above, the selectable strategy for each operation event can be obtained through a performance mapping table. Subsequently, according to the selection strategy, the target virtual block combination can be automatically determined from multiple candidate virtual block combinations and used to respond to the operation event. This effectively reduces the uneven performance of subsequent operations caused by the distribution differences of good blocks on different planes, thereby effectively improving the performance and / or operational stability of the storage device. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram illustrating the use of multiple virtual blocks to manage a memory module according to an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram illustrating the adjustment of the distribution of physical blocks in a virtual block according to an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram illustrating different types of virtual blocks corresponding to different operational performances according to embodiments of the present invention;

[0027] Figure 7 This is a schematic diagram of a performance mapping table according to an embodiment of the present invention;

[0028] Figure 8 This is a schematic diagram of a performance mapping table according to an embodiment of the present invention;

[0029] Figure 9 This is a schematic diagram of a virtual block usage strategy that includes selection rules for initial candidate virtual block combinations, as shown in an embodiment of the present invention.

[0030] Figure 10 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0031] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0032] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0033] The host system 11 may include a processor 111 and a first buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0034] The first buffer memory 112 is connected to the processor 111 and is used to cache data. For example, the first buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. The first buffer memory 112 can be used as the main memory of the host system 11. In addition, the host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0035] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0036] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0037] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0038] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0039] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0040] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0041] In one embodiment, the memory controller 123 may further include a second buffer memory 24. The second buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the second buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The second buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0042] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0043] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(C). Each physical unit includes multiple storage cells for non-volatile storage of data.

[0044] In one embodiment, an entity unit may include at least one entity programmable unit. For example, an entity programmable unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on an entity programmable unit to write data to that entity programmable unit, multiple memory cells in that entity programmable unit may be synchronously programmed to store the corresponding data. For example, when programming an entity programmable unit, a write voltage may be applied to that entity programmable unit to change the threshold voltage of at least some of the memory cells in that entity programmable unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell. In one embodiment, an entity programmable unit is also referred to as an entity page. For example, the storage capacity of an entity programmable unit may be 16 kilobytes, and the invention is not limited thereto.

[0045] In one embodiment, an entity programming unit includes multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0046] In one embodiment, a physical erase unit may include multiple physical programmable units. For example, the multiple physical programmable units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the multiple physical programmable units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programmable units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0047] In one embodiment, an entity unit may include at least one entity erase unit. In another embodiment, if an entity unit includes multiple entity erase units, this entity unit is also referred to as a virtual block. Multiple entity erase units contained in the same virtual block can operate synchronously.

[0048] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0049] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0050] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0051] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0052] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0053] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0054] In one embodiment, the memory module 122 may include one or more chip-enabled (CE) regions. For example, the memory module 122 may include one or more dies. Dies are obtained from a wafer by laser dicing. Each die may be divided into one or more chip-enabled regions. Each chip-enabled region may contain one or more planes (also referred to as memory planes). Each plane may contain multiple physical blocks. Furthermore, the memory control circuitry 23 can access the memory module 122 through multiple channels (also referred to as memory channels) to improve access performance to the memory module 122.

[0055] In one embodiment, the memory control circuit 23 may be configured with multiple virtual blocks. Each virtual block may span multiple physical blocks located on multiple planes. Subsequently, the memory control circuit 23 can manage and / or access the memory module 122 by operating these virtual blocks. For example, the memory control circuit 23 may use one or more virtual blocks to synchronously write, read, or delete (i.e., erase) data on physical blocks located on different planes in the memory module 122.

[0056] Figure 4 This is a schematic diagram illustrating the use of multiple virtual blocks to manage a memory module according to an embodiment of the present invention. Please refer to... Figure 4Assume that memory module 122 includes planes PL(0)-PL(3). In one embodiment, memory control circuitry 23 may configure multiple virtual blocks to manage and access multiple physical blocks distributed on planes PL(0)-PL(3). For example, the configured virtual blocks may include virtual blocks VB(0)-VB(10).

[0057] In one embodiment, the virtual blocks VB(0)-VB(10) may sequentially include physical blocks PB(0)-PB(3), physical blocks PB(4)-PB(7), physical blocks PB(8)-PB(11)... and physical blocks PB(40)-PB(43). The distribution of physical blocks PB(0)-PB(43) in the plane PL(0)-PL(3) is as follows: Figure 4 As shown. It should be noted that the total number of planes PL(0)-PL(3), the distribution of solid blocks PB(0)-PB(43) in planes PL(0)-PL(3), and the distribution of solid blocks contained in virtual blocks VB(0)-VB(10) in planes PL(0)-PL(3) can all be adjusted according to practical needs, and the present invention does not impose any restrictions.

[0058] In one embodiment, a virtual block can also span multiple chip enable regions within the memory module 122. Furthermore, in Figure 4 In the embodiment, it is assumed that all entity blocks PB(0)-PB(43) are good blocks (i.e., all entity blocks PB(0)-PB(43) can be used normally).

[0059] In one embodiment, the memory control circuit 23 may identify at least one of the physical blocks PB(0)-PB(43) as a bad block. For example, if the data read from physical block PB(i) contains too many error bits (e.g., the total number of error bits exceeds a preset number), the memory control circuit 23 may identify physical block PB(i) as a bad block.

[0060] In one embodiment, if any of the physical blocks PB(0)-PB(43) is determined to be a bad block, then this bad block will be removed from the corresponding virtual block, and this bad block can be replaced by a good block in the memory module 122. Figure 4 For example, assuming that physical block PB(0) is determined to be a bad block, this physical block PB(0) will be removed from the virtual block VB(0), and the original position of physical block PB(0) in the virtual block VB(0) will be replaced by a good block in memory module 122. In other words, in one embodiment, based on the detected bad block, memory control circuit 23 can adjust the distribution of physical blocks in the virtual blocks to remove the bad block from the corresponding virtual block.

[0061] Figure 5This is a schematic diagram illustrating the adjustment of the distribution of physical blocks within a virtual block according to an embodiment of the present invention. Please refer to... Figure 4 and Figure 5 In one embodiment, the virtual block VB(2) can be adjusted to include physical blocks PB(8)-PB(10) and PB(40). Physical block PB(40) can be used to replace a bad block (e.g., physical block PB(11)) in plane PL(3). Specifically, in the adjusted virtual block VB(2), physical blocks PB(8) and PB(40) are actually located in the same plane (i.e., plane PL(0)), while physical blocks PB(9) and PB(10) are located in planes PL(1) and PL(2), respectively.

[0062] In one embodiment, the virtual block VB(3) can be adjusted to include physical blocks PB(12)-PB(14) and PB(41). Physical block PB(41) can be used to replace a bad block (e.g., physical block PB(15)) in plane PL(3). Specifically, in the adjusted virtual block VB(3), physical blocks PB(13) and PB(41) are actually located in the same plane (i.e., plane PL(1)), while physical blocks PB(12) and PB(14) are located in planes PL(0) and PL(2), respectively.

[0063] In one embodiment, the virtual block VB(4) may be adjusted to include physical blocks PB(16), PB(17), PB(20), and PB(21). Physical blocks PB(20) and PB(21) may be used to replace bad blocks (e.g., physical blocks PB(18) and PB(19)) located on planes PL(2) and PL(3), respectively. Specifically, in the adjusted virtual block VB(4), physical blocks PB(16) and PB(20) are actually located on the same plane (i.e., plane PL(0)), and physical blocks PB(17) and PB(21) are also actually located on the same plane (i.e., plane PL(1)).

[0064] In one embodiment, the virtual block VB(5) can be adjusted to include physical blocks PB(24), PB(28), PB(32), and PB(36). The physical blocks PB(28), PB(32), and PB(36) can respectively replace bad blocks (e.g., physical blocks PB(25) to PB(27)) located on planes PL(1) to PL(3). Specifically, in the adjusted virtual block VB(5), physical blocks PB(24), PB(28), PB(32), and PB(36) are all located on the same plane (i.e., plane PL(0)).

[0065] In one embodiment, the memory control circuit 23 can determine a virtual block as a normal virtual block or a mixed-plane virtual block. For example, if all entity blocks in a virtual block are completely distributed across different planes, the memory control circuit 23 can determine this virtual block as a normal virtual block. In other words, in a normal virtual block, there must be no multiple entity blocks located on the same plane. For example, the memory control circuit 23 can... Figure 5 The virtual blocks VB(0) and VB(1) in the code are determined to be normal virtual blocks.

[0066] On the other hand, if all entity blocks in a virtual block are not completely distributed across different planes, the memory control circuit 23 can define this virtual block as a mixed-plane virtual block. In other words, in a mixed-plane virtual block, there must exist multiple entity blocks located on the same plane. For example, the memory control circuit 23 can... Figure 5 The virtual blocks VB(2) to VB(5) in the middle are determined to be mixed plane virtual blocks.

[0067] In one embodiment, multiple entity blocks in a normal virtual block may lie on a certain number (also referred to as a first number) of planes. Multiple entity blocks in a mixed-plane virtual block may lie on another number (also referred to as a second number) of planes. The first number is greater than the second number.

[0068] by Figure 5 For example, the entity blocks in virtual blocks VB(0) and VB(1) (i.e., normal virtual blocks) are located on a total of 4 planes (i.e., the first number). The entity blocks in virtual blocks VB(2) and VB(3) (i.e., mixed-plane virtual blocks) are located on a total of 3 planes (i.e., the second number). The entity blocks in virtual block VB(4) (i.e., mixed-plane virtual block) are located on a total of 2 planes (i.e., the second number). In addition, the entity blocks in virtual block VB(5) (i.e., mixed-plane virtual block) are located on 1 plane (i.e., the second number).

[0069] In one embodiment, the memory control circuit 23 can determine the type of a virtual block based on the distribution of multiple physical blocks within a virtual block across multiple planes in the memory module 122. For example, different types of virtual blocks may span different numbers of planes. Figure 5 For example, the memory control circuit 23 can determine virtual blocks VB(0) and VB(1) as virtual blocks of type A; virtual blocks VB(2) and VB(3) as virtual blocks of type B1; virtual block VB(4) as virtual block of type B2; and virtual block VB(5) as virtual block of type C. Different types of virtual blocks can correspond to different operating performance.

[0070] In one embodiment, after initially establishing the various types of virtual blocks, the memory module 122 can further reorganize virtual blocks of type A (the best-performing virtual blocks) and virtual blocks of type C (the worst-performing virtual blocks) into virtual blocks of type B1 or B2. Thus, by reorganizing virtual blocks with extremely high performance into virtual blocks with moderate performance, the operational stability of the storage device 12 can be improved in subsequent operations.

[0071] Figure 6 This is a schematic diagram illustrating different types of virtual blocks corresponding to different operational performances according to embodiments of the present invention. Please refer to... Figure 6 Taking the four planes in memory module 122 as an example, when accessing memory module 122 by operating on a virtual block of type A (e.g., writing data to memory module 122), data can be transferred to the four planes (e.g., planes PL(0)-PB(3)) in one operation cycle. After the data transfer is completed in a single operation cycle, the write circuit inside memory module 122 performs parallel data writing for the physical blocks in these four planes.

[0072] When accessing memory module 122 by operating on a virtual block of type B1 (e.g., writing data to memory module 122), the data must be spread across three planes (e.g., planes PL(0)-PB(2)) in two operation cycles. After each operation cycle of data transfer is completed, parallel data writing to physical blocks in these three planes is performed by the write circuitry inside memory module 122.

[0073] When accessing memory module 122 by operating on a virtual block of type B2 (e.g., writing data to memory module 122), the data must also be distributed across two operation cycles to two planes (e.g., planes PL(0)-PB(1)). After each operation cycle of data transfer is completed, the write circuit inside memory module 122 performs parallel data writing to the physical blocks in these two planes.

[0074] Furthermore, when accessing memory module 122 by operating on a virtual block of type C (e.g., writing data to memory module 122), the data must be transmitted sequentially to a single plane (e.g., plane PL(0)) over four operation cycles. After each operation cycle of data transmission is completed, a separate data write for the physical block in this single plane is performed by the write circuitry inside memory module 122.

[0075] In one embodiment, the memory control circuit 23 can evaluate the operational performance corresponding to different types of virtual blocks. Figure 6For example, the memory control circuit 23 can represent the operating performance corresponding to different types of virtual blocks according to the following formulas (1)-(4).

[0076]

[0077] In formulas (1)-(4), PER(A) represents the performance evaluation information corresponding to the virtual block of type A, PER(B1) represents the performance evaluation information corresponding to the virtual block of type B1, PER(B2) represents the performance evaluation information corresponding to the virtual block of type B2, PER(C) represents the performance evaluation information corresponding to the virtual block of type C, tDMA represents the duration of performing Direct Memory Access (DMA) on memory module 122, tProg represents the duration of performing programming operation (i.e., write operation) on memory module 122, and NP represents the total number of physical pages in a physical block. It should be noted that formulas (1)-(4) can also be adjusted according to practical needs, and this invention does not impose any restrictions.

[0078] In one embodiment, PER(A), PER(B1), PER(B2), and PER(C) can be used to reflect the time (i.e., duration) required to access the memory module 122 through different types of virtual blocks (i.e., type A, type B1, type B2, and type C), respectively. Thus, the memory control circuit 23 can utilize PER(A), PER(B1), PER(B2), and PER(C) to evaluate and / or represent the operational performance corresponding to different types of virtual blocks.

[0079] In one embodiment, PER(A), PER(B1), PER(B2), and PER(C) respectively reflect the total time required to fill a virtual block when accessing a single virtual block of different types. In particular, according to formulas (1)-(4), PER(A) is less than PER(B1), PER(B1) is equal to PER(B2), and PER(B1) is less than PER(C). That is, PER(A), PER(B1), PER(B2), and PER(C) reflect that the time required to access the memory module 122 through a virtual block of type A is the shortest, the time required to access the memory module 122 through a virtual block of type B1 or B2 is moderate, and the time required to access the memory module 122 through a virtual block of type C is the longest.

[0080] In one embodiment, assuming that the operation performance corresponding to the virtual block of type A is set to "100%" based on the virtual block of type A, then according to formulas (1)-(4), the memory control circuit 23 can set the operation performance corresponding to the virtual blocks of types B1 and B2 to "75%" and the operation performance corresponding to the virtual block of type C to "50%". That is to say, accessing the memory module 122 through the virtual block of type A can perfectly achieve the highest efficiency. Compared with the virtual block of type A, accessing the memory module 122 through the virtual block of type B1 or B2 can only achieve "75%" of the highest efficiency (i.e., medium efficiency). In addition, compared with the virtual block of type A, accessing the memory module 122 through the virtual block of type C can only achieve "50%" of the highest efficiency (i.e., the lowest efficiency).

[0081] In one embodiment, during the operation of the storage device 12, the memory control circuit 23 can select a suitable virtual block from various types of virtual blocks based on the performance evaluation information and the type of operation event to be executed. Then, the memory control circuit 23 can access the memory module 122 based on the selected virtual block. Thus, an attempt is made to achieve the target performance as much as possible during the execution of the operation corresponding to the operation event.

[0082] In one embodiment, assuming the target performance is "85%" of the highest performance supported by memory module 122, and the achievable operational performance by accessing memory module 122 using virtual blocks of types A, B1 (or B2), and C is "100%", "75%", and "50%", respectively, then the memory control circuit 23 can choose to use only type A virtual blocks to access memory module 122 to achieve the target performance. Alternatively, the memory control circuit 23 can also choose to use one type A virtual block combined with one type B1 (or B2) virtual block to access memory module 122 to achieve the target performance (actual performance achievement rate of approximately 85.7%). Alternatively, the memory control circuit 23 can also choose to use five type A virtual blocks combined with one type C virtual block to access memory module 122 to achieve the target performance (actual performance achievement rate of approximately 85.7%).

[0083] In other words, even without (fully) using the most efficient type A virtual blocks (i.e., normal virtual blocks) to access the memory module 122, the target performance can still be achieved by using the aforementioned combination of virtual blocks (e.g., one type A virtual block paired with one type B1 (or B2) virtual block, or five type A virtual blocks paired with one type C virtual block). Simultaneously, by reducing the amount of type A virtual blocks used, the rate at which type A virtual blocks are consumed can be reduced. Therefore, this avoids the situation where, in certain circumstances, there is an urgent need to use normal virtual blocks to ensure performance or operational stability, resulting in a lack of sufficient normal virtual blocks available.

[0084] In one embodiment, the memory control circuit 23 can determine the target performance based on current performance requirements. For example, this performance requirement can be dynamically requested by the host system 11 or determined automatically by the memory control circuit 23 based on pre-stored system information.

[0085] In one embodiment, the memory control circuit 23 may receive instructions from the host system 11. These instructions may contain information about the performance requirements. The memory control circuit 23 may then parse these instructions to determine the target performance.

[0086] In one embodiment, the memory control circuit 23 can read system information from the memory module 122. For example, this system information may be pre-stored in the memory module 122 before the storage device 12 leaves the factory. This system information may be maintained (e.g., updated) by the supplier or administrator of the storage device 12. When the storage device 12 is operating, the memory control circuit 23 can determine the target performance based on this system information.

[0087] In one embodiment, this system information may also be stored (e.g., programmed into) the memory controller 123. For example, this system information may be stored in a one-time programming circuit in the memory controller 123. For example, this one-time programming circuit may include a read-only memory (ROM) or an electronic fuse structure. When the storage device 12 is operating, the memory control circuit 23 may read this system information from the memory controller 123 and determine the target performance based on this system information.

[0088] In one embodiment, the memory control circuit 23 may establish a performance mapping table based on the target performance. Alternatively, the memory control circuit 23 may obtain a performance mapping table from an external circuit, which is established based on the target performance. This performance mapping table may record the correspondence between multiple types of virtual block combinations (i.e., multiple candidate virtual block combinations) and multiple performance levels. Furthermore, the performance mapping table may also record the correspondence between multiple candidate virtual block combinations and different types of virtual blocks.

[0089] In one embodiment, the performance mapping table records candidate virtual block combinations including a first type of candidate virtual block combination and a second type of candidate virtual block combination. The first type of candidate virtual block combination contains only normal virtual blocks. For example, the first type of candidate virtual block combination may only contain virtual blocks belonging to type A. The second type of candidate virtual block combination may contain normal virtual blocks and mixed-plane virtual blocks. For example, the second type of candidate virtual block combination may simultaneously contain virtual blocks belonging to type A and at least one virtual block belonging to type B1, B2, or C.

[0090] In one embodiment, the ratio of normal virtual blocks to mixed-plane virtual blocks differs in different types of second-type candidate virtual block combinations. For example, in the above example, assuming the target performance is "85%" of the highest performance supported by memory module 122, and the achievable operational performance by accessing memory module 122 through virtual blocks of types A, B1 (or B2), and C is "100%", "75%", and "50%", respectively. In one second-type candidate virtual block combination, a type A virtual block is configured to be used in conjunction with a type B1 (or B2) virtual block (i.e., the ratio of normal virtual blocks to mixed-plane virtual blocks is 1:1) to achieve the target performance. Furthermore, in another second-type candidate virtual block combination, five type A virtual blocks are configured to be used in conjunction with a type C virtual block (i.e., the ratio of normal virtual blocks to mixed-plane virtual blocks is 5:1) to achieve the target performance.

[0091] Figure 7 This is a schematic diagram of a performance mapping table according to an embodiment of the present invention. Please refer to... Figure 7 In one embodiment, the memory control circuit 23 can establish a performance mapping table based on the target performance. The performance mapping table can record the correspondence between different types of virtual blocks, combinations of different types of virtual blocks (i.e., candidate combinations of virtual blocks), and different performance levels.

[0092] In one embodiment, the performance mapping table may present the following three candidate virtual block combinations and the corresponding usage and performance information for these three candidate virtual block combinations:

[0093] (1) All virtual blocks in this candidate virtual block combination are normal virtual blocks (i.e., type A virtual blocks). Each virtual block in this candidate virtual block combination can achieve maximum performance (i.e., "100%" operational performance) when used individually. Therefore, this candidate virtual block combination can correspond to the highest performance level (e.g., performance level 0).

[0094] (2) This candidate virtual block combination includes mixed-plane virtual blocks, particularly those of type B1 and / or B2. The operational performance achievable when the mixed-plane virtual blocks in this candidate combination are used alone (e.g., the highest performance of "75%)" is slightly lower than that achievable when using normal virtual blocks alone. Therefore, this candidate virtual block combination corresponds to the second-highest performance level (e.g., performance level 1). Specifically, in use, this candidate virtual block combination is limited to requiring at least one mixed-plane virtual block (i.e., a type B1 or B2 virtual block) to be paired with at least one normal virtual block (i.e., a type A virtual block) to achieve the target performance (e.g., 85%). That is, in this candidate virtual block combination, the ratio of normal virtual blocks to mixed-plane virtual blocks is 1:1.

[0095] (3) This candidate virtual block combination includes mixed-plane virtual blocks, particularly type C virtual blocks. The operational performance achievable when the mixed-plane virtual blocks in this candidate virtual block combination are used alone (e.g., the highest performance of "50%)) is significantly lower than that achievable when using normal virtual blocks alone. Therefore, this candidate virtual block combination corresponds to the lowest performance level (e.g., performance level 2). In particular, when used, this candidate virtual block combination is limited to requiring at least one mixed-plane virtual block (i.e., a type C virtual block) to be used in conjunction with at least five normal virtual blocks (i.e., type A virtual blocks) to achieve the target performance (e.g., 85%). That is, in this candidate virtual block combination, the ratio of normal virtual blocks to mixed-plane virtual blocks is 5:1.

[0096] It should be noted that for memory modules 122 with different specifications (e.g., containing different numbers of planes, different numbers of chip enable regions, and / or different numbers of dies), the types of candidate virtual block combinations recorded or presented in the performance mapping table, as well as the corresponding usage and performance information, can be adjusted accordingly. Furthermore, the recording format and information content of the performance mapping table can be adjusted according to practical needs.

[0097] Figure 8 This is a schematic diagram of a performance mapping table according to an embodiment of the present invention. Please refer to... Figure 8 In one embodiment, the memory control circuit 23 can establish a performance mapping table based on the target performance. The performance mapping table can record the correspondence between different types of virtual blocks, combinations of different types of virtual blocks (i.e., candidate combinations of virtual blocks), and different performance levels.

[0098] Compared to Figure 7 In the embodiments, Figure 8In some embodiments, the performance map can present more types (e.g., six types) of candidate virtual block combinations and corresponding usage and performance information for these candidate virtual block combinations. For example, the performance map can present candidate virtual block combinations corresponding to a single type (e.g., type A) of normal virtual blocks and corresponding usage and performance information for these candidate virtual block combinations. Furthermore, the performance map can also present multiple candidate virtual block combinations corresponding to multiple types (e.g., types B to F) of mixed-plane virtual blocks and corresponding usage and performance information for these candidate virtual block combinations.

[0099] Taking the candidate virtual block combination corresponding to a type D mixed-plane virtual block as an example, according to the performance mapping table, the memory control circuit 23 can determine that the performance level corresponding to the type D mixed-plane virtual block is 2 (between performance levels 1 and 3) and the performance achievement rate (approximately between 73.9% and 65%). Furthermore, according to the performance mapping table, the memory control circuit 23 can also determine that when using the candidate virtual block combination corresponding to a type D mixed-plane virtual block, one mixed-plane virtual block (i.e., a type D virtual block) must be paired with at least two normal virtual blocks (i.e., type A virtual blocks) to achieve the target performance (e.g., 85%). That is, in this candidate virtual block combination, the ratio of normal virtual blocks to mixed-plane virtual blocks is 2:1.

[0100] Taking the candidate virtual block combination corresponding to a mixed-plane virtual block of type E as an example, according to the performance mapping table, the memory control circuit 23 can determine that the performance level corresponding to the mixed-plane virtual block of type E is 3 (between performance levels 2 and 4) and the performance achievement rate (approximately between 65% and 58.6%). Furthermore, according to the performance mapping table, the memory control circuit 23 can also determine that when using the candidate virtual block combination corresponding to the mixed-plane virtual block of type E, one mixed-plane virtual block (i.e., a virtual block of type E) must be paired with at least three normal virtual blocks (i.e., virtual blocks of type A) to achieve the target performance (e.g., 85%). That is, in this candidate virtual block combination, the ratio of normal virtual blocks to mixed-plane virtual blocks is 3:1.

[0101] Taking the candidate virtual block combination corresponding to a mixed-plane virtual block of type F as an example, according to the performance mapping table, the memory control circuit 23 can determine that the performance level of the mixed-plane virtual block corresponding to type F is 4 (between performance levels 3 and 5) and the performance achievement rate (approximately between 58.6% and 53.1%). Furthermore, according to the performance mapping table, the memory control circuit 23 can also determine that when using the candidate virtual block combination corresponding to a mixed-plane virtual block of type F, one mixed-plane virtual block (i.e., a virtual block of type F) must be paired with at least four normal virtual blocks (i.e., virtual blocks of type A) to achieve the target performance (e.g., 85%). That is, in this candidate virtual block combination, the ratio of normal virtual blocks to mixed-plane virtual blocks is 4:1.

[0102] Similarly, usage and performance information for various types of candidate virtual block combinations can be obtained based on the performance mapping table. Related content can also be found in [reference needed]. Figure 7 The description of the embodiments will not be repeated here. In addition, the recording format and information content of the performance mapping table can be adjusted according to practical needs.

[0103] In one embodiment, the memory control circuit 23 can detect operation events. For example, this operation event could be a host write event, a data defragmentation event, or a system data update event. A host write event is used to store data instructed to be stored by the host system 11. For example, a host write event can be automatically generated based on a write instruction from the host system 11. This write instruction can instruct the storage of data from the host system 11.

[0104] Data compaction events are used to organize data already stored in memory module 122. For example, a data compaction event can be used to migrate data stored in one physical block of memory module 122 to another physical block of memory module 122 for storage. Data compaction events may include garbage collection events, wear leveling events, data refresh events, or other operation events involving internal data compaction of memory module 122. Garbage collection events may be automatically generated based on a triggered garbage collection operation. Wear leveling events may be automatically generated based on a triggered wear leveling operation. Data refresh events may be automatically generated based on a triggered data refresh operation.

[0105] During garbage collection, valid data can be migrated from the source block to the target block for storage, while the source block can be erased and released as idle physical units. By performing garbage collection, the number of idle physical units in memory module 122 can be increased, and the exhaustion of idle physical units in memory module 122 can be avoided.

[0106] In wear-leveling operations, data can be moved to physical blocks with relatively high wear (or usage) levels for long-term storage, reducing operations (e.g., reads, writes, and / or erases) on these blocks. Meanwhile, physical blocks with relatively low wear (or usage) levels can be used to receive new data, increasing operations (e.g., reads, writes, and / or erases) on the blocks with relatively high wear (or usage). Thus, wear-leveling can be performed on a portion of the physical blocks in memory module 122, thereby extending the lifespan of memory module 122.

[0107] Furthermore, during a data refresh event, data previously stored in the source block can be read and re-stored in the target block to refresh the data. During the data refresh process, erroneous bits in the data can be corrected simultaneously, and / or the critical voltage of the storage cells can be adjusted. This reduces the bit error rate of the refreshed data.

[0108] System data update events are used to update system data. System data update events can be generated automatically based on a triggered system data update operation. For example, this system data can be stored in the system area of ​​memory module 122. The data in this system area may not belong to any logical unit to avoid access or modification by the host system 11. For example, this system data may include various system parameters, firmware codes, or control codes used to operate storage device 12.

[0109] In one embodiment, upon detecting an operation event, the memory control circuit 23 can obtain a selection strategy corresponding to the operation event through a performance mapping table. The memory control circuit 23 can then determine at least one virtual block combination (also referred to as a target virtual block combination) from a plurality of candidate virtual block combinations according to this selection strategy. This selection strategy is based on achieving the target performance corresponding to the operation event. The memory control circuit 23 can then use this target virtual block combination to respond to the operation event. For example, the memory control circuit 23 can access the memory module 122 (e.g., perform a host write operation, data defragmentation operation, or system data update operation, etc.) through this target virtual block combination in response to the operation event.

[0110] In one embodiment, after detecting an operation event, the memory control circuit 23 can detect the type of the operation event. For example, the type of the operation event may reflect that the operation event is a host write event, a data defragmentation event, or a system data update event. The memory control circuit 23 can query a performance mapping table according to the type of the operation event to obtain a query result. For example, this query result may reflect the selection rules for the target virtual block combination, such that the selected target virtual block combination can meet the target performance. Based on this query result, the memory control circuit 23 can determine at least one virtual block combination from multiple candidate virtual block combinations as the target virtual block combination. Then, the memory control circuit 23 can use this target virtual block combination to perform the operation behavior (also called the target operation) corresponding to the operation event. For example, the target operation may be a host write operation, a data defragmentation operation, or a system data update operation.

[0111] In one embodiment, when the detected operation event is a host write event or a data defragmentation event, the selection strategy determined according to the performance mapping table can be a certain selection strategy (also referred to as the first selection strategy). That is, when the detected operation event is a host write event or a data defragmentation event, the memory control circuit 23 can determine a target virtual block combination from multiple candidate virtual block combinations based on the first selection strategy, and use this target virtual block combination to perform the target operation (e.g., a host write operation or a data defragmentation operation).

[0112] In one embodiment, when the detected operation event is a system data update event, the selection strategy determined according to the performance mapping table can be another selection strategy (also referred to as the second selection strategy). The first selection strategy may be the same as or different from the second selection strategy. That is, when the detected operation event is a system data update event, the memory control circuit 23 can determine a target virtual block combination from multiple candidate virtual block combinations based on the second selection strategy, and use this target virtual block combination to perform the target operation (e.g., a system data update operation).

[0113] In one embodiment, the first selection strategy may include: sequentially determining multiple candidate virtual block combinations as target virtual block combinations in descending order of performance level. Specifically, the higher the performance level, the fewer normal virtual blocks are present in the candidate virtual block combinations. Figure 8For example, performance level 0 is the highest performance level, while performance level 5 is the lowest. Therefore, selecting candidate virtual block combinations in descending order of performance level means starting from the candidate virtual block combination with the highest or relatively high performance level, and sequentially selecting the corresponding type of candidate virtual block combination as the target virtual block combination in the direction from performance level 0 to performance level 5. Thus, when the detected operation event is a host write event or a data defragmentation event, priority can be given to ensuring that the target operation performed on the memory module 122 through the target virtual block combination has the highest or relatively high performance and / or operational stability, and only secondarily considering saving the usage of normal virtual blocks (i.e., type A virtual blocks).

[0114] Furthermore, the first selection strategy can also indicate whether it is necessary to change the performance level to determine the target virtual block combination from the candidate virtual block combinations corresponding to another performance level. For example, when responding to an operation event using the target virtual block combination corresponding to the currently selected performance level, if the target virtual block combination corresponding to the current performance level is full, the performance level can be lowered by one, and the target virtual block combination can be determined from the candidate virtual block combinations corresponding to the next performance level, and so on, selecting the target virtual block combination level by level in descending order of performance level.

[0115] On the other hand, a second selection strategy may include: sequentially determining the target virtual block combination from multiple candidate virtual block combinations in ascending order of performance level. Similarly, using... Figure 8 For example, the performance-level ascending order means starting with the candidate virtual block combination with the lowest or relatively low performance level, and sequentially selecting candidate virtual block combinations of the corresponding type as the target virtual block combination from performance level 5 towards performance level 0. Therefore, when the detected operation event is a system data update event, the target operation can be executed using the worst or relatively worst performing virtual blocks while achieving the target performance as much as possible, thus saving the usage of normal virtual blocks (i.e., type A virtual blocks). The second selection strategy can also indicate whether it is necessary to change the performance level to determine the target virtual block combination; the specific implementation is the same as the first selection strategy described above, and will not be repeated here.

[0116] In summary, during the operation of storage device 12, by selecting appropriate combinations of virtual blocks (i.e., target virtual block combinations) to execute target operations under different scenarios, the memory control circuit 23 can automatically manage and allocate the use of different types of virtual blocks. For example, for host write events and data compaction events, the virtual block combinations corresponding to the highest or relatively high performance level can be prioritized for executing target operations, prioritizing performance and operational stability. Furthermore, for system data update events, the virtual block combinations corresponding to the lowest or relatively low performance level can be prioritized for executing target operations, saving on the consumption of normal virtual blocks. Therefore, by appropriately adjusting the usage strategy for different types of virtual blocks under different operating scenarios, the performance and / or operational stability of storage device 12 can be maintained effectively and sustainably over the long term.

[0117] In one embodiment, data processing events can be further subdivided into delayed processing events, controlled maintenance events, and autonomous maintenance events. Delayed processing events refer to data processing events that occur synchronously with host write events. That is, when a delayed processing event is detected, it indicates that the data processing operation corresponding to this delayed processing event will be executed synchronously or interleaved with the host write operation within the same time frame.

[0118] A controlled maintenance event is a data preparation event that occurs before a host write event. That is, when a controlled maintenance event is detected, it means that the data preparation operation corresponding to this controlled maintenance event will be performed before the host write operation. After this data preparation operation is completed, the host write operation can proceed.

[0119] A self-maintenance event refers to a data preparation event detected during a period when no host write events occur. In other words, when a self-maintenance event is detected, it indicates that the corresponding data preparation operation will be performed within a timeframe during which no host write operations are required.

[0120] In one embodiment, under the first selection strategy, the memory control circuit 23 can further determine a starting candidate virtual block combination and use this starting candidate virtual block combination as the target virtual block combination to perform the target operation. That is, the starting candidate virtual block combination refers to the first target virtual block combination selected to perform the target operation after the corresponding operation event is detected.

[0121] In one embodiment, when the detected operation event is a host write event or a delayed processing event, the memory control circuit 23 can refer to the aforementioned performance mapping table to determine the candidate virtual block combination corresponding to the first performance level in descending performance level order as the starting candidate virtual block combination. Figure 8For example, the first performance level in the descending performance level order is performance level 0. Then, the memory control circuit 23 can preferentially use this initial candidate virtual block combination as the initial target virtual block combination to perform the target operation.

[0122] On the other hand, when the detected operation event is a controlled maintenance event or a autonomous maintenance event, the memory control circuit 23 can refer to the aforementioned performance mapping table and determine the candidate virtual block combination corresponding to the second-ranked performance level in descending performance level order as the starting candidate virtual block combination. Figure 8 For example, the first performance level in the performance level descending order is performance level 1. Then, the memory control circuit 23 can preferentially use this initial candidate virtual block combination as the initial target virtual block combination to perform the target operation.

[0123] Based on this, if the candidate virtual block combinations of each performance level are traversed sequentially from the second performance level in descending order of performance level, the subsequent virtual block combination corresponding to the first performance level can also be used as the target virtual block combination.

[0124] In one embodiment, under the second selection strategy, the memory control circuit 23 can refer to the aforementioned performance mapping table to determine the candidate virtual block combination corresponding to the lowest performance level in the ascending performance level order as the starting candidate virtual block combination. Figure 8 For example, the lowest performance level in the descending performance level order is performance level 5. Then, the memory control circuit 23 can preferentially use this initial candidate virtual block combination as the initial target virtual block combination to perform the target operation.

[0125] In one embodiment, if the selected target virtual block combination contains both normal virtual blocks and mixed-plane virtual blocks, the memory control circuit 23 can determine, according to a determined selection strategy, whether to prioritize using normal virtual blocks or mixed-plane virtual blocks in the target virtual block combination to perform the target operation. For example, for host write events, system data update events, and controlled maintenance events, the memory control circuit 23 can prioritize using the most efficient or relatively high-performance virtual blocks (e.g., normal virtual blocks) in the target virtual block combination (equivalent to sequentially selecting from high-performance to low-performance virtual blocks in the target virtual block combination) to perform the target operation. Furthermore, for delayed processing events and autonomous maintenance events, the memory control circuit 23 can switch to prioritizing the least efficient or relatively low-performance virtual blocks (e.g., mixed-plane virtual blocks) in the target virtual block combination (equivalent to sequentially selecting from low-performance to high-performance virtual blocks in the target virtual block combination) to perform the target operation.

[0126] Figure 9This is a schematic diagram of a virtual block usage strategy including selection rules for initial candidate virtual block combinations, as shown in an embodiment of the present invention. Please refer to... Figure 9 For operation events categorized as host write events, system data update events, delayed processing events, controlled maintenance events, and autonomous maintenance events, the memory control circuit 23 can establish a management table. The memory control circuit 23 can refer to the management table to determine the selection rules for the initial candidate virtual block combination, the order of use of candidate virtual block combinations corresponding to different performance levels, and the order of use of different types of virtual blocks in the target virtual block combination for different types of operation events. The relevant operational details have been described above and will not be repeated here. It should be noted that the record format and information content of the management table can be adjusted according to practical needs.

[0127] Figure 10 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 10 In step S1001, based on the operation event, the selection strategy for the corresponding operation event is obtained through the performance mapping table. In step S1002, according to the selection strategy, a target virtual block combination is determined from multiple candidate virtual block combinations. In step S1003, the target virtual block combination is used to respond to the operation event.

[0128] However, Figure 10 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 10 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 10 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0129] In summary, the memory management method and storage device proposed in this invention can dynamically detect the type of operation event to be executed and determine an appropriate combination of virtual blocks to execute the target operation corresponding to the operation event based on this type. Therefore, while always ensuring that the operating performance of the storage device at least reaches the target performance, the optimal balance between improving the performance of the storage device and maintaining long-term operational stability can be achieved by dynamically adjusting the ratio of normal virtual blocks to mixed-plane virtual blocks under different situations.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, include: Based on performance requirements, a target performance is determined, wherein the target performance is a specific percentage of the highest performance supported by the memory module; Establish a performance mapping table based on the target performance; Based on the operation event, the selection strategy corresponding to the operation event is obtained through the performance mapping table; According to the selection strategy, a target virtual block combination is determined from multiple candidate virtual block combinations; The target virtual block combination is used to respond to the operation event. The performance mapping table is used to record multiple candidate virtual block combinations, which include a first type of candidate virtual block combination and a second type of candidate virtual block combination. The first type of candidate virtual block combination only contains normal virtual blocks. The second type of candidate virtual block combination includes the normal virtual block and the mixed-plane virtual block. In the normal virtual block, multiple entity blocks are located on a first number of planes, and in the mixed-plane virtual block, multiple entity blocks are located on a second number of planes, where the first number is greater than the second number. In different types of combinations of second-class candidate virtual blocks, the ratio of normal virtual blocks to mixed-plane virtual blocks varies. The target performance can be achieved when multiple virtual blocks in each candidate virtual block combination are used together.

2. The memory management method according to claim 1, characterized in that: When the operation event is a host write event or a data cleanup event, the selection strategy is the first selection strategy; as well as When the operation event is a system data update event, the selection strategy is the second selection strategy.

3. The memory management method according to claim 2, characterized in that, The first selection strategy includes: sequentially determining the multiple candidate virtual block combinations as the target virtual block combination in descending order of performance level; the higher the performance level, the fewer normal virtual blocks are in the corresponding candidate virtual block combination. The second selection strategy includes: sequentially determining the multiple candidate virtual block combinations as the target virtual block combination according to the ascending order of performance level.

4. The memory management method according to claim 3, characterized in that, The first selection strategy further includes: determining the initial candidate virtual block combination as the target virtual block combination, wherein the data processing event includes delayed processing event, controlled maintenance event and autonomous maintenance event; When the operation event is the host write event or the delayed processing event, the candidate virtual block combination corresponding to the first performance level in the performance level descending order is determined as the starting candidate virtual block combination; When the operation event is the controlled maintenance event or the autonomous maintenance event, the candidate virtual block combination corresponding to the second-ranked performance level in the performance level descending order is determined as the starting candidate virtual block combination.

5. The memory management method according to claim 3, characterized in that, The second selection strategy further includes: determining the starting candidate virtual block combination as the target virtual block combination, and determining the candidate virtual block combination corresponding to the lowest performance level in the performance level ascending order as the starting candidate virtual block combination.

6. The memory management method according to claim 1, characterized in that, The performance mapping table is also used to record the correspondence between the multiple candidate virtual block combinations and multiple performance levels.

7. The memory management method according to claim 1, characterized in that, The performance mapping table is also used to record the correspondence between the multiple candidate virtual block combinations and different types of virtual blocks.

8. The memory management method according to claim 7, characterized in that, The different types of virtual blocks span different numbers of planes.

9. The memory management method according to claim 7, characterized in that, The different types of virtual blocks correspond to different operational performance.

10. The memory management method according to claim 1, characterized in that, In the normal virtual block, there are no multiple entity blocks located on the same plane.

11. The memory management method according to claim 1, characterized in that, In the mixed-plane virtual block, there are multiple physical blocks located on the same plane.

12. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the memory management method according to any one of claims 1-11.

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