Register data online error detection and correction system and method

Abstract

The application discloses a register data online error detection and correction system and method, which comprises a timing module and an ECC control module, the ECC control module is internally provided with an ECC calculation module, the timing module is used for generating a periodic trigger signal, and the ECC control module is driven by the register to start an ECC checking process; the ECC control module is used for grouping a register value to be checked, an address and an ECC code, and then inputting the register value, the address and the ECC code into the ECC calculation module in a timing manner; based on the register value and the ECC code, a new ECC code is generated by recalculation; the calculated ECC code and the input ECC code are subjected to XOR judgment; an error bit is located and corrected; the corrected data is written back to the register; and for an uncorrectable error, error information is reported.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more specifically, to a system and method for online error detection and correction of register data. Background Technology

[0002] With the increasing demand for high-speed, high-precision data storage and processing, registers, as the core data storage units in processors, bear a large number of computational and data transfer tasks. However, in high-speed computing and complex working environments, the data stored in registers is susceptible to interference from various factors, leading to hardware errors or data corruption. If these errors are not detected and corrected in time, they may affect system stability and even cause system crashes or data loss.

[0003] To ensure system reliability and stability, Error Detection and Correction Code (ECC) technology is widely used in computer hardware. ECC technology adds redundant bits to the data, enabling the system to automatically detect and correct some errors. However, existing ECC technology still has limitations in real-time error detection and correction of register data. These limitations include: ECC verification often relies on specific access behaviors (such as read / write) or external interrupt signals, making it impossible to perform periodic automatic verification of register contents, which can lead to errors remaining undetected for extended periods. Traditional methods often configure independent ECC hardware logic for each register, resulting in significant hardware resource redundancy and difficulty adapting to the dynamic verification needs of large-scale register groups. Even when register data errors are detected, traditional solutions still require software intervention to locate the specific erroneous bit, complete the correction, and write back to the original register, making it difficult to meet the system requirements that balance real-time performance and reliability. Summary of the Invention

[0004] The main purpose of this application is to provide an online error detection and correction system and method for register data. By periodically triggering the ECC verification process, introducing a time-sharing multiplexing mechanism to efficiently utilize ECC computing resources, and cooperating with real-time write-back of verification results and error information reporting, the system can realize real-time error correction and detection functions for register data.

[0005] To achieve the above objectives, the first aspect of this application proposes an online register data error detection and correction system, comprising: a timing module and an ECC control module. The ECC control module has a built-in ECC calculation module. The timing module is used to generate periodic trigger signals to drive the ECC control module to start the ECC verification process in conjunction with the register. The ECC control module is used to periodically input the register value, address, and ECC code to be verified into the ECC calculation module after grouping them. Based on the register value and ECC code, a new ECC code is recalculated and generated. The calculated ECC code and the input ECC code are XORed to locate and correct the erroneous bits. The corrected data is written back to the register. For errors that cannot be corrected, error information is reported.

[0006] In one embodiment of this disclosure, the timing module generates timing pulses and the register generates drive signals, which together trigger the ECC verification enable signal to start the counter. Based on the real-time count value of the counter, the register data, address and ECC code to be verified are grouped and input to the ECC calculation module for processing. Each group contains 64 bits of register data and 64 bits of address data.

[0007] In one embodiment of this disclosure, the ECC calculation module is configured to recalculate and generate a new ECC code based on the input register data and the ECC code, and then re-decode the new ECC code into a corresponding index value, which is used to detect and locate errors in the register data.

[0008] In one embodiment of this disclosure, the ECC control module is configured to perform an XOR operation between the input ECC code and the calculated ECC code. If all bits of the XOR result are 0, it indicates no fault; if the highest bit of the XOR result is 1 and the other bits are not all 0, it indicates a single-bit fault is detected; if the highest bit of the XOR result is 0 and the other bits are not all 0, it indicates a double-bit fault is detected.

[0009] In one embodiment of this disclosure, for a single-bit fault, the ECC control module is configured to regroup the original 64-bit register data and address into 8-bit groups based on the high-order bits of the index value output by the ECC decoder, determine the position of the faulty bit using the low-order bits of the index value, perform a single-bit flip on the data through a shift-XOR operation, and write the corrected register data and address back to the original register.

[0010] In one embodiment of this disclosure, for a double-bit fault, the ECC control module is configured to report the error information, indicating that there is an uncorrectable error in the system.

[0011] Secondly, a method for online error detection and correction of register data is provided, suitable for execution in the online error detection and correction system of register data in the first aspect, comprising: starting a counter according to the ECC verification enable signal generated by the timing module and the register; grouping the register value, address and ECC code to be verified according to the real-time count value of the counter and inputting them into the ECC calculation module; in the ECC calculation module, generating a new ECC code according to the register value and ECC code, and re-decoding the new ECC code into the corresponding index value; performing an XOR operation between the new ECC code and the original ECC code, and determining whether a fault has occurred and the fault type according to the operation result; and performing error correction or error reporting according to the fault type.

[0012] In one embodiment of this disclosure, the new ECC code is XORed with the original ECC code. The determination of whether a fault has occurred and the fault type based on the operation result includes: if all bits of the XOR result are 0, it indicates no fault; if the highest bit of the XOR result is 1 and the other bits are not all 0, it indicates a single-bit fault is detected; if the highest bit of the XOR result is 0 and the other bits are not all 0, it indicates a double-bit fault is detected.

[0013] In one embodiment of this disclosure, error correction or error reporting based on the fault type includes: for single-bit faults, regrouping the original 64-bit register data and address according to the index value output by the ECC decoder, with each group consisting of 8 bits; using the low bit segment of the index value to determine the position of the fault bit; performing a single-bit flip on the data through a shift-XOR operation to complete the error correction process; and writing the corrected register data and address back to the original register; for double-bit faults, reporting the error information to indicate that the system has an uncorrectable error.

[0014] Thirdly, a chip is provided, in which the program is executed by a processor to implement the online error detection and correction method for register data.

[0015] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0016] As can be seen from the above scheme, this application adopts a time-division multiplexing mechanism, grouping registers and polling them into a unified ECC calculation module in time slices, significantly reducing hardware overhead and improving resource utilization. By using the error index output from ECC decoding, combined with the two-level grouping structure of address and data, the location of a single-bit error is accurately pinpointed, and bit flipping correction is automatically completed through shift and XOR operations, ensuring real-time write-back and repair of register data. By introducing an error judgment mechanism based on XOR results into ECC calculation, it is possible to clearly distinguish between error-free, single-bit correctable errors, and double-bit uncorrectable errors, and uncorrectable errors are reported immediately, facilitating fault-tolerance or protection measures at the system level, thereby ensuring the integrity and reliability of register data. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings:

[0018] Figure 1 The structural block diagram of the online register data error detection and correction system provided in this application;

[0019] Figure 2 Timing diagram of the online register data error detection and correction system provided in this application;

[0020] Figure 3 A schematic flowchart illustrating the online error detection and correction method for register data provided in this application. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0022] This application provides an online error detection and correction system and method for register data, which aims to improve the utilization efficiency of ECC computing resources and realize real-time error correction and detection of register data. By periodically performing ECC verification on register data, introducing a time-sharing multiplexing mechanism, writing back the corrected data in real time, and promptly reporting uncorrectable errors, the integrity and reliability of register data are ensured.

[0023] Figure 1A block diagram of the online register data error detection and correction system provided in this application. (Refer to...) Figure 1 As shown, the online error detection and correction system for register data includes a timing module and an ECC control module. The ECC control module has a built-in ECC calculation module. The timing module is used to generate periodic trigger signals, which work with the register to drive the ECC control module to start the ECC verification process. The ECC control module is used to periodically input the register value, address, and ECC code to be verified into the ECC calculation module after grouping them. Based on the register value and ECC code, a new ECC code is recalculated and generated. The calculated ECC code and the input ECC code are XORed to locate and correct the erroneous bits. The corrected data is written back to the register. For errors that cannot be corrected, error information is reported.

[0024] Figure 2 Timing diagram of the online register data error detection and correction system provided in this application. Combined with... Figure 1 and Figure 2The timing module generates a timing pulse (Timingpulse), and the register generates a drive signal (Driver_en), which together trigger the ECC verification enable signal (ECC_EN), starting the counter and providing a timing reference for subsequent time-division multiplexing. Based on the real-time counter value (ECC_CNT), the register data, address, and ECC code (DATA / ADDR / ECC_IN) to be verified are grouped and input into the ECC calculation module for processing. Each group contains 64 bits of register data and 64 bits of address data. In the ECC calculation module, based on the input register data and ECC code, a new ECC code (ECC_OUT) is recalculated and generated. The new ECC code is then decoded into the corresponding index value (Ecc_index), which is used to detect and locate errors in the register data. The input ECC code is XORed with the calculated ECC code using a shift-and-XOR operation. If all bits of the XOR result are 0, there is no fault. If the highest bit of the XOR result is 1 and the other bits are not all 0, a single-bit fault (Single_err) is detected. If the highest bit of the XOR result is 0 and the other bits are not all 0, a double-bit fault (Double_err) is detected. For a single-bit fault, the ECC control module regroups the original 64-bit register data (Data_in) and address (Address_in) into 8-bit groups based on the high bit segment (Ecc_index[high]) of the ECC decoder output. The low bit segment (Ecc_index[low]) is used to determine the position of the faulty bit. The data is then flipped bit-by-bit using a shift-and-XOR operation, and the corrected register data and address are written back to the original register (ECC_WRITE). For a double-bit fault, the ECC control module reports the error message Ecc_double_err, indicating that there is an uncorrectable error in the system.

[0025] Figure 3 A schematic flowchart illustrating the online register data error detection and correction method provided in this application. Figure 3 As shown, firstly, the counter is started according to the ECC verification enable signal generated by the timing module and the register. Based on the real-time count value of the counter, the register value, address and ECC code to be verified are grouped and processed (each group contains 64 bits of register value and 64 bits of address), and then input into the ECC calculation module.

[0026] In the ECC calculation module, a new ECC code is generated based on the register value and the original ECC code. This new ECC code is then decoded back to its corresponding index value. The new ECC code is XORed with the original ECC code, and the result is used to determine if a fault has occurred and its type. If all bits of the XOR result are 0, there is no fault. In this case, the register has not been disturbed, the data is intact, and no bit flips have occurred. If the highest bit of the XOR result is 1, and the other bits are not all 0, a single-bit fault is detected. If the highest bit of the XOR result is 0, and the other bits are not all 0, a double-bit fault is detected.

[0027] Error correction or reporting is performed based on the fault type. For single-bit faults, the original 64-bit register data and address are regrouped according to the index value output by the ECC decoder. After grouping, the address and data are each 8 bits. The position of the faulty bit is determined using the low bit segment of the index value. The data is then flipped bit by bit using a shift-XOR operation to complete the error correction process. The corrected register data and address are then written back to the original register. For double-bit faults, the error message is reported, indicating that there is an uncorrectable error in the system. The chip enters a deepsafe state to prevent data errors from further affecting system stability. The specific implementation process is as follows:

[0028] Condition 1: No interference, no register toggling errors

[0029] In this situation, the register remains undisturbed, the data is intact, and no bit flipping occurs. Operation:

[0030] Perform register grouping.

[0031] Perform ECC checks periodically to ensure data consistency.

[0032] Because there are no single-bit or double-bit errors, the system does not need to correct any data.

[0033] No ECC errors (such as ecc_double_err) will be reported.

[0034] Condition 2: The register is interfered with, resulting in a single-bit error.

[0035] In this situation, the register was interfered with, resulting in a single bit error. Operation:

[0036] Perform register grouping.

[0037] Periodically perform ECC checks and detect single-bit errors.

[0038] The system will immediately correct the single-bit error and write the corrected data back to the corresponding address.

[0039] Since single-bit errors are corrected, double-bit errors will not be reported.

[0040] Condition 3: The register is interfered with, resulting in a two-bit error.

[0041] In this situation, the register is subjected to more severe interference, leading to a double-bit error. Operation:

[0042] Perform register grouping.

[0043] The ECC check was performed periodically, and a double-bit error was detected.

[0044] Since double-bit errors cannot be resolved through conventional correction methods, the system will immediately report ecc_double_err.

[0045] The chip enters a deepsafe state to prevent data errors from further affecting system stability.

[0046] Under these operating conditions, the system periodically performs ECC checks to monitor the error status of the registers in real time. Single-bit errors are corrected promptly, while double-bit errors cause the system to enter a safe state to protect data integrity. Through precise verification procedures and reasonable fault handling strategies, the system ensures rapid response and processing of data errors in the registers under various operating conditions, thereby guaranteeing the normal operation of electronic equipment.

[0047] In addition to providing a method and system for online error detection and correction of register data, this application also provides a corresponding chip. When the program in the chip is executed by the processor, it implements the method for online error detection and correction of register data.

[0048] In summary, this application employs a time-division multiplexing mechanism, grouping registers and polling them into a unified ECC calculation module in time slices, significantly reducing hardware overhead and improving resource utilization. By using the error index output from ECC decoding, combined with a two-level address and data grouping structure, the location of single-bit errors is accurately pinpointed, and bit flipping correction is automatically completed through shift and XOR operations, ensuring real-time write-back and repair of register data. By introducing an error judgment mechanism based on XOR results into ECC calculation, it is possible to clearly distinguish between error-free, single-bit correctable errors, and double-bit uncorrectable errors, and uncorrectable errors are reported immediately, facilitating fault-tolerance or protection measures at the system level.

[0049] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0050] Obviously, those skilled in the art should understand that the various units or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device, or fabricating them separately as individual integrated circuit modules, or fabricating multiple modules or steps into a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0051] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A register data online error detection and correction system, characterized in that, include: The system includes a timing module and an ECC control module. The ECC control module has a built-in ECC calculation module. The timing module generates timing pulses, and the register generates a drive signal, which together trigger the ECC verification enable signal to start the counter. Based on the real-time count value of the counter, the register value, address, and ECC code to be verified are grouped and input into the ECC calculation module for processing. Each group contains 64 bits of register data and 64 bits of address data. The ECC control module is used to input the grouped register value, address, and ECC code to be verified into the ECC calculation module at regular intervals. Based on the register value and ECC code, a new ECC code is recalculated and generated. The calculated ECC code and the input ECC code are XORed to locate and correct the erroneous bits. The corrected data is written back to the register. For errors that cannot be corrected, error information is reported. The ECC control module is configured to perform an XOR operation between the input ECC code and the calculated ECC code. If all bits of the XOR result are 0, it indicates no fault. If the highest bit of the XOR result is 1 and the other bits are not all 0, it indicates a single-bit fault is detected. If the highest bit of the XOR result is 0 and the other bits are not all 0, it indicates a double-bit fault is detected. For single-bit faults, the ECC control module is configured to regroup the original 64-bit register data and address into 8-bit groups based on the high-order bits of the index value output by the ECC decoder. The low-order bits of the index value are used to determine the position of the faulty bit. A shift-XOR operation is used to flip the data bit by bit, and the corrected register data and address are written back to the original register. For double-bit faults, the ECC control module is configured to report the error information, indicating that there is an uncorrectable error in the system.

2. The online register data error detection and correction system according to claim 1, characterized in that, The ECC calculation module is configured to recalculate and generate a new ECC code based on the input register data and ECC code, and then re-decode the new ECC code into the corresponding index value, which is used to detect and locate errors in the register data.

3. A method for online error detection and correction of register data, suitable for execution in the online error detection and correction system for register data as described in any one of claims 1-2, characterized in that, include: The counter is started based on the ECC verification enable signal generated by the timing module and the register. The register value, address and ECC code to be verified are grouped and processed according to the real-time count value of the counter and then input into the ECC calculation module. In the ECC calculation module, a new ECC code is generated based on the register value and the ECC code, and the new ECC code is re-decoded into the corresponding index value; Perform an XOR operation between the new ECC code and the original ECC code, and determine whether a fault has occurred and the type of fault based on the result. as well as Correct or report errors based on the type of fault.

4. The online error detection and correction method for register data according to claim 3, characterized in that, The step of performing an XOR operation between the new ECC code and the original ECC code, and determining whether a fault has occurred and the type of fault based on the result, includes: If all bits of the XOR result are 0, it indicates no fault; if the highest bit of the XOR result is 1 and the other bits are not all 0, it indicates a single-bit fault is detected; if the highest bit of the XOR result is 0 and the other bits are not all 0, it indicates a double-bit fault is detected.

5. The online error detection and correction method for register data according to claim 4, characterized in that, The error correction or error reporting based on the fault type includes: For a single-bit fault, the original 64-bit register data and address are regrouped according to the index value output by the ECC decoder. After grouping, the address and data are each 8 bits. The position of the faulty bit is determined by the low bit segment of the index value. The data is flipped one bit by one through a shift XOR operation to complete the error correction process. The corrected register data and address are then written back to the original register. For double-bit faults, an error message will be reported, indicating that there is an uncorrectable error in the system.

6. A chip, characterized in that, When the program in the chip is executed by the processor, it implements the online register data error detection and correction method according to any one of claims 3 to 5.

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