Image region segmentation detection system based on lightweight shared convolution

Abstract

The application relates to the technical field of image processing, and discloses an image region segmentation detection system based on a lightweight shared convolution, which comprises a feature storage module for storing shared weight base element data; an addressing regulation module for calculating feature frequency gradients and second-order derivatives thereof based on pixel gray scale distribution, generating an address mapping sequence and controlling weight addressing pointer steps; and a bit stream logic processing module for executing a bit-by-bit exclusive OR operation on weight bit streams and a mask sequence through a bit mask logic gate circuit, inducing nonlinear jumps of convolution kernel values and generating a logic convolution kernel; and an image convolution operation unit for calling the logic convolution kernel to extract edge features with topological continuity under the addressing constraint determined by the address mapping sequence. The application solves the semantic homogenization defects of shared weights in a lightweight architecture through weight bit stream logic reconstruction, realizes multi-scale receptive field switching, and effectively improves the edge segmentation quality of a target under a heterogeneous texture background.

Description

Technical Field

[0001] This invention relates to an image region segmentation and detection system based on lightweight shared convolution, belonging to the field of image processing technology. Background Technology

[0002] Image region segmentation currently occupies a core position in the field of visual inspection. Existing convolutional neural networks extract image pixel features to perform semantic recognition tasks of targets. In order to ensure industrial inspection accuracy, the network architecture has evolved to be deeper and more multi-channel, which causes the convolution operators to occupy weight storage space. During the inference task performed by embedded processors, the cache capacity and memory access bandwidth constitute the basic physical constraints. Commonly used lightweight solutions use weight quantization or channel pruning. Although the parameter scale is reduced, it will lead to the loss of semantic information in the feature space, especially when processing fine edges or complex textures, resulting in a decrease in segmentation accuracy.

[0003] Industry attempts have attempted to introduce weight-sharing mechanisms to alleviate memory interaction load, but the uniqueness of physical weights leads to a high degree of linear correlation between convolution kernels in different feature channels. Due to the lack of nonlinear jumps in numerical distribution, the system struggles to distinguish features with similar spatial structures but different texture attributes. If a multi-scale strategy with increased operator branches is adopted, it will lead to an increase in hardware addressing frequency, resulting in periodic blocking of the video memory bus. Hardware-level physical compression is insufficient to address the core issues, and rigid control logic restricts the upper limit of system representation. For example, Chinese invention patent CN110428421A discloses a method and device for macular image region segmentation, which uses a machine learning model to extract features and map them to generate a heatmap to achieve region of interest segmentation. However, the solution does not address the semantic homogenization dilemma of shared weights from the underlying mechanism, lacks nonlinear induction of weight bitstream, and struggles to generate discriminative feature responses when faced with textures that are spatially similar but physically different. It also lacks deep coupling with the underlying addressing logic. When faced with large-scale target features, stacking operator branches to gain perception range exacerbates periodic dynamic blocking of the bus, making it difficult to achieve both low-latency response and high-precision segmentation.

[0004] Therefore, the technical problem to be solved by this invention is how to reconstruct the coupling relationship between the physical storage of weights and the logical response, so that the physical shared weights can undergo nonlinear numerical evolution during the reading process, thereby solving the problem of homogenization of semantic expression in image feature extraction. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: An image region segmentation and detection system based on lightweight shared convolution, the system comprising:

[0006] The feature storage module is used to store the preset shared weight primitive data, which serves as the physical storage basis for multiple feature channels.

[0007] The addressing control module is connected to the feature storage module. The addressing control module is used to acquire the image to be segmented, calculate the feature frequency gradient based on the pixel spatial frequency distribution of the image to be segmented, and generate an address mapping sequence based on the second derivative of the feature frequency gradient, so as to control the addressing pointer step size of the weight reading instruction through the address mapping sequence.

[0008] The bitstream logic processing module is connected to the feature storage module. The bitstream logic processing module includes bitmask logic gates. The bitstream logic processing module is used to assign a unique bitmask sequence to each feature channel. In the physical path of the shared weight primitive data being transmitted from the feature storage module to the arithmetic register, the bitmask logic gates are used to perform a bitwise XOR operation on the read shared weight primitive data and the bitmask sequence. This induces nonlinear jumps in the convolution kernel values ​​without changing the physical storage state of the shared weight primitive data, generating logical convolution kernels with uncorrelated numerical distributions.

[0009] The image convolution operation unit is connected to the addressing control module and the bitstream logic processing module, respectively. Under the addressing constraints determined by the address mapping sequence, the image convolution operation unit calls the logical convolution kernel to perform multi-scale convolution operation on the image to be segmented, extracts edge features with topological continuity, and outputs the image region segmentation detection results.

[0010] Preferably, the bitstream logic processing module is used to complete bit plane reassembly within a single physical clock cycle through bitmask logic gate circuits, thereby changing the bitstream distribution characteristics of a single physical weight; the bitstream logic processing module is also used to feed back and adjust the perturbation intensity of the bitmask sequence based on the grayscale spatial distribution entropy value of the image to be segmented, so that the numerical response range of the generated logical convolution kernel is aligned with the local semantic feature space of the image to be segmented, thereby suppressing the interference of heterogeneous texture background on the target edge segmentation.

[0011] Preferably, the addressing control module is also used to identify a local region of the image to be segmented as a high-frequency texture region and maintain the addressing pointer step size as the standard read increment when the energy gradient of the local region of the image to be segmented exceeds a preset threshold; when the local region of the image to be segmented belongs to a smooth background region, the read span of the addressing pointer step size is increased through address jump logic to perform non-contiguous address reading, so as to adjust the multi-scale feature capture range under a single shared weight framework and reduce the memory bandwidth occupied by multi-branch operations.

[0012] Preferably, the system further includes an integrity monitoring module, which is connected to the image convolution operation unit. The integrity monitoring module is used to: while the image convolution operation unit is performing operations, simultaneously enable the bitmask logic gate circuit to count the feature sum of the read weights and compare it with a preset integrity index by XOR; the integrity monitoring module is also used to trigger an addressing correction instruction when the comparison result indicates that the hardware address addressing has an offset.

[0013] Preferably, the system further includes a phase compensation module, which is connected to the image convolution operation unit. The phase compensation module is used to calculate the feature distribution deviation value between different feature channels in the image to be segmented, and to generate phase compensation parameters based on the feature distribution deviation value. The phase compensation module is also used to inject the phase compensation parameters into the output end of the image convolution operation unit and perform phase correction on the feature stream after convolution processing, so as to distinguish texture features that are spatially topologically similar but have different physical properties.

[0014] Preferably, the specific logic for the phase compensation module to perform phase correction follows the following mathematical relationship: ,in, This is the corrected feature output vector. The original convolution feature values ​​output by the image convolution operation unit. For phase compensation parameters, This is a standardized factor that characterizes the dispersion of the current feature channel weight distribution.

[0015] Preferably, the feature storage module uses a compact array structure to store shared weight primitive data, and the physical address of the shared weight primitive data in the memory is mapped to a circular buffer; the addressing control module is also used to determine the rate of change of the addressing pointer step size based on the spatial evolution rate of the feature frequency gradient, and control the contraction of the receptive field in the texture abrupt change region of the image to be segmented.

[0016] Preferably, the image convolution operation unit is also used to perform feature fusion operations in parallel during the convolution operation, and to aggregate the multi-scale feature maps extracted under different address pointer strides with weights to generate a comprehensive feature descriptor that includes local anisotropic feature precision information and global topological connectivity feature information.

[0017] Preferably, the bitmask sequence is pre-stored in the mask register of the bitstream logic processing module, and the bit width of the bitmask sequence is consistent with the bit width of the shared weight primitive data. The bitstream logic processing module is also used to improve the response speed of the image convolution operation unit when processing image features without increasing the physical storage unit density by using the logical XOR chain of the bitmask logic gate circuit.

[0018] Preferably, the image region segmentation detection result output by the image convolution operation unit is sent to the post-processing unit of the system, which is used to superimpose a pseudo-color segmentation mask on the image to be segmented based on the image region segmentation detection result.

[0019] Compared with the prior art, the beneficial effects of the present invention are:

[0020] 1. In image region segmentation and detection, by constructing a resident high-speed cache of weight primitive matrix and cooperating with address offset logic, the system does not need to frequently read independent weight tensors for each feature channel during feature processing. Since the convolution execution engine directly guides the hardware address pointer based on the topology transformation operator, it can logically generate the convolution kernel required for each channel by simply adjusting the memory read path. This reduces the periodic blocking of the data bus when processing high-resolution images, and reduces the memory bandwidth pressure during feature extraction to the level of a single template, thereby achieving quasi-instantaneous response of image feature processing flow in edge computing environment.

[0021] 2. By embedding bit-plane reassembly in the physical path of weight data transmission to the arithmetic register using bit-mask logic gates, a single physical weight can generate logical convolution kernels with uncorrelated numerical distributions. Combined with phase compensation logic for feature distribution deviation values, the system induces nonlinear evolution of convolution kernel values ​​by performing logical operations on the weight bit stream without increasing physical storage units. This processing method enables the system to distinguish texture features with similar spatial topology but subtle differences in physical properties, eliminates the semantic homogenization phenomenon common in lightweight architectures, and improves the topological continuity of target edge segmentation in complex industrial backgrounds.

[0022] 3. The read increment step size of the addressing pointer is dynamically adjusted according to the feature frequency gradient to achieve zero-cost switching of the receptive field of the convolution kernel. When the system detects high-frequency detail areas, standard addressing is maintained. In smooth background areas, non-contiguous address reading is performed through address jumps. This enables the system to have multi-scale feature capture capabilities under a single shared weight framework, ensuring that the clarity of the edges of slender scratches and the connectivity of large-sized geometric defects are achieved simultaneously. At the same time, since multi-scale feature extraction is merged into a single addressing process, the secondary conflicts of multi-branch operations on cache throughput are reduced. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating the overall system architecture and data processing principle of the lightweight shared convolution of this invention.

[0024] Figure 2 This is a timing diagram of parallel integrity monitoring and addressing correction during the convolution operation process of this invention. Detailed Implementation

[0025] The present invention will now be described in conjunction with specific embodiments. It should be noted that, unless otherwise specified, the following embodiments and their technical features can be combined with each other, and the specific embodiments described herein are only for explaining the present invention and are not intended to limit the scope of protection of the present invention.

[0026] This invention provides an image region segmentation and detection system based on lightweight shared convolution, including a feature storage module, an addressing and control module, a bitstream logic processing module, and an image convolution operation unit. The feature storage module stores shared weight primitive data. The addressing and control module, connected to the feature storage module, generates an address mapping sequence that controls the step size of the addressing pointer based on the pixel spatial frequency distribution. The bitstream logic processing module, also connected to the feature storage module, performs a bitwise XOR operation on the weight bitstream using bitmask logic gates to generate a logical convolution kernel. The image convolution operation unit, connected to both the addressing and control module and the bitstream logic processing module, calls the logical convolution kernel under the addressing constraints of the address mapping sequence to extract edge features and outputs the image region segmentation and detection results. The feature storage module uses a compact array structure in a static random access memory to store the preset shared weight primitive data. This data serves as the physical storage foundation for multiple feature channels. To address the memory alignment access bottleneck in embedded systems during high-frequency addressing, the feature storage module stores shared weight primitive data at the physical level through an aligned array structure in static random access memory. The system will be provided by Each weight component Composition take The weight matrix is ​​mapped to a continuous path. Bit-word-width storage units, and based on the address pointer step size of the current feature channel. Calculate the memory offset; when the addressing control module outputs a non-contiguous address read instruction, the address decoding circuit of the feature storage module redirects the start bit of the circular buffer read according to the memory offset, achieving parallel loading of all components of the logical convolution kernel without increasing the data bus turnover cycle; share weight primitive data. The physical address in memory is mapped as a circular buffer. During feature processing, the system generates the convolution kernels required for each channel by changing the memory read path.

[0027] The addressing control module performs memory access frequency scheduling. The system uses an aligned array structure in static random access memory to store shared weight primitive data. The nine weight components are mapped to contiguous 128-bit word-width memory cells, based on the address pointer step size. With reference address The product determines the physical address offset of the current read instruction. The address pointer step size, To share the weights, the starting physical address in the circular buffer is determined when the second derivative of the characteristic frequency gradient... The absolute value is less than or equal to the preset frequency threshold. At the same time, the control logic increases the read step size to a 3-5 pixel interval through the address decoding circuit and triggers burst read commands. It uses a single physical memory copy to generate logic cores with different receptive field spans, so that the memory bus occupancy during multi-scale feature extraction is maintained at a single-path weight access level. The bitstream logic processing module is used to change the bitstream distribution characteristics of the physical weights. This module assigns a unique bitmask sequence to each feature channel. And bitmask sequence Bit width and shared weight primitive data The quantization bit widths are consistent, all being... Bits; in shared weighted basic metadata In the physical path from the feature storage module to the arithmetic register, the bitmask logic gate will read the weight components. AND bitmask sequence Perform a bitwise XOR operation, i.e., according to the formula The logical weights are calculated. The bitstream logic processing module generates logical convolution kernels, and the system selects feature channel index numbers. For input parameters, according to the formula The 8-bit wide bit mask sequence was calculated. ,in For the corresponding number A sequence of feature channel bitmasks This is the feature channel index number. The values ​​17 and 43 are the preset prime factors and offset constants. Before performing the bitwise XOR operation, the system processes the shared weight primitive data. Bit-plane sensitivity detection is performed to determine the high-order effective bits as the logically locked region. By performing logical transition operations only on the low-order bits, nonlinear differences in the numerical distribution are induced, maintaining the logical convolution kernel's ability to extract topological features from the original image. For logical weights, These are the original weight components read from the feature storage module. For the corresponding number The bitmask sequence for each feature channel; logical operations generate logical convolution kernels with uncorrelated numerical distributions; the bitstream logic processing module also adjusts the bitmask sequence according to the grayscale spatial distribution entropy value of the image to be segmented. The perturbation intensity is adjusted to align the numerical response range of the logical convolution kernel with the local semantic feature space of the image to be segmented.

[0028] The addressing and control module is used to acquire the image to be segmented and calculate the feature frequency gradient. This module is based on the characteristic frequency gradient. The second derivative generates an address mapping sequence, which is used to control the address pointer step size of the weighted read instruction; the address control module identifies local region attributes of the image, and when the energy gradient of a local region exceeds a preset frequency threshold... When the region is a high-frequency texture area, the system identifies it as such and maintains the address pointer step size as the standard read increment. When the local area is a smooth background area, the address control module increases the read span of the address pointer step size through address transition logic, performing non-contiguous address reads. This process switches the receptive field of the convolution kernel by adjusting the address step value. The address control module also adjusts the address frequency gradient. The spatial evolution rate determines the rate of change of the address pointer step size, controlling the receptive field contraction in areas of abrupt changes in image texture. The image convolution operation unit is used to call the logical convolution kernel under the addressing constraints determined by the address mapping sequence to perform multi-scale convolution operations on the image to be segmented. During the convolution operation, this unit performs feature fusion in parallel, weighting and aggregating the multi-scale feature maps extracted under different address pointer steps to generate a comprehensive feature descriptor containing local anisotropic feature information and global topological connectivity feature information. The segmentation detection results output by the image convolution operation unit are sent to the post-processing unit, which is used to overlay a pseudo-color segmentation mask on the image to be segmented. The system also includes an integrity monitoring module, which is connected to the image convolution operation unit. When the image convolution operation unit performs operations, the integrity monitoring module uses bitmask logic gate circuits in parallel to statistically analyze the features of the readout weights. The system will combine features and The system compares the data with the preset integrity indicators. If the comparison result indicates that the hardware address addressing has deviated, the integrity monitoring module triggers an addressing correction command, and the control system obtains the weight components from the physical redundancy backup area of ​​the weight primitive data.

[0029] The system also includes a phase compensation module, which is connected to the image convolution operation unit; the phase compensation module calculates the feature distribution deviation values ​​between different feature channels in the image to be segmented. And generate phase compensation parameters The phase compensation module will adjust the phase compensation parameters. The phase correction is performed on the feature stream after convolution by injecting the image convolution operation unit's output. The specific correction logic follows the formula below: Determine the preset frequency threshold. During the system deployment phase, environmental baseline calibration is performed, 50 background images are acquired, and the spatial frequency distribution is calculated. Standard deviation and sensor noise level According to the formula Determine the critical point that triggers the addressing step size jump. This is a preset frequency threshold, measured in pixel frequencies. The standard deviation of the spatial frequency distribution. To characterize the fixed offset of the noise floor level, the phase compensation module uses the characteristic distribution deviation value. Deviation from global average Proportional relationship generates phase compensation parameters The feature flow correction is then performed at the output of the image convolution operation unit, ensuring that the final generated image region segmentation detection result maintains spatial topological consistency under different illumination environments. This is the corrected feature output vector. The original convolution feature values ​​output by the image convolution operation unit. For phase compensation parameters, This is a standardized factor that characterizes the dispersion of the current feature channel weight distribution.

[0030] Example 1: In an industrial scenario involving the segmentation and detection of minute scratches on the surface of highly reflective metal parts, the visual inspection terminal is limited by the hardware bandwidth of the embedded processor and the capacity of the high-speed cache memory. Because the metal surface has a brushed texture, its spatial frequency overlaps with the scratch features, making it difficult for traditional weight-sharing methods to distinguish between background texture and target defects during feature extraction due to the linear correlation of operator distribution. When the system executes image processing tasks, the feature storage module loads a single feature from a specified address space in the static random access memory. take Shared weight base metadata This data serves as the basic weights and resides in memory. To address the obstacle of insufficient differentiation in heterogeneous textures, the bitstream logic processing module determines a set of preset bitmask sequences for the feature channels currently being extracted from scratch edges. When the image convolution operation unit obtains the shared weight primitive data through the addressing control module... Weight components in At that time, the bitmask logic gate circuit will assign this weight component AND bitmask sequence Performing a bitwise XOR operation, i.e., performing... The logical transformation process; among which, For logical weights, These are the original weight components read from the feature storage module. For the corresponding number Bitmask sequences for each feature channel; for a given edge detection channel, if the read original weight components... binary data And the corresponding bitmask for The generated logical weights Transform into This process is completed within a single clock cycle when the weights are transferred from memory to the arithmetic unit. While maintaining the video memory read traffic, it causes a jump in the numerical distribution of the convolution kernels that ultimately participate in the calculation.

[0031] The addressing control module acquires the image to be segmented and calculates the feature frequency gradient of the local region. When the gradient value of a high-frequency texture region exceeds a preset frequency threshold, During this process, the addressing control module controls the step size of the addressing pointer, enabling the image convolution operation unit to perform feature sampling using a compact address mapping sequence. The numerical jumps generated by the bitstream logic processing module and the receptive field switching generated by the addressing control module work in synergy. The nonlinear numerical features provided by the bitmask logic gate circuit provide a differentiated response benchmark for the sampling path of the addressing control module, allowing the addressing control module to utilize the texture sensitivity of the logical convolution kernel to suppress background streaks and enhance the extraction accuracy of scratch edges when performing dense sampling. Under conditions where non-uniform illumination causes local brightness variations in the image, the phase compensation module intervenes and calculates the feature distribution deviation value. The phase compensation parameters are determined according to the following formula. : ;in, For phase compensation parameters, This represents the feature distribution deviation value of the current feature channel. This is the global average deviation value, whose unit is the deviation value from the characteristic distribution value. Consistent, To prevent the denominator from being zero, a smoothing constant is used; the system adjusts the initial phase offset of the address pointer. The system counteracts the phase shift caused by uneven illumination. The image convolution operation unit ultimately outputs image region segmentation and detection results containing defect location and morphological information. The edge contour of the scratch exhibits topological continuity in the segmentation mask, and the memory bus occupancy rate is maintained at the single-path weight read level. By reconstructing the weight bitstream logic, the system transforms the feature homogenization problem, which originally required increasing hardware bandwidth or weight scale, into the bit operations of the underlying logic gate circuit and the dynamic modulation of the address pointer, thereby achieving the separation of small targets in complex backgrounds under the condition of limited hardware resources.

[0032] Example 2: In a test scenario simulating surface defect detection on a high-speed continuous production line for sheet metal, the test platform adopted a system equipped with... GB / s video memory bus bandwidth and An embedded vision processing system with MB high-speed synchronous dynamic random access memory; the experimental data comes from a set of... An industrial dataset of high-resolution metal surface images, with a single image resolution of [missing information]. take To verify the system's anti-interference capability in a real industrial environment, pixels were actively superimposed onto the original image stream during the experiment, with a signal-to-noise ratio of [missing value]. dB of Gaussian white noise; the key performance boundaries of this experimental platform lie in the real-time performance of image convolution processing and the average intersection-union ratio of the segmentation mask, among which the addressing control module involves a preset frequency threshold. The settings are determined through the following procedures: Identification The core parameter for controlling the weighted read density is influenced by factors including the center frequency distribution of the board background texture and the edge gradient of scratches and defects. The technical trade-off lies in balancing the feature integrity of edge extraction with the access frequency of memory addressing by setting this value. The decision rule stipulates that when the local energy gradient of the image is within a certain range... Hz to When fluctuating within the Hz range, in order to lock the deterministic scratch edge and filter out random texture interference, The value of is proportional to the standard deviation of the background grayscale distribution. Under typical operating conditions, the system performs statistical analysis on the background samples and then... Anchored as Used to trigger the address pointer step size in the standard read increment and The experiment group used the image region segmentation and detection system based on lightweight shared convolution provided by this invention, while the control group used the traditional weighted shared convolution scheme without bitmask processing and dynamic addressing logic. The processing delay, memory bandwidth usage and segmentation accuracy were recorded under different working conditions during the experiment.

[0033] Table 1: Performance Indicator Comparison Data Table

[0034]

[0035] Based on the data shown in Table 1, comparing experimental group 2 and control group 2, it can be seen that, under the same conditions... Under dB noise interference, the average cross-union ratio of the sample group of the present invention is determined by Upgraded to Meanwhile, the video memory bandwidth usage has increased from GB / s decreased to GB / s, the data indicates that the logical convolution kernel generated by the bitstream logic processing module has feature decorrelation. Combined with the dynamic receptive field switching of the addressing control module, the system performs dense sampling only on defect regions with high-frequency significance when processing image data, while performing address-jump reading on background regions. The synergistic effect of this mechanism decouples the constraint between computational accuracy and memory overhead. Analysis of the data trends of the boundary group and the out-of-range group shows that when When the setting is too low, the system identifies the background texture as the feature to be detected, causing the address transition logic to fail, and the memory bandwidth usage to rise sharply in group 1 (out of range). GB / s, causing bus congestion, and when When the setting is too high, the convolution sampling becomes too sparse, leading to the loss of subtle defect features, and the average intersection-union ratio drops to [value missing] in the out-of-range group 2. To address the localized brightness saturation phenomenon in images caused by non-uniform illumination, the phase compensation module adjusts the phase compensation based on the characteristic distribution deviation value. Dynamic injection of phase compensation parameters to change trend When the local illumination deviation of the image reaches At that time, the uncompensated characteristic response center will appear Pixel spatial offset, after the phase compensation module intervenes, according to the formula Perform feature flow correction, where, This is the corrected feature output vector. The original convolution feature values ​​output by the image convolution operation unit. For phase compensation parameters, The feature distribution deviation value of the current feature channel, and the compensated feature vector. Alignment with the actual geometric center of the defect in spatial topology was achieved; during the experiment, the integrity monitoring module ran in parallel, and the characteristics output by the statistical bitmask logic gate circuit were analyzed. In simulated injection When the address flips, the response time of the module outputting the address correction command is [time value missing]. ms.

[0036] Example 3: This example combines Figures 1 to 2 The following describes an image region segmentation and detection system based on lightweight shared convolution, such as... Figure 1 As shown, the system architecture and data processing flow include the input of the image to be segmented and the collaborative processing of the image by multiple modules. On the one hand, the pixel spatial frequency distribution is transmitted to the addressing and control module, which generates an address mapping sequence by calculating the second derivative of the frequency gradient, thereby controlling the step size of the addressing pointer. On the other hand, the original image data stream is transmitted to the image convolution operation unit. The feature storage module is used to store shared weight primitive data and serve as the physical basis for multiple feature channels. The shared weight primitive data output by the module enters the bitstream logic processing module, and uses the bitmask logic gate circuit to perform XOR-induced nonlinear jump to generate a logic convolution kernel (nonlinear jump). The kernel is transmitted to the image convolution operation unit, which calls the logic kernel under the constraint of the address mapping sequence to extract topological continuity edge features, generate multi-scale feature segmentation results, and finally output the image region segmentation detection results.

[0037] like Figure 2As shown, the system's timing interaction logic during operation involves an image convolution operation unit, an integrity monitoring module, a bitmask logic gate circuit, an XOR comparator, a redundancy backup area, and an addressing control module. The system initiates parallel execution monitoring. During the convolution operation performed by the image convolution operation unit, the integrity monitoring module executes a synchronous monitoring process. It uses the bitmask logic gate circuit to statistically read out the features and Sw of the weights, obtains the preset integrity index, and uses the XOR comparator to perform an XOR comparison. If the comparison result is normal, the system performs weight integrity confirmation and instructs to continue normal operation. If an address offset is detected, the XOR comparator indicates the hardware address offset and triggers an addressing correction instruction. After receiving the instruction, the addressing control module performs path redirection, obtains the correct weight components by accessing the physical redundancy backup area, and enables the image convolution operation unit to resume normal operation and output the segmentation detection result.

[0038] Example 4: In an industrial scenario involving image region segmentation detection of micron-level fiber defects in a high-speed nonwoven fabric production line, the visual terminal faces challenges such as dense fiber background texture and low grayscale contrast. Under the given conditions, the system determines the initial input state of the image to be segmented as follows: single-channel grayscale matrix with bit depth The addressing and control module acquires the single-channel grayscale matrix. Post-use take The Laplace operator of a window calculates the spatial frequency distribution. And calculate the second derivative of the characteristic frequency gradient. Specifically, the second derivative of the characteristic frequency gradient The calculation formula is as follows: ;in, The second derivative of the characteristic frequency gradient, , as well as These represent the spatial frequency distribution values ​​at adjacent sampling points; the system uses the second derivative of the characteristic frequency gradient. The absolute value of the address mapping sequence is set, and its step size logic is specified as follows: when the second derivative of the characteristic frequency gradient... The absolute value is greater than the preset frequency threshold. At this time, the address pointer step size is set to 1 to guide the image convolution operation unit to perform pixel-by-pixel sampling. When the second derivative of the feature frequency gradient... The absolute value is less than or equal to the preset frequency threshold. At that time, the address pointer step size Follow the formula below: ;in, This is the address pointer step size, measured in pixels. This is a preset frequency threshold.

[0039] The bitstream logic processing module executes bitmask sequences for different feature channels. The generation procedure of the system involves the shared weight primitive data in the feature storage module. Mean normalization is performed, causing the weights to fluctuate around the median of 127 within the quantization range of 0 to 255; the bitstream logic processing module then processes the data based on the index number of the current feature channel. Calculate the bitmask sequence Specifically, bitmask sequence The calculation formula is as follows: ;in, For bitmask sequence, This is the index number of the feature channel; the system reads the original weight components from the feature storage module through bitmask logic gates. AND bitmask sequence Perform a bitwise XOR operation and output the logical weight. Taking the processing of the 5th feature channel as an example, the bitmask sequence The binary code is If the original weight components The binary code is Then the output logical weights The binary code is That is, quantified numerical values The image convolution operation unit receives logical weights. The convolution operation is performed under the constraint of the address mapping sequence. When the system detects a sudden change in the local edge caused by fiber breakage, the address pointer step size is adjusted. Automatically shrinks to 1, while in a smooth fiber background area, the address pointer step size... Expanding to 5 to filter texture noise, the final output image region segmentation detection result achieves a high level of edge accuracy. And the real-time load of the video memory bandwidth is stable at GB / s; The system transforms the mutation rate calculation in texture space into discretized address step instructions and anchors the feature differences between channels to a bitmask generation function based on the index number.

[0040] Example 5: During the commissioning of the track area anomaly detection system deployed on a high-speed railway comprehensive inspection vehicle, the system executes shared weight primitive data. The initial calibration is obtained through the image acquisition unit. The system contains standard sample images of rails with different degrees of corrosion and wear, and calculates the average gradient energy distribution characteristics of the sample set. The system searches the weight parameter space to minimize the mean square error, determining the values ​​that can cover the background texture spectrum distribution as shared weight primitive data. The initial values; the feature storage module will determine the weight components according to... The bit width is quantized into integers, and the quantized value is written into the circular buffer of the static random access memory; this calibration logic establishes the background frequency distribution of the rails and shared weight primitive data. The statistical correlation between them reduces the interference of numerical randomness in the weight initialization stage on the response accuracy of the logical convolution kernel.

[0041] When the rail surface changes from a dry, rust-free material to a wet, slippery, highly reflective material after rain, the addressing and control module performs a pre-baseline calibration to adjust the preset frequency threshold according to environmental changes. The system performs continuous operation within the inspection area. Pixel sampling for each period, calculating the spatial frequency distribution of the image. Standard deviation The addressing control module is based on a linear proportional relationship. Determine the trigger threshold for the current material; where, This is a preset frequency threshold, with units of pixel frequency. The standard deviation of the spatial frequency distribution of the image. A fixed offset is used to characterize the sensor's noise floor level; after parameter calibration, the address mapping sequence output by the addressing and control module matches the complexity of the track environment texture. When extracting edge features, the system dynamically adjusts the addressing pointer step size to control the single-frame processing delay within a certain range. Below milliseconds.

[0042] Example 6: In a deployment scenario for image region segmentation detection of fasteners and micro-fatigue cracks on the surface of high-speed rails, the onboard vision processing system faces the challenges of drastic changes in light and shadow at tunnel entrances and an imbalance in feature energy distribution caused by the anisotropy of reflections from the rail metal surface. To ensure that the image convolution operation unit completes environmental alignment before production operations, the system executes a deployment calibration process; the sensor noise floor calibration status is determined by acquiring data under shaded light conditions. The frame dark field image is used to calculate the average pixel value as the sensor noise floor level. Inject addressing and control module; the system acquires reference images under no-load conditions and calculates the feature distribution deviation values ​​of feature channels at different scales. The image convolution operation unit calculates the feature fusion weights used for weighted fusion based on the principle of energy conservation. The specific formula is as follows: ;in, For the first The feature fusion weights at each scale are dimensionless normalized coefficients. For the first The feature distribution deviation value of each scale feature channel has the same dimension as the pixel gray value of the image to be segmented. The total number of scales participating in the fusion is set to 3 under the current operating conditions.

[0043] The system loads shared weighted primitive data that satisfy the rail texture features through the feature storage module. Furthermore, for high-reliability orbital safety verification scenarios, offline filling of pre-defined integrity indicators is performed, namely, reading pre-defined shared weight primitive data. Parallel computation is performed before the weighted bit stream enters the accumulator. take All value components within the primitive matrix The arithmetic summation is used to generate the baseline feature sum. The system will combine the baseline features and Stored in a dedicated register, the integrity monitoring module will collect online statistical features and and If the comparison result indicates that the hardware addressing has shifted due to strong vibrations in the vehicle environment, the system automatically redirects the addressing pointer to the physical redundant storage area. The bitstream logic processing module adjusts the bitmask sequence according to the real-time illumination deviation. Perform a cyclic shift operation to align the response region of the logistic convolution kernel inversely with the gradient of the optical field, where the bit mask sequence... Follow the generation function The system's average cross-joint ratio for segmented masks of micron-level shallow pits and cracks on rail surfaces remains stable at [value missing]. And when the ambient light level changes When fluctuations are within a certain range, the geometric center deviation of the segmentation mask remains within a certain range. Within pixels.

[0044] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An image region segmentation and detection system based on lightweight shared convolution, characterized in that, The system includes: The feature storage module is used to store the preset shared weight primitive data, which serves as the physical storage basis for multiple feature channels. The addressing control module is connected to the feature storage module. The addressing control module is used to acquire the image to be segmented, calculate the feature frequency gradient based on the pixel spatial frequency distribution of the image to be segmented, and generate an address mapping sequence based on the second derivative of the feature frequency gradient, so as to control the addressing pointer step size of the weight reading instruction through the address mapping sequence. The bitstream logic processing module is connected to the feature storage module. The bitstream logic processing module includes bitmask logic gates. The bitstream logic processing module is used to assign a unique bitmask sequence to each feature channel. In the physical path of the shared weight primitive data being transmitted from the feature storage module to the arithmetic register, the bitmask logic gates are used to perform a bitwise XOR operation on the read shared weight primitive data and the bitmask sequence. This induces nonlinear jumps in the convolution kernel values ​​without changing the physical storage state of the shared weight primitive data, generating logical convolution kernels with uncorrelated numerical distributions. The image convolution operation unit is connected to the addressing control module and the bitstream logic processing module, respectively. Under the addressing constraints determined by the address mapping sequence, the image convolution operation unit calls the logical convolution kernel to perform multi-scale convolution operation on the image to be segmented, extracts edge features with topological continuity, and outputs the image region segmentation detection results.

2. The image region segmentation and detection system based on lightweight shared convolution according to claim 1, characterized in that, The bitstream logic processing module is used to complete bit plane reassembly within a single physical clock cycle through bitmask logic gate circuits, thereby changing the bitstream distribution characteristics of a single physical weight. The bitstream logic processing module is also used to feed back and adjust the perturbation intensity of the bitmask sequence based on the grayscale spatial distribution entropy value of the image to be segmented, so that the numerical response range of the generated logical convolution kernel is aligned with the local semantic feature space of the image to be segmented.

3. The image region segmentation and detection system based on lightweight shared convolution according to claim 1, characterized in that, The addressing control module is also used to identify a local region of the image to be segmented as a high-frequency texture region and maintain the addressing pointer step size as the standard read increment when the energy gradient of the local region of the image to be segmented exceeds a preset threshold; when the local region of the image to be segmented belongs to a smooth background region, the read span of the addressing pointer step size is increased through address jump logic to perform non-contiguous address reads, so as to adjust the multi-scale feature capture range under a single shared weight framework and reduce the memory bandwidth occupied by multi-branch operations.

4. The image region segmentation and detection system based on lightweight shared convolution according to claim 1, characterized in that, The system also includes an integrity monitoring module, which is connected to the image convolution operation unit. The integrity monitoring module is used to: while the image convolution operation unit is performing operations, simultaneously enable the bitmask logic gate circuit to count the feature sum of the read weights and compare it with the preset integrity index by XOR; the integrity monitoring module is also used to trigger an addressing correction instruction when the comparison result indicates that the hardware address addressing has an offset.

5. The image region segmentation and detection system based on lightweight shared convolution according to claim 1, characterized in that, The system also includes a phase compensation module, which is connected to the image convolution operation unit. The phase compensation module is used to calculate the feature distribution deviation value between different feature channels in the image to be segmented, and generate phase compensation parameters based on the feature distribution deviation value. The phase compensation module is also used to: inject the phase compensation parameters into the output end of the image convolution operation unit, perform phase correction on the feature stream after convolution processing, and distinguish texture features that are spatially topologically similar but have different physical properties.

6. The image region segmentation and detection system based on lightweight shared convolution according to claim 5, characterized in that, The specific logic of the phase compensation module in performing phase correction follows the mathematical relationship below: ,in, This is the corrected feature output vector. The original convolution feature values ​​output by the image convolution operation unit. For phase compensation parameters, This is a standardized factor that characterizes the dispersion of the current feature channel weight distribution.

7. The image region segmentation and detection system based on lightweight shared convolution according to claim 1, characterized in that, The feature storage module uses a compact array structure to store shared weight primitive data, and the physical address of the shared weight primitive data in the memory is mapped to a circular buffer; the addressing control module is also used to determine the rate of change of the addressing pointer step size based on the spatial evolution rate of the feature frequency gradient, and to control the shrinkage of the receptive field in the texture abrupt change region of the image to be segmented.

8. The image region segmentation and detection system based on lightweight shared convolution according to claim 1, characterized in that, The image convolution operation unit is also used to perform feature fusion operations in parallel during the convolution operation, and to aggregate the multi-scale feature maps extracted under different address pointer strides with weights to generate a comprehensive feature descriptor that includes local anisotropic feature precision information and global topological connectivity feature information.

9. The image region segmentation and detection system based on lightweight shared convolution according to claim 1, characterized in that, The bitmask sequence is pre-stored in the mask register of the bitstream logic processing module, and the bit width of the bitmask sequence is consistent with the bit width of the shared weight primitive data. The bitstream logic processing module is also used to improve the response speed of the image convolution operation unit when processing image features without increasing the physical storage unit density by using the logical XOR chain of the bitmask logic gate circuit.

10. The image region segmentation and detection system based on lightweight shared convolution according to claim 1, characterized in that, The image region segmentation detection result output by the image convolution operation unit is sent to the post-processing unit of the system. The post-processing unit is used to superimpose a pseudo-color segmentation mask on the image to be segmented based on the image region segmentation detection result.

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